Package and method for forming the same

Abstract

This invention provides a package and a method for manufacturing the same. The package includes a semiconductor die, an insulating encapsulator, and a redistribution structure. The redistribution structure includes a dielectric layer and stacked via structures embedded in the dielectric layer. The stacked via structures include a first via plug, a first diffusion layer including a plurality of first dopants, a second via plug, and a second diffusion layer including a plurality of second dopants. The first via plug includes a plurality of first dopants dispersed within a first metal material of the first via plug, and the second via plug includes a plurality of second dopants dispersed within a second metal material of the second via plug.

Description

Technical Field

[0001] The embodiments of the present invention relate to a package having a redistributed circuit structure and a method for forming the same. Prior Technology

[0002] During the packaging process of semiconductor chips, a redistribution circuit structure, including metal wiring patterns, pads, and vias, is formed for wiring and interconnecting chips and / or semiconductor devices in the package. Summary of the Invention

[0003] An embodiment of the present invention provides a package comprising: a molded structure including a first semiconductor die and a second semiconductor die, laterally surrounded by an insulating encapsulator; and a redistributed circuit structure disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die, wherein the redistributed circuit structure includes a dielectric layer and a stacked via structure in the dielectric layer, wherein the stacked via structure includes: a first diffusion layer including a first dopant, wherein the first dopant includes silver, zinc, or manganese; a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metal material and the first dopant dispersed within the first metal material; a second diffusion layer disposed on the first via plug, wherein the second diffusion layer includes a second dopant; and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metal material and the second dopant dispersed within the second metal material, and the second metal material includes copper.

[0004] An embodiment of the present invention provides a package comprising: a semiconductor die; an insulating encapsulator laterally surrounding the semiconductor die; and a redistribution structure disposed on the semiconductor die and the insulating encapsulator and electrically connected to the semiconductor die, wherein the redistribution structure comprises: a first dielectric layer having a first opening extending through the first dielectric layer; a first diffusion layer disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer comprises a first dopant; a first conductive via plug disposed on the first diffusion layer, wherein the first conductive via plug comprises the first dopant dispersed therein; a second dielectric layer disposed on the first dielectric layer and having a second opening exposing the first conductive via plug; a second diffusion layer disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer comprises a second dopant; a second conductive via plug disposed on the second diffusion layer, wherein the second conductive via plug comprises the second dopant dispersed therein; and a third dielectric layer disposed on the second dielectric layer and partially covering the second conductive via plug.

[0005] An embodiment of the present invention provides a method for forming a package, comprising: providing a semiconductor die; forming an insulating encapsulation surrounding the semiconductor die; and forming a redistribution structure on the insulating encapsulation and on the semiconductor die, wherein forming the redistribution structure comprises: forming a first dielectric layer having a first opening extending through the first dielectric layer; forming a first diffusion layer on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; forming a first conductive via plug on the first diffusion layer above the first dielectric layer, wherein the first conductive via plug fills the first opening and has the first diffusion layer sandwiched in between, and the first conductive via plug includes a dopant dispersed therein. The method comprises: a first dopant; forming a second dielectric layer on the first dielectric layer and having a second opening that exposes the first conductive via plug; forming a second diffusion layer on the second dielectric layer and covering the second opening and the exposed first conductive via plug, wherein the second diffusion layer comprises the second dopant; forming a second conductive via plug on the second diffusion layer above the second dielectric layer, wherein the second conductive via plug fills the second opening, and the second diffusion layer is located between the first conductive via plug and the second conductive via plug, and the second conductive via plug comprises the second dopant dispersed therein; and forming a third dielectric layer on the second dielectric layer and partially covering the second conductive via plug. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1 to 6 are schematic cross-sectional views of various stages of a manufacturing method for forming a semiconductor package structure according to some exemplary embodiments of the present disclosure.

[0008] Figures 7A to 7F are schematic enlarged cross-sectional views of various stages in a manufacturing method for forming stacked through-holes in a redistributed circuit structure according to some exemplary embodiments of the present disclosure.

[0009] Figure 8 is a schematic cross-sectional view of a portion of a semiconductor package structure having stacked through-holes according to an exemplary embodiment of the present disclosure.

[0010] Figure 9 schematically illustrates a portion of the stacked vias and wiring patterns in a redistribution wiring structure according to an embodiment of this disclosure.

[0011] Figure 10 is a schematic cross-sectional view illustrating a package structure with stacked through-holes according to some exemplary embodiments of the present disclosure. Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "under," "lower," "above," and "upper" to describe the relationship between one element or feature and another, as shown in the figure. In addition to the orientation depicted in the figure, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0014] In addition, for ease of description, this article may use terms such as "first," "second," "third," and "fourth" to describe similar or different elements or features as shown in the figure, and these terms may be used interchangeably depending on the order of appearance or the context of the description.

[0015] Other features and processes may also be included. For example, test structures may be included to assist in verifying and testing 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on redistribution layers or substrates, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with intermediate verification test methods incorporating known good dies to increase yield and reduce costs.

[0016] Figures 1 to 6 are schematic cross-sectional views of various stages in a manufacturing method for forming a semiconductor package structure with a redistribution circuit structure according to some exemplary embodiments of the present disclosure. Figures 7A to 7F are schematic enlarged cross-sectional views of various stages in a manufacturing method for forming stacked vias in a redistribution circuit structure according to some exemplary embodiments of the present disclosure.

[0017] Referring to Figure 1, a semiconductor die 10D is provided. The semiconductor die 10D can be an integrated circuit die formed from a semiconductor wafer. In some embodiments, the semiconductor die 10D includes a semiconductor substrate 110 and a plurality of semiconductor devices 115 formed on or within the semiconductor substrate 110. For example, the semiconductor substrate 110 may include an active layer of a doped or undoped bulk silicon substrate or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 110 may include other semiconductor materials, such as germanium, compound semiconductor materials (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), and alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP). In some embodiments, the semiconductor substrate 110 may be or include a multilayer or gradient substrate. For example, a plurality of semiconductor devices 115 are formed within a device layer 116 on the semiconductor substrate 110. In some embodiments, device layer 116 is formed together with a plurality of semiconductor devices 115, the plurality of semiconductor devices 115 including active devices (e.g., transistors, diodes, etc.) and optionally including passive devices (e.g., capacitors, resistors, inductors, etc.).

[0018] Additionally, referring to FIG1, the semiconductor die 10D further includes an interconnect structure 120 on the device layer 116, a plurality of conductive pads 128 connected to the interconnect structure 120, a passivation layer 130 covering the plurality of conductive pads 128 and the interconnect structure 120, a plurality of conductive pillars 132 disposed on the plurality of conductive pads 128, and a protective layer 134 covering the plurality of conductive pillars 132 and the passivation layer 130. In some embodiments, the interconnect structure 120 includes a plurality of metallization patterns 124 embedded in a dielectric material 122. For example, a plurality of metallization patterns 124 including a plurality of metal lines and a plurality of vias are embedded in a dielectric material 122 formed as one or more low-k dielectric layers. The interconnect structure 120 is electrically interconnected with a plurality of semiconductor devices 115 in the device layer 116 to form an integrated circuit, and electrically connects the plurality of semiconductor devices 115 in the device layer 116 to the plurality of conductive pads 128 and the plurality of conductive pillars 132. In some embodiments, a passivation layer 130 is formed on an interconnect structure 120 above a semiconductor substrate 110 and has a plurality of contact openings exposing a plurality of conductive pads 128. For example, the plurality of conductive pads 128 may be or include aluminum pads, copper pads, or other suitable metal or metal pads, and the passivation layer 130 may be or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. In some embodiments, a plurality of conductive pillars 132 are formed on the plurality of conductive pads 128 by plating. In some embodiments, the plurality of conductive pillars 132 include metal pillars, such as copper pillars or copper alloy pillars. The plurality of conductive pillars 132 can serve as die connectors. For example, a protective layer 134 formed on the passivation layer 130 may include multiple layers and at least include a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers. A protective layer 134 is formed on top of the passivation layer 130, completely covering the multiple conductive pillars 132.

[0019] In some embodiments, the semiconductor die 10D may be or include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, optoelectronic dies, or sensor dies. In some embodiments, the semiconductor die 10D may be a stacked structure comprising multiple semiconductor dies, such as a hybrid memory cube (HMC) die or a high bandwidth memory (HBM) die.

[0020] In some embodiments, the semiconductor die 10D is a known good die (KGD) obtained through wafer testing, and only the KGD undergoes subsequent processing. For simplicity, the detailed construction of the semiconductor device formed in the device layer 116 and the interconnect structure 120 will be omitted in the following figures.

[0021] In some embodiments, referring to FIG2, a carrier 102 coated thereon with a debonding layer 104 is provided. In some embodiments, the carrier 102 comprises any suitable carrier for a method of manufacturing an integrated fan-out (InFO) package structure. In some embodiments, the carrier 102 is a glass carrier or a temporary carrier. In some embodiments, the debonding layer 104 is formed of any material suitable for bonding and debonding the carrier 102 to the aforementioned components or any grains disposed thereon. In some embodiments, the debonding layer 104 comprises a light-to-heat-conversion (LTHC) release coating film that can be peeled off from the carrier 102 at room temperature by applying laser irradiation. In some embodiments, the debonding layer 104 comprises an ultraviolet (UV) adhesive that loses its adhesive properties upon exposure to UV light. In some embodiments, the debonding layer 104 may be dispensed and cured as a liquid, or it may be a laminated film laminated onto the carrier 102.

[0022] Referring to Figure 2, after a release layer 104 is provided on the carrier 102, a plurality of semiconductor dies 10D are provided and placed on the carrier 102. In some embodiments, the plurality of semiconductor dies 10D are picked up and placed on the carrier 102. In some embodiments, the plurality of semiconductor dies 10D are arranged side by side with their back faces facing the release layer 104, such that the back faces of the plurality of semiconductor dies 10D are attached to the release layer 104. In the embodiments described herein, the manufacturing process is for die-first and face-up wafer-level packaging processes.

[0023] Referring to Figure 3, an insulating encapsulation 150 is formed on the top surface of the carrier 102, completely covering and filling between the plurality of semiconductor dies 10D to encapsulate the plurality of semiconductor dies 10D to form a molded structure 15M. In some embodiments, the insulating encapsulation 150 includes a resin material such as epoxy resin, phenolic resin, silicone resin, or combinations thereof, and a filler including silica filler or metal oxide filler. In some embodiments, the method of forming the insulating encapsulation 150 includes forming an insulating resin material (not shown) on a release layer 104 on the carrier 102 through a molding process (e.g., transfer molding, compression molding, or over molding) to completely cover and encapsulate the plurality of semiconductor dies 10D. In some embodiments, the insulating encapsulation 150 completely covers the top surface and sidewalls of the plurality of semiconductor dies 10D. Referring to Figures 1 and 3, in some embodiments, the conductive pillars 132 of a plurality of semiconductor dies 10D are covered by a protective layer 134, so that the conductive pillars 132 of the plurality of semiconductor dies 10D are not exposed and are well protected by the protective layer 134.

[0024] Referring to Figure 4, in some embodiments, a planarization process is performed to partially remove the insulating encapsulation 150 of the molded structure 15M to become a reconstructed wafer 15M'. In some embodiments, during the planarization process, the insulating encapsulation 150 and the protective layer 134 are partially removed until the tops of a plurality of conductive pillars 132 are exposed. In some embodiments, the planarization process includes performing a mechanical polishing process and / or a chemical mechanical polishing (CMP) process. In some embodiments, after the planarization process, the conductive pillars 132 of the plurality of semiconductor dies 10D are exposed from the polished protective layer 134 and the polished insulating encapsulation 150. After the planarization process, a plurality of active surfaces 10DA of the plurality of semiconductor dies 10D are coplanar and flush with the top surface 150T of the polished insulating encapsulation 150. That is, the plurality of conductive pillars 132 are exposed from the active surfaces 10DA of the plurality of semiconductor dies 10D.

[0025] Referring to Figures 5 and 6, a redistribution circuit structure 160 is formed on the top surface of the reconstructed wafer 15M', and a plurality of bump connectors 170 are formed on the redistribution circuit structure 160. In some embodiments, the plurality of bump connectors 170 are or include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or similar.

[0026] In some embodiments, a redistribution circuit structure 160 is disposed on a plurality of semiconductor dies 10D and distributed over a polished insulating encapsulation 150, which laterally surrounds the plurality of semiconductor dies 10D on a carrier 102. In some embodiments, the redistribution circuit structure 160 includes alternating dielectric layers 161, 163, 165, 167, and 169, and conductive layers 162, 164, 166, and 168, with the conductive layers 162, 164, 166, and 168 sandwiched between dielectric layers 161, 163, 165, 167, and 169. The conductive layers 162, 164, 166, and 168 may be referred to as redistribution circuit layers and contain a plurality of metallization patterns. Here, the redistributed circuit structure 160 is shown as an example of a four-layer metallization pattern sandwiched between five dielectric layers. However, it should be understood that more or fewer dielectric layers and metallization patterns can be formed in the redistributed circuit structure 160. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0027] In some embodiments, referring to FIG5, the formation of the redistribution circuit structure 160 begins with the deposition of a dielectric layer 161 on the reconstruction wafer 15M'. In some embodiments, the dielectric layer 161 is made of a dielectric material comprising polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer class. For example, the dielectric layer 161 can be formed by suitable fabrication techniques, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or combinations thereof. In some embodiments, the dielectric layer 161 is made of a photosensitive polymer material that can be directly patterned using a lithography mask. After the dielectric layer 161 is formed, a conductive layer 162 is then formed on the dielectric layer 161. In some embodiments, the conductive layer 162 is formed having a plurality of metallization patterns, including routing lines 162L and vias 162V1 and 162V2. Referring to FIG5, the routing lines 162L (e.g., wires or traces) are located on and extend along the top surface of the dielectric layer 161, while the vias 162V1 and 162V2 extend through the dielectric layer 161 to physically contact and electrically couple to corresponding conductive pillars 132 (die connectors) of a plurality of semiconductor dies 10D. In some embodiments, a seed layer (not shown) and a diffusion layer 1622 are formed directly below the conductive layer 162 and cover the bottom surface of the conductive layer 162, as shown in the partial enlarged view at the top of FIG5. Additionally, the conductive layer 162 is formed having dopants 1623 dispersed therein.

[0028] The formation examples of the redistributed circuit structure will be described in more detail through the formation methods shown in Figures 7A to 7F.

[0029] Figures 7A to 7F show cross-sectional views of a portion of a redistribution circuit structure 760 according to some embodiments. In the illustrated embodiments, the redistribution circuit structure 760 formed on a semiconductor die 70D can be implemented as a portion of a redistribution circuit structure 160 formed on a semiconductor die 10D within a reconstruction wafer 15M' (see Figures 5 and 6). The semiconductor die 70D is similar to the semiconductor die 10D shown above with reference to Figure 1, and similar features are labeled with similar reference numerals, and similar features will not be described again here. For example, the semiconductor die 70D includes a plurality of conductive pillars 72 exposed from a protective layer 74.

[0030] Referring to FIG. 7A, in some embodiments, a dielectric layer 761 is formed on a semiconductor die 70D. In some embodiments, the material of the dielectric layer 761 includes a photosensitive polymer material that can be directly patterned using a lithography mask. In one embodiment, the dielectric layer 761 is formed via spin coating, deposition, or lamination. In some embodiments, the dielectric layer 761 is formed via spin coating. The dielectric layer 761 is then patterned to form a plurality of openings S1 (only one is shown), exposing at least a plurality of conductive pillars 72 of the semiconductor die 70D. When the dielectric layer 761 is made of a photosensitive material such as PBO or PI, patterning may include performing any acceptable process, such as exposing the dielectric layer 761 and then developing it to remove unexposed portions to form the plurality of openings S1. In some embodiments, a baking process may optionally be performed before or after exposure. Alternatively, the dielectric layer 761 may be patterned together with a photoresist pattern by etching using, for example, anisotropic etching. In some embodiments, the dielectric layer 761 is subjected to an annealing process, and the annealing process is performed at a temperature above 200 degrees Celsius. In one embodiment, the annealing process is carried out at a temperature of about 230 degrees Celsius for about 2 to 6 hours.

[0031] Referring to FIG7A, in some embodiments, a seed layer 750 is formed on a dielectric layer 761 having an opening S1. In some embodiments, the seed layer 750 is formed on the dielectric layer 761 and in the opening to cover the bottom surface of the opening S1. In some embodiments, the seed layer 750 is a single metal layer or a composite layer comprising multiple sublayers formed of different metals or metal materials. In some embodiments, the metal material of the seed layer 750 includes silver, copper, antimony, titanium, alloys thereof, or combinations thereof. In one embodiment, the seed layer 750 includes a titanium layer as a diffusion barrier layer and a copper layer above the titanium layer. The seed layer 750 can be formed using, for example, physical vapor deposition (PVD) or sputtering. In some embodiments, the thickness of the seed layer 750 or the remaining seed pattern 750' is relatively thin, and it is acceptable that the seed layer is not retained as a continuous layer. Referring to Figure 7A, due to the contour of the opening S1, the seed layer 750 covers the top surface of the dielectric layer 761 and the bottom surface of the opening S1, but does not cover the sidewalls of the opening S1. In some other embodiments, the seed layer 750 not only covers the dielectric layer 761, but also conformally covers the opening S1.

[0032] Referring to Figures 7A and 7B, in some embodiments, a photoresist pattern 755 having a plurality of openings S2 (only one is shown) is then formed on the seed layer 750. For example, the photoresist pattern 755 is formed by spin coating, cured, and then exposed for patterning. In some embodiments, as shown in Figure 7A, the photoresist pattern 755 is directly disposed on the seed layer 750, covering the seed layer 750 but exposing the openings S1 and partially exposing the seed layer 750 surrounding the openings S1. In some embodiments, the openings S2 include trench openings S2T and via openings S2H connected to the trench openings S2T. In some embodiments, the via openings S2H are connected to the underlying openings S1 to form via plug openings. The patterns of the photoresist pattern 755 and the dielectric layer 761 correspond to the pattern of the metallization pattern to be formed. For example, the position and contour of the via plug opening correspond to the via plug to be formed.

[0033] Referring to FIG7B, a diffusion layer 752 is formed in openings S2 and S1 and on the exposed seed layer 750. In some embodiments, the diffusion layer 752 is formed on the seed layer 750 exposed by opening S2 and conformally covers opening S1 (directly on the sidewalls of opening S1 and on the seed layer 750 on the bottom surface of opening S1). In some embodiments, the formed diffusion layer 752 may conform to the contour of opening S1 and uniformly cover the bottom surface of opening S2. For example, the exposed portion of seed layer 750 may be used as a seed crystal, and the diffusion layer 752 may be formed by plating such that the diffusion layer 752 is formed on the seed layer 750 exposed by opening S2, extends along the sidewalls of opening S1 and covers and extends on the seed layer 750 on the bottom surface of opening S1, but the diffusion layer 752 does not extend to the sidewalls of opening S2 or to the top surface of photoresist pattern 755. In some embodiments, the diffusion layer 752 is formed by plating, such as electroplating or electrochemical plating.

[0034] In some embodiments, the diffusion layer 752 comprises or is made of a metal layer, and the material of the metal layer includes silver (Ag), manganese (Mn), zinc (Zn), alloys thereof, or combinations thereof. The diffusion layer 752 includes metal atoms that can readily diffuse into the subsequently formed metal or a feature of the metal (i.e., a conductive layer). In some embodiments, the diffusion layer 752 can serve as a source of dopant (i.e., a dopant supply layer) to dope the subsequently formed conductive layer. That is, the diffusion layer 752 contains dopant. The thickness of the diffusion layer 752 can be adjusted according to the size or thickness of the subsequently formed feature or layer, and is adjusted to be thick enough to provide sufficient dopant or metal atoms to the aforementioned feature or layer. In some embodiments, the diffusion layer 752 is formed to have a substantially uniform thickness. In some embodiments, the thickness T1 of the diffusion layer 752 can range from about 0.01 micrometers to about 1.0 micrometer, or from about 0.1 micrometers to about 0.5 micrometers. In other embodiments, the diffusion layer 752 on the seed layer 752 on the dielectric layer 761 may be thicker than the diffusion layer 752 on the sidewall of the opening S1, but not thinner than (approximately the same) the diffusion layer 752 on the bottom surface of the opening S1.

[0035] Referring to FIG7C, a conductive layer 740 is formed on the diffusion layer 752, inside the pattern of the photoresist pattern 755 (e.g., inside the opening S2), and fills the openings S1 and S2. In some embodiments, the conductive layer 740 is formed by depositing a metal material (not shown) onto the photoresist pattern 755 to form a diffusion layer 752 covering the photoresist pattern 755, filling the openings S1 and S2, and covering the seed layer 750, and then removing the excess metal material. For example, excess metal material located above the photoresist pattern 755 is removed by etching, and the conductive layer 740 is flattened and flush with the top surface of the photoresist pattern 755.

[0036] Referring to FIG7C, in some embodiments, the conductive layer 740 includes a metallization pattern formed as a routing trace (or routing line) 744 in the trench opening S2T and a through-hole plug 742 formed inside the through-hole plug opening (the hole opening S2H engaging with the opening S1). In some embodiments, the metallic material of the conductive layer 740 is formed by plating, such as electroplating or electrochemical plating. The metallic material may include, for example, aluminum, titanium, copper, nickel, tungsten, cobalt and / or alloys thereof. In some embodiments, the conductive layer 740 fills the openings S1 and S2, and the thickness of the conductive layer 740 may range from about 0.5 micrometers to about 10 micrometers, depending on the thickness of the photoresist pattern 755 and the dielectric layer 761. In some embodiments, the bulk thickness T2 of the through-hole plug 742 of the conductive layer 740 ranges from about 1.5 micrometers to about 6 micrometers. Referring to FIG7C, in some embodiments, the thickness T1 of the diffusion layer 752 may range from about 1% to about 20% of the thickness T2 relative to the bulk thickness T2 of the via plug 742 of the conductive layer 740, provided that the diffusion layer 752 can provide sufficient dopant or doped atoms. In one embodiment, the thickness T1 is greater than 1% of the thickness T2 and less than or equal to 15% of the thickness T2.

[0037] Referring to Figure 7C, during the formation of the conductive layer 740, dopant 741 diffuses from the diffusion layer 752 into the conductive layer 740. That is, the conductive layer 740 is formed with embedded dopant 741. In some embodiments, dopant 741 is or includes metal atoms initially contained within the metallic material of the diffusion layer 752, and dopant 741 may exist in the conductive layer 740 as a single solid metal atom or in the form of tiny grains or particles. For example, the metallic material of the conductive layer 740 is like a solid solution in which metal atoms (dopant 741) are dispersed. It is understood that dopant 741 present at the atomic scale (indicated by small circles in the figure) may not be visible to the naked eye but can be detected by microscopic examination. In some embodiments, the conductive layer 740 is formed with dopant 741 contained therein, and the average content of dopant 741 is from about 5 at% (atomic percentage) to about 11 at% relative to the total number of atoms in the entire conductive layer 740.

[0038] For example, the content of dopant 741 (e.g., metal atoms) in diffusion layer 752 is much higher than that in conductive layer 740. This is because diffusion layer 752 can be formed of a bulk metallic material composed of dopant or metal atoms, and some metal atoms can diffuse out of diffusion layer 752 and move from the contact surface into conductive layer 740 through thermally driven atomic diffusion. In some embodiments, the concentration of dopant 741 in conductive layer 740 can gradually decrease from the interface (contact surface) between conductive layer 740 and diffusion layer 752. That is, more dopant 741 is located in the region of conductive layer 740 near the contact surface (interface) between conductive layer 740 and diffusion layer 752, while less dopant 741 is located in the region of conductive layer 740 away from the contact surface (interface) between conductive layer 740 and diffusion layer 752.

[0039] In some embodiments, the diffusion layer 752 is made of silver (Ag), manganese (Mn), or zinc (Zn), and the dopant 741 comprises Ag atoms, Mn atoms, or Zn atoms. In some embodiments, the diffusion layer 752 is made of silver, or the diffusion layer 752 comprises a silver layer, and the dopant 741 comprises Ag atoms, single atoms, or clusters of atoms. Due to the presence of the diffusion layer 752, taking the electrochemical plating (ECP) process for forming the conductive layer 740 as an example, copper is co-plated with metal atoms (e.g., Ag atoms) diffused from the diffusion layer 752, such that compared to copper formed by the same plating process without the diffusion layer 752, the plated copper has a smaller crystal grain size and more or a larger portion of the copper has a preferred crystal orientation, such as Cu(111).

[0040] Referring to Figure 7D, the photoresist pattern 755 is removed by a suitable etching process using plasma (using oxygen plasma) and / or an acceptable ashing or stripping process. When removing the photoresist pattern 755, the portion of the seed layer 750 underlying the photoresist pattern 755 is removed by the same process, or the seed pattern 750' is formed by using an additional etching process, such as wet etching or dry etching. Here, the portions of the photoresist pattern 755 and the seed layer 750 on which no conductive material is formed are removed.

[0041] As can be seen from the schematic three-dimensional view at the top of Figure 7D, part of the stack 753 of the conductive layer 740, the underlying diffusion layer 752, and the seed pattern 750' is inverted. The diffusion layer 752 completely covers the entire bottom surface of the conductive layer 740 (including the bottom surface of the routing trace 744 and the bottom surface of the through-hole plug 742), while the seed pattern 750' covers the bottom surface of the protrusion 742V of the through-hole plug 742, the bottom surface of the lip portion 742L of the through-hole plug 742, and the bottom surface of the routing trace 744.

[0042] In some embodiments, after the photoresist pattern 755 is removed, a stack 753 (or combination) of the conductive layer 740, the underlying diffusion layer 752, and the seed pattern 750' remains as a metallized pattern disposed on the dielectric layer 761 and contacting (physically and electrically) the conductive pillars 72 of the semiconductor die 70D. In some embodiments, the diffusion layer 752 is thick enough that it remains on the bottom surface of the conductive layer 740, even if some of the metal material of the diffusion layer 752 is consumed or diffused out of the diffusion layer 752.

[0043] Referring to FIG7E, in some embodiments, a dielectric layer 763 is formed on dielectric layer 761, covering conductive layer 740, and having a plurality of openings S3 (only one shown) exposing portions of conductive layer 740. The material and formation method of dielectric layer 763 may be the same as or similar to dielectric layer 761, and will not be described further here. In some embodiments, during the formation of dielectric layer 763, an annealing process is performed at a temperature of about 230 degrees Celsius for about 2 to 6 hours to set dielectric layer 763. During the annealing process, conductive layer 740 and the underlying diffusion layer 752 are also annealed simultaneously, and more dopant 741 diffuses from diffusion layer 752 into conductive layer 740, thereby further increasing the dopant content in conductive layer 740 (especially via plug 742). In some embodiments, after the annealing process, the content of dopant 741 is about 7 at% to about 12 at% relative to the total number of atoms in conductive layer 740.

[0044] Through this annealing process, more conductive layers 740 are formed in a preferred crystal orientation, resulting in a further reduction in the grain size and an increase in grain boundaries within the metallic material of the conductive layer 740. When the metallic material of the conductive layer 740 has a smaller grain size or increased grain boundaries, dislocation resistance increases, and the conductive layer 740 provides higher mechanical strength (including higher hardness and higher toughness) and a higher Young's modulus. Due to the presence of the diffusion layer 752, during the annealing process, when forming the conductive layer 740 with copper as an example, more and more copper will transform into (become) the dominant crystal orientation, such as Cu(111), and the grain size of copper can be further reduced. In some embodiments, after the annealing process, the diffusion layer 752 remains on the bottom surface of the conductive layer 740.

[0045] Referring to FIG. 7E, opening S3 penetrates dielectric layer 763 to expose via plug 742 of conductive layer 740. After forming dielectric layer 763, referring to FIG. 7F, another seed layer 731 is formed on dielectric layer 763 around opening S3 and covers the exposed surface of via plug 742. Subsequently, another diffusion layer 732 is conformally formed over opening S3 and covers seed layer 731. In some embodiments, diffusion layer 732 covers seed layer 731 on dielectric layer 763 around opening S3, sidewalls of opening S3, and seed layer 731 on via plug 742. In some embodiments, another conductive layer 730 including a metallized pattern is formed on diffusion layer 732 on dielectric layer 763 and fills opening S3. Conductive layer 730 includes via plug 734 filled in opening S3 and seated on via plug 742. Referring to Figure 7F, the via plug 734, directly disposed on the diffusion layer 732 on the seed layer 731, extends through the dielectric layer 763 to be physically and electrically connected to the underlying via plug 742. The seed layer 731 and diffusion layer 732 can be formed using similar materials and methods to the seed layer 750 / seed pattern 750' and diffusion layer 752; details will not be repeated here. Additionally, the conductive layer 730 can be formed using similar materials and methods to the conductive layer 740, but with a different metallization pattern, which will not be described again here.

[0046] In some embodiments, the material of the conductive layer 730 is different from that of the conductive layer 740, and the materials of the seed layer 731 and the diffusion layer 732 are different from those of the seed layer 750 and the diffusion layer 752.

[0047] Referring to FIG7F, in some embodiments, a conductive layer 730 embedded with a dopant 731 is formed after a diffusion layer 732 is pre-formed. In some embodiments, the dopant 731 is or includes metal atoms initially contained within the metallic material of the diffusion layer 732, and the dopant 731 may exist in the conductive layer 730 as individual metal atoms or in the form of tiny grains or particles. Although not shown in FIG7F, the conductive layer 730 may be formed with other metallization patterns, such as wires or traces extending along the main surface of the dielectric layer 763.

[0048] In some embodiments, by adjusting the thickness of the diffusion layer 732 relative to the via plug 734, more or less dopant 731 is contained within the via plug 734 compared to the via plug 742. In some embodiments, the content of dopant 741 in the conductive layer 740 (via plug 742 and routing trace 744) differs from the content of dopant 731 in the conductive layer 730 (via plug 734).

[0049] Referring back to Figures 5 and 6, and following the exemplary process steps and formation method shown in Figures 7A to 7F, within the redistributed circuit structure 160, before the formation of conductive layers 162, 164, and 166, diffusion layers 1622, 1642, and 1662 are formed. The subsequently formed conductive layers 162, 164, and 166 are then formed directly on the diffusion layers 1622, 1642, and 1662, and contain dispersed dopants (e.g., dopant 1623 in the enlarged view of Figure 5). Here, since the dopants may be invisible and are not shown in some figures for simplicity, it is understood that the dopants provided by the diffusion layers are diffused and dispersed into the subsequently formed conductive layers and / or their metallic characteristics. Here, for simplicity, seed layers or seed patterns are not shown in the figures.

[0050] In some embodiments, a conductive layer 168 is formed without an underlying diffusion layer, thus forming a layer that is doped. Depending on the product design, one or more conductive layers may be formed without pre-forming a diffusion layer, and doped conductive layers may be formed. Doped conductive layers can exhibit greater mechanical strength (higher hardness, higher toughness, and higher modulus) compared to conductive layers formed without doping. The metal materials of the via plugs 162V1 / 162V2 and other via plugs in conductive layers 162, 164, and 166 have smaller crystal grain sizes, resulting in greater mechanical strength compared to via plugs in doped conductive layers. As a result, redistribution circuit structures (especially stacked via plugs) with doped conductive layers are more reliable and can withstand more demanding processing conditions, with correspondingly improved production yields.

[0051] Figure 8 is a schematic cross-sectional view of a portion of a semiconductor package structure with stacked through-holes according to an exemplary embodiment of the present disclosure. A redistributed circuit structure is formed according to the exemplary process steps and formation methods shown in Figures 7A to 7F. Referring to Figure 8, the redistributed circuit structure 860 is shown as an example having four metallization patterns 862, 864, 866, and 868 (four conductive layers) sandwiched between five dielectric layers 861, 863, 865, 867, and 869. In some embodiments, the redistributed circuit structure 860 is formed on a molding structure 850 having semiconductor dies 810 and 820 laterally encapsulated by an insulating molding compound 830. In one embodiment, the material of the molding compound 830 includes epoxy resin, phenolic resin, or silicone-containing resin, and filler particles, such as silicon dioxide particles.

[0052] Metallized patterns 862, 864, 866, and 868 can be formed using materials and methods similar to those described in the preceding paragraphs for forming conductive layers 730 and 740 with metallized patterns, and will not be repeated here. In some embodiments, dielectric layers 861, 863, 865, 867, and 869 are made of polymeric materials, such as photosensitive polymeric materials that can be directly patterned using a lithography mask. Dielectric layers 861, 863, 865, 867, and 869 can be formed using the same or similar materials and methods as those described in the preceding paragraphs for dielectric layers 761 and 763. Similarly, the formation of dielectric layers 861, 863, 865, 867, and 869 may involve performing one or more annealing processes, and the annealing processes may be performed at a temperature of about 230 degrees Celsius for about 2 to 6 hours.

[0053] Referring to Figure 8, in the stacked structure of metallization patterns 862, 864, 866, and 868, the stacked structure SV1 (stacked vias) of via plugs 862V, 864V, 866V, and 868V is electrically connected to the underlying semiconductor die 810, while the stacked structure SV2 (stacked vias) of via plugs 862V, 864V, and 866V is electrically connected to the underlying semiconductor die 820. In some embodiments, the semiconductor die 810 is electrically connected to a plurality of bump connectors 880 (only one shown) through the routing trace 868L of the stacked structure SV1 and the metallization pattern 868, while the semiconductor die 820 is electrically connected to the bump connectors 880 through the routing traces 866L, 868L, via plugs 868V, and the stacked structure SV2. In some embodiments, the bump connector 880 includes a C4 bump. Further referring to FIG8, in some embodiments, through-hole plugs 862V, 864V, 866V, and 868V have inclined sidewalls. In some embodiments, at least one through-hole plug 868V is laterally displaced relative to the stacked structure SV2 (stacked through-holes) of through-hole plugs 862V, 864V, and 868V. In some embodiments, through-hole plugs 862V, 864V, 866V, and 868V in stacked structure SV1 or stacked structure SV2 are stacked perpendicularly to each other.

[0054] As shown in Figure 8, metallized patterns 862, 864, 866, and 868 are formed such that their bottom surfaces are covered by diffusion layers 8622, 8642, 8662, and 8682, respectively, and sandwiched between their bottom surfaces and underlying seed layers 8621, 8641, 8661, and 8681. Seed layers 8621, 8641, 8661, 8681, and diffusion layers 8622, 8642, 8662, and 8682 can be formed using materials and methods similar to those used for seed layers 731, 750, 732, and 752. Similarly, metallization patterns 862, 864, 866, and 868 are formed with dopants 8623, 8643, 8663, and 8683 dispersed therein. Through the same or similar formation process, with diffusion layers 8622, 8642, 8662, and 8682 directly below and dopants 8623, 8643, 8663, and 8683 dispersed therein, the metallic material of metallization patterns 862, 864, 866, and 868 is formed with a predominant crystal orientation, resulting in a further reduction in crystal grain size and an increase in the number of crystal boundaries formed therein. Compared to undoped through-hole plugs, the through-hole plugs 862V, 864V, 866V, and 868V have smaller crystal grain sizes, resulting in higher mechanical strength. Therefore, the formed metallization patterns 862, 864, 866, and 868 (especially through-hole plugs 862V, 864V, 866V, and 868V) exhibit high mechanical strength and a high Young's modulus, with very few or no voids. Consequently, even after multiple thermal cycles, a reliable stacked structure for the redistributed circuitry (especially stacked through-holes or stacked through-hole plugs) can be formed with very few or no cracking.

[0055] By forming metallization patterns 862, 864, 866, and 868 with dopants 8623, 8643, 8663, and 8683, respectively, stronger and harder via plugs 862V, 864V, 866V, and 868V are formed. As described above, the redistribution structure 860 is more robust regardless of whether the via plugs are stacked or interleaved. Therefore, due to fewer defects caused by strain in the redistribution structure 860, the redistribution structure becomes more reliable and durable, improving its process window and design flexibility. Consequently, for packages or semiconductor devices including such redistribution structures, better wiring efficiency and reliability can be achieved.

[0056] Figure 9 schematically illustrates a portion of the stacked vias and wiring patterns in a redistribution structure according to an embodiment of this disclosure. Referring to Figure 9, it can be seen that the stacked via plugs V1, V2, and V3 form a diffusion layer DB that covers the bottom surfaces of via plugs V1, V2, and V3 respectively, but does not cover the top surfaces of via plugs V1, V2, and V3. As shown in Figure 9, the diffusion layer DB is located between and sandwiched between via plugs V1 and V2, and between via plugs V2 and V3. That is, the diffusion layer DB located between via plugs V1 and V2 physically separates via plugs V1 and V2, and the diffusion layer DB located between via plugs V2 and V3 physically separates via plugs V2 and V3. Furthermore, the routing trace R1 has a diffusion layer DB formed on its bottom surface. In some embodiments, the stacked through-hole plugs V1, V2, and V3 are electrically connected to each other.

[0057] Compared to through-hole plugs formed by plating without a diffusion layer or dopants, copper through-hole plugs with a silver layer (as a diffusion layer on their bottom surface) exhibit the following effects when the diffusion layer thickness is approximately 15% of the through-hole plug's body thickness and the dopant content (such as Ag / Ag atoms) in the through-hole plug is approximately 7 at% (atomic percentage): the copper crystal grain size is reduced by approximately 30%, the through-hole plug's hardness increases by 20% (1.2 times), its toughness increases by approximately 32%, and its modulus (Young's modulus) increases by approximately 8% to 10%, if measured using an indentation test.

[0058] Figure 10 is a schematic cross-sectional view illustrating a package structure with stacked through-holes according to some exemplary embodiments of the present disclosure.

[0059] Referring to FIG10, in some embodiments, a package structure 18 is shown, which includes at least one package unit 90 mounted and bonded to a circuit substrate 9S via a plurality of bump connectors 94. In some embodiments, the package unit 90 includes a first semiconductor die 90D1 and a second semiconductor die 90D2 laterally surrounded by an insulating encapsulation 92, a redistribution circuit structure 96 formed on the first semiconductor die 90D1 and the second semiconductor die 90D2 and extending on the encapsulation 92, and a plurality of bump connectors 94 located on the redistribution circuit structure 96. In some embodiments, the first semiconductor die 90D1 and the second semiconductor die 90D2 are different types of dies or perform different functions. In some embodiments, the first semiconductor die 90D1 may include one or more of an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless application chip (e.g., a Bluetooth chip or an RF chip), a voltage regulation chip, or a system-on-a-chip (SoC). In some embodiments, the second semiconductor die 90D2 includes one or more memory chips, such as high bandwidth memory (HBM) chips, dynamic random access memory (DRAM) chips, or static random access memory (SRAM) chips. Figure 10 shows two dies as exemplary dies in a package structure; however, it should be understood that multiple dies, or two or more types of dies, or different types of dies, may be included within the package structure. In some embodiments, dies and chips may be used interchangeably.

[0060] In some embodiments, a first semiconductor die 90D1 and a second semiconductor die 90D2 (face down, active surface facing the redistribution structure 96) are bonded to the redistribution structure 96 through a plurality of die connectors 902 of the first semiconductor die 90D1 and the second semiconductor die 90D2. Additionally, an underfill 95 fills the space between the circuit substrate 9S and the redistribution structure 96 and surrounds a plurality of bump connectors 94. In some embodiments, the underfill 95 fills the gap between the package unit 90 and the circuit substrate 9S, and the underfill 95 may overflow to partially cover the sidewalls of the redistribution structure 96. In some embodiments, the first semiconductor die 90D1, the second semiconductor die 90D2, and the redistribution structure 96 are substantially the same as or similar to the corresponding elements described in the preceding paragraphs, and detailed descriptions will be skipped. As shown in FIG10, the circuit substrate 9S can provide double-sided electrical connections and further electrical connections through a plurality of conductive balls 98. In some embodiments, the circuit substrate 9S is a printed circuit board (PCB), a flexible PCB, or any suitable laminated circuit substrate. In some embodiments, taking a circular bump as an example, the size (diameter) of the conductive ball 98 is larger than the size (diameter) of the bump connector 94. Through these conductive connections and the redistributed circuit structure, the finer-pitch semiconductor dies 90D1 and 90D2 are electrically connected to the larger-pitch circuit substrate 9S.

[0061] Following the exemplary process steps and formation method shown in Figures 7A to 7F, the redistributed circuit structure 96 is formed with three conductive layers 962, 964, and 966 (as a three-layer metallization pattern) sandwiched between four dielectric layers 961, 963, 965, and 967. Through the same or similar formation process, the conductive layers 962, 964, and 966 are formed with diffusion layers 9622, 9642, and 9662 located directly below them, and these layers contain dopants. Here, for simplicity, the seed layer or seed pattern is not shown in the figures. As shown in the partial enlarged view of Figure 10, dopants 9623 and 9643 are formed in the conductive layers 962 and 964, and the diffusion layers 9622 and 9642 cover the surfaces of the conductive layers 962 and 964 (the top surface in Figure 10). Although not shown in Figure 10, conductive layer 966 is formed with dopants (metal atoms). In some embodiments, the metallization pattern of conductive layers 962, 964, and 966 includes at least via plugs 962V, 964V, and 966V. Therefore, by forming conductive layers containing dopants (using a metallic material), the metallization pattern including via plugs 962V, 964V, and 966V is formed to have higher mechanical strength and a higher Young's modulus. As a result, the package structure with this redistribution structure becomes more reliable and provides excellent electrical performance. For packages with such redistribution structures, cracks formed in the redistribution structure (especially stacked vias or stacked via plugs) are minimal or nonexistent, thereby enabling reliable and satisfactory electrical interconnection and wiring.

[0062] According to the exemplary embodiments described above, a package structure can be suitably formed after the process of manufacturing an integrated fan-out (InFO) wafer-level package structure. More than one or more redistribution layers (RDLs) can be provided in the package structure, or more than one or more redistribution layers (RDLs) can be arranged on the front and back sides of a die or wafer for signal redistribution among multiple dies or wafers. The structures and / or processes disclosed herein are not limited to the exemplary embodiments. According to the exemplary embodiments described above, the layout and configuration of the redistribution structure can be suitably formed within the wafer-level package structure. Additionally, the package structure may also include additional die or sub-package units disposed above or below the die, and another redistribution structure or layer may be formed to electrically connect the additional die or sub-package units. The structures and / or processes disclosed herein are not limited to the exemplary embodiments.

[0063] The presence of dopants within the conductive metallization pattern of the redistributed circuit structure enhances its mechanical strength and provides reliable electrical connections. By forming a diffusion layer before the metal material forming the conductive metallization pattern in the redistributed circuit structure, dopants are incorporated into the conductive metallization pattern, which strengthens mechanical properties and improves structural integrity. Through this redistributed circuit structure, the through-hole plug stack structure exhibits higher mechanical strength and fewer cracks, thereby improving the reliability of the packaging structure.

[0064] This disclosure is not limited to the type or number of semiconductor packages connected to the circuit substrate. It is evident that different types of semiconductor package units can be used to produce semiconductor device package structures that include the circuit substrates disclosed herein, and all such semiconductor devices are intended to fall within the scope of this specification and the appended claims. For example, chip-on-wafer-on-substrate (CoWoS) structures, three-dimensional integrated circuit (3DIC) structures, chip-on-wafer (CoW) packages, and package-on-package (PoP) structures can all be used individually or in combination as semiconductor package units.

[0065] According to some embodiments, the package includes a molded structure having a first semiconductor die and a second semiconductor die laterally surrounded by an insulating encapsulant, and a redistributed circuit structure disposed on the molded structure and electrically connected to the first and second semiconductor dies. The redistributed circuit structure includes a dielectric layer and a stacked via structure embedded in the dielectric layer. The stacked via structure includes a first via plug, a first diffusion layer including a first dopant, a second via plug, and a second diffusion layer including a second dopant. The first via plug is disposed on the first diffusion layer. The first via plug includes a first dopant dispersed within a first metal material of the first via plug, and a first surface of the first via plug is covered by the first diffusion layer. The second diffusion layer is disposed on the second via plug. The second via plug disposed on the second diffusion layer includes a second dopant dispersed within a second metal material of the second via plug. The second metal material includes copper. According to some embodiments, the package includes a molded structure and a redistributed circuit structure. The molded structure includes a first semiconductor die and a second semiconductor die laterally surrounded by an insulating encapsulant. The redistributable circuit structure includes a dielectric layer and a stacked via structure embedded in the dielectric layer. The redistributable circuit structure is disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die, wherein the redistributable circuit structure includes a dielectric layer and a stacked via structure within the dielectric layer. The stacked via structure includes a first diffusion layer comprising a first dopant, wherein the first dopant includes silver, zinc, or manganese; a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metal material and the first dopant dispersed within the first metal material; a second diffusion layer disposed on the first via plug, wherein the second diffusion layer includes a second dopant; and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metal material and the second dopant dispersed within the second metal material, and the second metal material includes copper. In some embodiments, the copper in the second metal material has a predominantly Cu(111) crystal orientation. In some embodiments, the redistribution structure includes a first routing trace embedded in the dielectric layer, the first routing trace being connected to the first via plug, and the first routing trace being lined with a first diffusion layer covering the surface of the first routing trace. In some embodiments, the redistribution structure includes a second routing trace embedded in the dielectric layer, the second routing trace being connected to the second via plug, and the second routing trace being lined with a second diffusion layer covering the surface of the second routing trace. In some embodiments, the first routing trace includes the first dopant, and the second routing trace includes the second dopant. In some embodiments, the first metal material includes copper, and the content of the first dopant in the first via plug is approximately or less than 12 at% and greater than 5 at%.In some embodiments, the second dopant includes silver, zinc, or manganese, and the content of the second dopant in the second through-hole plug is approximately or less than 12 at% and greater than 5 at%.

[0066] According to some embodiments, the package structure includes a semiconductor die, an insulating encapsulation laterally surrounding the semiconductor die, and a redistribution structure disposed on and extending over the semiconductor die and the insulating encapsulation. The redistribution structure is electrically connected to the semiconductor die. The redistribution structure includes first, second, and third dielectric layers, first and second diffusion layers, and first and second conductive via plugs. The first diffusion layer is disposed on the first dielectric layer and covers a first opening in the first dielectric layer. The first diffusion layer includes a first dopant. The first dopant comprises silver, zinc, or manganese. The first conductive via plug is disposed on the first diffusion layer and fills the first opening, with the first diffusion layer sandwiched therebetween. The first conductive via plug includes the first dopant dispersed therein. A second dielectric layer is disposed on the first dielectric layer and has a second opening exposing the first conductive via plug. The second diffusion layer is disposed on the second dielectric layer and covers the second opening and the exposed first conductive via plug. The second diffusion layer includes a second dopant. A second conductive via plug is disposed on the second diffusion layer and fills the second opening, with the second diffusion layer sandwiched between the first and second conductive via plugs. The second conductive via plug includes a second dopant dispersed therein. A third dielectric layer is disposed on the second dielectric layer and partially covers the second conductive via plug. According to some embodiments, the package includes a semiconductor die; an insulating encapsulation laterally surrounding the semiconductor die; and a redistributed wiring structure disposed on the semiconductor die and the insulating encapsulation, and electrically connected to the semiconductor die. The redistribution structure includes: a first dielectric layer having a first opening extending through the first dielectric layer; a first diffusion layer disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; a first conductive via plug disposed on the first diffusion layer, wherein the first conductive via plug includes the first dopant dispersed therein; a second dielectric layer disposed on the first dielectric layer and having a second opening exposing the first conductive via plug; a second diffusion layer disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer includes a second dopant; a second conductive via plug disposed on the second diffusion layer, wherein the second conductive via plug includes the second dopant dispersed therein; and a third dielectric layer disposed on the second dielectric layer and partially covering the second conductive via plug. In some embodiments, the material of the first diffusion layer includes silver, zinc, or manganese, and the material of the second diffusion layer includes silver, zinc, or manganese. In some embodiments, the first conductive via plug includes copper, the first dopant includes silver, and the content of the first dopant in the first conductive via plug is approximately or less than 12 at% and greater than 5 at%. In some embodiments, the second conductive via plug comprises copper, the second dopant comprises silver, and the content of the second dopant in the second conductive via plug is approximately or less than 12 at% and greater than 5 at%.In some embodiments, the content of the first dopant in the first conductive via plug is different from the content of the second dopant in the second conductive via plug. In some embodiments, the package further includes a third conductive via plug disposed on the third dielectric layer and directly disposed on the second conductive via plug, wherein the third conductive via plug does not contain any dopant. In some embodiments, the first conductive via plug is made of a first metal material with a first crystal grain size, the second conductive via plug is made of a second metal material with a second crystal grain size, and the third conductive via plug is made of a third metal material with a third crystal grain size, wherein the first crystal grain size is substantially the same as and smaller than the second crystal grain size. In some embodiments, the package further includes a circuit substrate and a plurality of connectors disposed on the redistributable circuit structure, wherein the circuit substrate is electrically connected to the redistributable circuit structure and the semiconductor die through the plurality of connectors.

[0067] According to some embodiments, a method for manufacturing a package structure is provided. After providing a semiconductor die, an insulating encapsulation is formed around the semiconductor die. A redistribution structure is formed on the insulating encapsulation and on the semiconductor die. The formation of the redistribution structure includes forming a first dielectric layer having a first opening extending through a first dielectric layer, and forming a first diffusion layer on the first dielectric layer and covering the first opening. The first diffusion layer includes a first dopant. Subsequently, a first conductive via plug is formed on the first diffusion layer on the first dielectric layer, filling the first opening, with the first diffusion layer sandwiched therebetween, and the first conductive via plug includes a first dopant dispersed therein. After forming a second dielectric layer on the first dielectric layer and having a second opening exposing the first conductive via plug, a second diffusion layer is formed on the second dielectric layer and covering the second opening and the exposed first conductive via plug. The second diffusion layer includes a second dopant. A second conductive via plug is formed on the second diffusion layer on the second dielectric layer, filling the second opening, and the second diffusion layer is between the first and second conductive via plugs. The second conductive via plug includes a second dopant dispersed therein. Then a third dielectric layer is formed on the second dielectric layer and partially covers the second conductive via plug. According to some embodiments, a method of forming a package includes: providing a semiconductor die; forming an insulating encapsulation surrounding the semiconductor die; and forming a redistribution structure on the insulating encapsulation and on the semiconductor die. Forming the redistribution structure includes: forming a first dielectric layer having a first opening extending through the first dielectric layer; forming a first diffusion layer on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; forming a first conductive via plug on the first diffusion layer above the first dielectric layer, wherein the first conductive via plug fills the first opening and has the first diffusion layer sandwiched in between, and the first conductive via plug includes the first dopant dispersed therein; forming a second dielectric layer on the first dielectric layer and having a third dielectric layer exposing the first conductive via plug. The process includes: forming a second diffusion layer on the second dielectric layer and covering the second opening and the exposed first conductive via plug, wherein the second diffusion layer includes a second dopant; forming a second conductive via plug on the second diffusion layer above the second dielectric layer, wherein the second conductive via plug fills the second opening, and the second diffusion layer is located between the first conductive via plug and the second conductive via plug, and the second conductive via plug includes the second dopant dispersed therein; and forming a third dielectric layer on the second dielectric layer and partially covering the second conductive via plug. In some embodiments, forming the first diffusion layer includes performing an electrochemical plating process to form a silver layer, and the first dopant includes silver.In some embodiments, forming the first conductive via plug includes performing copper electrochemical plating to add silver as the first dopant to the first conductive via plug. In some embodiments, forming the second diffusion layer includes performing an electrochemical plating process to form a silver layer, and the second dopant includes silver. In some embodiments, forming the second conductive via plug includes performing copper electrochemical plating to add silver as the second dopant to the second conductive via plug.

[0068] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0069] 9S: Circuit substrate 10D, 70D, 810, 820: Semiconductor chips 10DA: Active Surface 15M, 850: Molded structure 15M': Reconstructed Wafer 18: Packaging Structure 72, 132: Conductive pillars 74, 134: Protective layer 90: Packaging Unit 90D1: First semiconductor die / semiconductor die 90D2: Second semiconductor die / semiconductor die 92: Encapsulation / Insulating Encapsulation 94, 170, 880: Protrusion connector 95: Bottom filler 96, 160, 760, 860: Re-laid circuit structure 98: Conductive sphere 102: Carrier 104: Peel-off layer 110: Semiconductor substrate 115: Semiconductor Devices 116: Device Layer 120: Internal Wiring Structure 122: Dielectric materials 124, 862, 864, 866, 868: Metallized patterns 128: Conductive pad 130: Passivation layer 150: Insulating Encapsulation 150T: Top surface 161, 163, 165, 167, 169, 761, 763, 861, 863, 865, 867, 869, 961, 963, 965, 967: Dielectric layer 162, 164, 166, 168, 730, 740, 962, 964, 966: Conductive layer 162L: Router cable 162V1, 162V2: Through-hole / Through-hole plug 731, 750, 8621, 8641, 8661, 8681: Seed layers 732, 752, 1622, 1642, 1662, 8622, 8642, 8662, 8682, 9622, 9642, 9662: Diffusion layer 741, 1623, 8623, 8643, 8663, 8683, 9623, 9643: Dopants 742, 734, 862V, 864V, 866V, 868V, V1, V2, V3, 962V, 964V, 966V: Through-hole plugs 742L: Lip area 742V: Protruding part 744, 866L, 868L, R1: Routing traces 750': Seed pattern 753: Stacking 755: Photoresist pattern 830: Molded compound 902: Grain connector DB: Diffusion Layer / Diffusion Initiation Layer S2H: Hole opening S2T: Ditch opening SV1, SV2: Stacked structure T1, T2: Thickness S1, S2, S3: Openings

Claims

1. A package comprising: A molded structure, comprising a first semiconductor die and a second semiconductor die, is laterally surrounded by an insulating encapsulation. A redistributable circuit structure is disposed on the molded structure and electrically connected to the first semiconductor die and the second semiconductor die. The redistributable circuit structure includes a dielectric layer and a stacked via structure within the dielectric layer. The stacked via structure includes: a first diffusion layer comprising a first dopant, wherein the first dopant includes silver, zinc, or manganese; a first via plug disposed on the first diffusion layer, wherein the first via plug includes a first metal material and the first dopant dispersed within the first metal material, wherein the first metal material includes copper, and the content of the first dopant in the first via plug is approximately or less than 12 at% and greater than 5 at%; a second diffusion layer disposed above the first via plug, wherein the second diffusion layer includes a second dopant; and a second via plug disposed on the second diffusion layer, wherein the second via plug includes a second metal material and the second dopant dispersed within the second metal material, and the second metal material includes copper.

2. The package as claimed in claim 1, wherein the copper in the second metal material has a predominantly Cu(111) crystal orientation.

3. The package as claimed in claim 1, wherein the redistribution structure includes a first routing trace embedded in the dielectric layer, the first routing trace being connected to the first via plug, and the first routing trace being lined with the first diffusion layer covering the surface of the first routing trace.

4. A package comprising: Semiconductor grains; An insulating encapsulation is laterally surrounding the semiconductor grain; And a redistribution circuit structure disposed on the semiconductor die and the insulating encapsulation, and electrically connected to the semiconductor die, wherein the redistribution circuit structure includes: a first dielectric layer having a first opening extending through the first dielectric layer; A first diffusion layer, disposed on the first dielectric layer and covering the first opening, wherein the first diffusion layer includes a first dopant; a first conductive via plug, disposed on the first diffusion layer, wherein the first conductive via plug includes the first dopant dispersed therein, wherein the first conductive via plug includes copper, the first dopant includes silver, and the content of the first dopant in the first conductive via plug is approximately or less than 12 at% and greater than 5 at%; a second dielectric layer, disposed on the first dielectric layer and having a second opening exposing the first conductive via plug; a second diffusion layer, disposed on the second dielectric layer and covering the second opening, wherein the second diffusion layer includes a second dopant; a second conductive via plug, disposed on the second diffusion layer, wherein the second conductive via plug includes the second dopant dispersed therein; and a third dielectric layer, disposed on the second dielectric layer and partially covering the second conductive via plug.

5. The package as claimed in claim 4, wherein the material of the first diffusion layer comprises silver, zinc, or manganese, and the material of the second diffusion layer comprises silver, zinc, or manganese.

6. The package as claimed in claim 4 further includes a third conductive via plug disposed on the third dielectric layer and directly disposed on the second conductive via plug, wherein the third conductive via plug does not contain any dopant.

7. A method of forming a package, comprising: Provide semiconductor chips; An insulating encapsulation is formed around the semiconductor grain; And forming a redistribution circuit structure on the insulating encapsulation and on the semiconductor die, wherein forming the redistribution circuit structure includes: forming a first dielectric layer having a first opening extending through the first dielectric layer; A first diffusion layer is formed on the first dielectric layer and covers the first opening, wherein the first diffusion layer includes a first dopant; a first conductive via plug is formed on the first diffusion layer above the first dielectric layer, wherein the first conductive via plug fills the first opening and sandwiches the first diffusion layer in the middle, and the first conductive via plug includes the first dopant dispersed therein, wherein the first conductive via plug includes copper, the first dopant includes silver, and the content of the first dopant in the first conductive via plug is about or less than 12 at% and greater than 5 at%; a second dielectric layer is formed on the first dielectric layer and has a second opening exposing the first conductive via plug; a second diffusion layer is formed on the second dielectric layer and covers the second opening and the exposed first conductive via plug, wherein the second diffusion layer includes a second dopant; A second conductive via plug is formed on a second diffusion layer above the second dielectric layer, wherein the second conductive via plug fills the second opening, and the second diffusion layer is located between the first conductive via plug and the second conductive via plug, and the second conductive via plug includes the second dopant dispersed therein; and a third dielectric layer is formed on the second dielectric layer and partially covers the second conductive via plug.

8. The method of forming an encapsulation as claimed in claim 7, wherein forming the first diffusion layer includes performing an electrochemical plating process to form a silver layer, and the first dopant includes silver.

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