Semiconductor structures and methods of forming the same

Abstract

A method for forming a semiconductor structure is provided. A substrate has a first region and a second region. A through-hole is formed in the substrate in the first region. A first conductive pattern covering the through-hole is formed in the first region, and a first conductive layer is simultaneously formed on the substrate in the second region. A second conductive pattern is formed on the first conductive pattern in the first region, and a second conductive layer is simultaneously formed on the first conductive layer in the second region.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods of forming them. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generation after generation of ICs, each generation smaller and more complex than the last. In the development of ICs, functional density (the number of interconnected devices per die area) typically increases, while geometry (the smallest component (or line) that can be created using manufacturing processes) decreases. This miniaturization process generally benefits by increasing production efficiency and reducing associated costs. While existing semiconductor structures are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided. A substrate has a first region and a second region. A through-hole is formed in the substrate in the first region. A first conductive pattern covering the through-hole is formed in the first region, and simultaneously a first conductive layer is formed on the substrate in the second region. A second conductive pattern is formed on the first conductive pattern in the first region, and simultaneously a second conductive layer is formed on the first conductive layer in the second region.

[0004] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided. A first die is provided and formed by the following operations: A substrate has a first region and a second region. A lower through-hole is formed in the first region, extending from a first side of the substrate to a second side. An upper through-hole is formed on the substrate in the first region, and the upper through-hole contacts the lower through-hole, wherein at the substrate surface, the width of the upper through-hole is greater than the width of the lower through-hole. The substrate is thinned to expose the lower through-hole.

[0005] According to one aspect of this disclosure, a semiconductor structure includes a substrate, a via, and a first conductive pattern. The substrate has a first region and a second region. The via is formed in the substrate in the first region. The first conductive pattern is formed on the substrate and lands on the via in the first region, wherein the width of the first conductive pattern is greater than the width of the via. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1 to 16 show cross-sectional views of methods for forming semiconductor structures according to some embodiments of the present disclosure. Figure 17A shows a top view and a cross-sectional view of a portion of the semiconductor structure in Figure 16 according to some embodiments of the present disclosure. Figures 17B to 17D show different cross-sectional views of portions of the semiconductor structure in Figure 16 according to other embodiments of the present disclosure. Figures 18 to 20 show different cross-sectional views of semiconductor structures according to some embodiments of the present disclosure. Figure 21 shows a flowchart of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Figure 22 shows a flowchart of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself prescribe relationships between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptions used herein shall be interpreted accordingly. Unless otherwise expressly stated, components with the same reference numerals refer to the same components and are assumed to have the same material composition and the same range of thickness.

[0009] This disclosure relates to semiconductor structures and methods of forming them. In some embodiments, one or more substrate vias are formed as semiconductor substrates through a die or wafer. Substrate vias can be used to electrically connect components at opposite sidewalls of the semiconductor substrate and allow multiple dies to be stacked to form a 3D package or 3D integrated circuit (3DIC). Related substrate vias are formed by defining a single deep opening through dry etching and wet stripping, followed by a single electroplating process. These substrate vias require a guard ring to prevent moisture effects caused by the prolonged wet stripping process during the deep opening definition step. However, the substrate vias of this disclosure are defined by forming multiple shallow openings and alternating multiple electroplating processes. The wet stripping process is short and has less moisture impact, thus eliminating the need for a guard ring. Furthermore, in this disclosure, multiple shallow conductive patterns of the substrate vias and multiple adjacent conductive layers of the interconnect structure can be simultaneously defined using the same multiple photomasks. The method of this disclosure is compatible with existing processes and does not increase process steps or cost.

[0010] Figures 1 to 16 show cross-sectional views of methods for forming semiconductor structures according to some embodiments of the present disclosure. It should be understood that the present disclosure is not limited to the methods described below. For additional embodiments of the method, additional operations may be provided before, during, and / or after the method, and some operations described below may be replaced or eliminated. Although Figures 1 to 16 are described with respect to methods, it should be understood that the structures disclosed in Figures 1 to 16 are not limited to this method but may exist independently of this method.

[0011] Referring to Figure 1, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In other embodiments, the substrate 100 includes elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 100 is on the order of hundreds of micrometers. The substrate 100 has a first region 100a and a second region 100b adjacent to each other. In some embodiments, the first region 100a is a through-hole region, and the second region 100b is a device region. The substrate has a first side S1 and a second side S2 opposite to the first side S1. In some embodiments, the first side S1 is a front side or active side, and the second side S2 is a rear side or non-active side.

[0012] In some embodiments, device 101 is formed on a first side S1 of substrate 100. In some embodiments, device 101 may include active and / or passive devices. For example, device 101 may include transistors, diodes, capacitors, resistors, etc., formed by any suitable forming method.

[0013] Figures 1 and 2 illustrate the formation of at least one through-hole TV1 in a substrate 100. In some embodiments, at least one opening 102 extending from a first side S1 to a second side S2 of the substrate 100 is formed by lithography and etching processes. In some embodiments, a mask layer HM (e.g., photoresist, dielectric material, or both) is formed over the substrate 100, and the substrate is etched using the mask layer HM as an etching mask to form the opening 102. The opening 102 may be defined by a photomask. The mask layer HM is then removed by a suitable etching process.

[0014] Next, an insulating liner 103 is used to line the opening 102. The insulating liner 103 may include silicon oxide and may be formed by a deposition process such as chemical vapor deposition (CVD). Then, a metal liner 104 and a metal layer 106 are formed in the opening 102. In some embodiments, the metal liner 104 includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. The seed layer may include Cu, Al, etc. For example, the metal liner 104 may contain Ti and Cu. The metal liner 104 may be formed by a sputtering process or a deposition process. The metal layer 106 may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, etc., or combinations thereof. The metal layer 106 may be formed by an electroplating process or a deposition process. In some embodiments, the metal layer 106 is formed in the opening 102 by using the metal liner 104 as a seed. Excess material outside the opening 102 is then removed by a planarization process (e.g., a chemical mechanical polishing (CMP) process). In some examples, the remaining metal liner 104 and the remaining metal layer 106 constitute a lower through-hole TV1 in the first region 100a. The top surface of the lower through-hole TV1 is substantially flush with the first side S1 of the substrate 100. In some examples, the lower through-hole TV1 is referred to as the “zeroth conductive pattern” of the substrate perforation.

[0015] Figures 3 to 9 illustrate the formation of an upper through-hole TV2 in a first region 100a and the simultaneous formation of an interconnect structure IS1 in a second region 100b. In some embodiments, the upper through-hole TV2 comprises multiple stacked conductive patterns, and the interconnect structure IS1 comprises multiple stacked conductive layers, with the conductive patterns and conductive layers formed simultaneously on substantially the same horizontal plane. The detailed process is described below.

[0016] Figures 3 and 4 show a first conductive pattern P1 formed on a lower through hole TV1 in the first region 100a, and a first conductive layer ML1 formed on a substrate 100 in the second region 100b.

[0017] In some embodiments, a dielectric layer DL1 is formed on a substrate 100 spanning a first region 100a and a second region 100b. The dielectric layer DL1 includes at least one etch-stop material and at least one dielectric material having different materials and etch selectivity. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, as shown in the enlarged views of Figures 17A to 17D, the dielectric layer DL1 may include two dielectric materials DM1 and two etch-stop materials EM1 stacked alternately. The dielectric layer DL1 is patterned to form a first level opening 114a in the first region 100a and a first level opening 114b in the second region 100b. The first level openings 114a and 114b are formed simultaneously using the same photolithography and etching processes. The first-level opening 114a in the first region 100a is a hole used to define a portion of the upper through-hole. The first-level opening 114b in the second region 100b is a double-dotted opening, including a groove for defining a conductor and a lower hole for defining a through-hole. The first-level openings 114a and 114b are defined by the same photomask. Depending on the process, one or two photomasks may be used to form the first-level openings 114a and 114b.

[0018] Referring to Figure 4, a metal liner 108a and a metal layer 110a are formed in the first layer opening 114a in the first region 100a, and a metal liner 108b and a metal layer 110b are formed in the first layer opening 114b in the second region 100b.

[0019] In some embodiments, each of the metal substrates 108a and 108b includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. The seed layer may include Cu, Al, etc. For example, both metal substrates 108a and 108b contain Ti and Cu. Metal substrates 108a and 108b are formed simultaneously using the same sputtering or deposition process.

[0020] In some embodiments, each of the metal layers 110a and 110b may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, or combinations thereof. The metal layers 110a and 110b are formed simultaneously using the same electroplating or deposition process. For example, metal layers 110a and 110b are then formed in the first-level openings 114a and 114b, respectively, using metal substrates 108a and 108b as seed crystals.

[0021] Next, excess material beyond the first-level openings 114a and 114b is removed by a planarization process such as chemical mechanical polishing (CMP). In some examples, the remaining metal substrate 108a and the remaining metal layer 110a form a first conductive pattern P1 covering the lower through-hole TV1 in the first region 100a. In some examples, the remaining metal substrate 108b and the remaining metal layer 110b form a first metal layer ML1 on the device 101 in the second region 100b. The top surface of the first conductive pattern P1 is substantially flush with the top surface of the first metal layer ML1.

[0022] Figure 5 illustrates the formation of a second conductive pattern P2 on a first conductive pattern P1 in a first region 100a and the simultaneous formation of a second conductive layer ML2 on a first conductive layer ML1 in a second region 100b. In some embodiments, the method for forming the second conductive pattern P2 and the second conductive layer ML2 is similar to the method for forming the first conductive pattern P1 and the first conductive layer ML1.

[0023] In some embodiments, a dielectric layer DL2 is formed on the dielectric layer DL1 across a first region 100a and a second region 100b. The dielectric layer DL2 includes at least one etch-stop material with different materials and etch selectivity, and at least one dielectric material. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, as shown in the enlarged views of Figures 17A to 17D, the dielectric layer DL2 may include two dielectric materials DM2 and two etch-stop materials EM2 stacked alternately. The dielectric layer DL2 is patterned to form second-level openings in the first region 100a and second region 100b. The second-level openings are formed simultaneously by the same lithography and etching processes. The second-level openings in the first region 100a are holes used to define a portion of an upper through-hole. The second-level opening in zone 100b is a dual-damascene opening, comprising a groove for defining a conductor and a lower aperture for defining a through-hole. The second-level opening is defined by the same photomask. Depending on the process, one or two photomasks may be applied to form the second-level opening.

[0024] Next, metal liner 112a and metal layer 113a are formed in the second-level opening in the first region 100a, and metal liner 112b and metal layer 113b are formed in the second-level opening in the second region 100b.

[0025] In some embodiments, each of the metal substrates 112a and 112b includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. The seed layer may include Cu, Al, etc. For example, both metal substrates 112a and 112b contain Ti and Cu. The metal substrates 112a and 112b are formed simultaneously using the same sputtering or deposition process.

[0026] In some embodiments, each of the metal layers 113a and 113b may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, or combinations thereof. The metal layers 113a and 113b are formed simultaneously using the same electroplating or deposition process. For example, metal layers 113a and 113b are then formed in the second-level openings using metal substrates 112a and 112b as seed crystals.

[0027] Next, excess material outside the second-level opening is removed by a planarization process such as chemical mechanical polishing (CMP). In some examples, the remaining metal substrate 112a and the remaining metal layer 113a form a second conductive pattern P2 on the first conductive pattern P1 in the first region 100a. In some examples, the remaining metal substrate 112b and the remaining metal layer 113b form a second metal layer ML2 on the first metal layer ML1 in the second region 100b.

[0028] Figure 6 illustrates the formation of a third conductive pattern P3 on a second conductive pattern P2 in a first region 100a, and simultaneously the formation of a third conductive layer ML3 on a second conductive layer ML2 in a second region 100b. In some embodiments, the method for forming the third conductive pattern P3 and the third conductive layer ML3 is similar to the method for forming the first conductive pattern P1 and the first conductive layer ML1.

[0029] In some embodiments, a dielectric layer DL3 is formed on the dielectric layer DL2 across a first region 100a and a second region 100b. The dielectric layer DL3 includes at least one etch-stop material with different materials and etch selectivity, and at least one dielectric material. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, as shown in the enlarged views of Figures 17A to 17D, the dielectric layer DL3 may include two dielectric materials DM3 and two etch-stop materials EM3 ​​stacked alternately. The dielectric layer DL3 is patterned to form a third-level opening in the first region 100a and a third-level opening in the second region 100b. The third-level opening is formed simultaneously by the same lithography and etching process. The third-level opening in the first region 100a is a hole used to define a portion of an upper through-hole. The third-level opening in zone 100b is a dual-damascene opening, comprising a groove for defining the conductor and a lower aperture for defining the through-hole. The third-level opening is defined by the same photomask. Depending on the process, one or two photomasks may be used to form the third-level opening.

[0030] Next, metal liner 116a and metal layer 118a are formed in the third-level opening in the first region 100a, and metal liner 116b and metal layer 118b are formed in the third-level opening in the second region 100b.

[0031] In some embodiments, each of the metal substrates 116a and 116b includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. The seed layer may include Cu, Al, etc. For example, both metal substrates 116a and 116b contain Ti and Cu. Metal substrates 116a and 116b are formed simultaneously using the same sputtering or deposition process.

[0032] In some embodiments, each of the metal layers 118a and 118b may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, or combinations thereof. The metal layers 118a and 118b are formed simultaneously using the same electroplating or deposition process. For example, the metal layers 118a and 118b are then formed in the third-level opening using metal substrates 116a and 116b as seed crystals.

[0033] Next, excess material outside the third-level opening is removed by a planarization process such as chemical mechanical polishing (CMP). In some examples, the remaining metal substrate 116a and the remaining metal layer 118a form a third conductive pattern P3 on the second conductive pattern P2 in the first region 100a. In some examples, the remaining metal substrate 116b and the remaining metal layer 118b form a third metal layer ML3 on the second metal layer ML2 in the second region 100b.

[0034] Figure 7 illustrates the formation of a fourth conductive pattern P4 on a third conductive pattern P3 in a first region 100a, and simultaneously the formation of a fourth conductive layer ML4 on a third conductive layer ML3 in a second region 100b. In some embodiments, the method for forming the fourth conductive pattern P4 and the fourth conductive layer ML4 is similar to the method for forming the first conductive pattern P1 and the first conductive layer ML1.

[0035] In some embodiments, a dielectric layer DL4 is formed on the dielectric layer DL3 across a first region 100a and a second region 100b. The dielectric layer DL4 includes at least one etch-stop material and at least one dielectric material with different materials and etch selectivity. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, as shown in the enlarged views of Figures 17A to 17D, the dielectric layer DL4 may include two dielectric materials DM4 and two etch-stop materials EM4 stacked alternately. The dielectric layer DL4 is patterned to form a fourth-level opening in the first region 100a and a fourth-level opening in the second region 100b. The fourth-level opening is formed simultaneously by the same lithography and etching process. The fourth-level opening in the first region 100a is a hole used to define a portion of an upper through-hole. The fourth-level opening in zone 100b is a dual-damascene opening, comprising a groove for defining the conductor and a lower aperture for defining the through-hole. The fourth-level opening is defined by the same photomask. Depending on the process, one or two photomasks may be used to form the fourth-level opening.

[0036] Next, a metal liner 120a and a metal layer 122a are formed in the fourth-level opening in the first region 100a, and a metal liner 120b and a metal layer 122b are formed in the fourth-level opening in the second region 100b.

[0037] In some embodiments, each of the metal substrates 120a and 120b includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. The seed layer may include Cu, Al, etc. For example, both metal substrates 120a and 120b contain Ti and Cu. Metal substrates 120a and 120b are formed simultaneously using the same sputtering or deposition process.

[0038] In some embodiments, each of the metal layers 118a and 118b may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, or combinations thereof. Metal layers 122a and 122b are formed simultaneously using the same electroplating or deposition process. For example, metal layers 122a and 122b are then formed in the fourth-level opening using metal substrates 120a and 120b as seed crystals.

[0039] Next, excess material outside the fourth-level opening is removed by a planarization process such as chemical mechanical polishing (CMP). In some examples, the remaining metal substrate 120a and the remaining metal layer 122a constitute a fourth conductive pattern P4 on the third conductive pattern P3 in the first region 100a. In some examples, the remaining metal substrate 120b and the remaining metal layer 122b constitute a fourth metal layer ML4 on the third metal layer ML3 in the second region 100b.

[0040] In some embodiments disclosed herein, the first conductive pattern P1, the second conductive pattern P2, the third conductive pattern P3, and the fourth conductive pattern P4 constitute the upper through-hole TV2. The upper through-hole TV2 covers and contacts the lower through-hole TV1, and the upper through-hole TV2 and the lower through-hole TV1 are collectively referred to as the substrate through-hole 30.

[0041] Figure 8 illustrates a fifth conductive layer ML5 formed by electrically connecting a fourth conductive pattern P4 in the first region 100a and a fourth conductive layer ML4 in the second region 100b. In some embodiments, the method for forming the fifth conductive layer ML5 is similar to the method for forming the first conductive layer ML1.

[0042] In some embodiments, a dielectric layer DL5 is formed on a dielectric layer DL4 spanning a first region 100a and a second region 100b. The dielectric layer DL5 includes at least one etch-stop material and at least one dielectric material having different materials and etch selectivity. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, as shown in the enlarged views of Figures 17A to 17D, the dielectric layer DL5 may include two dielectric materials DM5 and two etch-stop materials EM5 stacked alternately. The dielectric layer DL5 is patterned to form fifth-level openings in the first region 100a and the second region 100b. The fifth-level openings are formed by lithography and etching processes. Each of the fifth-level openings in the first region 100a and the second region 100b is a dual damascene opening, which includes a trench for defining a conductor and an underpass for defining a via. The fifth-level opening is defined by the same photomask. Depending on the process, one or two photomasks may be used to form the fifth-level opening.

[0043] Next, a metal liner 124 and a metal layer 126 are formed in the fifth-level opening in the first zone 100a and the second zone 100b.

[0044] In some embodiments, the metal substrate 304 includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or a combination thereof. The seed layer may include Cu, Al, etc. For example, the metal substrate 304 comprises Ti and Cu. The metal substrate 304 is formed by a sputtering process or a deposition process.

[0045] The metal layer 126 may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, or combinations thereof. The metal layer 126 is formed by an electroplating process or a deposition process. For example, the metal layer 126 may then be formed in a fifth-level opening using a metal substrate 124 as a seed crystal.

[0046] Next, excess material outside the fifth-level opening is removed by a planarization process such as chemical mechanical polishing (CMP). In some examples, the remaining metal substrate 124 and the remaining metal layer 126 constitute the fifth metal layer ML5 on the fourth conductive pattern P4 in the first region 100a and the fifth metal layer ML5 on the fourth metal layer ML4 in the second region 100b.

[0047] Figure 9 illustrates the formation of a sixth conductive layer ML6 electrically connected to the fifth conductive layer ML5. In some embodiments, the method for forming the sixth conductive layer ML6 is similar to the method for forming the first conductive layer ML1.

[0048] In some embodiments, a dielectric layer DL6 is formed on the dielectric layer DL5 across a first region 100a and a second region 100b. The dielectric layer DL6 includes at least one etch-stop material and at least one dielectric material with different materials and etch selectivity. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, the dielectric layer DL6 may include two dielectric materials and two etch-stop materials stacked alternately. The dielectric layer DL6 is patterned to form a sixth-level opening in the second region 100b. The sixth-level opening is formed by a lithography and etching process. Each of the sixth-level openings is a dual-damascene opening, including a trench for defining a conductor and an underpass for defining a via. The sixth-level opening is defined by the same photomask. Depending on the process, one or two photomasks may be applied to form the sixth-level opening.

[0049] Next, a metal liner and a metal layer are formed in the sixth-level opening. The materials and formation methods of the metal liner and the metal layer are similar to those of metal liner 124 and metal layer 126, and will not be described again here. Metal liner 124 and metal layer 126 form a sixth metal layer ML6 on the fifth metal layer ML5. In some embodiments, the sixth metal layer ML6 is formed in the second region 100b, but this disclosure is not limited thereto. In other embodiments, the sixth metal layer ML6 is formed across the first region 100a and the second region 100b.

[0050] Figure 10 illustrates at least one metal pad MP1 electrically connected to the sixth conductive layer ML6. In some embodiments, the metal pad MP1 is embedded in the passivation layer PA1. In some embodiments, the metal pad MP1 is an aluminum pad. The aluminum pad is a test pad and may have probe markings on it. In other embodiments, the metal pad MP1 is a copper pad. The passivation layer PA1 may comprise a polymeric material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or combinations thereof. This completes the first grain 10 of the first embodiment of this disclosure. The lower through-hole TV1 is not currently exposed.

[0051] Figure 11 shows the thinning of substrate 100 until the surface of the lower through-hole TV1 is exposed. In some embodiments, the first grain 10 of Figure 10 is flipped, and a carrier C is attached to the passivation layer PA1, with an adhesive layer AL located therebetween. The carrier C is a sacrificial carrier and will be removed later. The carrier C may include a silicon carrier or a glass carrier. The adhesive layer AL may include ultraviolet (UV) adhesive, photothermal conversion (LTHC) adhesive, etc., but other types of adhesives may also be used.

[0052] Next, a dielectric layer 302 is formed to encapsulate and cover the first die 10. The dielectric layer 303 may contain silicon oxide, etc. Then, a thinning process is performed on the second side S2 to reduce the thickness of the substrate 100. For example, the thinned substrate 100 ranges from approximately 10 μm to 20 μm. The thinning process includes a grinding process or a polishing process. The thinning process removes a portion of the substrate 100, a portion of the insulating liner 103, and a portion of the metal liner 104, so that the surface of the remaining metal layer 106 of the lower through-hole TV1 is coplanar with the surface of the second side S2 of the substrate 100. The thinning process also removes a portion of the dielectric layer 302, so that the remaining dielectric layer 302 is coplanar with the back side of the substrate 100.

[0053] Figure 12 illustrates a bonding structure BS1 formed on a lower through-hole TV1. In some embodiments, the bonding structure BS1 includes one or more bonding metal features BM1 embedded in a bonding dielectric layer BF1. The bonding metal features BM1 include bonding pads. The bonding metal features BM1 include Cu, Al, Co, Cr, W, Ti, Ta, TiN, TaN, and combinations thereof. The bonding dielectric layer BF1 includes silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the bonding structure BS1 is considered part of the first grain 10 of this disclosure. In some embodiments, the bonding structure BS1 extends beyond the sidewalls of the first grain 10, as shown in Figure 12. However, this disclosure is not limited thereto. In other embodiments, the sidewalls of the bonding structure BS1 are substantially flush with the sidewalls of the first grain 10.

[0054] Figures 13 and 14 illustrate providing a second grain 20 and bonding the second grain 20 to a first grain 10. In some embodiments, the second grain 20 may include a substrate 200 on the active side (e.g., the front side) of a substrate 200, a device 201, an interconnect structure IS2 on the active side of the substrate 200, a metal pad MP2 on the interconnect structure IS2, and a bonding structure BS2 on the metal pad MP2.

[0055] In some embodiments, substrate 200 may be a semiconductor substrate, such as a silicon substrate. In other embodiments, substrate 200 includes elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Substrate 200 is on the order of hundreds of micrometers.

[0056] In some embodiments, device 201 may include active and / or passive devices. For example, device 201 may include transistors, diodes, capacitors, resistors, etc., formed by any suitable forming method.

[0057] In some embodiments, the interconnect structure IS2 includes metal features embedded in the dielectric layer. The metal features include metal wires and metal vias electrically connected to each other. Each metal feature includes a metal liner material and a metal material. In some embodiments, the metal liner material includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. The seed layer may include Cu, Al, etc. For example, the metal liner material includes Ti and Cu. In some embodiments, the metal material may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, etc., or combinations thereof. The dielectric layer includes a dielectric material and an etch-stop material between adjacent dielectric materials. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon carbide, or a low-k material with a dielectric constant less than 3.5 or 2.5.

[0058] In some embodiments, the metal pad MP2 is embedded in the passivation layer PA2. In some embodiments, the metal pad MP2 is an aluminum pad. The aluminum pad is a test pad and may have probe markings on it. In other embodiments, the metal pad MP2 is a copper pad. The passivation layer PA2 may include polymeric materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or combinations thereof.

[0059] In some embodiments, the bonding structure BS2 includes one or more bonding metal features BM2 embedded in the bonding dielectric layer BF2. The bonding metal features BM2 include bonding pads, bonding vias, or combinations thereof. The bonding metal features BM2 include Cu, Al, Co, Cr, W, Ti, Ta, TiN, TaN, etc., or combinations thereof. The bonding dielectric layer BF2 includes silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the bonding structure BS2 is considered part of the second grain 20 of this disclosure. In some embodiments, the sidewalls of the bonding structure BS2 are substantially flush with the sidewalls of the second grain 20. However, this disclosure is not limited thereto. In other embodiments, the bonding structure BS2 extends beyond the sidewalls of the second grain 20.

[0060] Referring to FIG. 14, the second grain 20 is bonded to the first grain 10 by a hybrid bonding comprising metal-to-metal bonding and dielectric-to-dielectric bonding. For example, bonding metal feature BM2 is bonded to bonding metal feature BM1, and bonding dielectric layer BF2 is bonded to bonding dielectric layer BF1. In some embodiments, the width of bonding metal feature BM2 is substantially the same as the width of bonding metal feature BM1, but this disclosure is not limited thereto. In other embodiments, the width of bonding metal feature BM2 is different from (e.g., greater than or less than) the width of bonding metal feature BM1. In some embodiments, the material of bonding dielectric layer BF2 (e.g., silicon oxynitride) is different from the material of bonding dielectric layer BF1 (e.g., silicon oxide), but this disclosure is not limited thereto. In other embodiments, the material of bonding dielectric layer BF2 is the same as the material of bonding dielectric layer BF1.

[0061] Subsequently, a dielectric layer 303 is formed to encapsulate and cover the second die 20. The dielectric layer 303 may comprise silicon oxide or the like. In some embodiments, a thinning process is performed on the substrate 200 or the second die 20 to reduce the thickness of the substrate 200. For example, the thinned substrate 200 is approximately 10 μm to 20 μm thick. The thinning process also removes a portion of the dielectric layer 303, so the remaining dielectric layer 303 is coplanar with the back surface of the substrate 200.

[0062] Figure 15 illustrates the attachment of the support substrate 300 to the second die 20. In some embodiments, the support substrate 300 includes a silicon support or a suitable support. In some embodiments, the support substrate 300 has a thickness of about 500 μm to about 1000 μm, for example, about 600 μm to about 800 μm. The thicker support substrate 300 disclosed herein is beneficial for heat dissipation and package rigidity. In some examples, the support substrate 300 is referred to as a "heat dissipation carrier".

[0063] In some embodiments, the support substrate 300 is attached to the second grain 20 via a buffer layer 301. In some embodiments, the buffer layer 301 may comprise a dielectric material, such as SiO2, SiN, SiON, SiC, SiCN, SiCO, or combinations thereof. In some embodiments, the buffer layer 301 may be made of a thermally conductive and electrically insulating heat sink material. The thermal conductivity k of the heat sink material should be between about 10 and 500 W / m / K (e.g., between about 20 and 450 W / m / K or between about 50 and 400 W / m / K) to absorb heat dissipation. For example, the heat sink material may comprise AlN, GaN, ZnO, BN, Al2O3, HfO2, TiO2, or combinations thereof. In some embodiments, the buffer layer 301 has a thickness of about 0.01 μm to about 2.5 μm. The buffer layer 301 disclosed herein may have a single-layer or multi-layer structure.

[0064] Next, the structure of FIG15 is flipped over and the carrier C is removed from the first die 10. In some embodiments, the adhesive layer AL is further removed to expose the passivation layer PA1 of the first die 10. In some embodiments, the removal process includes an etching process or a suitable process.

[0065] Figure 16 illustrates the formation of bumps 132 electrically connected to the first die 10. In some embodiments, under-bump metallization (UBM) pads 130 are formed through the passivation layer PA1 and bonded to metal pads MP1. In some embodiments, the UBM pads 130 are part of a redistribution layer structure (RDL) disposed between bumps 132 and metal pads MP2. The redistribution layer structure may include metal features embedded by dielectric layers and electrically connected to each other. The metal features include metal lines and metal vias electrically connected to each other. Each metal feature includes a metal liner material and a metal material. In some embodiments, the metal liner material includes a barrier layer and a seed layer. The barrier layer may include Ta, TaN, Ti, TiN, CoW, or combinations thereof. The seed layer may include Cu, Al, etc. For example, the metal liner material includes Ti and Cu. In some embodiments, the metal material may include Cu, Al, Ti, Ta, W, Ru, Co, Ni, etc., or combinations thereof. The dielectric layer includes a dielectric material and an etch stop material between adjacent dielectric materials. The etch-stop material may include aluminum nitride, aluminum oxide, aluminum oxynitride, silicon nitride, silicon carbide, or combinations thereof. The dielectric material may include silicon oxide, silicon oxynitride, silicon oxycarbide, or a low-k material with a dielectric constant less than 3.5 or 2.5. In some embodiments, the redistribution layer structure is considered part of the first grain 10. In some embodiments, the critical size of the redistribution layer structure is greater than the critical size of the interconnect structure IS1.

[0066] Next, conductive terminals or bumps 132 are formed over and electrically connected to the UBM pad 130 of the redistribution layer structure. In some embodiments, the bumps 132 may be solder bumps, and / or may include metal pillars (e.g., copper pillars), solder caps formed on metal pillars, etc. The bumps 132 may be formed by appropriate processes, such as evaporation, electroplating, drop balling, or screen printing. This completes the semiconductor structure 1 of some embodiments.

[0067] The related substrate vias in the relevant semiconductor structure are formed by defining a single deep opening using dry etching and wet stripping, followed by a single electroplating process. Related substrate vias require a guard ring to prevent moisture damage during the prolonged wet stripping process in the deep opening definition step. However, the substrate vias disclosed herein do not have a guard ring because they are formed by multiple stacked conductive patterns, rather than a single conductive via. The wet stripping process is short and has minimal moisture impact, thus eliminating the need for a guard ring. Since the substrate vias disclosed herein are TSV structures without a guard ring, the keep-out zone (KOZ) is relatively small.

[0068] Figure 17A shows a top view and a cross-sectional view of a portion A of the semiconductor structure in Figure 16 according to some embodiments of the present disclosure. Figures 17B to 17D show different cross-sectional views of portions of the semiconductor structure in Figure 16 according to other embodiments of the present disclosure.

[0069] As shown in Figure 17A, the forbidden zone (KOZ) D1 from the sidewall of the lower through-hole TV1 to the sidewall of the interconnect structure IS1 is less than about 1.5 μm. In some embodiments, the substrate vias 30 have a stepped profile at the silicon substrate interface. For example, the distance D2 from the sidewall of the lower through-hole TV1 to the sidewall of the upper through-hole TV2 is greater than zero, for example, about 0.1 μm or more, or about 0.5 μm or more. In some embodiments, the barrier thickness D3 of the upper through-hole TV2 is greater than zero, for example, about 0.02 μm or more. In some embodiments, the barrier thickness D3 of the upper through-hole TV2 is 0.5 μm or less. In some embodiments, the lower through-hole TV1 has a depth D4 and a width D5, and the aspect ratio of D4 / D5 is less than about 12, less than about 5, or less than about 1. In some embodiments, when the first grain 10 includes a plurality of substrate vias 30, the spacing D6 of the substrate vias 30 is about 3 μm or less.

[0070] In some embodiments, the upper through-hole TV2 has smooth sidewalls, wherein the sidewalls of adjacent conductive patterns are substantially flush with each other, as shown in FIG17A. However, this disclosure is not limited thereto. In other embodiments, the upper through-hole TV2 may have stepped or non-smooth sidewalls, wherein the sidewalls of adjacent conductive patterns are not flush with each other, as shown in FIGS17B and 17C. Specifically, at least one conductive pattern in the upper through-hole TV2 may protrude or recess relative to adjacent conductive patterns, thus the sidewalls of the upper through-hole TV2 have one or more turning points.

[0071] In some embodiments, the central axis of the lowest conductive pattern P1 of the upper through-hole TV2 is substantially aligned with the central axis of the lower through-hole TV1, as shown in FIG17A. However, this disclosure is not limited thereto. In other embodiments, the central axis of the lowest conductive pattern P1 of the upper through-hole TV2 is offset (e.g., displaced) from the central axis of the lower through-hole TV1, so that the distances D2 from the opposite sidewalls of the lower through-hole TV1 to the corresponding sidewalls of the lower through-hole TV1 are different from each other.

[0072] In some embodiments, each conductive pattern in the upper through-hole TV2 has substantially straight sidewalls, as shown in Figures 17A to 17C. However, this disclosure is not limited thereto. In other embodiments, each conductive pattern in the upper through-hole TV2 has stepped sidewalls, as shown in Figure 17D. In some embodiments, each conductive pattern in the upper through-hole TV2 has a double damascene structure or a T-shaped structure.

[0073] As shown in Figure 16, N conductive patterns (where N=4) of the upper through-hole TV2 are formed simultaneously with N conductive layers (where N=4) of the interconnect structure IS1. The Nth conductive pattern (e.g., P4) and the Nth conductive layer (e.g., ML4) are electrically connected to the (N+1)th conductive layer (e.g., ML5) of the interconnect structure IS1. However, this disclosure does not limit the number N of conductive patterns or conductive layers. Depending on the process requirements, the number N in conductive patterns or conductive layers can be less than 4 or greater than 4. Figures 18 to 20 show the cases where N=1, N=2, and N=3, as shown in semiconductor structures 2, 3, and 4, respectively. Furthermore, the different sidewall profiles (e.g., smooth or stepped sidewalls) shown in Figures 17A to 17D are applicable to the upper through-hole TV2 of semiconductor structures 2, 3, and 4.

[0074] Figure 21 illustrates a method for forming a semiconductor structure according to some embodiments. Although the method is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not shown may be included.

[0075] In action 402, a substrate having a first region and a second region is provided. Figure 1 shows a cross-sectional view corresponding to some embodiments of action 402.

[0076] In action 404, a through hole is formed in the substrate in the first region. Figures 1 and 2 show cross-sectional views corresponding to some embodiments of action 404.

[0077] In action 406, a first conductive pattern covering the through-hole is formed in the first region, and simultaneously a first conductive layer is formed on the substrate in the second region. Figures 3 and 4 show cross-sectional views corresponding to some embodiments of action 406. In some embodiments, the width of the first conductive pattern is greater than the width of the through-hole.

[0078] In action 408, a second conductive pattern is formed on the first conductive pattern in the first region, and simultaneously a second conductive layer is formed on the first conductive layer in the second region. Therefore, at least two conductive patterns are stacked on the through-hole in the first region. Figures 5 to 7 show cross-sectional views corresponding to some embodiments of action 408. In some embodiments, the sidewalls of the second conductive pattern are aligned with the sidewalls of the first conductive pattern. In other embodiments, the sidewalls of the second conductive pattern are offset from the sidewalls of the first conductive pattern.

[0079] In some embodiments, a third conductive pattern is selectively formed between a first conductive pattern and a second conductive pattern in the first region, and simultaneously a third conductive layer is formed between the first conductive pattern and the second conductive layer in the second region (action 407). Accordingly, at least three conductive patterns are stacked on the through-hole in the first region, as shown in Figures 6 and 7. In some embodiments, the sidewall of the third conductive pattern is aligned with the sidewall of the first conductive pattern or the second conductive pattern. In other embodiments, the sidewall of the third conductive pattern is offset from the sidewall of the first conductive pattern or the second conductive pattern.

[0080] In action 410, a top conductive layer is formed across the first and second regions above the second conductive pattern and the second conductive layer. Figure 8 shows a cross-sectional view corresponding to some embodiments of action 410.

[0081] Figure 22 illustrates a method for forming a semiconductor structure according to some embodiments. Although the method is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not shown may be included.

[0082] In action 500, a first die is provided. In some embodiments, action 500 includes actions 502 to 510.

[0083] In action 502, a substrate having a first region and a second region is provided. Figure 1 shows a cross-sectional view corresponding to some embodiments of action 502.

[0084] In action 504, a lower through-hole is formed in the first region, extending from a first side of the substrate to a second side. Figures 1 and 2 show cross-sectional views corresponding to some embodiments of action 504.

[0085] In action 506, an upper through-hole is formed on the substrate in the first region, and the upper through-hole contacts a lower through-hole, wherein the width of the upper through-hole is greater than the width of the lower through-hole at the surface of the substrate. Figures 3 to 10 show cross-sectional views corresponding to some embodiments of action 506. In some embodiments, forming the upper through-hole includes forming a plurality of conductive patterns stacked on top of each other. In some embodiments, during the formation of the upper through-hole in the first region, an interconnect structure is further formed and simultaneously formed on the substrate in the second region. In some embodiments, the upper through-hole and the interconnect structure are defined by the same photomask.

[0086] In action 508, the substrate is thinned to expose the underlying through-hole. Figure 11 shows a cross-sectional view corresponding to some embodiments of action 508.

[0087] In action 510, a first joining structure is formed above the lower through hole on the second side of the substrate. Figure 12 shows a cross-sectional view corresponding to some embodiments of action 510.

[0088] In action 512, a second grain including a second bonding structure is provided. Figure 13 shows a cross-sectional view corresponding to some embodiments of action 512.

[0089] In action 514, the second grain is bonded to the first grain via the second bonding structure and the first bonding structure. Figure 14 shows a cross-sectional view corresponding to some embodiments of action 514.

[0090] In action 516, the support carrier is attached to the second grain. Figures 15 and 16 show cross-sectional views corresponding to some embodiments of action 516.

[0091] The semiconductor structure disclosed herein is described below with reference to Figures 16 to 20. In some embodiments, the semiconductor structure 1 / 2 / 3 / 4 includes a substrate 100, a through-hole TV1, and a first conductive pattern P1. The substrate 100 has a first region 100a and a second region 100b. The through-hole TV1 is disposed in the substrate 100 in the first region 100a. The first conductive pattern P1 is disposed on the substrate 100 and lands on (e.g., contacts) the through-hole TV1 in the first region 100a. In some embodiments, the width of the first conductive pattern P1 is greater than the width of the through-hole TV1.

[0092] In some embodiments, the semiconductor structure 1 / 2 / 3 / 4 further includes a first conductive layer ML1 disposed on a substrate 100 in the second region 100b, and the top surface of the first conductive pattern P1 is coplanar with the top surface of the first conductive layer ML1. Specifically, the first conductive pattern P1 and the first conductive layer ML1 are disposed on approximately the same horizontal plane.

[0093] In some embodiments, the semiconductor structure 1 / 3 / 4 further includes a second conductive pattern P2 located on a first conductive pattern P1 in the first region 100a and a second conductive layer ML2 disposed on a first conductive layer ML1 in the second region 100b, wherein the top surface of the second conductive pattern P2 is coplanar with the top surface of the second conductive layer ML2 in the second region 100b. Specifically, the second conductive pattern P2 and the second conductive layer ML2 are disposed on substantially the same horizontal plane.

[0094] In some embodiments, the sidewalls of the first conductive pattern P1 are flush with the sidewalls of the second conductive pattern P2. In other embodiments, the sidewalls of the first conductive pattern P1 are offset from the sidewalls of the second conductive pattern P2.

[0095] In some embodiments, the semiconductor structure 1 / 4 further includes a third conductive pattern P3 landed on the second conductive pattern P2 in the first region 100a and a third conductive layer ML3 disposed on the second conductive layer ML2 in the second region 100b, wherein the top surface of the third conductive pattern P3 and the top surface of the third conductive layer ML3 are coplanar. Specifically, the third conductive pattern P3 and the third conductive layer ML3 are disposed on substantially the same horizontal plane.

[0096] In some embodiments, the sidewalls of the third conductive pattern P3 are flush with the sidewalls of the second conductive pattern P2. In other embodiments, the sidewalls of the third conductive pattern P3 are offset from the sidewalls of the second conductive pattern P2.

[0097] In summary, the substrate vias disclosed in this invention are defined by forming multiple shallow openings and alternating multiple electroplating processes. The wet stripping process is short and has minimal moisture impact, thus eliminating the need for a protective ring. Accordingly, the substrate vias disclosed in this invention increase the forbidden area and provide design flexibility. Furthermore, in this disclosure, multiple shallow conductive patterns of the substrate vias and multiple adjacent conductive layers of the interconnect structure can be simultaneously defined using the same multiple photomasks. The method disclosed in this invention is compatible with existing processes and does not increase process steps or costs.

[0098] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided. A substrate has a first region and a second region. A through-hole is formed in the substrate in the first region. A first conductive pattern covering the through-hole is formed in the first region, and simultaneously a first conductive layer is formed on the substrate in the second region. A second conductive pattern is formed on the first conductive pattern in the first region, and simultaneously a second conductive layer is formed on the first conductive layer in the second region.

[0099] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided. A first die is provided and formed by the following operations: A substrate has a first region and a second region. A lower through-hole is formed in the first region, extending from a first side of the substrate to a second side. An upper through-hole is formed on the substrate in the first region, and the upper through-hole contacts the lower through-hole, wherein at the substrate surface, the width of the upper through-hole is greater than the width of the lower through-hole. The substrate is thinned to expose the lower through-hole.

[0100] According to one aspect of this disclosure, a semiconductor structure includes a substrate, a via, and a first conductive pattern. The substrate has a first region and a second region. The via is formed in the substrate in the first region. The first conductive pattern is formed on the substrate and lands on the via in the first region, wherein the width of the first conductive pattern is greater than the width of the via.

[0101] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0102] 1, 2, 3, 4: Semiconductor Structure 10: First grain 20: Second grain 30: Base perforation 100, 200: Base 100a: Zone 1 100b: Second Zone 101, 201: Device 102: Opening 103: Insulating Liner 104, 108a, 108b, 112a, 112b, 116a, 116b, 120a, 120b, 124, 304: Metallic backing 106, 110a, 110b, 113a, 113b, 118a, 118b, 122a, 122b, 126: Metal layers 114a, 114b: First-level openings 130: UBM mat 132: Bump 300: Supporting base 301: Buffer layer 302, 303, DL1, DL2, DL3, DL4, DL5, DL6: Dielectric layers 402, 404, 406, 407, 408, 410, 500, 502, 504, 506, 508, 510, 512, 514, 516: Actions AL: Adhesive layer BF1, BF2: Bonding dielectric layers BM1, BM2: Features of the bonding metal BS1, BS2: Joint structure C: Carrier D1: Restricted Area D2: Distance D3: Barrier Thickness D6: Spacing DM1, DM2, DM3, DM4, DM5: Dielectric materials EM1, EM2, EM3, EM4, EM5: Etching Stop Materials HM: Covering Layer IS1, IS2: Internal Wiring Structure ML1: First conductive layer / first metal layer ML2: Second conductive layer / second metal layer ML3: Third conductive layer / Third metal layer ML4: Fourth conductive layer / fourth metal layer ML5: Fifth conductive layer / fifth metal layer ML6: Sixth conductive layer / sixth metal layer MP1, MP2: Metal pads P1: First conductive pattern P2: Second conductive pattern P3: Third conductive pattern P4: Fourth conductive pattern PA1, PA2: Passivation layers TV1, TV2: Through holes S1: First side S2: Second side

Claims

1. A method for forming a semiconductor structure, comprising: Provide a base with a first zone and a second zone; A through-hole is formed in the substrate in the first region; A first conductive pattern covering the through hole is formed in the first region, and a first conductive layer is formed on the substrate in the second region; and a second conductive pattern is formed on the first conductive pattern in the first region, and a second conductive layer is formed on the first conductive layer in the second region.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the width of the first conductive pattern is greater than the width of the through-hole.

3. The method of forming a semiconductor structure as claimed in claim 1, wherein the sidewalls of the second conductive pattern are aligned with the sidewalls of the first conductive pattern.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein the sidewalls of the second conductive pattern are offset from the sidewalls of the first conductive pattern.

5. A method for forming a semiconductor structure, comprising: Providing a first grain, wherein the method of forming the first grain includes: providing a substrate having a first region and a second region; forming a lower through-hole extending from a first side of the substrate to a second side in the first region; forming an upper through-hole on the substrate in the first region, wherein the upper through-hole contacts the lower through-hole, wherein at a surface of the substrate, the width of the upper through-hole is greater than the width of the lower through-hole; and thinning the substrate to expose the lower through-hole.

6. A method of forming a semiconductor structure as claimed in claim 5, wherein forming the upper through-hole includes forming a plurality of conductive patterns stacked on top of each other.

7. The method of forming a semiconductor structure as claimed in claim 5 further includes forming an interconnect structure on the substrate in the second region during the formation of the upper through-hole in the first region.

8. A method for forming a semiconductor structure as claimed in claim 7, wherein the upper through-hole and the interconnect structure are defined by a plurality of identical photomasks.

9. A semiconductor structure, comprising: A base having a first region and a second region; A through hole is provided in the substrate in the first region; A first conductive pattern is disposed on the substrate and the through hole in the first region, wherein the width of the first conductive pattern is greater than the width of the through hole. A first conductive layer is disposed on the substrate in the second region. The second conductive pattern is on the first conductive pattern in the first region; And a second conductive layer on the first conductive layer in the second region.

10. The semiconductor structure of claim 9, wherein the top surface of the first conductive pattern is substantially coplanar with the top surface of the first conductive layer.

Images