Manufacturing method of memory device

Abstract

A method for manufacturing a memory device includes: forming a rigid mask layer over a substrate, wherein the rigid mask layer is made of an oxide-based material and has a first width; forming a trench in the substrate through the rigid mask layer; performing a first cleaning process on the substrate, wherein the first width of the rigid mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer to line the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; forming a capping layer in the trench and above the second word line layer; removing the rigid mask layer; and forming a gate contact layer above the capping layer.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a memory device. Prior Technology

[0002] A typical dynamic random access memory (DRAM) cell includes capacitors and transistors, where capacitors temporarily store data based on their charged state. Bit lines are electrically connected to the source / drain regions of the transistor, and word lines are electrically connected to the gate region of the transistor. As technology scales, the manufacturing process for forming memory cells faces increasing challenges. For example, as trenches become narrower, it becomes more difficult to fill the trenches with material. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method for manufacturing a memory device, including: forming a rigid mask layer over a substrate, wherein the rigid mask layer is made of an oxide-based material and has a first width; forming a trench in the substrate through the rigid mask layer; performing a first cleaning process on the substrate, wherein the first width of the rigid mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer thereby lining the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; forming a top cover layer in the trench and above the second word line layer; removing the rigid mask layer; and forming a gate contact layer above the top cover layer.

[0004] In some embodiments, the manufacturing method further includes forming a second dielectric layer over a substrate prior to forming a rigid mask layer, wherein the second dielectric layer has a third width prior to the first cleaning process, and the third width of the second dielectric layer is reduced to a fourth width after the first cleaning process is completed.

[0005] In some embodiments, both the rigid mask layer and the second dielectric layer are made of oxide-based materials.

[0006] In some embodiments, the rigid mask layer and the second dielectric layer are made of the same material.

[0007] In some embodiments, the corners of the rigid mask layer become more rounded after the first cleaning process is completed.

[0008] In some embodiments, the manufacturing method further includes performing a second cleaning process after forming the first character line layer, such that the second width of the rigid mask layer is reduced to a third width after the second cleaning process is completed.

[0009] In some embodiments, the manufacturing method further includes forming a third dielectric layer after performing a second cleaning process to line the trench and cover the first character line layer, wherein the third dielectric layer contacts the sidewalls and bottom surface of the second character line layer.

[0010] In some embodiments, a portion of the first dielectric layer is exposed by the first word line layer, and a second cleaning process is performed to remove that portion of the first dielectric layer.

[0011] In some embodiments, the manufacturing method further includes performing a thermal process on the substrate after performing a first cleaning process to form a thermal oxide layer, thereby lining the trench, wherein a portion of the oxide layer is exposed after a second cleaning process is completed.

[0012] In some embodiments, the manufacturing method further includes performing a third cleaning process after forming the second character line layer, such that the third width of the hard mask layer is reduced to a fourth width after the third cleaning process is completed.

[0013] Some embodiments of this disclosure provide a method for manufacturing a memory device, including: forming a rigid mask layer over a substrate, wherein the rigid mask layer is made of an oxide-based material and has a first height; forming a trench in the substrate through the rigid mask layer; performing a first cleaning process on the substrate, wherein the first height of the rigid mask layer is reduced to a second height after the first cleaning process is completed; forming a first dielectric layer thereby lining the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; forming a top cover layer in the trench and above the second word line layer; and forming a gate contact layer above the top cover layer.

[0014] In some embodiments, the manufacturing method further includes performing a second cleaning process after forming the first character line layer, such that the second height of the rigid mask layer is reduced to a third height after the second cleaning process is completed.

[0015] In some embodiments, forming the first character line layer includes forming a conductive layer to overfill the trench and etching back the conductive layer until one of the top surfaces of the conductive layer is below the top surface of the substrate, wherein a portion of the first dielectric layer is exposed after etching back the conductive layer.

[0016] In some embodiments, this portion of the first dielectric layer is removed after the second cleaning process is completed.

[0017] In some embodiments, the corners of the rigid mask layer become more rounded after the second cleaning process is completed.

[0018] In some embodiments, the manufacturing method further includes forming a second dielectric layer after performing a second cleaning process, thereby lining the trench and covering the top surface of the first character line layer.

[0019] In some embodiments, forming the second character line layer includes forming a conductive layer to overfill the trench and etching back the conductive layer until the top surface of the conductive layer is below the top surface of the substrate, wherein a portion of the second dielectric layer is exposed after etching back the conductive layer.

[0020] In some embodiments, the manufacturing method further includes performing a third cleaning process after forming the second character line layer, such that the third height of the rigid mask layer is reduced to a fourth height after the third cleaning process is completed.

[0021] In some embodiments, this portion of the second dielectric layer is removed after the third cleaning process is completed.

[0022] In some embodiments, the corners of the rigid mask layer become more rounded after the third cleaning process is completed.

[0023] It should be understood that the foregoing general description and the following detailed description are for illustrative purposes and are intended to provide further explanation of this disclosure as claimed. Simple Explanation of the Diagram

[0024] This disclosure will be more fully understood by referring to the following detailed description of the embodiments, which is accompanied by the accompanying drawings: Figures 1 through 12 illustrate cross-sectional views of memory structures formed in some embodiments disclosed herein. Figure 13 illustrates a circuit diagram of a memory device in some embodiments disclosed herein. Implementation

[0025] Some embodiments disclosed herein relate to methods for forming memory structures. Specifically, the character line layers in the memory layers of this disclosure are formed with fewer pores to achieve better performance of the memory structure.

[0026] Figures 1 through 12 illustrate cross-sectional views of memory structures formed in some embodiments disclosed herein. Referring to Figure 1, a substrate 100 is provided, and an isolation structure 105 is formed in the substrate 100 to define an active region AA in the substrate 100. The active region AA is a protruding portion of the substrate 100. The active region AA and the substrate 100 excluding the active region AA may have different conductivity types. In some embodiments, if the active region AA is an n-type region, then the substrate 100 excluding the active region AA is a p-type region. If the active region AA is a p-type region, then the substrate 100 excluding the active region AA is an n-type region. In some embodiments, the substrate 100 is made of a semiconductor such as silicon. In some embodiments, the isolation structure 105 is made of silicon oxide, silicon nitride, or the like.

[0027] Subsequently, dielectric layer 112 and rigid masking layer 114 are formed over substrate 100 and isolation structure 105. Dielectric layer 112 and rigid masking layer 114 expose a portion of substrate 100 and isolation structure 105. Dielectric layer 112 and rigid masking layer 114 may be made of oxide-based materials. Dielectric layer 112 and rigid masking layer 114 may be made of the same material such as silicon oxide. Rigid masking layer 114 has a height H1 and a width W1. Dielectric layer 112 has a width W2. In some embodiments, the composite of dielectric layer 112 and rigid masking layer 114 may be different. For example, the oxygen content of dielectric layer 112 and rigid masking layer 114 may be different.

[0028] Referring to Figure 2, a trench T is formed in the substrate 100 and the isolation structure 105 through the dielectric layer 112 and the rigid masking layer 114. The trench T can be formed by performing an etching process to etch the substrate 100 and the isolation structure 105 through the dielectric layer 112 and the rigid masking layer 114. In some embodiments, the trench T can be formed by performing a dry etching process.

[0029] Referring to Figure 3, a first cleaning process is performed on substrate 100 to remove byproducts formed in previous stages. For example, the byproducts may be native oxide formed on the exposed surface of substrate 100. Since dielectric layer 112 and hard masking layer 114 are also made of oxide, the first cleaning process also partially etches dielectric layer 112 and hard masking layer 114. For example, the width W1 of hard masking layer 114 is reduced to width W3 after the first cleaning process. The height H1 of hard masking layer 114 is reduced to height H2 after the first cleaning process. The corners of hard masking layer 114 become more rounded after the first cleaning process. The width W2 of dielectric layer 112 is reduced to width W4 after the first cleaning process. In some embodiments, the first cleaning process is performed by using a mixture of ammonia and hydrogen peroxide (APM), a mixture of sulfuric acid and hydrogen peroxide (SPM), or other suitable solutions as etchants.

[0030] Referring to Figure 4, a thermal process is performed on substrate 100 to conformally form a thermal oxide layer 120 on the exposed surface of substrate 100. Subsequently, a dielectric layer 122 is formed lining trench T and over rigid masking layer 114. Since the first cleaning process is performed in Figure 3, the thermal oxide layer 120 conformally formed on substrate 100 is smooth and has fewer defects. After forming thermal oxide layer 120 and dielectric layer 122, conductive layer 132 is formed to overfill trench T. In some embodiments, thermal oxide layer 120 may be a silicon oxide layer. Dielectric layer 122 may be made of silicon oxide, silicon nitride, or the like. Conductive layer 132 is made of titanium nitride. Since the height and width of rigid masking layer 114 are reduced after the first cleaning process, the aspect ratio of trench T can also be reduced after the first cleaning process. Therefore, it is easier to form a conductive layer 132 with fewer pores in the trench T.

[0031] Referring to Figure 5, the conductive layer 132 is etched back until the top surface of the conductive layer 132 is lower than the top surface of the substrate 100, so that the character line layer 130 is formed in the trench T. A portion of the dielectric layer 122 is exposed after the conductive layer 132 is etched back. Since the conductive layer 132 with fewer pores has been formed in the previous stage, the resulting character line layer 130 also has fewer pores, even when the hard masking layer 114 is made of silicon oxide.

[0032] Referring to Figure 6, a second cleaning process is performed to remove byproducts formed in previous stages, such as the process of forming character line layer 130. These byproducts may be etch residues or native oxide on character line layer 130. The second cleaning process also partially etches dielectric layer 112 and hard mask layer 114. For example, the width W3 of hard mask layer 114 is reduced to width W5 after the second cleaning process. The height H2 of hard mask layer 114 is reduced to height H3 after the second cleaning process. The corners of hard mask layer 114 become more rounded after the second cleaning process. The width W4 of dielectric layer 112 is reduced to width W6 after the second cleaning process. A portion of dielectric layer 122 exposed by character line layer 130 is also partially removed after the second cleaning process. In some embodiments, a portion of dielectric layer 122 is removed, exposing thermal oxide layer 120 after the second cleaning process. In some embodiments, the second cleaning process is performed by using diluted hydrofluoric acid (DHF) or other suitable solutions as etchants.

[0033] Referring to Figure 7, a dielectric layer 124 is formed to line the trench T and cover the top surface of the word line layer 130. The dielectric layer 124 may be made of silicon oxide, silicon nitride, or the like. Subsequently, a conductive layer 142 is formed overfilling the trench T and above the word line layer 130. In some embodiments, the conductive layer 142 is made of polycrystalline silicon. Since the height of the hard mask layer 114 and the width of the top surface of the hard mask layer 114 decrease after the second cleaning process, the aspect ratio of the trench T can also be reduced after the second cleaning process. Therefore, it is easier to form a conductive layer 142 with fewer pores in the trench T.

[0034] Referring to Figure 8, the conductive layer 142 is etched back until its top surface is lower than the top surface of the substrate 100, so that the character line layer 140 is formed in the trench T above each character line layer 130. A portion of the dielectric layer 124 is exposed after the conductive layer 142 is etched back. The character line layers 130 and 140 are separated from the dielectric layer 124, and the dielectric layer 124 contacts the sidewalls and bottom surface of the character line layer 140. Because the conductive layer 142 with fewer pores has been formed in the previous stage, the resulting character line layer 140 also has fewer pores, even when the hard masking layer 114 is made of silicon oxide. Each character line layer 130 and its overlying character line layer 140 can be collectively referred to as the character line structure WL.

[0035] Referring to Figure 9, a third cleaning process is performed to remove byproducts formed in previous stages, such as the process of forming character line layer 140. These byproducts may be etch residues or native oxide on character line layer 140. The third cleaning process also partially etches dielectric layer 112 and hard mask layer 114. For example, the width W5 of hard mask layer 114 is reduced to width W7 after the third cleaning process. The height H3 of hard mask layer 114 is reduced to height H4 after the third cleaning process. The corners of hard mask layer 114 become more rounded after the third cleaning process. The width W6 of dielectric layer 112 is reduced to width W8 after the third cleaning process. A portion of dielectric layer 124 exposed by character line layer 140 is also partially removed after the third cleaning process. In some embodiments, a portion of dielectric layer 124 is removed, exposing thermal oxide layer 120 after the third cleaning process. In some embodiments, the third cleaning process is performed by using DHF as an etchant.

[0036] Referring to Figure 10, a dielectric layer 126 is formed, thereby lining the trench T and covering the top surface of the character line layer 140 and the rigid mask layer 114. The dielectric layer 126 may be made of silicon oxide, silicon nitride, or the like.

[0037] Subsequently, dielectric layer 152 overfills trench T and forms above dielectric layer 126. Since the height of hard masking layer 114 and the width of its top surface decrease after the third cleaning process, the aspect ratio of trench T can also be reduced after the third cleaning process. Therefore, it is easier to form dielectric layer 152 with fewer pores in trench T. In some embodiments, dielectric layer 152 may be a silicon nitride layer.

[0038] Referring to Figure 11, planarization is performed to remove excess material from dielectric layer 152. In some embodiments, planarization is performed until dielectric layer 112 is exposed. The remaining portion of dielectric layer 152 in trench T is referred to as capping layer 150. Because dielectric layer 152 with fewer pores has been formed in a previous stage, the resulting capping layer 150 also has fewer pores in the case that rigid masking layer 114 is made of silicon oxide.

[0039] In more detail, the first cleaning process in Figure 2, the second cleaning process in Figure 6, and the third cleaning process in Figure 8 are performed to remove byproducts (e.g., native oxides) obtained from their respective processes, and such cleaning processes also cause the rigid mask layer 114 and the dielectric layer 112 to shrink. The width of the top surface of the rigid mask layer 114, the height of the rigid mask layer 114, and the width of the top surface of the dielectric layer 112 gradually decrease after the cleaning process. Therefore, the aspect ratio of the trench T is continuously reduced after the cleaning process, and the gap filling capability of the trench is improved. Materials such as the word line layer 130, word line layer 140, and capping layer 150 formed in the trench T thus have less porosity. Furthermore, the rigid mask layer 114 and the dielectric layer 112, made of silicon oxide, have lower stress, thus applying less stress to the underlying material, such as the substrate 100. The wiggling problem of the contours of the character line layer 130, character line layer 140, and top cover layer 150 formed in the trench T is thus reduced.

[0040] Referring to Figure 12, a dielectric layer 160 is formed over the capping layer 150 and the dielectric layer 112. Subsequently, a gate contact layer 170 is formed over the capping layer 150 and the dielectric layer 160. In some embodiments, the dielectric layer 160 may be a silicon nitride layer. The gate contact layer 170 may be made of a conductive material such as polycrystalline silicon.

[0041] After the gate contact layer 170 is formed, subsequent processes can be performed to form other components, such as bit lines and capacitors, to form a memory device. Figure 13 illustrates a circuit diagram of a memory device in some embodiments disclosed herein. Referring to Figure 13, a memory device (e.g., dynamic random access memory, DRAM) may include a plurality of memory cells MC. A typical DRAM memory cell also has a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charged state of the capacitor CA. Bit lines BL are electrically connected to the source / drain regions of the transistor TR, and word lines WL are electrically connected to the gate region of the transistor TR. Capacitor CA is electrically connected to another source / drain region of each individual transistor TR. In some embodiments, the word line structure WL in Figure 8 may serve as the gate electrode of the transistor TR, dielectric layers 122, 124, and 126 may serve as the gate dielectric layers of the transistor TR, substrate 100 may serve as the channel region of the transistor TR, and active region AA may serve as the source / drain region of the transistor TR.

[0042] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the additional claims should not be limited to the description of the embodiments contained herein.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope and spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the following patent applications.

[0044] 100:Substrate 105: Isolation Structure 112: Dielectric layer 114: Rigid masking layer 120: Thermal oxide layer 122: Dielectric layer 124: Dielectric layer 126: Dielectric layer 130: Character Line Layer 132: Conductive layer 140: Character Line Layer 142: Conductive layer 150: Top Cover Layer 152: Dielectric layer 160: Dielectric layer 170: Gate contact layer AA: Active Zone BL: Bitline CA: Capacitor H1: First Height H2: Height H3: Height H4: Height MC: Memory Unit TR: Transistor T: Trench W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width W7: Width W8: Width WL: Character Line Structure / Character Line

[0045] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a memory device, comprising the following steps: forming a rigid mask layer over a substrate, wherein the rigid mask layer is made of an oxide-based material and has a first width; forming a trench in the substrate through the rigid mask layer; performing a first cleaning process on the substrate, wherein the first width of the rigid mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer thereby lining the trench; forming a first word line layer in the trench; forming a second word line layer in the trench and above the first word line layer; after forming the first word line layer, performing a second cleaning process such that the second width of the rigid mask layer is reduced to a third width after the second cleaning process is completed; forming a capping layer in the trench and above the second word line layer; removing the rigid mask layer; and forming a gate contact layer above the capping layer.

2. The manufacturing method as claimed in claim 1 further comprises the following steps: forming a second dielectric layer on the substrate prior to forming the rigid mask layer, wherein the second dielectric layer has a fourth width prior to the first cleaning process, and the fourth width of the second dielectric layer is reduced to a fifth width after the first cleaning process is completed.

3. The manufacturing method as described in claim 2, wherein both the rigid mask layer and the second dielectric layer are made of oxide-based materials.

4. The manufacturing method as described in claim 2, wherein the rigid mask layer and the second dielectric layer are made of the same material.

5. The manufacturing method as described in claim 1, wherein one corner of the rigid mask layer becomes more rounded after the first cleaning process is completed.

6. The manufacturing method as claimed in claim 1, further comprising: after performing the second cleaning process, forming a third dielectric layer to line the trench and cover the first character line layer, wherein the third dielectric layer is in contact with a sidewall and a bottom surface of the second character line layer.

7. The manufacturing method as claimed in claim 1, wherein a portion of the first dielectric layer is exposed by the first character line layer, and wherein the second cleaning process is performed such that the portion of the first dielectric layer is removed.

8. The manufacturing method as claimed in claim 7, further comprising: performing a thermal process on the substrate after the completion of the first cleaning process to form a thermal oxide layer thereby lining the trench, wherein a portion of the thermal oxide layer is exposed after the completion of the second cleaning process.

9. The manufacturing method as claimed in claim 1 further comprises: after forming the second character line layer, performing a third cleaning process such that the third width of the hard mask layer is reduced to a sixth width after the third cleaning process is completed.

10. A method for manufacturing a memory device, comprising the steps of: forming a rigid mask layer over a substrate, wherein the rigid mask layer is made of an oxide-based material and has a first height and a first width; forming a trench in the substrate through the rigid mask layer; performing a first cleaning process on the substrate, wherein the first height of the rigid mask layer is reduced to a second height and the first width of the rigid mask layer is reduced to a second width after the first cleaning process is completed; forming a first dielectric layer thereby lining the trench; forming a first word line layer in the trench; after forming the first word line layer, performing a second cleaning process such that the second height of the rigid mask layer is reduced to a third height and the second width of the rigid mask layer is reduced to a third width after the second cleaning process is completed; and forming a second word line layer in the trench and over the first word line layer. A top cover layer is formed in the trench and above the second character line layer; and a gate contact layer is formed above the top cover layer.

11. The manufacturing method as claimed in claim 10, wherein the step of forming the first character line layer comprises: forming a conductive layer to overfill the trench; and etching back the conductive layer until one top surface of the conductive layer is lower than one top surface of the substrate, wherein a portion of the first dielectric layer is exposed after etching back the conductive layer.

12. The manufacturing method as described in claim 11, wherein the portion of the first dielectric layer is removed after the second cleaning process is completed.

13. The manufacturing method as described in claim 10, wherein one corner of the rigid mask layer becomes more rounded after the second cleaning process is completed.

14. The manufacturing method as claimed in claim 10 further comprises: after performing the second cleaning process, forming a second dielectric layer as a top surface lining the trench and covering the first character line layer.

15. The manufacturing method as claimed in claim 14, wherein the step of forming the second character line layer comprises the steps of: forming a conductive layer to overfill the trench; and etching back the conductive layer until one top surface of the conductive layer is lower than one top surface of the substrate, wherein a portion of the second dielectric layer is exposed after etching back the conductive layer.

16. The manufacturing method as described in claim 15 further comprises the following steps: after forming the second character line layer, performing a third cleaning process such that the third height of the hard mask layer is reduced to a fourth height after the third cleaning process is completed.

17. The manufacturing method as described in claim 16, wherein the portion of the second dielectric layer is removed after the third cleaning process is completed.

18. The manufacturing method as described in claim 16, wherein one corner of the rigid mask layer becomes more rounded after the third cleaning process is completed.

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