Semiconductor structure and manufacturing method thereof

Abstract

This disclosure provides a semiconductor structure. This semiconductor structure includes a substrate, a bitline structure, a seed layer, a first spacer, a second spacer, a third spacer, and an air gap. The substrate has a groove, wherein the groove has sharp corners. The bitline structure is located on the substrate, wherein the groove surrounds the bitline structure. The seed layer is located on the sidewalls of the bitline structure. The first spacer is located on the sidewalls of the seed layer and on the bottom surface of the groove. The second spacer fills the groove. The third spacer is located on the substrate and adjacent to the first spacer. The air gap is located between the first and third spacers. The bottom of the air gap exposes a portion of the top surface of the second spacer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for manufacturing the same. Prior Technology

[0002] In recent decades, with the continuous improvement of electronic products, the demand for storage capacity has been increasing. In order to increase the storage capacity of storage devices (such as DRAM elements), more storage cells are integrated into the storage devices. With the increase in integration density, leakage current problems may occur in the semiconductor structure. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes the following steps: A bitline structure is provided on a substrate, wherein a groove surrounds the bitline structure. A seed layer is formed, wherein a first portion of the seed layer is located on the top surface of the bitline structure, a second portion of the seed layer is located on the sidewall of the bitline structure, and a third portion of the seed layer is located on the bottom surface of the groove. The first portion and the third portion of the seed layer are removed, such that the second portion of the seed layer remains on the sidewall of the bitline structure. A first spacer is formed on the top surface of the bitline structure, the sidewall of the second portion of the seed layer, and the bottom surface of the groove. A second spacer is formed to fill the groove. A sacrificial spacer is formed on the top surface of the bitline structure and the sidewall of the first spacer. A third spacer is formed on the sacrificial spacer. A portion of the third spacer and a portion of the sacrificial spacer are removed to expose the top surface of the bitline structure. A gas etching process is performed to remove the sacrificial spacer, wherein an air gap is formed between the first spacer and the third spacer.

[0004] According to some embodiments, the first spacer and the third spacer are made of the same material.

[0005] According to some embodiments, the first spacer and the third spacer comprise nitride and hydrogen.

[0006] According to some embodiments, the first spacer, the second spacer, and the third spacer comprise nitrides.

[0007] According to some embodiments, the sacrificial spacer includes an oxide.

[0008] According to some embodiments, the seed layer comprises silicon.

[0009] According to some embodiments, the precursor for forming the seed layer includes dichlorosilane.

[0010] According to some embodiments, the method further includes: forming a polycrystalline silicon layer on the top surface of a substrate after performing a gas etching process, and forming a tungsten layer on the polycrystalline silicon layer and the bit line structure, wherein the gas gap is sealed by the tungsten layer.

[0011] According to some embodiments, the method further includes: removing a portion of the tungsten layer to define a landing pad on the top surface of the in-situ line structure.

[0012] According to some embodiments, the method further includes: forming an isolation layer on the tungsten layer after removing a portion of the tungsten layer.

[0013] According to one embodiment of the present disclosure, a semiconductor structure is provided. This semiconductor structure includes a substrate, a bit line structure, a seed layer, a first spacer, a second spacer, a third spacer, and an air gap. The substrate has a groove, wherein the groove has sharp corners. The bit line structure is located on the substrate, wherein the groove surrounds the bit line structure. The seed layer is located on the sidewalls of the bit line structure. The first spacer is located on the sidewalls of the seed layer and on the bottom surface of the groove. The second spacer fills the groove. The third spacer is located on the substrate and adjacent to the first spacer. The air gap is located between the first spacer and the third spacer. The bottom of the air gap exposes a portion of the top surface of the second spacer.

[0014] According to some embodiments, the bit line structure includes a first conductive layer, a second conductive layer on the first conductive layer, a first hard mask layer on the second conductive layer, and a second hard mask layer on the first hard mask.

[0015] According to some embodiments, the top surface of the second spacer is coplanar with the top surface of the substrate.

[0016] According to some embodiments, the semiconductor structure further includes a polycrystalline silicon layer and a tungsten layer. The polycrystalline silicon layer is located on a substrate. The tungsten layer is located on the top surface of the polycrystalline silicon layer and the bit line structure, wherein the air gap is sealed by the tungsten layer.

[0017] According to some embodiments, the semiconductor structure further includes a landing pad and an isolation layer. The landing pad is located on the top surface of the bit line structure. The isolation layer is located on the tungsten layer, wherein the air gap is sealed by the isolation layer and the tungsten layer.

[0018] According to some embodiments, the groove has the maximum depth adjacent to the bit line structure.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the disclosures for which protection is claimed. Simple Explanation of the Diagram

[0020] To make the purpose of this disclosure more apparent and understandable, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings: Figure 1 is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments. Figure 2 is a cross-sectional schematic diagram of the semiconductor structure after the seed layer is formed according to some embodiments. Figure 3 is a schematic cross-sectional view of the semiconductor structure after a portion of the seed layer has been removed according to some embodiments. Figure 4 is a schematic cross-sectional view of the semiconductor structure after the first spacer is formed according to some embodiments. Figure 5 is a schematic cross-sectional view of the semiconductor structure after the second spacer is formed according to some embodiments. Figure 6 is a schematic cross-sectional view of the semiconductor structure after a portion of the second spacer has been removed according to some embodiments. Figure 7 is a schematic cross-sectional view of the semiconductor structure after the sacrificial spacer is formed according to some embodiments. Figure 8 is a schematic cross-sectional view of the semiconductor structure after the third spacer is formed according to some embodiments. Figure 9 is a schematic cross-sectional view of the semiconductor structure after removing a portion of the third spacer and the sacrificial spacer according to some embodiments. Figure 10 is a schematic cross-sectional view of the semiconductor structure after the sacrificial spacer has been removed according to some embodiments. Figure 11 is a schematic cross-sectional view of a semiconductor structure forming a polycrystalline silicon layer and a tungsten layer according to some embodiments. Figure 12 is a schematic cross-sectional view of the semiconductor structure after the isolation layer is formed according to some embodiments. Implementation

[0021] Reference will now be made in detail to embodiments disclosed herein, examples of which are shown in the drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0022] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific embodiments or examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or symbols may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, this disclosure uses spatially relative terms such as "below," "under," "lower," "above," and "upper" to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0024] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there can be intermediate components or layers.

[0025] Figures 1 through 12 are schematic cross-sectional views of various intermediate stages in the formation of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be applied to an integrated circuit (IC) or a portion thereof, such as logic circuits, resistors, capacitors, sensors, or storage devices (e.g., dynamic random access memory (DRAM)). It should be understood that, for simplicity, some components of the semiconductor structure 100 are not shown in Figures 1 through 12, and other embodiments of the semiconductor structure 100 may include additional components.

[0026] In some embodiments, substrate 110 may be a semiconductor substrate, such as a host semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, substrate 110 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of substrate 110 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors, or combinations thereof. Substrate 110 may also be formed of other materials, such as sapphire, indium tin oxide, etc.

[0027] As shown in the figure, the bitline structure 120 may include a first conductive layer 122, a second conductive layer 124, a first hard masking layer 126, and a second hard masking layer 128. The second conductive layer 124 is formed on the first conductive layer 122. The first hard masking layer 126 is formed on the second conductive layer 124. The second hard masking layer 128 is formed on the first hard masking layer 126. In some embodiments, the first conductive layer 122 and the second conductive layer 124 may include conductive materials such as metals, metal alloys, and metal nitrides. For example, the first conductive layer 122 may include polycrystalline silicon. For example, the second conductive layer 124 may include tungsten. In some embodiments, the first hard masking layer 126 and the second hard masking layer 128 may include nitrides, other dielectric materials, or combinations thereof.

[0028] As shown in Figure 1, substrate 110 includes a recess 112. The recess 112 may surround bitline structure 120. In some embodiments, the recess 112 includes sharp corners. In other words, the recess 112 has a maximum depth D1 near bitline structure 120, and the depth of the recess 112 decreases with distance from bitline structure 120 until it approaches zero. For example, the recess 112 has a vertical triangular cross-sectional profile. The recess 112 may be formed before or after bitline structure 120 is formed.

[0029] Referring to Figure 2, a seed layer 130 is formed on the bit line structure 120 and the groove 112. Specifically, a first portion 130-1 of the seed layer 130 is formed on the top surface 120T of the bit line structure 120, a second portion 130-2 is formed on the sidewall 120S of the bit line structure 120, and a third portion 130-3 is formed on the bottom surface 112B of the groove 112. As shown in Figure 2, the seed layer 130 is conformally formed on the bit line structure 120 and the groove 112. In some embodiments, the precursor for forming the seed layer 130 includes dichlorosilane (DCS). In some embodiments, the seed layer 130 includes silicon. In some embodiments, the seed layer 130 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0030] Referring to Figure 3, a portion of the seed layer 130 is removed. Specifically, the first portion 130-1 of the seed layer 130 on the top surface 120T of the bit line structure 120 is removed, and the third portion 130-3 of the seed layer 130 on the bottom surface 112B of the recess 112 is removed. The second portion 130-2 of the seed layer 130 remains on the sidewall 120S of the bit line structure 120. The top surface 120T of the bit line structure 120 and the bottom surface 112B of the recess 112 are exposed. A suitable directional dry etching process (such as plasma reactive etching, ion beam etching, etc.) can be used to remove the portion of the seed layer 130.

[0031] Referring to Figure 4, a first spacer 140 is formed on the bit line structure 120 and the seed layer 130. Specifically, a first portion 140-1 of the first spacer 140 is formed on the top surface 120T of the bit line structure 120, a second portion 140-2 is formed on the sidewall 130S of the seed layer 130, and a third portion 140-3 is formed on the bottom surface 112B of the groove 112. As shown in Figure 4, the first spacer 140 is conformally formed on the bit line structure 120, the seed layer 130, and above the groove 112. In some embodiments, the precursors used to form the first spacer 140 include dichlorosilane (DCS), NH3, and H2. In some embodiments, the first spacer 140 includes nitrides and hydrogen. In some embodiments, the first spacer 140 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. The seed layer 130 can support the first spacer 140 near the bit line structure 120 to maintain the thickness uniformity of the first spacer 140 during the subsequent air gap formation process.

[0032] Referring to Figure 5, a second spacer 150 is formed on the first spacer 140 and in the groove 112. Specifically, the second spacer 150 fills the groove 112 and covers the first spacer 140. In some embodiments, the precursors used to form the second spacer 150 include dichlorosilane (DCS) and NH3. In some embodiments, the second spacer 150 comprises a nitride. In some embodiments, the first spacer 140 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0033] Referring to Figure 6, a portion of the second spacer 150 is removed. The second spacer 150 covering the first spacer 140 is removed. In other words, the second spacer 150 filling the recess 112 is retained. As shown in Figure 6, after the removal process, the top surface 150T of the second spacer 150 may be coplanar with the top surface 110T of the substrate 110. In some embodiments, a first portion 140-1 of the first spacer 140 is removed to expose the top surface 120T of the bit line structure 120. A second portion 140-2 of the first spacer 140 is retained on the sidewall 130S of the seed layer 130. A suitable directional dry etching process (such as plasma reactive etching, ion beam etching, etc.) can be used to remove a portion of the second spacer 150. The second spacer 150 may support the first spacer 140 at the bottom to reduce collapse during subsequent air gap formation processes.

[0034] Referring to Figure 7, a sacrificial spacer 160 is formed on the bit line structure 120. Specifically, the sacrificial spacer 160 may be formed on the top surface 120T of the bit line structure 120, and the sacrificial spacer 160 may be formed on the sidewall 140S of the first spacer 140. As shown in Figure 7, the sacrificial spacer 160 is conformally formed over the bit line structure 120 and on the first spacer 140. In some embodiments, the sacrificial spacer 160 comprises an oxide. In some embodiments, the sacrificial spacer 160 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0035] Referring to Figure 8, a third spacer 170 is formed on the bit line structure 120. Specifically, the third spacer 170 may be formed on the top surface 160T of the sacrificial spacer 160, and the third spacer 170 may be formed on the sidewalls 160S of the sacrificial spacer 160. As shown in Figure 8, the third spacer 170 is conformally formed above the sacrificial spacer 160. In some embodiments, the precursors used to form the third spacer 170 include dichlorosilane (DCS), NH3, and H2. In some embodiments, the third spacer 170 includes nitrides and hydrogen. In some embodiments, the third spacer 170 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the third spacer 170 and the first spacer 140 are made of the same material.

[0036] Referring to Figure 9, a portion of the third spacer 170 and a portion of the sacrificial spacer 160 are removed. Specifically, after the removal process, the top surface 120T of the bit line structure 120 is exposed. A suitable directional dry etching process (such as plasma reactive etching, ion beam etching, etc.) can be used to remove a portion of the third spacer 170 and a portion of the sacrificial spacer 160.

[0037] Referring to Figure 10, the sacrificial spacer 160 is removed to form the air gap 162. After the sacrificial spacer 160 is removed, a portion of the top surface 150T of the second spacer 150 is exposed in the air gap 162. In some embodiments, the sacrificial spacer 160 is removed via a gas etching process. The sacrificial spacer 160, comprising oxides, has etch selectivity relative to the first spacer 140 and the third spacer 170. In other words, the etching rate on the sacrificial spacer 160 is higher than the etching rates on the first spacer 140 and the third spacer 170. The gas etching process can selectively etch the sacrificial spacer 160 without damaging the first spacer 140 to maintain the thickness uniformity of the first spacer 140 and reduce leakage current issues.

[0038] Referring to Figure 11, a polycrystalline silicon layer 180 is formed on substrate 110, and a tungsten layer 182 is formed on the polycrystalline silicon layer 180. Specifically, the tungsten layer 182 may cover the top surface 120T of the bitline structure 120, and the tungsten layer 182 may seal the air gap 162. Referring to Figure 12, a portion of the tungsten layer 182 is removed, and an isolation layer 184 is formed on the tungsten layer 182. Then, a landing pad 182L is defined on the top surface 120T of the bitline structure. When the landing pad 182L is defined, a portion of the first spacer 140 and a portion of the third spacer 170 are removed. Next, the isolation layer 184 reseals the air gap 162. In some embodiments, the isolation layer 184 may include a nitride, other dielectric materials, or a combination thereof.

[0039] As shown in Figures 1 through 12, the semiconductor structure 100 includes a substrate 110, a bitline structure 120, a seed layer 130, a first spacer 140, and an air gap 162. The substrate 110 has a recess 112, wherein the recess 112 has sharp corners and a maximum depth D1 near the bitline structure 120. The recess 112 has a vertical triangular cross-sectional profile. The bitline structure 120 is located on the substrate 110, and the recess 112 surrounds the bitline structure 120. The seed layer 130 is located on the sidewall 120S of the bitline structure 120. A portion of the seed layer 130 is below the top surface 110T of the substrate 110. The first spacer 140 is located on the sidewall 130S of the seed layer 130 and on the bottom surface 112B of the recess 112. The second spacer 150 fills the groove 112, and the top surface 150T of the second spacer 150 is coplanar with the top surface 110T of the substrate 110. The third spacer 170 is located on the substrate 110 and on the top surface 150T of the second spacer 150. The third spacer 170 is adjacent to the first spacer 140. An air gap 162 is located between the first spacer 140 and the third spacer 170, wherein the bottom of the air gap 162 exposes a portion of the top surface 150T of the second spacer 150.

[0040] Semiconductor structure 100 includes a polysilicon layer 180, a tungsten layer 182, a landing pad 182L, and an isolation layer 184. The polysilicon layer 180 is located on the top surface 110T of substrate 110 and is in contact with a third spacer 170. The tungsten layer 182 is located on the polysilicon layer 180 and above the top surface 120T of bitline structure 120. The tungsten layer 182 is in contact with the third spacer 170. An air gap 162 is sealed by the tungsten layer 182. The landing pad 182L is located on the top surface 120T of bitline structure 120. The isolation layer 184 is located on the tungsten layer 182, wherein the air gap 162 is sealed by the isolation layer 184. The isolation layer 184 is in contact with the sidewall 120S of bitline structure 120.

[0041] This disclosure provides a semiconductor structure and a method for manufacturing the same. According to the method provided, a sacrificial spacer is removed to form an air gap between a first spacer and a third spacer. A seed layer can support the first spacer on the side closest to the bit line structure to maintain the thickness uniformity of the first spacer during air gap formation. Furthermore, a second spacer can support the first spacer at the bottom to reduce collapse during air gap formation. Therefore, the integrity of the air gap can be improved, and leakage current and parasitic capacitance failures can be reduced. The air gap can effectively reduce the parasitic capacitance between the bit line and adjacent contact elements, thereby increasing the stability of the semiconductor structure.

[0042] Although this disclosure has been described in considerable detail with reference to certain embodiments therein, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims.

[0044] 100: Semiconductor Structure 110:Substrate 110T: Top surface 112: Groove 112B: Bottom surface 120: Bitline Structure 120S: Sidewall 120T: Top surface 122: First conductive layer 124: Second conductive layer 126: First hard mask layer 128: Second hard mask layer 130: Seed layer 130-1: Part One 130-2: Part Two 130-3: Part Three 130S: Sidewall 140: First spacer 140-1: Part One 140-2: Part Two 140-3: Part Three 140S: Sidewall 150: Second spacer 150T: Top surface 160: Sacrificial spacer 160S: Sidewall 160T: Top surface 162: Air gap 170: Third spacer 180: Polycrystalline silicon layer 182: Tungsten layer 182L: Landing mat 184: Isolation Layer D1: Depth

[0045] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor structure, comprising: A bit line structure is provided on a substrate, wherein a groove surrounds the bit line structure; a seed layer is formed, wherein a first portion of the seed layer is located on a top surface of the bit line structure, a second portion of the seed layer is located on a side wall of the bit line structure, and a third portion of the seed layer is located on a bottom surface of the groove. Remove the first portion and the third portion of the seed layer, leaving the second portion of the seed layer on the sidewall of the bit line structure; form a first spacer on the top surface of the bit line structure, one sidewall of the second portion of the seed layer, and the bottom surface of the groove. A second spacer is formed to fill the groove; a sacrificial spacer is formed on the top surface of the bit line structure and on one side wall of the first spacer; A third spacer is formed on the sacrificial spacer; a portion of the third spacer and a portion of the sacrificial spacer are removed to expose the top surface of the bit line structure; and a gas etching process is performed to remove the sacrificial spacer, wherein an air gap is formed between the first spacer and the third spacer.

2. The method as described in claim 1, wherein the first spacer and the third spacer are made of the same material.

3. The method as described in claim 1, wherein the first spacer and the third spacer comprise nitride and hydrogen.

4. The method as described in claim 1, wherein the first spacer, the second spacer and the third spacer comprise nitrides.

5. The method as described in claim 1, wherein the sacrificial spacer comprises an oxide.

6. The method as described in claim 1, wherein the seed layer comprises silicon.

7. The method as described in claim 1, wherein a precursor forming the seed layer comprises dichlorosilane.

8. The method as described in claim 1, further comprising: After performing the gas etching process, a polycrystalline silicon layer is formed on the top surface of the substrate; A tungsten layer is formed on the polycrystalline silicon layer and the bit line structure, wherein the air gap is sealed by the tungsten layer.

9. The method as described in claim 8, further comprising: A portion of the tungsten layer is removed to define a landing pad on the top surface of the bit line structure.

10. The method as described in claim 9, further comprising: After a portion of the tungsten layer is removed, an isolation layer is formed on the tungsten layer.

11. A semiconductor structure, comprising: A substrate having a groove with a pointed corner; a bit line structure located on the substrate, wherein the groove surrounds the bit line structure; a seed layer located on a sidewall of the bit line structure; a first spacer located on a sidewall of the seed layer and a bottom surface of the groove; a second spacer filling the groove, wherein a top surface of the second spacer is coplanar with a top surface of the substrate; a third spacer located on the substrate and adjacent to the first spacer; and an air gap located between the first spacer and the third spacer, wherein a bottom of the air gap exposes a portion of the top surface of the second spacer.

12. The semiconductor structure as described in claim 11, wherein the bit line structure comprises: First conductive layer; A second conductive layer is disposed on the first conductive layer; A first hard mask layer on the second conductive layer; and a second hard mask layer on the first hard mask layer.

13. The semiconductor structure as described in claim 11, further comprising: A polycrystalline silicon layer is located on the substrate; A tungsten layer is located on a top surface of the polycrystalline silicon layer and the bit line structure, wherein the air gap is sealed by the tungsten layer.

14. The semiconductor structure as described in claim 13, further comprising: A landing pad is located on the top surface of the bit structure; and an isolation layer is located on the tungsten layer, wherein the air gap is sealed by the isolation layer and the tungsten layer.

15. The semiconductor structure as claimed in claim 11, wherein the groove has the maximum depth adjacent to the bit line structure.

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