Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device with good data retention characteristics and reliability. The semiconductor memory device includes a memory block comprising a first sub-memory block and a second sub-memory block, bit lines and source lines, and control circuitry. The first sub-memory block and the second sub-memory block respectively include a first memory cell and a second memory cell, as well as a first word line and a second word line. During the erase operation of the memory block, the control circuit performs a first determination operation to determine the write state of the second memory cell, a first erase operation when the second memory cell is in a write state, and a second erase operation when the second memory cell is in an erase state. In the first erase operation, an erase voltage is applied to the bit lines and source lines, and a selective erase voltage lower than the erase voltage is applied to the first word line and the second word line. In the second erase operation, an erase voltage is applied to the bit lines and source lines, a selective erase voltage is applied to the first word line, and a non-selective erase voltage lower than the erase voltage but higher than the selective erase voltage is applied to the second word line.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Prior Technology

[0002] A semiconductor memory device is known, comprising a substrate, memory blocks arranged with the substrate in a first direction intersecting the surface of the substrate, and a control circuit for controlling the memory blocks. Summary of the Invention

[0003] This invention provides a semiconductor memory device with good data retention characteristics and reliability.

[0004] One embodiment of a semiconductor memory device includes: a substrate; a memory block including a first sub-memory block and a second sub-memory block arranged in a first direction intersecting the surface of the substrate; a bit line disposed on one side of the first direction relative to the memory block; a source line disposed on the other side of the first direction relative to the memory block; and a control circuit for controlling the memory block. The first sub-memory block includes: a first memory cell electrically connected to the bit line and the source line; and a first word line electrically connected to the first memory cell. The second sub-memory block includes: a second memory cell electrically connected to the bit line and the source line; and a second word line electrically connected to the second memory cell. The control circuit is configured to perform the following actions during an erase operation on the memory block: a first determination action to determine whether the second memory cell is in a write state; a first erase action performed when the second memory cell is in a write state; and a second erase action performed when the second memory cell is in an erase state. In the first erase operation, an erase voltage is applied to one or both of the bit lines and source lines, and a selective erase voltage lower than the erase voltage is applied to the first word line and the second word line. In the second erase operation, an erase voltage is applied to one or both of the bit lines and source lines, a selective erase voltage is applied to the first word line, and a non-selective erase voltage lower than the erase voltage but higher than the selective erase voltage is applied to the second word line. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic block diagram for illustrating the semiconductor memory device of the first embodiment. Figure 2 is a schematic side view for illustrating the semiconductor memory device. Figure 3 is a schematic plan view for illustrating the semiconductor memory device. Figure 4 is a schematic block diagram for illustrating the semiconductor memory device. Figure 5 is a schematic circuit diagram for illustrating the semiconductor memory device. Figure 6 is a schematic perspective view for illustrating the semiconductor memory device. Figure 7 is a schematic plan view for illustrating the semiconductor memory device. Figure 8 is a schematic cross-sectional view for illustrating the semiconductor memory device. Figure 9 is a schematic cross-sectional view for illustrating the semiconductor memory device. Figures 10(a) to 10(c) are schematic histograms used to illustrate the threshold voltage of a memory cell MC that records 3 bits of data. Figure 11 is a timing diagram illustrating the operation method of the semiconductor memory device. Figure 12 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 13 is a flowchart illustrating the operation method of the semiconductor memory device. Figure 14 is a timing diagram illustrating the operation method of the semiconductor memory device. Figure 15 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 16 is a flowchart illustrating the operation method of the semiconductor memory device. Figure 17 is a timing diagram illustrating the operation method of the semiconductor memory device. Figure 18 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 19 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 20 is a flowchart illustrating the operation method of the semiconductor memory device. Figure 21 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 22 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 23 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 24 is a timing diagram illustrating the operation method of the semiconductor memory device. Figure 25 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 26 is a graph used to illustrate the semiconductor memory device. Figure 27 is a graph used to illustrate the semiconductor memory device of the comparative example. Figure 28 is a graph used to illustrate the semiconductor memory device of the first embodiment. Figure 29(a) and Figure 29(b) are histograms used to illustrate the semiconductor memory device of the comparative example. Figure 30 is a flowchart illustrating the operation method of the semiconductor memory device in the second embodiment. Figure 31 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 32 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 33 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 34 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 35 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 36 is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. Figure 37 is a graph used to illustrate the semiconductor memory device. Figure 38 is a graph used to illustrate the semiconductor memory device. Figure 39 is a schematic perspective view for illustrating the semiconductor memory device of the third embodiment. Figure 40 is a flowchart illustrating the operation method of the semiconductor memory device. Figure 41 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 42 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 43 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 44 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 45 is a flowchart illustrating the operation method of the semiconductor memory device in the fourth embodiment. Figure 46 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 47 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 48 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 49 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 50 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 51 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 52 is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 1 bit of data. Figure 53 is a flowchart illustrating the operation method of the semiconductor memory device in the fifth embodiment. Figure 54 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 55 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 56 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Figure 57 is a schematic diagram illustrating an example of the write status of a sub-block of the semiconductor memory device. Implementation

[0006] Next, the semiconductor memory device of the embodiment will be described in detail with reference to the drawings.

[0007] Furthermore, the following embodiments are merely examples and are not intended to limit the invention.

[0008] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes refers to a memory chip, and sometimes to a memory system that includes a controller die, such as a memory card or solid-state drive (SSD). Moreover, it sometimes refers to a structure that includes a host computer, such as a smartphone, tablet, or personal computer.

[0009] Furthermore, in this specification, when it is mentioned that the first structure is "electrically connected" to the second structure, the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] In addition, in this specification, when it is said that the first structure is "connected between the second structure and the third structure", it sometimes means that the first structure, the second structure and the third structure are connected in series, and the second structure is connected to the third structure through the first structure.

[0011] Furthermore, in this specification, when referring to a circuit or the like that makes two wirings "conduct", it may mean, for example, that the circuit or the like includes a transistor or the like, which is placed in the current path between the two wirings and is in an ON state.

[0012] [First Implementation Form] [Memory System 10] Figure 1 is a schematic block diagram showing the structure of the memory system 10 in the first embodiment.

[0013] The memory system 10 reads, writes, and erases user data based on signals sent by the autonomous computer 20. The memory system 10 is, for example, a system capable of storing user data from a memory card, SSD, or other storage devices. The memory system 10 includes multiple memory chips (MDs) for storing user data, and a controller chip (CD) connected to these multiple memory chips (MDs) and the host computer 20. The controller chip (CD) includes, for example, a processor and random access memory (RAM), performing logical address to physical address conversion, bit error detection / correction, waste collection (compression), and wear leveling. The controller chip (CD) may also include a temporary register (RG). The temporary register (RG) may hold information related to the state of the memory chips (MDs), such as information about the erase and write states of sub-block units (described later).

[0014] Figure 2 is a schematic side view showing a structural example of the memory system 10 of this embodiment. Figure 3 is a schematic plan view showing the structural example. For ease of explanation, a portion of the structure is omitted in Figures 2 and 3.

[0015] As shown in Figure 2, the memory system 10 of this embodiment includes: a mounting substrate MSB, a plurality of memory chips MD stacked on the mounting substrate MSB, and a controller chip CD stacked on the memory chips MD. A solder pad electrode P is provided at the end region in the Y direction of the upper surface of the mounting substrate MSB, and other regions are bonded to the lower surface of the memory chips MD via an adhesive or the like. A solder pad electrode P is provided at the end region in the Y direction of the upper surface of the memory chips MD, and other regions are bonded to the lower surface of other memory chips MD or controller chips CD via an adhesive or the like. A solder pad electrode P is provided at the end region in the Y direction of the upper surface of the controller chip CD.

[0016] As shown in Figure 3, the mounting substrate MSB, multiple memory chips MD, and controller chip CD each include multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P disposed on the mounting substrate MSB, multiple memory chips MD, and controller chip CD are interconnected via bonding lines B.

[0017] Furthermore, the structures shown in Figures 2 and 3 are merely illustrative, and the specific structures can be adapted accordingly. For example, in the examples shown in Figures 2 and 3, controller chips CD are stacked on multiple memory chips MD, and these structures are connected by bonding lines B. In this structure, multiple memory chips MD and controller chips CD are contained within a single package. However, the controller chips CD may be contained in a different package than the memory chips MD. Additionally, multiple memory chips MD and controller chips CD may also be interconnected via through electrodes or the like, rather than via bonding lines B.

[0018] [Structure of memory chip MD] Figure 4 is a schematic block diagram showing the structure of the memory die MD in the first embodiment. Figure 5 is a schematic circuit diagram showing a portion of the structure of the memory die MD. For ease of explanation, a portion of the structure is omitted in Figures 4 and 5.

[0019] Furthermore, Figure 4 illustrates multiple control terminals. These control terminals may be represented as control terminals corresponding to active high signals (positive logic signals), active low signals (negative logic signals), or both active high and active low signals. In Figure 4, the symbol for the control terminal corresponding to the active low signal includes an overline. In this specification, the symbol for the control terminal corresponding to the active low signal includes a forward slash (" / "). Furthermore, Figure 4 is illustrative, and the specific configuration can be adjusted accordingly. For example, some or all active high signals may be set to active low signals, or some or all active low signals may be set to active high signals.

[0020] As shown in Figure 4, the memory die MD includes memory cell arrays MCA0 and MCA1 for storing user data, and peripheral circuitry PC connected to memory cell arrays MCA0 and MCA1. Furthermore, in the following description, memory cell arrays MCA0 and MCA1 will sometimes be referred to as memory cell arrays MCA.

[0021] [Circuit structure of Memory Cell Array (MCA)] As shown in Figure 5, the Memory Cell Array (MCA) includes multiple memory blocks (BLK). Each of these memory blocks (BLK) includes multiple string units (SU). Each of these string units (SU) includes multiple memory strings (MS). One end of each memory string (MS) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each memory string (MS) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0022] The memory string (MS) includes: a drain-side selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MCs) (memory cell transistors), and a source-side selection transistor (STS). Hereinafter, the drain-side selection transistor (STD) and the source-side selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0023] Memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of memory cell MC varies according to the amount of charge in the charge storage film. Memory cell MC stores one or more bits of user data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are commonly connected to all memory strings MS in a memory block BLK.

[0024] Select transistors (STD, STS) are field-effect transistors comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the select transistor (STD, STS) is connected to a drain-side select gate line (SGD) and a source-side select gate line (SGS). The drain-side select gate line (SGD) is correspondingly provided with a serial cell (SU) and is connected to all memory strings (MS) in a serial cell (SU). The source-side select gate line (SGS) is connected to all memory strings (MS) in a memory block (BLK). Hereinafter, the drain-side select gate line (SGD) and the source-side select gate line (SGS) will sometimes be simply referred to as select gate lines (SGD, SGS).

[0025] [Circuit structure of the peripheral circuit PC] For example, as shown in Figure 4, the peripheral circuit PC includes column decoders RD0 and RD1, and sense amplifiers SA0 and SA1, which are respectively connected to memory cell arrays MCA0 and MCA1. Additionally, the peripheral circuit PC includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes input / output control circuits (I / O), logic circuits CTR, address registers ADR, command registers CMR, and status registers STR. Moreover, in the following description, column decoders RD0 and RD1 will sometimes be referred to as column decoders RD, and sense amplifiers SA0 and SA1 will be referred to as sense amplifiers SA.

[0026] For example, as shown in Figure 5, the column decoder RD (Figure 4) includes an address decoder 22 that decodes the address data Add (Figure 4). Additionally, the column decoder RD (Figure 4) includes a block selection circuit 23 and a voltage selection circuit 24 that transmit operating voltages to the memory cell array MCA based on the output signal of the address decoder 22.

[0027] Address decoder 22 is connected to multiple block select lines BLKSEL and multiple voltage select lines 33. Address decoder 22 refers to the column address RA of address register ADR (Figure 4) sequentially according to the control signal from sequencer SQC.

[0028] The block selection circuit 23 includes multiple block selection sections 34 corresponding to memory blocks BLK. Each block selection section 34 includes multiple block selection transistors 35 corresponding to word lines WL and select gate lines (SGD, SGS). The block selection transistors 35 are, for example, field-effect transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS). The source electrodes of the block selection transistors 35 are electrically connected to the voltage supply line 31 via wiring CG and the voltage selection circuit 24. The gate electrodes of the block selection transistors 35 are commonly connected to the corresponding block selection lines BLKSEL.

[0029] The voltage selection circuit 24 includes multiple voltage selection sections 36 corresponding to the word line WL and the selected gate lines (SGD, SGS). Each of these multiple voltage selection sections 36 includes multiple voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word line WL or selected gate lines (SGD, SGS) via wiring CG and block selection circuit 23. The source terminals are electrically connected to the corresponding voltage supply lines 31. The gate terminals are connected to the corresponding voltage selection lines 33.

[0030] Sensing amplifiers SA0 and SA1 (Figure 4) respectively include sensing amplifier modules SAM0 and SAM1, and cache memory CM0 and CM1 (data registers). Cache memory CM0 and CM1 respectively include latch circuits XDL0 and XDL1. Furthermore, in the following description, sensing amplifier modules SAM0 and SAM1 are sometimes referred to as sensing amplifier modules SAM, cache memory CM0 and CM1 are sometimes referred to as cache memory CM, and latch circuits XDL0 and XDL1 are sometimes referred to as latch circuits XDL.

[0031] The sense amplifier module (SAM) includes, for example, sense circuits corresponding to multiple bit lines (BL) and multiple latch circuits connected to the sense circuits.

[0032] The cache memory CM includes multiple latch circuits XDL. Each latch circuit XDL is connected to a latch circuit within the sense amplifier module SAM. The latch circuits XDL store, for example, user data written to or read from the memory unit MC.

[0033] For example, a row decoder is connected to the cache memory CM. The row decoder decodes the row address CA stored in the address register ADR (Figure 4) and selects the latch circuit XDL corresponding to the row address CA.

[0034] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transmitted to the latch circuits within the sense amplifier module SAM during the write operation. Additionally, the user data Dat contained in the latch circuits within the sense amplifier module SAM is sequentially transmitted to the latch circuit XDL during the read operation. Finally, the user data Dat contained in the latch circuit XDL is sequentially transmitted to the input / output control circuit I / O during the data output operation.

[0035] For example, as shown in Figure 5, the voltage generation circuit VG (Figure 4) is connected to multiple voltage supply lines 31. The voltage generation circuit VG includes, for example, a buck circuit such as a regulator and a boost circuit such as a charge pump circuit 32. These buck and boost circuits are connected to the voltage supply lines supplying the power supply voltage VCC and the ground voltage VSS (Figure 4), respectively. These voltage supply lines are connected, for example, to the pad electrodes P as described with reference to Figures 2 and 3. The voltage generation circuit VG generates, for example, various operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, according to control signals from the sequencer SQC, and simultaneously outputs them to the multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are appropriately adjusted according to the control signals from the sequencer SQC.

[0036] The sequencer SQC (Figure 4) outputs internal control signals to the column decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG according to the command data Cmd stored in the command register CMR. Additionally, the sequencer SQC appropriately outputs the status data Stt, representing the state of the memory chip MD, to the status register STR.

[0037] Additionally, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / ( / BY). During the period when the terminal RY / ( / BY) is in the "L" state (busy period), access to the memory chip MD is essentially disabled. Conversely, during the period when the terminal RY / ( / BY) is in the "H" state (ready period), access to the memory chip MD is permitted. Furthermore, the terminal RY / ( / BY) is implemented, for example, using the pad electrode P described with reference to Figures 2 and 3.

[0038] As shown in Figure 4, the address register ADR is connected to the input / output control circuit (I / O) and stores the address data Add input from the I / O. The address register ADR may include, for example, multiple 8-bit register rows. During internal operations such as read, write, or erase, the register rows retain the address data Add corresponding to the ongoing internal operation.

[0039] Furthermore, the address data Add includes, for example, row address CA (Figure 4) and column address RA (Figure 4). The column address RA includes, for example, the block address for determining the memory block BLK (Figure 5), the page address for determining the serial cell SU and word line WL, the plane address for determining the memory cell array MCA (plane), and the chip address for determining the memory die MD.

[0040] The command register (CMR) is connected to the input / output control circuit (I / O) and stores the command data (Cmd) input from the I / O. The command register CMR, for example, includes at least one set of 8-bit register rows. When the command data Cmd is stored in the command register CMR, a control signal is sent to the sequencer (SQC).

[0041] The status register STR is connected to the input / output control circuit (I / O) and stores the status data Stt output to the I / O. The status register STR may include, for example, multiple 8-bit register rows. These register rows, for example, maintain the status data Stt associated with internal operations such as read, write, or erase operations. Additionally, the register rows may also maintain ready / busy information for memory cell arrays MCA0 and MCA1.

[0042] The input / output control circuit I / O (Figure 4) includes data signal input / output terminals DQ0~DQ7, data select signal input / output terminal DQS, data select signal input / output terminal / DQS, shift register, and buffer circuit.

[0043] Data input / output terminals DQ0 to DQ7 and data select signal input / output terminals DQS and DQS are implemented, for example, using pad electrodes P as described with reference to Figures 2 and 3. Data input via data input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or command register CMR according to the internal control signal from the logic circuit CTR. Similarly, data output via data input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0044] Signals input via the Data Select Signal Input / Output Terminals DQS and DQS (e.g., the Data Select Signal and its complementary signal) are used when data is input via Data Signal Input / Output Terminals DQ0 to DQ7. Data input via Data Signal Input / Output Terminals DQ0 to DQ7 is fed into the shift register within the input / output control circuit I / O at the timing of the rising edge (input signal switching) and falling edge (input signal switching) of the voltage at the Data Select Signal Input / Output Terminals DQS, and at the timing of the falling edge (input signal switching) and rising edge (input signal switching) of the voltage at the Data Select Signal Input / Output Terminals DQS.

[0045] The logic circuit CTR (Figure 4) includes: multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuitry connected to these external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller chip CD via the external control terminals / CE, CLE, ALE, / WE, / RE, and RE, and correspondingly outputs internal control signals to the input / output control circuit (I / O).

[0046] Furthermore, the external control terminals / CE, CLE, ALE, / WE, / RE, and RE are each implemented, for example, by the pad electrode P described with reference to Figures 2 and 3.

[0047] [Structure of memory chip MD] Figure 6 is a schematic perspective view showing a portion of the structure of a memory die MD. Figure 7 is a schematic plan view showing a portion of the structure of a memory die MD. Figures 8 and 9 are schematic cross-sectional views showing a portion of the structure of a memory die MD. Figure 8 is a schematic cross-sectional view showing the structure shown in Figure 7 cut along line A-A' and viewed in the direction of the arrow. Figure 9 is a schematic cross-sectional view showing region D of Figure 8 magnified. For ease of explanation, a portion of the structure is omitted in Figures 6-9.

[0048] For example, as shown in FIG6, the semiconductor memory device of this embodiment includes a transistor layer LTR disposed on a semiconductor substrate 100 and a memory cell array layer LMCA disposed above the transistor layer LTR.

[0049] A wiring layer GC is disposed on the upper surface of the semiconductor substrate 100, separated by an insulating layer. The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. In addition, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are respectively connected to a connector CS.

[0050] Multiple electrodes gc face the surface of the semiconductor substrate 100 and function as gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC and electrodes of multiple capacitors.

[0051] Multiple connectors CS extend along the Z direction and are connected at their lower ends to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection portion between the connector CS and the semiconductor substrate 100. The connector CS may also include, for example, a laminated film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0052] Wiring layers D0, D1, and D2 each include multiple wirings, which are electrically connected to at least one of the structures in the memory cell array (MCA) and the peripheral circuitry (PC). These wirings may, for example, include multilayer films comprising a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0053] For example, as shown in Figure 6, a memory block BLK is set in the memory cell array layer L MCA.

[0054] In the example of Figure 7, the memory block BLK includes five serial cells SUa~SUe arranged from one side of the Y direction (the positive side of the Y direction in Figure 4) to the other side of the Y direction (the negative side of the Y direction in Figure 4). These serial cells SUa~SUe correspond to the serial cell SU described with reference to Figure 5. An inter-serial cell insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent serial cells SU in the Y direction. An inter-block structure ST is provided between two adjacent memory blocks BLK in the Y direction.

[0055] As shown in Figures 6 and 8, in the memory cell array layer LMCA, the memory block BLK includes the memory cell array layer LMCA1 and the memory cell array layer LMCA2 disposed above the memory cell array layer LMCA1. An insulating layer 151, such as silicon oxide (SiO2), is disposed between the memory cell array layers LMCA1 and LMCA2. The memory cell array layers LMCA1 and LMCA2 include a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

[0056] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. As shown in FIG9, the conductive layer 110 may also include a laminated film comprising a barrier conductive film 116 containing titanium nitride (TiN) and the like, and a metal film 115 containing tungsten (W) and the like. Furthermore, insulating metal oxide films 134 such as aluminum oxide (AlO) may also be provided on the upper and lower surfaces of the conductive layer 110 and on the surface facing the semiconductor layer 120. In addition, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). A connector CC (FIG. 6) is provided at the ends of the plurality of conductive layers 110 in the X direction. An insulating layer 101 such as silicon oxide (SiO 2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0057] As shown in Figure 8, semiconductor layers 111, 113, and 112 are disposed below the plurality of conductive layers 110, separated by an insulating layer 101. A portion of a gate insulating film 130 is disposed between semiconductor layers 111 and 112 and semiconductor layer 120. The lower ends of semiconductor layer 113 and semiconductor layer 120 are connected.

[0058] The upper surface of semiconductor layer 113 is connected to semiconductor layer 111, and the lower surface is connected to semiconductor layer 112. A conductive layer 114 may also be disposed on the lower surface of semiconductor layer 112. Semiconductor layers 111, 113, 112, and conductive layer 114 function as source lines SL (FIG. 1). For example, source lines SL can be commonly disposed for multiple memory blocks BLK. Semiconductor layers 111, 113, and 112 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Conductive layer 114 may also include, for example, a conductive layer of a metal such as tungsten (W), tungsten silicate, or other conductive layers.

[0059] One or more conductive layers 110 located at the bottom of the multiple conductive layers 110 disposed in the memory cell array layer L MCA1 function as the gate electrodes of the source-side select gate line SGS (FIG. 5) and the multiple source-side select transistors STS (FIG. 5) connected thereto. The conductive layers 110 are electrically independent for each memory block BLK.

[0060] Furthermore, one or more conductive layers 110 located above the memory cell array layer L MCA1 are provided as virtual conductive layers. Hereinafter, such conductive layers 110 are referred to as virtual conductive layers 110DM. Virtual conductive layers 110DM do not function as select gate lines (SGD, SGS) or word lines WL. No memory cells MC for recording data are provided between the virtual conductive layers 110DM and the semiconductor layer 120. Furthermore, hereafter, such virtual conductive layers 110DM are sometimes referred to as virtual word lines DWL.

[0061] Furthermore, several conductive layers 110 located higher up in the memory cell array layer L MCA1 function as gate electrodes for word lines WL (FIG. 5) and the multiple memory cells MC (FIG. 5) connected thereto. Memory cells MC for recording data are disposed between these conductive layers 110 and the semiconductor layer 120. Each of these conductive layers 110 is electrically independent for each memory block BLK.

[0062] In addition, one or more conductive layers 110 located at the top of the multiple conductive layers 110 disposed in the memory cell array layer L MCA1 are virtual conductive layers 110DM.

[0063] In addition, one or more conductive layers 110 located at the bottom of the multiple conductive layers 110 disposed in the memory cell array layer L MCA2 are virtual conductive layers 110DM.

[0064] Furthermore, several conductive layers 110 located higher up in the memory cell array layer L MCA2 function as gate electrodes for word lines WL (FIG. 5) and the multiple memory cells MC (FIG. 5) connected thereto. Memory cells MC for recording data are disposed between these conductive layers 110 and the semiconductor layer 120. Each of these conductive layers 110 is electrically independent for each memory block BLK.

[0065] Additionally, one or more conductive layers 110 located further above function as gate electrodes for the drain-side selected gate line SGD (FIG. 5) and the plurality of drain-side selected transistors STD (FIG. 5) connected thereto. These conductive layers 110 are narrower in the Y direction compared to the other conductive layers 110. Furthermore, an inter-cell insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. These conductive layers 110 are electrically independent for each inter-cell SU.

[0066] For example, as shown in Figures 6 and 7, the semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions. The semiconductor layer 120 functions as a channel region for multiple memory cells (MCs) and select transistors (STDs, STSs) contained in a memory string (MS) (Figure 5). The semiconductor layer 120 is, for example, a semiconductor layer of polycrystalline silicon (Si). For example, as shown in Figure 8, the semiconductor layer 120 has a generally bottomed cylindrical shape, and an insulating layer 125 of silicon oxide (SiO2) or the like is disposed in the central portion.

[0067] As shown in Figure 8, the semiconductor layer 120 includes a semiconductor region 120L contained in the memory cell array layer L MCA1 and a semiconductor region 120U contained in the memory cell array layer L MCA2. Additionally, the semiconductor layer 120 includes a semiconductor region 120J connected to the upper end of semiconductor region 120L and the lower end of semiconductor region 120U, an impurity region 122 connected to the lower end of semiconductor region 120L, and an impurity region 121 connected to the upper end of semiconductor region 120U.

[0068] Semiconductor region 120 L is a generally cylindrical region extending along the Z direction. The outer peripheral surface of semiconductor region 120 L is surrounded by a plurality of conductive layers 110 contained in memory cell array layer L MCA1, and faces the plurality of conductive layers 110.

[0069] Semiconductor region 120 U is a generally cylindrical region extending along the Z direction. The outer peripheral surface of semiconductor region 120 U is surrounded by a plurality of conductive layers 110 contained in memory cell array layer L MCA2, and faces the plurality of conductive layers 110.

[0070] Semiconductor region 120J is disposed above the plurality of conductive layers 110 contained in memory cell array layer L MCA1, and below the plurality of conductive layers 110 contained in memory cell array layer L MCA2.

[0071] Impurity region 122 is connected to semiconductor layer 113. Impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The portion of semiconductor layer 120 located directly above impurity region 122 functions as a channel region for source-side selective transistor (STS).

[0072] Impurity region 121 contains, for example, N-type impurities such as phosphorus (P). Impurity region 121 is connected to bit line BL via connector Ch and connector Cb (Fig. 6).

[0073] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as shown in FIG9, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is such as silicon nitride (SiN) and is a film capable of storing charge. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a generally cylindrical shape and extend along the Z direction along the outer peripheral surface of the semiconductor layer 120.

[0074] Furthermore, the gate insulating film 130 may also include, for example, a floating gate containing polycrystalline silicon or other materials with N-type or P-type impurities.

[0075] The inter-block structure ST is a structure that extends along the Z and X directions, and is divided in the Y direction into multiple insulating layers 101, multiple conductive layers 110, semiconductor layers 111 and 113, reaching the semiconductor layer 112. The inter-block structure ST may be, for example, an insulating layer such as silicon oxide (SiO2). Furthermore, the inter-block structure ST may also include a conductive layer such as tungsten extending along the X and Z directions at its center in the Y direction; additionally, the lower end of the conductive layer may be connected to the semiconductor layer 112.

[0076] [Radial width of semiconductor region 120 L, semiconductor region 120 U, semiconductor region 120 J] Next, the radial widths of semiconductor regions 120L, 120U, and 120J will be explained. Hereinafter, in this specification, the width of the semiconductor layer in the XY cross-section intersecting the Z direction, which is the extension direction of semiconductor regions 120L and 120U, will be referred to as the radial width. Furthermore, for ease of explanation, in Figure 8, etc., the width in the Y direction is illustrated as the radial width.

[0077] The radial width W 120LL of the lower end of the semiconductor region 120L (e.g., the portion located below the plurality of conductive layers 110 included in the memory cell array layer L MCA1) is smaller than the radial width W 120LU of the upper end of the semiconductor region 120L (e.g., the portion located above the plurality of conductive layers 110 included in the memory cell array layer L MCA1). That is, the closer the semiconductor region 120L is to the lower part of the substrate, the smaller its radial width.

[0078] The radial width W 120UL of the lower end of semiconductor region 120U (e.g., the portion located below the plurality of conductive layers 110 included in memory cell array layer L MCA2) is smaller than the radial width W 120UU of the upper end of semiconductor region 120U (e.g., the portion located above the plurality of conductive layers 110 included in memory cell array layer L MCA2). That is, the closer semiconductor region 120U is to the substrate and below semiconductor region 120J, the smaller its radial width, and the smallest radial width is located near the top of semiconductor region 120J. Furthermore, the width W 120UL is smaller than the width W 120LU.

[0079] The radial width W120J of semiconductor region 120J is set to be greater than the radial widths W120LL, W120LU, W120UL, and W120UU of semiconductor regions 120L and 120U.

[0080] [Records the threshold voltage of the memory cell MC for multiple bits] Next, referring to Figures 10(a) to 10(c), the threshold voltage of a memory cell MC that records multiple bits of data will be explained. In Figures 10(a) to 10(c), as an example, the threshold voltage of a memory cell MC that records 3 bits of data is shown.

[0081] Figure 10(a) is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 3 bits of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Figure 10(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the recorded data. Figure 10(c) is a table showing another example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the recorded data.

[0082] In the example of Figure 10(a), the threshold voltage of the memory cell MC is controlled in eight states. The threshold voltage of the memory cell MC controlled in state Er is less than the erase verification voltage VVFYEr. Additionally, for example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage VVFYA and less than the verification voltage VVFYB. Similarly, the threshold voltage of the memory cell MC controlled in states C to F is greater than the verification voltages VVFYC to VVFYF and less than the verification voltages VVFYD to VVFYG, respectively. Additionally, for example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage VVFYG and less than the read path voltage VREAD. The read path voltage VREAD is, for example, approximately 9 V.

[0083] Furthermore, in the example of Figure 10(a), a readout voltage VCGAR is set between the threshold value distribution corresponding to state Er and the threshold value distribution corresponding to state A. Additionally, a readout voltage VCGBR is set between the threshold value distribution corresponding to state A and the threshold value distribution corresponding to state B. Similarly, readout voltages VCGCR and VCGGR are set between the threshold value distribution corresponding to state B and the threshold value distribution corresponding to state C, and between the threshold value distribution corresponding to state F and the threshold value distribution corresponding to state G, respectively.

[0084] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC in the Er state is, for example, the memory cell MC in the erase state. For example, the data "111" is allocated to the memory cell MC in the Er state.

[0085] Additionally, state A corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state Er. For example, data "101" is allocated to memory cell MC in state A.

[0086] Additionally, state B corresponds to a threshold voltage that is higher than the threshold voltage corresponding to state A. For example, data "001" is allocated to memory cell MC in state B.

[0087] Similarly, in the following diagram, states C to G correspond to threshold voltages that are higher than the threshold voltages corresponding to states B to F. For example, data "011", "010", "110", "100", and "000" are assigned to memory cells MC in these states.

[0088] Furthermore, in the typical allocation illustrated in Figure 10(b), the data of the low-order bits can be determined by one readout voltage VCGDR, the data of the middle-order bits can be determined by three readout voltages VCGAR, VCGCR, and VCGFR, and the data of the high-order bits can be determined by three readout voltages VCGBR, VCGER, and VCGGR. This data allocation is sometimes referred to as a 1-3-3 code.

[0089] Furthermore, the number of bits of data recorded in the memory unit (MC), the number of states, and the data allocation for each state can be appropriately changed.

[0090] For example, in the typical allocation illustrated in Figure 10(c), the data of the least significant bit can be determined by one readout voltage VCGDR, the data of the middle bit can be determined by two readout voltages VCGBR and VCGFR, and the data of the most significant bit can be determined by four readout voltages VCGAR, VCGCR, VCGER, and VCGGR. This data allocation is sometimes referred to as a 1-2-4 code.

[0091] [action] Next, the operation of the semiconductor memory device of this embodiment will be explained.

[0092] [Read the action] The readout operation of the memory die (MD) in this embodiment will be explained. Figure 11 is a timing diagram for explaining the readout operation. Figure 12 is a schematic cross-sectional view for explaining the readout operation. Figure 12 shows the voltages supplied at times t103 to t105 in Figure 11.

[0093] Furthermore, in the following description, the drain-side selected gate line SGD corresponding to the string unit SU that is the object of the action is sometimes referred to as the drain-side selected gate line SGD S, and the drain-side selected gate line SGD corresponding to other string units SU is referred to as the drain-side selected gate line SGD U.

[0094] In addition, sometimes the character line WL that is the object of the action is called the selected character line WL S, and the other character lines WL are called the non-selected character lines WL U.

[0095] Furthermore, the following description illustrates an example of performing a read operation on a unit connected to the selection character line WLS (hereinafter sometimes referred to as "selection memory unit MC") among the multiple memory units MC contained in the string unit SU (Fig. 12), which is the object of the operation. Additionally, in the following description, the structure containing such multiple selection memory units MC is sometimes referred to as selection page PGS. Furthermore, the memory block BLK containing selection page PGS is sometimes referred to as selection memory block BLK tb.

[0096] Furthermore, the following description illustrates an example of how each memory cell (MC) stores multiple bits of data and uses various readout voltages during the readout process.

[0097] At the moment t100 of the read operation, the controller chip CD sequentially inputs the command data Cmd (Figure 4) and the address data Add (Figure 4) indicating the read operation to the memory chip MD. This causes the terminal RY / ( / BY) to enter the "L" state (busy period).

[0098] For example, as shown in Figure 11, at time t101, voltage VSG is supplied to the drain-side select gate line SGDS, drain-side select gate line SGDU, and source-side select gate line SGS, setting all select transistors (STD, STS) to the ON state. Additionally, read path voltage VREAD is supplied to the select word line WLS and read path voltage VREAD is supplied to the non-select word line WLU, setting all memory cells MC to the ON state.

[0099] For example, as shown in Figure 11, at time t102, a read path voltage VREAD is supplied to the non-selection word line WLU, turning on the memory cells MC connected to all non-selection word lines WLU. On the other hand, a ground voltage VSS is supplied to the select word line WLS, turning off the memory cells MC connected to the select word line WLS. Additionally, a voltage VSG is supplied to the drain-side select gate line SGDS and the source-side select gate line SGS of the serial cell SUa, which includes the select page PGS, turning on the select transistors STD and STS connected to them. Furthermore, a ground voltage VSS is supplied to the drain-side select gate lines SGDS of the serial cells SUB to SUE, which do not include the select page PGS, turning off the select transistors STD connected to them.

[0100] At time t103, a predetermined read voltage VCGR is supplied to the select character line WLS. The read voltage VCGR can be, for example, any one of the seven read voltages VCGAR~VCGGR described with reference to FIG10(a). Thereby, the select memory cells MC contained in the select page PG S become either on or off according to their respective threshold voltages. That is, a portion of the select memory cells MC in the select page PG S become on, and the remaining select memory cells MC become off.

[0101] Additionally, during the readout operation from time t103 to time t104, for example, charging of bit line BL is performed. Furthermore, for example, a voltage VSRC is supplied to the source line SL (semiconductor layer 112) to begin charging. The voltage VSRC has, for example, a magnitude similar to the ground voltage VSS. Subsequently, a sensing operation is performed by the sense amplifier module SAM (FIG. 4) to detect the on / off state of the memory cell MC, acquiring data representing the state of the memory cell MC.

[0102] At the moment of read operation t104, another read voltage VCGR is supplied to the select word line WLS. As a result, a portion of the select memory cells MC of the select page PG S are turned on, while the remaining select memory cells MC are turned off.

[0103] During the readout action from time t104 to time t105, similarly to time t103 to time t104, the sensing amplifier module SAM performs a sensing action to acquire data representing the state of the memory cell MC.

[0104] At the moment of the readout action t105, the ground voltage VSS is supplied to the select character line WLS, all non-select character lines WLU, and the select gate lines (SGD, SGS).

[0105] At time t106, the read operation in the memory chip MD ends. In addition, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory chip MD.

[0106] Furthermore, during the read operation, AND and OR operations are performed on the data representing the state of the memory cell MC to calculate the data recorded in the memory cell MC. Additionally, the data is transferred to the cache memory CM (Figure 4).

[0107] [Write action] Next, the writing operation of the memory die MD in this embodiment will be explained. Figure 13 is a flowchart for explaining the writing operation.

[0108] Furthermore, the following description illustrates an example of performing a write operation on multiple selected memory cells MC corresponding to the selected page PG S.

[0109] In step S101, the loop count nW is set to 1. The loop count nW is a variable representing the number of loops written.

[0110] In step S102, a program action is executed. The program action is to supply a program voltage V PGM (Figure 15) to the select word line WLS, thereby increasing the threshold voltage of the memory cell MC.

[0111] In step S103, a verification operation is performed. The verification operation is basically performed in the same way as the read operation described with reference to Figures 11 and 12. However, in the verification operation, instead of the specified read voltage VCGR, verification voltages VVFYA to VVFYG, as described with reference to Figures 10(a) to 10(c), are supplied to the select word line WLS to detect the on / off state of the memory cell MC and to detect whether the threshold voltage of the memory cell MC has reached the target value.

[0112] In step S104, the result of the verification operation is determined. For example, referring to a counter circuit (not shown), the number of memory cells MC whose threshold voltage has not reached the target value is counted. Furthermore, if the number of memory cells MC whose threshold voltage has not reached the target value is a certain number or more, the verification is determined to be FAIL, and the process proceeds to step S105. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is less than a certain number, the verification is determined to be PASS, and the process proceeds to step S107.

[0113] In step S105, it is determined whether the number of iterations nW has reached the predetermined number NW. If not, proceed to step S106. If so, proceed to step S108.

[0114] In step S106, the loop count nW is incremented by 1, and the process proceeds to step S102. Additionally, in step S106, for example, the program voltage V PGM (Figure 15) supplied to the selection word line WLS during program operation is increased only by a predetermined voltage ΔV. Therefore, the program voltage V PGM increases with the increase of the loop count nW.

[0115] In step S107, the status data Stt indicating that the write operation has been completed normally is saved in the status register STR (Figure 4), and the write operation ends. Furthermore, the status data Stt is output to the controller chip CD (Figure 1) through the status read operation.

[0116] In step S108, the status data Stt indicating that the write operation did not end properly is saved in the status register STR (Figure 4), and the write operation ends.

[0117] Figure 14 is a timing diagram illustrating the write operation. Figure 15 is a schematic cross-sectional view illustrating the write operation. Figure 15 shows the voltages supplied from time t113 to time t114 in Figure 14.

[0118] Hereinafter, the cell in the multiple select memory cells MC that performs threshold voltage adjustment is sometimes called the "write memory cell MC", and the cell that does not perform threshold voltage adjustment is called the "disable memory cell MC".

[0119] For example, as shown in Figure 14, at the time t110 of the write operation, the controller chip CD sequentially inputs the command data Cmd (Figure 4) and the address data Add (Figure 4) indicating the write operation to the memory chip MD. This occurs during the period when the RY / ( / BY) terminal is in the "L" state (busy period).

[0120] At times t110 to t111, for example, a voltage VSRC is supplied to the bit line BLW (Fig. 15) connected to the write memory cell MC, and a voltage VDD is supplied to the bit line BL connected to the disable memory cell MC. In addition, a voltage VSRC is supplied to the source line SL (semiconductor layer 112).

[0121] At time t111, voltage VSG is supplied to the drain-side selected gate line SGD S and the drain-side selected gate line SGD U, and all drain-side selected transistors STD are set to the ON state.

[0122] At time t112, a voltage VSGD is supplied to the drain-side select gate line SGD S. The voltage VSGD is less than the voltage VSG and has the magnitude to which the drain-side select transistor STD is turned on or off based on the voltage of the bit line BL. Additionally, a ground voltage VSS is supplied to the drain-side select gate line SGD U and the source-side select gate line SGS, setting the select transistors (STD, STS) connected to these lines to the off state. Furthermore, a write path voltage VPASS is supplied to the select word line WLS and the non-select word line WLU. The write path voltage VPASS may have the same magnitude as the read path voltage VREAD as described with reference to FIG12, or it may be greater than the read path voltage VREAD.

[0123] At time t113, a program voltage V PGM is supplied to the select word line WLS. The program voltage V PGM is greater than the write path voltage V PASS.

[0124] Here, for example as shown in Figure 15, a voltage VSRC is supplied from the bit line BL to the channel of the semiconductor layer 120 connected to the bit line BL W. A relatively large electric field is generated between this semiconductor layer 120 and the select word line WLS. As a result, electrons in the channel of the semiconductor layer 120 tunnel through the tunnel insulating film 131 (Figure 9) into the charge storage film 132 (Figure 9). This increases the threshold voltage for writing to the memory cell MC.

[0125] Furthermore, the channels of semiconductor layer 120 connected to bit lines BL other than BL W become electrically floating. The potential of these channels rises to approximately the write path voltage V PASS through capacitive coupling with the non-select word line WLU. In this configuration, only a smaller electric field than the aforementioned electric field is generated between semiconductor layer 120 and the select word line WLS. Therefore, electrons in the channels of semiconductor layer 120 do not tunnel through the charge accumulation film 132 (FIG. 9). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0126] At time t114, ground voltage VSS is supplied to the select word line WLS, the non-select word line WLU, the drain-side select gate line SGDS, the drain-side select gate line SGDU, and the source-side select gate line SGS.

[0127] At time t115, the write operation in the memory die MD ends. In addition, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0128] [Memory block erase action] Next, the memory block erasure operation of the memory die MD in this embodiment will be explained. Figure 16 is a flowchart for explaining the erasure operation.

[0129] Furthermore, the following description illustrates an example of performing an erase operation on the selected memory block BLK tb, which is the object of the action.

[0130] For example, as shown in Figure 16, in step S111, the number of cycles nE is set to 1. The number of cycles nE is a variable representing the number of erasure cycles.

[0131] In step S112, an erase voltage supply operation is performed. The erase voltage supply operation is to supply a ground voltage VSS to the word line WL and a voltage VERA (Figure 18; sometimes referred to as the erase voltage) to at least one of the source line SL and the bit line BL, thereby reducing the threshold voltage of the memory cell MC.

[0132] In step S113, an erase verification operation is performed. The erase verification operation is used to supply an erase verification voltage VFYEr to the character line WL, detect the on / off state of the memory cell MC, and detect whether the threshold voltage of the memory cell MC has reached the target value.

[0133] In step S114, the result of the erase verification operation is determined. For example, referring to the counter circuit, the number of memory cells MC whose threshold voltage has not reached the target value is counted. Furthermore, if the number of memory cells MC whose threshold voltage has not reached the target value is a certain number or more, the verification is deemed unsuccessful, and the process proceeds to step S115. On the other hand, if the number of memory cells MC whose threshold voltage has not reached the target value is less than a certain number, the verification is deemed successful, and the process proceeds to step S117.

[0134] In step S115, it is determined whether the number of iterations nE has reached the predetermined number NE. If not, proceed to step S116. If so, proceed to step S118.

[0135] In step S116, the cycle count nE is incremented by 1, and the process proceeds to step S112. Additionally, in step S116, a predetermined voltage ΔV is added to the voltage VERA (Fig. 18) supplied to at least one of the source line SL and bit line BL during the erase voltage supply operation, for example. Therefore, the voltage VERA (Fig. 18) increases with the cycle count nE.

[0136] In step S117, the status data Stt indicating that the erasure operation has ended normally is saved in the status register STR (Figure 4), and the erasure operation ends. Furthermore, the status data Stt is output to the controller chip CD (Figure 1) through the status read operation.

[0137] In step S118, the state data Stt indicating that the erasure operation did not end properly is saved in the state temporary register STR (Figure 4), and the erasure operation ends.

[0138] Figure 17 is a timing diagram illustrating the erasing operation. Figure 18 is a schematic cross-sectional view illustrating the erasing operation. Figure 18 shows the voltages supplied at times t122 ​​to t123 in Figure 17.

[0139] At the moment of the erase operation t120, the controller chip CD sequentially inputs the command data Cmd and the address data Add indicating the erase operation to the memory chip MD. During this period, the RY / ( / BY) terminal becomes "L" (busy period).

[0140] At the erase operation time t121, voltage VERA-V1 is supplied to the select gate lines (SGD, SGS) and ground voltage VSS is supplied to the word line WL. Furthermore, the voltage VERA-V1 supplied to the select gate lines (SGD, SGS) is greater than the ground voltage VSS supplied to the word line WL. Additionally, voltage VERA is supplied to the bit line BL and the source line SL (semiconductor layer 112). Furthermore, at the erase operation time t121, voltage VERA-V1 may also be supplied to either the drain-side select gate line SGD or the source-side select gate line SGS. When voltage VERA-V1 is supplied to the drain-side select gate line SGD, voltage VERA may also be supplied to the bit line BL. When voltage VERA-V1 is supplied to the source-side select gate line SGS, voltage VERA may also be supplied to the source line SL.

[0141] Between time t122 ​​and time t123, the data written to the memory cell MC is erased by the gate-induced drain leakage (GIDL) described later.

[0142] At time t123, ground voltage VSS is supplied to bit line BL, select gate line (SGD, SGS) and word line WL.

[0143] At time t124, the erase operation in the memory die MD is completed. In addition, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0144] [GIDL-based erasure action] During time intervals t122 ​​to t123 in Figure 17, as shown in Figure 18, a voltage VERA-V1 is supplied to the gate electrode of the selective transistor (STD, STS) via the selective gate line (SGD, SGS). Additionally, a voltage VERA is supplied to the channel region of the selective transistor (STD, STS) via the bit line BL and the source line SL. Therefore, a voltage V1 is applied between the gate electrode and the channel region of the selective transistor (STD, STS).

[0145] The voltage V1 is, for example, a voltage of the magnitude of GIDL generated near the channels of the selective transistors (STD, STS) (on the surface of semiconductor layer 120). By means of GIDL, electron-hole pairs are generated near the respective channels of the selective transistors (STD, STS), for example as shown in FIG18.

[0146] Electrons generated in the drain-side selective transistor (STD) are supplied to the bit line BL, and holes are supplied to the memory cell MC. Electrons generated in the source-side selective transistor (STS) are supplied to the source line SL, and holes are supplied to the memory cell MC. Consequently, holes accumulate in the channel region of the memory cell MC, and the voltage in the channel region of the memory cell MC increases.

[0147] Additionally, at times t122 ​​to t123 in Figure 17, a ground voltage VSS is supplied to the character line WL. Therefore, a voltage of approximately VERA is applied between the gate electrode and channel regions of the memory cell MC. This voltage represents the extent to which the electrical holes supplied by GIDL tunnel through the tunnel insulating film 131 and reach the charge storage film 132.

[0148] In this way, the holes generated by GIDL are accumulated in the charge storage film 132 (Fig. 9) of all memory cells MC contained in the selected memory block BLK tb, thereby reducing the threshold voltage of the memory cells MC and erasing the data of the memory cells MC.

[0149] [Erase verification action] Figure 19 is a schematic cross-sectional view illustrating the erase verification operation. For example, as shown in Figure 19, during the erase verification operation, a voltage VSG is supplied to the drain-side select gate line SGD S and the source-side select gate line SGS of the serial cell SUa, turning on the select transistors STD and STS connected to them. Additionally, a ground voltage VSS is supplied to the drain-side select gate lines SGD U of the other serial cells SUb to SUe, turning off the select transistors STD connected to them. Furthermore, an erase verification voltage VVFYEr is supplied to the word line WL to detect whether the threshold voltage of the memory cell MC contained in the serial cell SUa has reached the target value.

[0150] [Sub-block erase mode] With the increasing integration of semiconductor memory devices, the number of bits in each memory block (BLK) increases. Consequently, the number of erase units increases, and the number of write operations during waste collection increases. Therefore, the semiconductor memory device of the first embodiment is configured to operate in a sub-block erase mode. In the sub-block erase mode, a memory block (BLK) can be divided into two sub-blocks, and each sub-block is used as an erase unit. For example, in the sub-block erase mode, the structure contained in the memory cell array layer L MCA1 (described with reference to FIG8) within the memory block (BLK) is designated as one sub-block (SB1), and the structure contained in the memory cell array layer L MCA2 is designated as another sub-block (SB0).

[0151] [Select erase action (1)] The semiconductor memory device of this embodiment is configured to perform a selective erase operation (1). Figure 20 is a flowchart for explaining the selective erase operation (1).

[0152] In the example shown below, in memory block BLK, a write operation is performed on sub-block SB0 first, followed by a write operation on sub-block SB1.

[0153] Additionally, in the following explanation, when subblock SB is in a fully erased state, it means that all pages PG contained in subblock SB and all memory cells MC contained in page PG are in an erased state.

[0154] In step S121, it is determined whether sub-block SB1 is in a completely erased state. If sub-block SB1 is in a completely erased state, proceed to step S122; if sub-block SB1 is not in a completely erased state, proceed to step S123. Furthermore, the action of determining whether sub-block SB1 is in a completely erased state will be described later.

[0155] In step S122, the sub-block SB0 erasure operation described later is performed.

[0156] In step S123, the memory block erasure operation is performed (Figure 16).

[0157] [Action to determine whether sub-block SB1 is in a completely erased state] Figures 21-23 are schematic diagrams illustrating examples of the write status of sub-blocks.

[0158] Furthermore, Figures 21-23, 31-34, 41-44, and 46-51 below show the write status of page PGs corresponding to the multiple character lines WL and four string units SU0, SU1, SU2, and SU3 set in the memory block BLK. The write status of page PGs is shown as either write state Pg or erase state Er.

[0159] Furthermore, in the examples shown in Figures 21-23, 31-34, and 54-57, a total of 96 character lines WL are set. The nth character line WL (where n is an integer from 1 to 96) counting from one side is represented as character line WL(n-1). In the examples of Figures 21 and 22, sub-block SB0 includes character lines WL0 to WL47, and sub-block SB1 includes character lines WL48 to WL95.

[0160] In the examples shown in Figures 21-23, 31-34 and 54-57, the write operation is performed from character line WL0 to character line WL95 in ascending order of n in character line WL(n-1). In each character line WL, the write operation is performed in the order of string unit SU0, string unit SU1, string unit SU2 and string unit SU3.

[0161] This determination action is, for example, one of the actions performed inside the memory die MD when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0162] For example, as shown in Figures 21 and 22, in this action, the page PG_UF(1) that was initially written to in the page PG within subblock SB1 is read out. In the example shown in Figures 21 and 22, page PG_UF(1) is the page PG corresponding to the character line WL48 and string unit SU0 of subblock SB1.

[0163] Figure 21 shows the case where sub-block SB1 is in a completely erased state, but sub-block SB0 is not in a completely erased state. In this case, if the result obtained by the read operation is that page PG_UF(1) is in the erased state Er, it can be determined that sub-block SB1 is in a completely erased state.

[0164] Figure 22 shows the case where subblock SB1 is not in a completely erased state. If the result of the read operation shows that page PG_UF(1) is in a write state Pg, it can be determined that subblock SB1 is not in a completely erased state.

[0165] [Sub-block SB0 erase action] The subblock SB0 erase operation erases the data in all memory cells MC of subblock SB0. The subblock SB0 erase operation is performed in essentially the same way as the memory block erase operation (Figure 16). However, the erase voltage supply operation performed in the subblock SB0 erase operation is different from the erase voltage supply operation performed in the memory block erase operation (Figure 16).

[0166] Figure 24 is a timing diagram illustrating the sub-block SB0 erasure operation. Figure 25 is a schematic cross-sectional view illustrating the sub-block SB0 erasure operation.

[0167] As shown in Figures 24 and 25, at the moment t131 of the sub-block SB0 erasure operation, voltages VERA-V1 are supplied to the selected gate lines (SGD, SGS) respectively, and voltage VERA is supplied to the bit line BL and the source line SL (semiconductor layer 112).

[0168] Additionally, a ground voltage VSS is supplied to the word line WL of sub-block SB0. Simultaneously, a voltage of approximately VERA is applied between the gate electrode and channel regions of the memory cell MC in sub-block SB0.

[0169] Additionally, a non-selective erase voltage VX, larger than the ground voltage VSS, is supplied to the word line WL of sub-block SB1. Simultaneously, a voltage VERA-VX, smaller than the voltage VERA, is applied between the gate electrode and channel regions of the memory cell MC in sub-block SB1. The voltage VERA-VX is such that even when the memory cell MC in sub-block SB1 is in the Er state, i.e., when electrons are not accumulated in the charge accumulation film 132, holes will not tunnel through the tunnel insulating film 131. Furthermore, the voltage VERA-VX has the degree to which the memory cell MC is turned on when it operates as a P-type metal oxide semiconductor (PMOS) transistor.

[0170] Between time t132 and time t133, in the memory cell MC of sub-block SB0, the data in the memory cell MC is erased because holes in the tunnel insulating film 131 are deposited in the charge storage film 132 (Fig. 9). On the other hand, in the memory cell MC of sub-block SB1, the threshold voltage of the memory cell MC does not drop further (over-erasure) because holes do not tunnel through the tunnel insulating film 131.

[0171] Furthermore, during the erase voltage supply operation performed in the sub-block SB0 erase operation, as shown in Figure 25, holes generated near the channel of the select transistor STS can also be used to erase the memory cell MC. Alternatively, holes generated near the channel of the select transistor STD can be transmitted to sub-block SB0 via the channel region corresponding to sub-block SB1 for the erasure of the memory cell MC.

[0172] At time t133, ground voltage VSS is supplied to bit line BL, select gate line (SGD, SGS), word line WL of sub-block SB0 and sub-block SB1, and source line SL.

[0173] [Example of the erase action (1)] The action when subblock SB1 is in a completely erased state (Fig. 21) is called action example EX10. In action example EX10, in step S121, the PG_UF(1) is read. In addition, the subblock SB0 is erased in step S122, and all pages PG contained in memory block BLK are erased to the Er state (Fig. 23).

[0174] The action when subblock SB1 is not in a completely erased state (Fig. 22) is called action example EX11. In action example EX11, in step S121, the PG_UF(1) is read. In addition, in action example EX11, the memory block erase action in step S123 is performed, and all pages PG contained in memory block BLK are in the erased state Er (Fig. 23).

[0175] [Critical voltage distribution of memory cell MC during erase operation] Figures 26 and 28 are graphs used to illustrate the semiconductor memory device of this embodiment. Furthermore, Figures 26 to 28 below show the median value of the threshold voltage of multiple memory cells MC within the page PG corresponding to each word line WL, with word line WL0 to word line WL95 as the horizontal axis.

[0176] Figure 26 corresponds to the case where subblock SB0 is in a partially written state and subblock SB1 is in a completely erased state (Figure 21). Since the page PG corresponding to the multiple word lines WL on one side of subblock SB0 is in a written state Pg, the median threshold voltage is, for example, around voltage VPi (group Db_01p in Figure 26). Since the page PG corresponding to the multiple word lines WL on the other side of subblock SB0 is in an erased state Er, the median threshold voltage is, for example, around voltage VE0 (group Db_02e in Figure 26). Since the page PG corresponding to all word lines WL of subblock SB1 is in an erased state Er, the median threshold voltage is, for example, around voltage VE0 (group Db_10e in Figure 26).

[0177] [Comparative Example] Next, the comparative example semiconductor memory device will be described. Figure 27 is a graph used to describe the comparative example semiconductor memory device. In the comparative example semiconductor memory device, a memory block erase operation is performed regardless of the write status of the sub-block.

[0178] Figure 27 shows the memory block BLK in the states corresponding to Figures 21 and 26 when a memory block erase operation (Figure 16) has been performed. During the memory block erase operation, the page PG corresponding to the multiple word lines WL on one side of sub-block SB0 becomes an erased state Er after being written to, and the median value of the threshold voltage becomes, for example, around voltage VE0 (group Db_01e in Figure 27). On the other hand, from the erased state Er, a voltage of approximately VERA is further applied between the gate electrode and channel regions of the memory cell MC, thereby causing the holes to be over-injected into the charge storage film 132 (Figure 9), and the median value of the threshold voltage becomes, for example, a voltage VEX lower than voltage VE0 (group Db_02ex in Figure 27). In addition, the same applies to the page PG contained in all character lines WL of subblock SB1, and the median value of the threshold voltage is, for example, voltage VEX (group Db_10ex in Figure 27).

[0179] The following, as in groups Db_02ex and Db_10ex, refers to a situation where the threshold voltage after an erase operation is lower than the normal voltage VE0 by a voltage VEX, which is called an over-erased state. When a high voltage is applied to the gate electrode of the memory cell MC until it reaches an over-erased state, excessive stress is added to the gate insulating film of the memory cell MC. In this case, the data retention characteristics of the memory cell MC may sometimes be degraded.

[0180] Figures 29(a) and 29(b) are histograms used to illustrate the semiconductor memory device of the comparative example. In Figures 29(a) and 29(b), the horizontal axis represents the threshold voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0181] Figure 29(a) shows the critical voltage distribution of multiple memory cells MC in the original Er state (solid line, median value is voltage VE0) and the critical voltage distribution of multiple memory cells MC in the over-erased Er state (dashed line, median value is voltage VEX).

[0182] Figure 29(b) shows the threshold voltage distribution (solid line) when writing from the original Er state to states A through G respectively, and the threshold voltage distribution (dashed line) when writing from the over-erased Er state to states A through G respectively. Thus, if states A through G written from different Er states are mixed, the threshold voltage distribution of each state may widen, leading to read failures and reduced reliability.

[0183] [Effect] In this embodiment, the semiconductor memory device, by selecting the erase operation (1), does not supply erase voltage to the memory cells MC contained in the sub-block SB1 in the fully erased state.

[0184] Figure 28 shows the memory block BLK in the state corresponding to Figures 21 and 26 when a selective erase operation (1) is performed. By not supplying an erase voltage to the sub-block SB1 in the fully erased state, the median value of the threshold voltage is, for example, the maintenance voltage VE0 (group Db_10e in Figure 28). Therefore, a semiconductor memory device can be provided that prevents excessive stress on the memory cells MC contained in the sub-block SB1 and prevents the memory cells MC from becoming over-erased, thus exhibiting good data retention characteristics and reliability.

[0185] [Variations of the first implementation] In this modified example of the semiconductor memory device, the controller die CD includes a temporary register RG capable of recording the erase and write states of sub-block units.

[0186] In step S121 (Figure 20) of this variant example, the controller refers to the temporary register RG, etc., to determine whether the sub-block SB1 is in a completely erased state.

[0187] In step S122 (Figure 20) of this variant, the controller sends a command instructing the sub-block SB0 to erase to the memory die MD, and the memory die MD executes the sub-block SB0 erase operation.

[0188] In step S123 (Figure 20) of this variant, the controller sends a command instructing the memory block erase operation to the memory die MD, and the memory die MD performs the memory block erase operation (Figure 16).

[0189] [Second Implementation Form] Next, the semiconductor memory device of the second embodiment will be described. Furthermore, in the following description, structures and operations that are the same as those in the first embodiment will sometimes be omitted.

[0190] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of this embodiment is configured to perform a selective erase operation (2).

[0191] [Select erase action (2)] Figure 30 is a flowchart illustrating the selection of the erasure action (2).

[0192] Furthermore, in the following example, in memory block BLK, a write operation is performed on sub-block SB0 first, followed by a write operation on sub-block SB1.

[0193] Furthermore, in the following explanation, when subblock SB is in a partially written state, it means that a portion of the pages PG contained in subblock SB are in a written state (Pg), and the other pages PG are in an erased state (Er). Additionally, when subblock SB is not in a partially written state, or when subblock SB is in a fully written state, it means that all pages PG contained in subblock SB are in a written state (Pg).

[0194] In step S201, it is determined whether sub-block SB1 is in a completely erased state. If sub-block SB1 is in a completely erased state, proceed to step S202; if sub-block SB1 is not in a completely erased state, proceed to step S205. Step S201 is performed in the same way as step S121 (Figure 20).

[0195] In step S202, it is determined whether sub-block SB0 is in a partially written state. If sub-block SB0 is in a partially written state, proceed to step S203; if sub-block SB0 is in a fully written state, proceed to step S204. Furthermore, the action of determining whether sub-block SB0 is in a partially written state will be described later.

[0196] In step S203, the preprogram of sub-block SB0 (described later) is executed, and the process proceeds to step S204.

[0197] In step S204, the sub-block SB0 erasure operation is performed. Step S204 is performed in the same manner as step S122 (Figure 20).

[0198] In step S205, it is determined whether sub-block SB1 is in a partially written state. If sub-block SB1 is in a partially written state, proceed to step S206; if sub-block SB1 is in a fully written state, proceed to step S207. Furthermore, the action of determining whether sub-block SB1 is in a partially written state will be described later.

[0199] In step S206, the pre-program of sub-block SB1 (described later) is executed, and the process proceeds to step S207.

[0200] In step S207, a memory block erasure operation is performed (Figure 16).

[0201] [Action to determine whether sub-block SB0 is in a partial write state] Figures 31-34 are schematic diagrams illustrating examples of the write status of sub-blocks.

[0202] This action is, for example, one of the actions performed inside the memory die MD when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0203] Furthermore, prior to this action, for example, a read operation is performed on page PG_UF(1) (step S201). This action is performed when page PG_UF(1) is in the erase state Er.

[0204] For example, as shown in Figure 31, in this action, the page PG_LE(2) that was last written to in the page PG within subblock SB0 is read. In the example shown in Figure 31, page PG_LE(2) is the page PG corresponding to the character line WL47 and string unit SU3 of subblock SB0.

[0205] Figure 31 shows the case where subblock SB1 is in a completely erased state and subblock SB0 is in a partially written state. In this case, if the page PG_LE(2) is in the erased state Er by the read operation, as shown in Figure 31, it can be determined that subblock SB0 is in a partially written state.

[0206] [Action to determine whether sub-block SB1 is in a partial write state] This action is, for example, one of the actions performed inside the memory die MD when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0207] Furthermore, prior to this action, for example, a read operation of page PG_UF(1) is performed (step S201). This action is performed when page PG_UF(1) is in write state Pg.

[0208] For example, as shown in Figure 32, in this action, the page PG_UE(2) that was last written to in the page PG within subblock SB1 is read out. In the example shown in Figure 32, page PG_UE(2) is the page PG corresponding to the character line WL95 and the string unit SU3 of subblock SB1.

[0209] Figure 32 shows the case where subblock SB1 is in a partially written state. As shown in Figure 32, if page PG_UE(2) is in the erase state Er after the read operation, it can be determined that subblock SB1 is in a partially written state.

[0210] [Pre-programs for sub-blocks SB0 and SB1] Figures 35 and 36 are schematic cross-sectional views used to illustrate the pre-programmed code for sub-blocks SB0 and SB1.

[0211] The pre-programming of sub-block SB0 and sub-block SB1 is basically the same as the write operation (Figures 13-15).

[0212] However, in the programming operation of subblock SB0 in step S102 (Fig. 13), for example as shown in Fig. 35, all word lines WL of subblock SB0 are set as selected word lines WL S, and all word lines WL of subblock SB1 are set as non-selected word lines WL U. This supplies a programming voltage V PGM (Fig. 35) to the word lines WL of subblock SB0, increasing the threshold voltage of the write memory cells MC contained in subblock SB0.

[0213] Furthermore, in the programming operation of sub-block SB1 in step S102 (Fig. 13), for example as shown in Fig. 36, all word lines WL of sub-block SB1 are set as selected word lines WL S, and all word lines WL of sub-block SB0 are set as non-selected word lines WL U. This supplies a programming voltage V PGM (Fig. 36) to the word lines WL of sub-block SB1, increasing the threshold voltage of the write memory cells MC contained in sub-block SB1.

[0214] Furthermore, these preprograms can be performed on each string unit SU (Figures 35 and 36), or on multiple string units SU simultaneously.

[0215] By pre-programming subblock SB0 as shown in Figure 31, as shown in Figure 33, subblock SB0 becomes fully written. By pre-programming subblock SB1 as shown in Figure 32, as shown in Figure 34, subblock SB1 becomes fully written.

[0216] Furthermore, in the pre-programmed code for sub-blocks SB0 and SB1, steps S103 to S108 related to the verification action may not be performed (Figure 13).

[0217] In addition, in the preprogramming of sub-blocks SB0 and SB1, the time (time t113 to time t114) for supplying the program voltage V PGM to the selection character line WLS can also be longer than the example shown in Figure 14.

[0218] [Example of the erase action (2)] The action of setting subblock SB1 to a fully erased state and subblock SB0 to a partially written state (Figure 31) is called action example EX20. In action example EX20, after setting subblock SB0 to a fully written state by the pre-programmed step S203 (Figure 30) (Figure 33), the subblock SB0 erase action in step S204 is performed, so that all pages PG become erased state Er (Figure 23).

[0219] The action when subblock SB1 is in a fully erased state and subblock SB0 is in a fully written state is called action example EX21. In action example EX21, step S203 (Figure 30) is skipped, and the subblock SB0 erase action in step S204 is performed, so that all pages PG become erased state Er (Figure 23).

[0220] The action of setting subblock SB1 to a partially written state (Figure 32) is called action example EX22. In action example EX22, after setting subblock SB1 to a fully written state by the pre-program in step S206 (Figure 30) (Figure 34), the memory block erase action in step S207 is performed, so that all pages PG become erased state Er (Figure 23).

[0221] The action of setting subblock SB1 to a fully written state is called action example EX23. In action example EX23, step S206 (Figure 30) is skipped, and the memory block erasure action of step S207 is performed, so that all pages PG become erased state Er (Figure 23).

[0222] [Effect] Figures 37 and 38 are graphs used to illustrate the semiconductor memory device of this embodiment. Figures 37 and 38 use word lines WL0 to WL95 as the horizontal axis to represent the median value of the threshold voltage of multiple memory cells MC within the page PG corresponding to each word line WL.

[0223] Figure 37 shows the pre-programming of subblock SB0 corresponding to Figure 31. Through pre-programming, the page PG self-erasure state Er corresponding to the multiple word lines WL on the other side of subblock SB0 becomes the write state Pg, and the median value of the threshold voltage increases to, for example, around V Pi (group Db_02p in Figure 37).

[0224] Figure 38 shows the subblock SB0 erase operation performed after the pre-programming of subblock SB0 (Figure 37). The page PG in the erase state Er in subblock SB0 disappears due to the pre-programming, so as shown in Figure 38, the memory cell MC within subblock SB0 will not become over-erased during the subblock SB0 erase operation.

[0225] In action examples EX20 and EX21, by performing the erase operation only on sub-block SB0 in step S204, the memory cell MC contained in sub-block SB1 is prevented from becoming over-erased.

[0226] In action examples EX20 and EX22, the pre-programmed steps S203 and S206 prevent a portion of the erased state Er pages in sub-blocks SB0 and SB1 from becoming over-erased.

[0227] In action examples EX21 and EX23, by skipping the pre-programming in steps S203 and S206, write stress on the memory cell MC is prevented due to unnecessary pre-programming.

[0228] [Example of a variation of the second implementation] In this modified example of the semiconductor memory device, the controller die CD includes a temporary register RG capable of recording the erase and write states of sub-block units.

[0229] In step S201 (Figure 30) of this variant example, the controller refers to the temporary register RG, etc., to determine whether the sub-block SB1 is in a completely erased state.

[0230] In steps S202 and S205 (Figure 30) of this variant example, the controller refers to the temporary register RG, etc., to determine whether sub-block SB0 and sub-block SB1 are in a partially written state.

[0231] In steps S203 and S206 (Figure 30) of this variant example, the controller sends commands indicating the preprogrammed routines for sub-block SB0 and sub-block SB1 to the memory die MD, and the memory die MD executes the preprogrammed routines for sub-block SB0 and sub-block SB1, respectively.

[0232] In step S204 (Figure 30) of this variant, the controller sends a command instructing the sub-block SB0 to erase the sub-block SB0 to the memory die MD, and the memory die MD executes the sub-block SB0 erase operation.

[0233] In step S207 (Figure 30) of this variant, the controller sends a command instructing the memory block erase operation to the memory die MD, and the memory die MD performs the memory block erase operation (Figure 16).

[0234] [Third Implementation Form] Next, the semiconductor memory device of the third embodiment will be described. Figure 39 is a schematic perspective view showing a portion of the structure of the semiconductor memory device of the third embodiment. Furthermore, in the following description, structures and operations identical to those of the first embodiment will sometimes be omitted.

[0235] The semiconductor memory device of this embodiment is basically constructed in the same manner as the semiconductor memory device of the first embodiment. However, for example, as shown in FIG39, the memory block BLK of the semiconductor memory device of this embodiment further includes a memory cell array layer LMCA3 disposed above the memory cell array layer LMCA2.

[0236] The memory cell array layer L MCA3 is configured in a manner substantially similar to that of memory cell array layers L MCA1 and L MCA2. The memory cell array layer L MCA3 includes, for example, a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120. An insulating layer 151, such as silicon oxide (SiO2), is disposed between the memory cell array layer L MCA3 and the memory cell array layer L MCA2.

[0237] Furthermore, the semiconductor memory device of this embodiment is configured to perform a selective erase operation (3).

[0238] [Select erase action (3)] Figure 40 is a flowchart illustrating the selection of the erasure action (3).

[0239] Furthermore, in the following example, in memory block BLK, the write operation is performed first on sub-block SB0, followed by the write operations in the order of sub-block SB1, and then sub-block SB2.

[0240] In step S301, it is determined whether sub-block SB2 is in a completely erased state. If sub-block SB2 is in a completely erased state, proceed to step S302; if sub-block SB2 is not in a completely erased state, proceed to step S305. Furthermore, the action of determining whether sub-block SB2 is in a completely erased state will be described later.

[0241] In step S302, it is determined whether sub-block SB1 is in a completely erased state. If sub-block SB1 is in a completely erased state, proceed to step S303; if sub-block SB1 is not in a completely erased state, proceed to step S304. Step S302 is performed in the same way as step S121 (Figure 20).

[0242] In step S303, the sub-block SB0 is erased. Step S303 is essentially the same as step S122 (FIG. 20). However, in this step, the same non-selective erase voltage VX is supplied to the word line WL of sub-block SB2 as to sub-block SB1.

[0243] In step S304, the erase operations for sub-blocks SB0 and SB1 are performed. Step S304 is essentially the same as step S122 (FIG. 20). However, at time t132 (FIG. 24) of this operation, a ground voltage VSS is supplied to the word lines WL of sub-blocks SB0 and SB1, and a non-selective erase voltage VX is supplied to the word lines WL of sub-block SB2. Therefore, the memory cells MC contained in sub-block SB2 are not erased.

[0244] In step S305, the same action as the memory block erase action (Fig. 16) is performed. However, at the moment t122 ​​of the action (Fig. 17), the same ground voltage VSS as that of the word lines WL of sub-block SB2 and sub-block SB1 is also supplied to the word line WL.

[0245] [Action to determine whether sub-blocks SB1 and SB2 are in a completely erased state] Figures 41-44 are schematic diagrams illustrating examples of the write status of sub-blocks.

[0246] This action is, for example, one of the actions performed inside the memory die MD when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0247] Furthermore, in the examples shown in Figures 41-44 and 46-51, a total of 144 character lines WL are set. The m-th character line WL (where m is an integer from 1 to 144) counting from the bottom layer is represented as character line WL(m-1). In the examples of Figures 41-44, sub-block SB0 includes character lines WL0 to WL47, sub-block SB1 includes character lines WL48 to WL95, and sub-block SB2 includes character lines WL96 to WL143.

[0248] Furthermore, in the examples shown in Figures 41 to 44 and Figures 46 to 51, the write operation is performed from character line WL0 to character line WL143 in ascending order of m in character line WL(m-1). In each character line WL, the write operation is performed in the order of serial unit SU0, serial unit SU1, serial unit SU2, and serial unit SU3.

[0249] For example, as shown in Figures 41-43, in this action, the page PG_TF(1) that was initially written to in the page PG within subblock SB2 is read out. In the examples shown in Figures 41-43, page PG_TF(1) is the page PG corresponding to the character line WL96 and string unit SU0 of subblock SB2.

[0250] Figures 41 and 42 show the case where subblock SB2 is in a completely erased state. Figure 43 shows the case where subblock SB2 is not in a completely erased state. When page PG_TF(1) is in the erase state Er, it can be determined that subblock SB2 is in a completely erased state (Figures 41 and 42). When page PG_TF(1) is in the write state Pg, it can be determined that subblock SB2 is not in a completely erased state (Figure 43).

[0251] When page PG_TF(1) is in the erase state Er, in step S302 (Fig. 40), the page PG_UF(2) that was initially written to in page PG within subblock SB1 is read. In the examples shown in Fig. 41 and Fig. 42, page PG_UF(2) is the page PG corresponding to the character line WL48 and string unit SU0 of subblock SB1.

[0252] Figure 41 shows the case where subblock SB1 is in a completely erased state. Figure 42 shows the case where subblock SB1 is not in a completely erased state. When page PG_UF(2) is in the erase state Er, it can be determined that subblock SB1 is in a completely erased state (Figure 41). When page PG_UF(2) is in the write state Pg, it can be determined that subblock SB1 is not in a completely erased state (Figure 42).

[0253] [Example of the erase action (3)] The action when sub-blocks SB1 and SB2 are in a completely erased state (Figure 41) is called action example EX30. In action example EX30, the sub-block SB0 erase action of step S303 is performed, as shown in Figure 44, and all pages PG contained in memory block BLK are in the erased state Er.

[0254] The action when only sub-block SB2 is in a fully erased state (Figure 42) is called action example EX31. In action example EX31, the erase operation of sub-blocks SB0 and SB1 in step S304 is performed, as shown in Figure 44. All pages PG contained in memory block BLK are in the erased state Er.

[0255] The action when sub-blocks SB0, SB1, and SB2 are not in a completely erased state (Figure 43) is called action example EX32. In action example EX32, the memory block erase action of step S305 is performed, as shown in Figure 44, and all pages PG contained in memory block BLK are in the erased state Er.

[0256] [Effect] In action example EX30, by performing the erase operation only on sub-block SB0 in step S303, the memory cells MC contained in sub-block SB1 and sub-block SB2 are prevented from becoming over-erased.

[0257] In action example EX31, by performing the erase operation only on sub-blocks SB0 and SB1 in step S304, the memory cell MC contained in sub-block SB2 is prevented from becoming over-erased.

[0258] [Example of a variation of the third implementation] In this modified example of the semiconductor memory device, the controller die CD includes a temporary register RG capable of recording the erase and write states of sub-block units.

[0259] In steps S301 and S302 of this variant, the controller refers to the temporary register RG, etc., to determine whether sub-block SB2 and sub-block SB1 are in a completely erased state.

[0260] In step S303 of this variation, the controller sends a command instructing the sub-block SB0 to erase to the memory die MD, and the memory die MD executes the sub-block SB0 erase operation.

[0261] In step S304 of this variant, the controller sends a command instructing the erase operation of sub-block SB0 and sub-block SB1 to the memory die MD, and the memory die MD executes the erase operation of sub-block SB0 and sub-block SB1.

[0262] In step S305 of this variation, the controller sends a command instructing the memory block erase operation to the memory die MD, and the memory die MD performs the memory block erase operation (Figure 16).

[0263] [Fourth Implementation Form] Next, the semiconductor memory device of the fourth embodiment will be described. Furthermore, in the following description, structures and operations that are the same as those in the first to third embodiments will sometimes be omitted.

[0264] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the third embodiment. However, the semiconductor memory device of this embodiment is configured to perform a selective erase operation (4).

[0265] [Select erase action (4)] Figure 45 is a flowchart illustrating the selection of erase action (4). Figures 46 to 51 are schematic diagrams showing examples of the write status of sub-blocks.

[0266] Furthermore, in the following example, in memory block BLK, the write operation is performed first on sub-block SB0, followed by the write operations in the order of sub-block SB1, and then sub-block SB2.

[0267] In step S401, it is determined whether sub-block SB2 is in a completely erased state. If sub-block SB2 is in a completely erased state, proceed to step S402; if sub-block SB2 is not in a completely erased state, proceed to step S409. Step S401 is performed in the same way as step S301 (Figure 40).

[0268] In step S402, it is determined whether sub-block SB1 is in a completely erased state. If sub-block SB1 is in a completely erased state, proceed to step S403; if sub-block SB1 is not in a completely erased state, proceed to step S406. Step S402 is performed, for example, in the same way as step S302 (Figure 40).

[0269] In step S403, it is determined whether sub-block SB0 is in a partially written state. If sub-block SB0 is in a partially written state, proceed to step S404; if sub-block SB0 is in a fully written state, proceed to step S405. In step S403, the page PG_LE(3) (Figure 46) that was last written to the page PG in sub-block SB0 is read out to determine whether it is in a partially written state.

[0270] In step S404, the pre-program of sub-block SB0 is executed, and the process proceeds to step S405. Step S404 is essentially the same as step S203 (Figure 30). However, in step S404, in the program operation of step S102 (Figure 13), the character line WL of sub-block SB0 is set to the selected character line WL S, and the character lines WL of sub-blocks SB1 and SB2 are set to the non-selected character lines WL U.

[0271] In step S405, the sub-block SB0 erasure operation is performed. Step S405 is performed in the same way as step S303 (Figure 40).

[0272] In step S406, it is determined whether sub-block SB1 is in a partially written state. If sub-block SB1 is in a partially written state, proceed to step S407; if sub-block SB1 is in a fully written state, proceed to step S408. In step S406, the page PG_UE(3) (Figure 48) that was last written to the page PG in sub-block SB1 is read out to determine whether it is in a partially written state.

[0273] In step S407, the pre-program of sub-block SB1 is executed, and the process proceeds to step S408. Step S407 is essentially the same as step S206 (Figure 30). However, in step S407, the character line WL of sub-block SB1 is set to the selected character line WL S, and the character lines WL of sub-blocks SB0 and SB2 are set to the non-selected character lines WL U.

[0274] In step S408, the erase operations for sub-blocks SB0 and SB1 are performed. Step S408 is performed in the same manner as step S304 (Figure 40).

[0275] In step S409, it is determined whether sub-block SB2 is in a partially written state. If sub-block SB2 is in a partially written state, proceed to step S410; if sub-block SB1 is in a fully written state, proceed to step S411. In step S409, the page PG_TE(2) (Figure 50) that was last written to the page PG in sub-block SB2 is read out to determine whether it is in a partially written state.

[0276] In step S410, the pre-program of sub-block SB2 is executed, proceeding to step S411. Step S410 is essentially the same as step S407 (Figure 45). However, in step S410, the character line WL of sub-block SB2 is set to selected character line WL S, and the character lines WL of sub-blocks SB0 and SB1 are set to non-selected character lines WL U.

[0277] In step S411, a memory block erasure operation is performed (Figure 16).

[0278] [Example of the erase action (4)] The action of setting subblocks SB1 and SB2 to a fully erased state and subblock SB0 to a partially written state (Fig. 46) is called action example EX40. In action example EX40, in steps S401, S402, and S403, the read operations of pages PG_TF (1), PG_UF (2), and PG_LE (3) are performed respectively. In addition, in action example EX40, after setting subblock SB0 to a fully written state by step S404 (Fig. 45) (Fig. 47), the subblock SB0 is erased in step S405, so that all pages PG become erased state Er (Fig. 44).

[0279] The action of setting sub-blocks SB1 and SB2 to a completely erased state and sub-block SB0 to a completely written state is called action example EX41. Action example EX41 is basically the same as action example EX40, but step S404 is skipped in action example EX41 (Figure 45).

[0280] The action of setting subblock SB2 to a fully erased state and subblock SB1 to a partially written state (Fig. 48) is called action example EX42. In action example EX42, in steps S401, S402, and S406, the read operations of page PG_TF (1), page PG_UF (2), and page PG_UE (3) are performed respectively. In addition, in action example EX42, after setting subblock SB1 to a fully written state by step S407 (Fig. 45) (Fig. 49), the erase operation of subblock SB0 and subblock SB1 in step S408 is performed, so that all pages PG become erased state Er (Fig. 44).

[0281] The action of setting sub-block SB2 to a completely erased state and sub-block SB1 to a completely written state is called action example EX43. Action example EX43 is basically the same as action example EX42, but step S407 is skipped in action example EX43 (Figure 45).

[0282] The action of partially writing subblock SB2 (Fig. 50) is called action example EX44. In action example EX44, in steps S401 and S409, the read operations of page PG_TF (1) and page PG_TE (2) are performed respectively. In addition, in action example EX44, after setting subblock SB2 to a fully written state by step S410 (Fig. 45) (Fig. 51), the memory block BLK erase operation in step S411 is performed, so that all pages PG become erased state Er (Fig. 44).

[0283] The action of setting subblock SB2 to a fully written state is called action example EX45. Action example EX45 is basically the same as action example EX44, but step S410 is skipped in action example EX45 (Figure 45).

[0284] [Effect] In action examples EX40 and EX41, by performing the erase operation only on sub-block SB0 in step S405, the memory cells MC contained in sub-block SB1 and sub-block SB2 are prevented from becoming over-erased.

[0285] In action examples EX42 and EX43, by performing the erase operation only on sub-blocks SB0 and SB1 in step S408, the memory cell MC contained in sub-block SB2 is prevented from becoming over-erased.

[0286] In action examples EX40, EX42, and EX44, the pre-programmed steps S404, S407, and S410 prevent the page PG of a portion of the erased state Er contained in sub-blocks SB0, SB1, and SB2 from becoming over-erased.

[0287] In action examples EX41, EX43, and EX45, by skipping the pre-programming steps S404, S407, and S410, write stress on the memory cell MC is prevented due to unnecessary pre-programming.

[0288] [Example of a variation of the fourth implementation] In this modified example of the semiconductor memory device, the controller die CD includes a temporary register RG capable of recording the erase and write states of sub-block units.

[0289] In steps S401 and S402 of this variant, the controller refers to the temporary register RG, etc., to determine whether sub-block SB2 and sub-block SB1 are in a completely erased state.

[0290] In steps S403, S406, and S409 of this variant example, the controller refers to the temporary register RG, etc., to determine whether sub-block SB0, sub-block SB1, and sub-block SB2 are in a partially written state.

[0291] In steps S404, S407, and S410 of this variant, the controller sends commands indicating the preprogrammed sub-blocks SB0, SB1, and SB2 to the memory die MD, and the memory die MD executes the preprogrammed sub-blocks SB0, SB1, and SB2, respectively.

[0292] In step S405 of this variation, the controller sends a command instructing the sub-block SB0 to erase to the memory die MD, and the memory die MD executes the sub-block SB0 erase operation.

[0293] In step S408 of this variant, the controller sends a command instructing the erase operation of sub-block SB0 and sub-block SB1 to the memory die MD, and the memory die MD executes the erase operation of sub-block SB0 and sub-block SB1.

[0294] In step S411 of this variation, the controller sends a command instructing the memory block erase operation to the memory die MD, and the memory die MD performs the memory block erase operation (Figure 16).

[0295] [Fifth Implementation Form] Next, the semiconductor memory device of the fifth embodiment will be described. Furthermore, in the following description, structures and operations that are the same as those in the first to fourth embodiments will sometimes be omitted.

[0296] The semiconductor memory device of this embodiment is basically constructed in the same way as the semiconductor memory device of the second embodiment. However, the semiconductor memory device of this embodiment has two cases: one in which 3 bits are recorded in the memory cell MC (Figures 10(a) to 10(c)) and the other in which 1 bit is recorded in the memory cell MC (Figure 52). Furthermore, the case of recording 3 bits will sometimes be referred to as the 3-bit mode, and the case of recording 1 bit will be referred to as the 1-bit mode.

[0297] [Record the threshold voltage of the MC cell in a 1-bit memory cell] Figure 52 is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 1 bit of data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0298] In the example of Figure 52, the threshold voltage of the memory cell MC is controlled in two states. For example, the threshold voltage of the memory cell MC controlled in the low-order state is less than the erase verification voltage VVFYEr. On the other hand, the threshold voltage of the memory cell MC controlled in the high-order state is greater than the verification voltage VVFYS and less than the read path voltage VREAD.

[0299] Additionally, in the example of Figure 52, a readout voltage VCGR is set between the threshold distribution corresponding to the low-level state and the threshold distribution corresponding to the high-level state.

[0300] For example, a low-order state corresponds to a low threshold voltage. A memory cell MC in a low-order state is, for example, a memory cell MC in an erase state. For example, data "1" is allocated to a memory cell MC in a low-order state.

[0301] Additionally, the high-order state corresponds to a high threshold voltage. A memory cell MC in the high-order state is, for example, a memory cell MC in a write state. For example, allocating the data "0" to a memory cell MC in the high-order state.

[0302] Furthermore, the semiconductor memory device of this embodiment is configured to perform a selective erase operation (5).

[0303] [Select erase action (5)] Figure 53 is a flowchart illustrating the selection of erase action (5). Figures 54 to 57 are schematic diagrams showing examples of the write status of sub-blocks.

[0304] Furthermore, Figures 54-57 show the write status of page PGs corresponding to the multiple character lines WL and four string units SU0, SU1, SU2, and SU3 set in the memory block BLK. The write status of page PGs is shown as any one of the following: write status Pgs with 1 bit recorded, write status Pgt with 3 bits recorded, write status Pg after preprocessing, and erase status Er.

[0305] In the examples shown in Figures 54-57, within memory block BLK, the write operation is performed first on sub-block SB0, followed by the write operation on sub-block SB1. Furthermore, the write operations are performed in ascending order of n along word lines WL(n-1) from word line WL0 to word line WL95. Within each word line WL, the write operation is performed in the order of serial unit SU0, serial unit SU1, serial unit SU2, and serial unit SU3.

[0306] In step S501, if the selected memory block BLK has 3 bits recorded, proceed to step S502; if it has 1 bit recorded, proceed to step S506. In step S501, for example, the controller makes a determination by referring to information related to the selected memory block BLK held in the temporary register RG, etc.

[0307] In step S502, it is determined whether there are sub-blocks SB0 and SB1 in a partially written state. If there are sub-blocks SB0 and SB1 in a partially written state, proceed to step S503; if there are no sub-blocks SB0 and SB1 in a partially written state (sub-blocks SB0 and SB1 are in a fully written state), proceed to step S505. In step S502, for example, the controller makes the determination by referring to information related to sub-blocks SB0 and SB1 held in registers such as RG.

[0308] In step S503, a pre-program is executed on a portion of the sub-blocks SB0 and SB1 in the write state, and the process proceeds to step S504. In step S503, pages PG (unwritten pages) in the erase state Er contained in a portion of the sub-blocks SB0 and SB1 (in the example of Figure 54, sub-block SB0) in the write state are selected in sequence, and only pages PG in the erase state Er are pre-programmed and set to the write state Pg (Figure 55).

[0309] In step S504, the sub-block erasure operation is performed on the sub-block that was pre-programmed in step S503 (sub-block SB0 in the example of FIG55).

[0310] In step S505, a memory block erasure operation is performed (Figure 16).

[0311] In step S506, it is determined whether sub-blocks SB0 and SB1 are partially in a write state. If sub-blocks SB0 and SB1 are partially in a write state, the process proceeds to step S507; otherwise, it proceeds to step S509. In step S506, for example, the controller makes the determination by referring to information related to sub-blocks SB0 and SB1 held in registers such as RG.

[0312] In step S507, a pre-program is executed on sub-blocks SB0 and SB1 that are in a partial write state, and the process proceeds to step S508. Step S507 is performed in the same way as, for example, steps S203 and S206 (Figure 30).

[0313] In step S508, the sub-block erasure operation is performed on the sub-block that was pre-programmed in step S507 (sub-block SB0 in the example of FIG57).

[0314] In step S509, a block preprocessor is executed for memory block BLK. The block preprocessor is performed in essentially the same way as the preprocessor. However, in the program operation of step S102 (FIG. 13), the block preprocessor sets the character line WL of sub-blocks SB0 and SB1 to the selected character line WL S.

[0315] In step S510, a memory block erase operation is performed (Figure 16).

[0316] [Example of the erase action (5)] The action of setting subblock SB1 to a fully erased state and subblock SB0 to a partially written state in 3-bit mode (Figure 54) is called action example EX50. In action example EX50, in step S503, only the pages that have not been written are pre-programmed, and the pages PG (Figure 54) in the erased state Er of subblock SB0 become the written state Pg (Figure 55). Next, the erase operation is performed on subblock SB0 in step S504, so that all pages PG contained in memory block BLK become the erased state Er (Figure 23).

[0317] The action of writing subblocks SB0 and SB1 in 3-bit mode to a fully written state is called action example EX51. In action example EX51, step S503 is skipped, and the memory block erasure action of step S505 is performed. All pages PG contained in memory block BLK are in the erase state Er (Figure 23).

[0318] The action of setting subblock SB1 to a completely erased state and subblock SB0 to a partially written state in 1-bit mode (Figure 56) is called action example EX52. In action example EX52, the pre-programming of subblock SB0 is performed in step S507, and all pages PG of subblock SB0 (Figure 54) become write state Pg (Figure 57). Next, the erase operation is performed on subblock SB0 in step S508, and all pages PG contained in memory block BLK become erased state Er (Figure 23).

[0319] The action of fully writing subblocks SB0 and SB1 in 1-bit mode is called action example EX53. In action example EX53, the block preprocessing in step S509 is performed, and all pages PG contained in memory block BLK become write state Pg. Next, the block erase operation in step S510 is performed, and all pages PG contained in memory block BLK become erase state Er (Figure 23).

[0320] [Effect] In 1-bit mode, when a random pattern write is performed, sometimes about half of the memory cells (MCs) become Er states. In this case, if an erase operation is performed without pre-programming, the proportion of over-erased states of the memory cells (MCs) is high. Therefore, in 1-bit mode, by performing block pre-programming targeting the entire memory block BLK as in step S509, the generation of over-erased states of memory cells (MCs) can be suppressed.

[0321] In 3-bit mode, when random mode writes are performed, approximately 1 / 8 of the memory cells MC sometimes enter the Er state. In this case, the proportion of over-erased states in the memory cells MC is relatively low. Therefore, in 3-bit mode, a pre-programming operation is performed, targeting only the unwritten pages PG, as in step S503. This prevents unnecessary pre-programming from causing write stress on the memory cells MC.

[0322] [Variations of the fifth implementation form] In step S501, the controller-based determination may not be performed. The determination in step S501 can also be performed, for example, by a read operation performed by the memory die MD. In this read operation, for example, information is read from a portion of the initially written page PG within the memory block BLK, indicating whether the page PG is in 1-bit or 3-bit mode. This information can also be written to a portion of the initially written page PG in the memory block BLK during a write operation.

[0323] [Other Implementation Forms] The writing order of page PG shown in the first to fifth embodiments can be modified in various ways. For example, the writing operation of page PG can be performed in descending order of n of character line WL(n-1) and m of character line WL(m-1). In each character line WL, the writing operation can also be performed in a different order than serial unit SU0, serial unit SU1, serial unit SU2, and serial unit SU3.

[0324] [other] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0325] 10: Memory System 20: Main computer 22: Address Decoder 23: Block Selection Circuit 24: Voltage Selection Circuit 31: Voltage supply line 32: Charge pump circuit 33: Voltage Selection Line 34: Block Selection Department 35: Block Selection Transistor 36: Voltage Selection Section 37: Voltage Selective Transistor 100: Semiconductor substrate 101, 125, 151: Insulation layer 110, 114: Conductive layer 110DM: Virtual Conductive Layer 111, 112, 113, 120: Semiconductor layers 115:Metal film 116: Conductive film 120J, 120L, 120U: Semiconductor region 121, 122: Impurity regions 130: Gate insulating film 131: Tunnel insulation film 132: Charge storage membrane 133: Block insulating film 134: Metal oxide film ADR: Address Register Add: Address information ALE, / CE, CLE, / WE, RE, / RE: External control terminals B: Joint line BL, BL W: Bitline BLK: Memory Block BLKSEL: Block Selection Line BLK tb: Select memory block CA: Row Address Cb, CC, Ch, CS: Connectors CD: Controller chip CG: Wiring Cmd: Command Information CM0, CM1: High-speed cache memory CMR: Command Register CTR: Logic Circuits D: Area D0, D1, D2: Wiring layers Dat: User Profile Db_01e, Db_01p, Db_02e, Db_02ex, Db_02p, Db_10e, Db_10ex: group DQ0, DQ1, DQ2~DQ7: Data signal input / output terminals DQS, / DQS: Data selection communication input / output terminal Er: Erasure status GC: Wiring Layer gc: electrode I / O: Input / output control circuit L MCA, L MCA1, L MCA2, L MCA3: Memory Cell Array Layer L TR: Transistor layer MC: Memory Unit MCA, MCA0, MCA1: Memory Cell Array MD: Memory chip MS: Memory String MSB: Mounting baseboard NE, NW: Specified number of times nE, nW: Number of cycles P: Solder pad electrode PC: Peripheral Circuits Pg, Pgs, Pgt: Write status PG S: Select Page PG_LE(2), PG_LE(3), PG_TE(2), PG_TF(1), PG_UE(2), PG_UE(3), PG_UF(1), PG_UF(2): Page RA: Column address RD, RD0, RD1: Column decoder RG: Temporary Register RY / ( / BY): Terminal S101, S102, S103, S104, S105, S106, S107, S108, S111, S112, S113, S114, S115, S116, S117, S118, S121, S122, S123, S201, S202, S203, S204, S205, S206, S207, S 301, S302, S303, S304, S305, S401, S402, S403, S404, S405, S406, S407, S408, S409, S410, S411, S501, S502, S503, S504, S505, S506, S507, S508, S509, S510: Steps SA0, SA1: Sensing amplifiers SAM0, SAM1: Sensing amplifier modules SB0, SB1, SB2: Sub-blocks SGD: Drain-side gate selection (selective gate selection) SGD S, SGD U: Drain-side gate selection line SGS: Source-side gate selection (Gate selection) SHE: Inter-cell insulation layer SL: Source Line SQC: Sequencer ST: Inter-block structure STD: Drain-side selective transistor (selective transistor) STR: State register STS: Source-side selective transistor (selective transistor) Stt: Status Data SU, SU0, SU1, SU2, SU3, SUa, SUb, SUc, SUd, SUe: Serial units t100, t101, t102, t103, t104, t105, t106, t110, t111, t112, t113, t114, t115, t120, t121, t122, t123, t124, t131, t132, t133: Time points Tr: transistor V 1, V E0, V ERA, V ERA-V 1, V EX, V Pi, V SG, V SGD, V SRC: Voltage VCC: Power supply voltage V CGR, V CGAR, V CGBR, V CGCR, V CGDR, V CGER, V CGFR, V CGGR: Readout voltage VG: Voltage generation circuit V PASS: Write path voltage V PGM: Program Voltage V READ: Read the path voltage V SS: Grounding voltage V VFYA, V VFYB, V VFYC, V VFYD, V VFYE, V VFYF, V VFYG, V VFYS: Verification voltage V VFYEr: Erasure verification voltage VX: Non-selective erase voltage W 120J, W 120LL, W 120LU, W 120UL, W 120UU: Width WL, WL0, WL47, WL48, WL95, WL96, WL143: Character lines WL S: Select character lines WL U: Non-select character line X, Y, Z: Direction XDL0, XDL1: Latch circuits

Claims

1. A semiconductor memory device, comprising: substrate; The memory block includes a first sub-memory block and a second sub-memory block arranged in a first direction intersecting the surface of the substrate; Bit lines are disposed on one side of the first direction relative to the memory block; source lines are disposed on the other side of the first direction relative to the memory block. The system includes a control circuit to control the memory blocks. The first sub-memory block includes: a first memory cell electrically connected to the bit line and the source line; and a first word line electrically connected to the first memory cell. The second sub-memory block includes: a second memory cell electrically connected to the bit line and the source line; and a second word line electrically connected to the second memory cell. The control circuit is configured to perform the following actions during an erase operation on the memory blocks: a first determination action to determine whether the second memory cell is in a write state; a first erase action performed when the second memory cell is in a write state; and a second erase action performed when the second memory cell is in an erase state. In the first erase action, an erase voltage is applied to one or both of the bit line and the source line, and a selective erase voltage lower than the erase voltage is applied to the first word line and the second word line. In the second erase action… The erase voltage is applied to one or both of the bit lines and the source lines; the selective erase voltage is applied to the first word line; and a non-selective erase voltage, which is lower than the erase voltage but higher than the selective erase voltage, is applied to the second word line.

2. The semiconductor memory device as claimed in claim 1, wherein, The control circuit is configured such that, in the first determination action, it can perform a pre-erase read action on the second memory cell, in which a read voltage is applied to the second character line and a non-selective read voltage higher than the read voltage is applied to the first character line.

3. The semiconductor memory device as claimed in claim 1, wherein, The control circuit is configured to, during the first determination action, refer to a memory region within the control circuit, which holds information about the write status of the second sub-memory block.

4. The semiconductor memory device as claimed in claim 1, wherein, The control circuit is configured to send a set of commands instructing the first erasure action and a set of commands instructing the second erasure action.

5. The semiconductor memory device as claimed in claim 1, wherein, The control circuit is configured to perform a write operation, wherein when the first memory cell and the second memory cell are in an erase state, the write operation to the first memory cell is performed before the write operation to the second memory cell.

6. The semiconductor memory device as claimed in claim 1, wherein, The control circuit is configured to perform a write operation. The second sub-memory block contains multiple pages as units of the write operation. The second memory unit is contained in the page in which the write operation is initially performed.

7. The semiconductor memory device as claimed in claim 1, wherein, The first sub-memory block includes: a plurality of first conductive layers arranged in the first direction; a first semiconductor portion extending along the first direction and facing the plurality of first conductive layers; and a first charge storage film disposed between the plurality of first conductive layers and the first semiconductor portion. The second sub-memory block includes: a plurality of second conductive layers arranged in the first direction; a second semiconductor portion extending along the first direction, facing the plurality of second conductive layers and electrically connected to the first semiconductor portion; and a second charge storage film disposed between the plurality of second conductive layers and the second semiconductor portion. One of the plurality of first conductive layers functions as a first word line, and one of the plurality of second conductive layers functions as a second word line.

8. The semiconductor memory device of claim 7, comprising a semiconductor layer extending along the first direction, the semiconductor layer comprising: First semiconductor unit; Second semiconductor unit; And a third semiconductor section is disposed between the first sub-memory block and the second sub-memory block, and connected to the first semiconductor section and the second semiconductor section. If the width of the end of the first semiconductor section on the side of the third semiconductor section in the second direction intersecting the first direction is set as the first width, the width of the end of the second semiconductor section on the side of the third semiconductor section in the second direction is set as the second width, and the width of the third semiconductor section in the second direction is set as the third width, then the third width is greater than the first width and the second width.

9. A semiconductor memory device, comprising: substrate; The memory block includes a first sub-memory block and a second sub-memory block arranged in a first direction intersecting the surface of the substrate; Bit lines are disposed on one side of the first direction relative to the memory block; source lines are disposed on the other side of the first direction relative to the memory block. The system includes a control circuit to control the memory blocks. The first sub-memory block includes: a plurality of first memory cells electrically connected to the bit lines and the source lines; and a plurality of first word lines electrically connected to the plurality of first memory cells. The second sub-memory block includes: a plurality of second memory cells electrically connected to the bit lines and the source lines; and a plurality of second word lines electrically connected to the plurality of second memory cells. The control circuit is configured to perform the following actions during an erase operation on the memory blocks: a first determination action to determine whether at least one of the plurality of second memory cells is in a write state; a second determination action to determine whether at least one of the plurality of second memory cells is in an erase state; and a third determination action to determine whether at least one of the plurality of first memory cells is in an erase state. A first pre-erasure write operation is performed when at least one of the plurality of second memory cells is in a write state and at least one is in an erase state; and a second pre-erasure write operation is performed when at least one of the plurality of first memory cells is in a write state and at least one is in an erase state. In the first pre-erasure write operation, a program voltage is applied to the plurality of second word lines, and a non-selective write voltage lower than the program voltage is applied to the plurality of first word lines. In the second pre-erasure write operation, the program voltage is applied to the plurality of first word lines, and the non-selective write voltage is applied to the plurality of second word lines.

10. The semiconductor memory device as claimed in claim 9, wherein, The control circuit is configured to perform the following actions during an erase operation on the memory block: a first erase operation performed after a first erase-before-write operation; and a second erase operation performed after a second erase-before-write operation. In the first erase operation, an erase voltage is applied to one or both of the bit lines and the source lines, and a selective erase voltage lower than the erase voltage is applied to the plurality of first word lines and the plurality of second word lines. In the second erase operation, the erase voltage is applied to one or both of the bit lines and the source lines, the selective erase voltage is applied to the plurality of first word lines, and a non-selective erase voltage lower than the erase voltage and higher than the selective erase voltage is applied to the plurality of second word lines.

11. The semiconductor memory device as claimed in claim 9, wherein, The control circuit is configured to perform a pre-erase read operation on at least one of the plurality of second memory cells during the first determination operation and the second determination operation. During the pre-erase read operation, a read voltage is applied to at least one of the plurality of second character lines, and a non-selective read voltage higher than the read voltage is applied to the plurality of first character lines.

12. The semiconductor memory device as claimed in claim 9, wherein, The control circuit is configured to perform a pre-erase read operation on at least one of the plurality of first memory cells during the third determination operation. During the pre-erase read operation, a read voltage is applied to at least one of the plurality of first word lines, and a non-selective read voltage higher than the read voltage is applied to the plurality of second word lines.

13. The semiconductor memory device as claimed in claim 9, wherein, The control circuit is configured to, during the first determination action, the second determination action, and the third determination action, refer to a memory region within the control circuit, the memory region storing information about the write status of the first sub-memory block and the second sub-memory block.

14. The semiconductor memory device as claimed in claim 10, wherein, The control circuit is configured to send: a set of commands indicating the first write operation before erasure, a set of commands indicating the second write operation before erasure, a set of commands indicating the first erase operation, and a set of commands indicating the second erase operation.

15. The semiconductor memory device as claimed in claim 9, wherein, The control circuit is configured to perform a write operation, wherein when the plurality of first memory cells and the plurality of second memory cells are in an erase state, the write operation to the plurality of first memory cells is performed before the write operation to the plurality of second memory cells.

16. The semiconductor memory device as claimed in claim 9, wherein, The first sub-memory block includes: a plurality of first conductive layers arranged in the first direction; a first semiconductor portion extending along the first direction and facing the plurality of first conductive layers; and a first charge storage film disposed between the plurality of first conductive layers and the first semiconductor portion. The second sub-memory block includes: a plurality of second conductive layers arranged in the first direction; a second semiconductor portion extending along the first direction, facing the plurality of second conductive layers and electrically connected to the first semiconductor portion; and a second charge storage film disposed between the plurality of second conductive layers and the second semiconductor portion. The plurality of first conductive layers function as the plurality of first word lines, and the plurality of second conductive layers function as the plurality of second word lines.

17. The semiconductor memory device of claim 16, comprising a semiconductor layer extending along the first direction, the semiconductor layer comprising: First semiconductor unit; Second semiconductor unit; A third semiconductor section is disposed between the first sub-memory block and the second sub-memory block, and connected to the first semiconductor section and the second semiconductor section. If the width of the end of the first semiconductor section on the side of the third semiconductor section in the second direction intersecting the first direction is set as the first width, the width of the end of the second semiconductor section on the side of the third semiconductor section in the second direction is set as the second width, and the width of the third semiconductor section in the second direction is set as the third width, then the third width is greater than the first width and the second width.

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