Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device capable of suppressing defective step formation and a method for manufacturing the semiconductor memory device. The semiconductor memory device of the embodiment includes: a stacked body having a plurality of first conductive layers and a plurality of first insulating layers alternately stacked layer by layer; and a step portion disposed in a part of the stacked body, wherein the plurality of first conductive layers and the plurality of first insulating layers are processed into a step shape, having a plurality of stepped surfaces formed by the plurality of first conductive layers and a plurality of step surfaces connecting the plurality of stepped surfaces to each other along the stacking direction of the stacked body, and extending along a first direction intersecting the stacking direction. At least a portion of the layer thickness of the stepped surfaces of the plurality of first conductive layers is thicker than the layer thickness of other portions of the corresponding conductive layers. The bottommost first insulating layer of each of the plurality of first insulating layers has a tapered portion extending toward the stepped surface connected to the corresponding step surface on its lower side. The width of the lower surface of the tapered portion in a first direction is greater than the layer thickness of the first insulating layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Prior Technology

[0002] In three-dimensional non-volatile memory, there is, for example, a laminate with multiple conductive layers and multiple insulating layers alternately stacked. At the end of the laminate, the laminate is processed into a stepped shape to form a stepped section that leads each conductive layer out to the upper layer for wiring.

[0003] As the laminate becomes thinner and the number of layers increases, the processing of the stepped portion tends to become more difficult. Sometimes, poor formation of the stepped portion can lead to a deterioration in the electrical characteristics of the semiconductor memory device. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device that can suppress the formation defects of the step portion and a method for manufacturing the semiconductor memory device.

[0005] The semiconductor memory device of the embodiment includes: a stacked body having a plurality of first conductive layers and a plurality of first insulating layers stacked alternately layer by layer; and a stepped portion disposed in a part of the stacked body, wherein the plurality of first conductive layers and the plurality of first insulating layers are processed into a stepped shape, having a plurality of stepped surfaces formed by the plurality of first conductive layers and a plurality of stepped surfaces connecting the plurality of stepped surfaces to each other along the stacking direction of the stacked body, and extending in a first direction intersecting the stacking direction, wherein at least a portion of the portion of the plurality of first conductive layers forming the stepped surfaces is thicker than the thickness of other portions of the corresponding conductive layers, wherein the bottommost first insulating layer of each of the plurality of first insulating layers has a tapered portion extending toward the stepped surface connected to the corresponding stepped surface on the lower side, and the width of the lower surface of the tapered portion in the first direction is greater than the thickness of the first insulating layer. A method for manufacturing a semiconductor memory device according to an embodiment: forming a stacked body, wherein a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked layer by layer in the stacked body; in a portion of the stacked body, the plurality of first insulating layers and the plurality of second insulating layers are processed into a stepped shape to form a first stepped portion; the first stepped portion has a plurality of first step surfaces formed by the plurality of first insulating layers and a plurality of first step surfaces connecting the plurality of first step surfaces to each other along the stacking direction of the stacked body, and extending in a first direction intersecting the stacking direction; when forming the first stepped portion, the bottommost second insulating layer of each of the plurality of second insulating layers is processed into a tapered portion, the tapered portion extending toward the first step surface connected to the corresponding first step surface on the lower side, and the width of the lower surface of the tapered portion in the first direction is greater than the thickness of the first insulating layer; the entire first stepped portion is covered by a third insulating layer common to the first insulating layer; and the portion of the third insulating layer covering the plurality of first step surfaces is removed. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic structural example of the semiconductor memory device according to Embodiment 1. Figure 2 is a detailed structural example of the semiconductor memory device according to Embodiment 1. Figure 3 is a flowchart illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figure 4 is a flowchart illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figure 5 is a flowchart illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figure 6 is a flowchart illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figure 7 is a flowchart illustrating a portion of the manufacturing method of a comparative example semiconductor memory device. Figure 8 is a detailed structural example of the semiconductor memory device according to Embodiment 2. Figure 9 is a flowchart illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 2. Implementation

[0007] Hereinafter, embodiments will be described in detail with reference to the drawings. Furthermore, the present invention is not limited to the embodiments described below.

[0008] Moreover, the constituent elements in the following embodiments include those that can be readily conceived or are substantially the same as those of a person skilled in the art.

[0009] [Embodiment 1] (Structural Example of a Semiconductor Memory Device) FIG1 is a diagram showing a schematic structural example of the semiconductor memory device 1 according to Embodiment 1. FIG1(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, and FIG1(b) is a schematic plan view showing the layout of the semiconductor memory device 1. However, in FIG1(a), the shaded lines are omitted for ease of reading. Furthermore, a portion of the select gate line and upper layer wiring are omitted in FIG1(a).

[0010] Furthermore, in this specification, both the X and Y directions are directions along the orientation of the face of the character line WL (described later), and the X and Y directions are orthogonal to each other. Also, the electrical lead-out direction of the character line WL (described later) is sometimes referred to as the first direction, which is along the X direction. And, sometimes the direction intersecting the first direction is referred to as the second direction, which is along the Y direction. However, the semiconductor memory device 1 may contain manufacturing errors, therefore the first and second directions may not be orthogonal.

[0011] As shown in Figure 1, the semiconductor memory device 1 includes peripheral circuitry CUA, memory region MR, through contact region TP, and stepped region SR on substrate SB.

[0012] The substrate SB is, for example, a semiconductor substrate such as a silicon substrate. A peripheral circuit CUA, including transistors TS and wiring, is disposed on the substrate SB. The peripheral circuit CUA facilitates the operation of the memory cell, which will be described later.

[0013] The peripheral circuit CUA is covered by an insulating layer 50. A source line SL is disposed on the insulating layer 50. Multiple word lines WL are stacked on the source line SL. The multiple word lines WL are covered by an insulating layer 49. The insulating layer 49 also extends around the multiple word lines WL.

[0014] Multiple plate-shaped contact portions LI are arranged on multiple character lines WL, the plate-shaped contact portions LI penetrating the character lines WL along the stacking direction and extending along the X direction. In this way, the multiple character lines WL are divided by the multiple plate-shaped contact portions LI along the Y direction.

[0015] Between multiple plate-shaped contact portions LI, multiple memory regions MR, stepped regions SR, and through contact regions TP are arranged along the X direction. The multiple memory regions MR are arranged such that the stepped regions SR and through contact regions TP are sandwiched in the middle and separated from each other along the X direction.

[0016] In the memory region MR, a plurality of pillars PL are arranged to extend through the word line WL along the stacking direction. A plurality of memory cells are formed at the intersection of the pillars PL and the word line WL. Thus, the semiconductor memory device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are arranged in a three-dimensional manner in the memory region MR.

[0017] The stepped region SR contains multiple character lines WL that are excavated downwards along the stacking direction to form multiple stepped portions SP in the shape of a mortar. In a stepped region SR, for example, two stepped portions SP arranged along the Y direction are configured via a plate-like contact portion LI.

[0018] The stepped portion SP has a mortar-shaped section that descends in a stepped manner from both sides in the X direction and one side in the Y direction toward the bottom surface. The other side of the stepped portion SP in the Y direction is open to the side of the plate-shaped contact portion LI.

[0019] Each step of the stepped section SP contains character lines WL for each level. The character lines WL for each level are electrically connected on both sides of the stepped area SR in the X direction via the stepped portion on one side of the stepped section SP in the Y direction. On the stepped surface of each step of the stepped section SP, a contact part CC is provided to connect the character lines WL of each level to the upper layer wiring MX.

[0020] In this way, word lines WL, which are stacked in multiple layers, can be individually led out. From these contacts CC, write voltage and read voltage are applied to memory cells in memory regions MR on both sides of the X direction via word lines WL at the same height position as the memory cells.

[0021] A through-contact region TP is disposed on one side of the stepped region SR in the X direction. A through-contact C4 is disposed in the through-contact region TP, passing through multiple character lines WL. The through-contact C4 connects the peripheral circuit CUA disposed on the lower substrate SB to the upper wiring MX of the contact CC connected to the stepped region SP. Various voltages applied from the contact CC to the memory cell are controlled by the peripheral circuit CUA via the through-contact C4 and the upper wiring MX.

[0022] Figure 2 is a diagram showing a detailed structural example of the semiconductor memory device 1 according to Embodiment 1. Figure 2(a) is a cross-sectional view of the stepped region SR along the X direction. Figure 2(b) is a partially enlarged cross-sectional view showing the stepped portion SP disposed in the stepped region SR. However, in Figure 2(a), the structure below the substrate SB and the insulating layer 50 containing peripheral circuits such as CUA is omitted.

[0023] As shown in Figure 2(a), in the stepped region SR, a source line SL is disposed on the insulating layer 50, and a stacked body LM is disposed on the source line SL. The stacked body LM has a structure in which multiple word lines WL and multiple insulating layers OL are alternately stacked layer by layer. Each of the multiple word lines WL is, for example, a tungsten layer or a molybdenum layer. These word lines WL are an example of a first conductive layer. Moreover, each of the multiple insulating layers OL is, for example, a silicon oxide layer.

[0024] In the laminate LM, a stepped portion SP extending along the X direction is arranged. In the stepped portion SP, multiple character lines WL and multiple insulating layers OL are processed into a stepped shape. The entire stepped region SR including the stepped portion SP is covered, for example, by an insulating layer 51 that is a silicon oxide layer. Insulating layers 52 to 54 are formed on the upper surface of the insulating layer 51. Insulating layers 52 to 54, together with the insulating layer 51, constitute a part of the insulating layer 49 in FIG1.

[0025] Each step of the stepped section SP contains one or more character lines WL and an insulating layer OL. In each step, the top layer is the character line WL, and the bottom layer is the insulating layer OL. In the example in Figure 2, each step of the stepped section SP contains one character line WL and an insulating layer OL.

[0026] The upper surface of each character line WL constituting the stepped section SP is called the step surface TR. Furthermore, the X-direction end face of each character line WL constituting the stepped section SP and the insulating layer OL is called the step surface SS. That is, the stepped section SP has multiple step surfaces TR and multiple step surfaces SS.

[0027] Multiple stepped surfaces SS connect multiple stepped surfaces TR to each other along the stacking direction. Specifically, each stepped surface SS is connected above the upper stepped surface TR and below the lower stepped surface TR. The end face of the bottom insulating layer OL constituting the stepped surface SS has a tapered portion TPa extending toward the stepped surface TR.

[0028] The layer thickness of the portion of the forming step surface TR of the character line WL is thicker than the layer thickness of the other portions of the corresponding character line WL.

[0029] Furthermore, in this specification, the direction in which the step surface TR of each step of the stepped section SP faces is defined as the upward direction.

[0030] Each contact CC penetrates the insulating layer 52 and the insulating layer 51 to reach the character line WL of each step of the stepped portion SP. The contact CC includes an insulating layer 56 covering the sidewall of the contact CC and a conductive layer 22 filled inside the insulating layer 56. The lower end of the conductive layer 22 is connected to the stepped surface TR of the corresponding character line WL. The upper end of the conductive layer 22 is connected to the upper layer wiring MX disposed in the insulating layer 54 via a plug V0 extending in the insulating layer 53.

[0031] As described above, the semiconductor memory device 1 includes a peripheral circuit CUA (see Figure 1), and an upper layer wiring MX is electrically connected to the peripheral circuit CUA. The peripheral circuit CUA includes multiple transistors TS, which facilitate the electrical operation of the memory cell. Data reading and writing of the memory cell are performed by applying voltage to the memory cell through the peripheral circuit CUA, through contact C4, upper layer wiring MX, contact CC, and word line WL.

[0032] Figure 2(b) is used to illustrate the specific positional relationship between the stepped surface TR, the stepped surface SS, and the conical portion TPa.

[0033] Figure 2(b) illustrates, for example, a case where insulating layer OLm, character line WLm, insulating layer OLn, and character line WLn are sequentially stacked from bottom to top. The layer thickness To of insulating layers OLm and OLn is defined based on the distance between the stacked character lines WL so that they will not cause problems with component driving due to mutual electrical interference. That is, as long as the distance between the character lines WL is greater than or equal to the layer thickness To, the character lines WL will not cause problems with component driving due to mutual electrical interference.

[0034] A stepped surface TRm is formed on the character line WLm, and a stepped surface TRn is formed on the character line WLn. Furthermore, a stepped surface SSn connects to the stepped surface TRn above it and to the stepped surface TRm below it. The insulating layer OLn at the bottom of the stepped surface SSn has a tapered portion TPa that extends toward the stepped surface TRm.

[0035] The stepped surface TRm is the portion protruding in the X direction from the position SF on the upper surface of the character line WLm, which coincides with the X-direction end SEn of the character line WLn that is processed into a stepped shape. The stepped surface TRm has a first portion Pam that is thicker than the character line WLm and a second portion Pbm that is thinner than the first portion Pam.

[0036] The first part, Pam, is the region on the end side of the stepped surface TRm in the X direction. The layer thickness Twa of the character line WLm in the first part, Pam, is thicker than the layer thickness Twb in the second part, Pbm. A contact portion CC is connected to the first part, Pam. On the other hand, the second part, Pbm, is the region in the stepped surface TRm opposite to the end side of TRm in the X direction. The second part, Pbm, extends from position SG, which coincides with the end face SNm on the step surface SSn side of the first part, when viewed from above, to position SF. Therefore, the width Wa of the second part, Pbm, in the X direction corresponds to the distance between position SF and the end face SNm of the character line WLm.

[0037] The conical portion TPa extends along the second portion Pbm, and the end TPas of the conical portion TPa on the TRm side reaches the first portion Pam. That is, the first portion Pam covers the end TPas of the conical portion TPa on the TRm side. Thus, the second portion Pbm is covered by the conical portion TPa. At this time, the width Wb of the lower surface of the conical portion TPa in the X direction is slightly larger than the width Wa of the second portion Pbm in the X direction.

[0038] Furthermore, the width Wb of the lower surface of the tapered portion TPa in the X direction is formed to a thickness To of the insulating layer OLn. That is, the distance between the end SEn of the character line WLn and the end face SNm of the character line WLm will be ensured to be at least To. As a result, the character lines WLn and WLm are sufficiently separated in the X direction, avoiding problems caused by mutual electrical interference that could lead to component driving issues.

[0039] (Manufacturing Method of Semiconductor Memory Device) Next, the manufacturing method of semiconductor memory device 1 according to Embodiment 1 will be described using FIGS. 3 to 7. FIGS. 3 to 7 are diagrams illustrating a portion of the flow of the manufacturing method of semiconductor memory device 1 according to Embodiment 1 in sequence. Furthermore, it is assumed that before the process shown in FIGS. 3 to 7, a peripheral circuit CUA is formed on the substrate SB, and an insulating layer 50 covering the peripheral circuit CUA has been formed.

[0040] Figures 3-6 mainly illustrate the formation of stepped sections SP in the region that later becomes the stepped region SR. Figures 3-6 are cross-sectional views along the X direction of the region that later becomes the stepped region SR.

[0041] As shown in Figure 3(a), a source line SL is formed on the insulating layer 50. On the source line SL, a stacked body LMs is formed, consisting of multiple insulating layers NL and multiple insulating layers OL, which are stacked alternately layer by layer. The bottom layer of the stacked body LMs is the insulating layer OL, and the top layer is the insulating layer NL.

[0042] Multiple insulating layers NL are, for example, silicon nitride layers. These multiple insulating layers NL function as sacrificial layers that are subsequently replaced by character lines WL. These insulating layers NL are an example of a first insulating layer. Furthermore, multiple insulating layers OL are, for example, silicon oxide layers. These insulating layers OL are an example of a second insulating layer.

[0043] A mask pattern 72 is formed on the stacked layers LMs, covering a portion of the stacked layers LMs. The mask pattern 72 is, for example, a carbon-containing layer. Using the mask pattern 72, the exposed portions of the insulating layers NL and OL are removed layer by layer by etching. Then, by using a process such as oxygen plasma, the ends of the mask pattern 72 are retracted to expose the upper surface of the stacked layers LMs again, and the insulating layers NL and OL are further removed layer by layer by etching.

[0044] This process of slimming the mask pattern 72 and etching the insulating layers NL and OL of the laminates LMs is repeated multiple times. This forms the step portion SPa, which serves as the first step portion, as shown in Figure 3(b).

[0045] The stepped portion SPa extends along the X direction and has multiple insulating layers NL and OL processed into a stepped shape. The stepped portion SPa has stepped surfaces TRa formed by multiple insulating layers NL and multiple stepped surfaces SSa. The multiple stepped surfaces SSa connect the multiple stepped surfaces TRa to each other along the lamination direction of the laminate LMs.

[0046] The stepped surface TRa is the upper surface of the insulating layer NL of each step constituting the stepped portion SPa. Furthermore, the step surface SSa is the X-direction end face of the insulating layer NL and the insulating layer OL of each step constituting the stepped portion SPa. The upper side of the step surface SSa is the insulating layer NL, and the lower side is the insulating layer OL. The step surface SSa is connected to the stepped surface TRa above the insulating layer NL and below the insulating layer OL, respectively. The stepped surface TRa is an example of a first stepped surface. Furthermore, the step surface SSa is an example of a first step surface.

[0047] Furthermore, during the formation of the stepped portion SPa, the bottom insulating layer OL of the stepped surface SSa is machined to have a tapered portion TPa, which extends toward the stepped surface TRa that connects to the stepped surface SSa on the lower side. Thus, the area near the stepped surface SSa in the stepped surface TRa is covered by the tapered portion TPa. Moreover, during the machining of the tapered portion TPa, the width Wb of the lower surface of the tapered portion TPa in the X direction is greater than the layer thickness To of the insulating layer OL.

[0048] After the stepped section SPa is formed, the mask pattern 72 is removed by ashing using oxygen plasma or the like.

[0049] As shown in Figure 4(a), an insulating layer NLa is formed to cover the entire stepped portion SPa in a manner that follows the shape of the stepped portion SPa. This forms a stepped surface TRb above the stepped surface TRa.

[0050] The main components of the insulating layer NLa are the same as those of the insulating layer NL. Specifically, the insulating layer NLa is, for example, a silicon nitride layer. The insulating layer NLa is an example of a third insulating layer.

[0051] As shown in Figure 4(b), the insulating layer NLa covering the stepped portion SPa is etched back. At this time, for example, by using anisotropic etching such as reactive ion etching (RIE), the insulating layer NLa covering the stepped surface SSa can be removed while the insulating layer NLa constituting the stepped surface TRb remains.

[0052] Furthermore, the tapered portion TPa formed below the step surface SSa functions as an etch stop layer when removing the insulating layer NLa covering the step surface SSa. That is, the downward etching for removing the insulating layer NLa ends upon reaching the tapered portion TPa. This is because the tapered portion TPa, which is a silicon oxide layer or the like, has a certain etch selectivity relative to the insulating layer NLa, which is a silicon nitride layer or the like. Thus, the tapered portion TPa functions as an etch stop layer, thereby suppressing the etching of the step surface TRa connected below the step surface SSa.

[0053] In this way, the step section SPc, which later becomes the step section SP, is formed.

[0054] The stepped section SPc has multiple stepped surfaces TRb and multiple stepped surfaces SSc. The multiple stepped surfaces SSc are the X-direction end faces of insulating layers OL, NL, and NLa.

[0055] As shown in Figure 5(a), the insulating layer 51 is deposited at a height that covers the stepped portion SPc and reaches the upper surface of the unprocessed laminate LMs. Furthermore, an insulating layer 52 is formed that covers the upper surface of the unprocessed laminate LMs and the insulating layer 51.

[0056] Furthermore, although not illustrated, columns PL are formed in laminated bodies LMs using a prescribed method. Moreover, columns PL can also be formed before the formation of stepped regions SR.

[0057] The insulating layers NL and NLa of the stacked matrix LMs are removed using an etching solution, and a metal such as a tungsten layer is used to embed the removed portions. Thus, a character line WL as shown in Figure 5(b) is obtained. This process of replacing the insulating layer with the character line WL is sometimes called a replacement process.

[0058] Through the above processing, a laminate LM is formed by alternately stacking multiple character lines WL and multiple insulating layers OL. Furthermore, a stepped section SP with a stepped surface TR and a stepped surface SS is formed in the laminate LM.

[0059] In the stepped section SP, the layer thickness of the portion of the forming surface TR of the character line WL is made thicker than the layer thickness of the other portions of the corresponding character line WL. This is so that after depositing the insulating layer NLa on the stepped surface TRa of the insulating layer NL, the insulating layer NL and the insulating layer NLa are replaced with the character line WL.

[0060] Next, Figure 6 shows the formation of the contact portion CC. Similar to Figures 3-5, Figure 6 shows a cross-section along the X direction of the region including the stepped portion SP.

[0061] As shown in Figure 6(a), multiple contact holes HLc are formed that penetrate the insulating layer 52 and the insulating layer 51 to reach each step surface TR. The contact holes HLc are structured to become the contact portion CC that is connected to the character line WL.

[0062] These contact holes HLc have different depths. The deeper the contact hole HLc reaches the upper layer of the word line WL in the stacked matrix LM, the more excessive over-etching is required on the word line WL. However, because the layer thickness of the step surface TR forming the word line WL is thick, even when processing is carried out under etching conditions that allow processing of the contact hole HLc with the deepest reach, it is possible to prevent the lower ends of multiple contact holes HLc from penetrating the step surface TR.

[0063] As shown in Figure 6(b), insulating layers 56 are formed to cover the sidewalls of the contact hole HLc. Furthermore, a conductive layer 22, such as a tungsten layer, is filled into the voids of the contact hole HLc remaining inside the insulating layer 56. Through these steps, the contact portion CC is formed.

[0064] Furthermore, although not shown in the figure, after the contact portion CC is formed, an insulating layer 53 and an insulating layer 54 are formed on the insulating layer 52, and a plug V0 connected to the contact portion CC and extending in the insulating layer 53, and an upper wiring MX connected to the plug V0 and disposed in the insulating layer 54 are formed.

[0065] Furthermore, although not shown in the figure, a through contact C4 is formed in the through contact region TP after or before the formation of the contact CC. Also, a plate-shaped contact LI is formed before or during the formation of the through contact C4. The upper layer wiring MX is connected to the through contact C4, the plate-shaped contact LI, and the contact CC, and bit lines (not shown) are connected to the post PL.

[0066] By following the above steps, the semiconductor memory device 1 of Embodiment 1 is manufactured.

[0067] (Comparative Example) Next, the manufacturing method of the semiconductor memory device of the comparative example will be described using FIG7. FIG7 is a diagram illustrating a portion of the manufacturing method of the semiconductor memory device of the comparative example.

[0068] Figure 7(a) is a cross-sectional view showing the stepped portion SPbx with the insulating layer NLb formed in the manufacturing method of the semiconductor memory device of the comparative example. Figure 7(b) is a cross-sectional view showing an example of the state in which the insulating layer NLb in the stepped surface SSbx has been removed, and Figure 7(c) is a cross-sectional view showing another example of the state in which the insulating layer NLb in the stepped surface SSbx has been removed. That is, Figure 7(a) corresponds to Figure 4(a) of Embodiment 1, and Figures 7(b) and 7(c) correspond to Figure 4(b) of Embodiment 1.

[0069] As shown in Figure 7(a), in the manufacturing method of the semiconductor memory device in the comparative example, a tapered portion is not formed on the stepped portion SPbx. After the insulating layer NLb is formed on this stepped portion SPbx, the insulating layer NLb in the stepped surface SSbx is mainly removed by processing such as RIE.

[0070] Therefore, as shown in Figure 7(b), a recess TC is sometimes formed in a part of the stepped surface TRax. This is because both the insulating layer NLb, which is the target of removal, and the insulating layer NL that forms the stepped surface TRax are silicon nitride layers, etc. Therefore, even after the insulating layer NLb has been removed, the downward etching will not end, and the etching will continue until it reaches the stepped surface TRax.

[0071] If such a recess TC is formed on the TRax surface, it may sometimes lead to poor formation of the word line WL during subsequent replacement processing. As a result, for example, the voltage applied to the memory cell via the word line WL is hindered, and the electrical characteristics of the semiconductor memory device may sometimes deteriorate.

[0072] On the other hand, to avoid the formation of the recess TC, for example, it is considered to shorten the processing time of RIE, etc. At this time, as shown in Figure 7(c), it is possible to generate residue Rd of the insulating layer NLb on the step surface SSax.

[0073] If this residue Rd exists on the step surface SSax, during subsequent replacement processing, a portion of the residue Rd will be replaced with a tungsten layer or the like. This tungsten layer or the like spanning multiple word lines can sometimes become a leakage path, causing short circuits between multiple word lines.

[0074] (Summary) According to Embodiment 1, in a part of the stacked body LM, there is a stepped portion SP in which a plurality of word lines WL and a plurality of insulating layers OL are stacked alternately layer by layer, such that the layer thickness of the portion of the plurality of word lines WL that forms the step surface TR is made thicker than the layer thickness of the other portion of the corresponding word line WL.

[0075] In this way, when forming the contact portion CC, the penetration of the contact portion CC relative to the stepped surface TR can be suppressed, thereby suppressing the deterioration of the electrical characteristics of the semiconductor memory device 1.

[0076] Furthermore, the bottom insulating layer OL of the multiple stepped surfaces SSa of the stepped portion SP has a tapered portion TPa, which extends toward the stepped surface TRa connected to the corresponding stepped surface SSa on the lower side.

[0077] In this way, the tapered portion TPa protects the stepped surface TRa, thus suppressing the formation of recesses TC on the stepped surface TRa when the insulating layer NLa covering the stepped surface SSa is etched away. As a result, poor formation of word lines WL can be suppressed during subsequent replacement processing, thereby suppressing the deterioration of the electrical characteristics of the semiconductor memory device 1.

[0078] Furthermore, each of the multiple stepped surfaces TR has a first part Pam with a layer thickness of the character line WL and a second part Pbm with a layer thickness thinner than the first part Pam near the boundary with the corresponding stepped surface SS. The first part Pam covers the end of the conical part TPa on the side of the stepped surface TR.

[0079] In this way, the second part Pbm will be completely covered by the tapered part TPa, thus more effectively preventing the formation of the recess TC on the stepped surface TRa. As a result, the deterioration of the electrical characteristics of the semiconductor memory device 1 can be more effectively suppressed.

[0080] Furthermore, the width Wb of the lower surface of the tapered portion TPa in the X direction is greater than the thickness To of the insulating layer OL.

[0081] In this way, the distance between the first portions Pam of each of the multiple stepped surfaces TR can be set to a distance greater than that between the stepped surface SS of the upper character line WL and the thickened portion of the lower character line WL, so that they will not electrically affect each other. As a result, the deterioration of the electrical characteristics of the semiconductor memory device 1 can be suppressed.

[0082] [Embodiment 2] (Structural Example of a Semiconductor Memory Device) The semiconductor memory device 2 of Embodiment 2 will be described using FIG8. In the semiconductor memory device 2 of Embodiment 2, the shape of the tapered portion of the insulating layer OL is different from that of Embodiment 1. Furthermore, hereafter, the same symbols will sometimes be used for structures that are the same as those in Embodiment 1, and their descriptions will be omitted.

[0083] Figure 8 is a diagram showing a detailed structural example of the semiconductor memory device 2 according to Embodiment 2. Figure 8 corresponds to Figure 2(b) of Embodiment 1.

[0084] Figure 8 illustrates a case where, in Embodiment 2, the stack consists of insulating layer OLp, character line WLp, insulating layer OLq, and character line WLq stacked sequentially from bottom to top.

[0085] A stepped surface TRp is formed on the character line WLp, and a stepped surface TRq is formed on the character line WLq. Furthermore, a stepped surface SSq connects to the stepped surface TRq above and to the stepped surface TRp below.

[0086] The bottom insulating layer OLq of the stepped surface SSq has a tapered portion TPb extending toward the stepped surface TRp. The tapered portion TPb extends to the position corresponding to the character line WLq on the upper layer of the stepped surface SSq.

[0087] (Manufacturing Method of Semiconductor Memory Device) Next, the manufacturing method of the semiconductor memory device 2 according to Embodiment 2 will be described using FIG9. FIG9 is a diagram illustrating a portion of the flow of the manufacturing method of the semiconductor memory device 2 according to Embodiment 2. Furthermore, hereafter, the same reference numerals will sometimes be used for structures that are the same as those in the described embodiment, and their descriptions will be omitted.

[0088] Assume that prior to the processing shown in Figure 9, a peripheral circuit CUA is formed on the substrate SB, and an insulating layer 50 covering the peripheral circuit CUA has been formed.

[0089] Prior to the processing shown in Figure 9(a), a stepped portion SPd is formed in the same manner as in Embodiment 1. The stepped portion SPd is a stepped structure consisting of multiple insulating layers NL and multiple insulating layers OL extending along the X direction. Each step of the stepped portion SPd includes a set of insulating layers NL and OL.

[0090] The stepped portion SPd has stepped surfaces TRd formed by multiple insulating layers OL and multiple stepped surfaces SSd. The multiple stepped surfaces SSd connect the multiple stepped surfaces TRd to each other along the lamination direction of the laminate LMT. The stepped portion SPd is an example of a second stepped portion.

[0091] The stepped surface TRd is the upper surface of the insulating layer OL of each step constituting the stepped portion SPd. Furthermore, the stepped surface SSd is the X-direction end face of the insulating layer NL and insulating layer OL of each step constituting the stepped portion SPd. The upper side of the stepped surface SSd is the insulating layer OL, and the lower side is the insulating layer NL. The stepped surface TRd is an example of a second stepped surface. The stepped surface SSd is an example of a second stepped surface.

[0092] As shown in Figure 9(a), an insulating layer OLa, serving as the fourth insulating layer, is formed to cover the entire stepped portion SPd along its shape. The main component of the insulating layer OLa is the same as that of the insulating layer OL. Specifically, the insulating layer OLa is, for example, a silicon oxide layer. The insulating layer OLa is an example of the fourth insulating layer.

[0093] As shown in Figure 9(b), the portions of the insulating layer OLa that form on the multiple stepped surfaces TRd and the portions of the multiple insulating layers OL that form the multiple stepped surfaces TRd are etched. This exposes the multiple stepped surfaces TRe formed by the multiple insulating layers NL. Thus, a stepped portion SPe, serving as the first stepped portion, is formed.

[0094] The stepped portion SPe has multiple stepped surfaces TRe and multiple stepped surfaces SSe formed by multiple insulating layers NL. The multiple stepped surfaces TRe correspond to the multiple stepped surfaces TRa in Embodiment 1.

[0095] The stepped surface TRe is the upper surface of the insulating layer NL of each step constituting the stepped portion SPe. Furthermore, the step surface SSe is the X-direction end face of the insulating layer NL and the insulating layer OL of each step constituting the stepped portion SPe. The upper side of the step surface SSe is the insulating layer NL, and the lower side is the insulating layer OL. The step surface SSe is connected to the stepped surface TRe on the upper side of the insulating layer NL and the lower side of the insulating layer OL, respectively. The stepped surface TRe is an example of a first stepped surface. Furthermore, the step surface SSe is an example of a first step surface.

[0096] Furthermore, during the formation of the stepped portion SSe, processing is performed to give the underlying insulating layer OL a tapered portion TPb, which extends toward the stepped surface TRe connected to the lower side of the stepped surface SSe. In this way, the area near the stepped surface SSe in the stepped surface TRe is covered by the tapered portion TPb.

[0097] Furthermore, during the processing of the conical portion TPb, the insulating layer OLa covering the stepped surface SSd is processed to form a conical portion TPc. The conical portion TPc has a slope continuous with the conical portion TPb and extends from the position corresponding to the insulating layer NL on the stepped surface SSe towards the stepped surface TRe. Since the conical portion TPc contains the insulating layer OLa, its principal component is shared with the insulating layer OLa.

[0098] Thus, above the conical portion TPb containing the insulating layer OL, a conical portion TPc, shared by the principal component and the insulating layer OL, is deposited, thereby increasing the overall height of the conical portion. This enhances the function of the conical portion as an etch stop layer during subsequent removal of the insulating layer NLa. Furthermore, by increasing the overall height of the conical portion, the gradient of the conical shape becomes gentler. This allows for wider coverage of the stepped surface TRe.

[0099] Although not shown in the figure, an insulating layer NLa is deposited on the stepped surface TRe of the stepped portion Spe formed as described above. Then, insulating layers 51 and 52 are formed thereafter, similar to Embodiment 1, and a replacement process is performed to replace the insulating layers with character lines WL. Furthermore, contact portions CC, plugs V0, upper wiring MX, and through contact portions C4 are formed, thereby manufacturing the semiconductor memory device of Embodiment 2.

[0100] Furthermore, in the method for manufacturing the semiconductor memory device in Embodiment 2, the case where the tapered portion TPb extends to the position corresponding to the word line WL of the upper layer is described, but it is not limited to this. As long as the tapered portion TPb can function independently as an etch stop layer for the step surface TRe, it may not necessarily extend to the position corresponding to the word line WL of the upper layer.

[0101] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0102] 1, 2: Semiconductor memory devices 22: Conductive layer 49, 50, 51, 52, 53, 54, 56, NL, NLa, NLb, OL, OLa, OLm, OLn, OLp, OLq: Insulation layer 72: Masking Pattern C4: Penetrating contact area CC: Contact area CUA: Peripheral Circuits HLc: Contact hole LI: plate contact part LM, LMs, LMt: laminates MR: Memory Region MX: Upper layer wiring Pam: Part 1 Pbm: Part Two PL: Column Rd: Residue SB:Substrate SEn, TPas: End SF, SG: Position SL: Source Line SNm: End face SP, SPa, SPbx, SPc, SPd, SPe: Stepped section SR: Stepped Area SS, SSa, SSax, SSbx, SSc, SSd, SSe, SSn, SSq: step surface TC: Concave To, Twa, Twb: layer thickness TP: Penetrating contact area TPa, Tpan, TPb, TPc: Conical portion TR, TRa, TRax, TRb, TRd, TRe, TRm, TRn, TRp, TRq: step surface TS: Transistor V0: Plug Wa, Wb: Width WL, WLm, WLn, WLp, WLq: Character lines

Claims

1. A semiconductor memory device, comprising: The laminate consists of multiple first conductive layers and multiple first insulating layers stacked alternately layer by layer; The laminate includes a stepped portion, which is provided in a part of the laminate body. The plurality of first conductive layers and the plurality of first insulating layers are processed into a stepped shape, having a plurality of stepped surfaces formed by the plurality of first conductive layers and a plurality of stepped surfaces that connect the plurality of stepped surfaces to each other along the lamination direction of the laminate body, and extending in a first direction intersecting the lamination direction. The thickness of at least a portion of the stepped surface portion of the plurality of first conductive layers is thicker than the thickness of other portions of the corresponding conductive layers. The bottommost first insulating layer of each of the plurality of first insulating layers has a tapered portion that extends toward the stepped surface connected to the corresponding stepped surface on the lower side. The width of the lower surface of the tapered portion in the first direction is greater than the thickness of the first insulating layer.

2. The semiconductor memory device of claim 1, wherein each of the plurality of stepped surfaces has: a first portion having a thick first conductive layer; and a second portion having a thinner layer near a boundary with a corresponding stepped surface, the first portion covering the tapered portion extending toward the stepped surface.

3. A method for manufacturing a semiconductor memory device, comprising forming a stacked body having a plurality of first insulating layers and a plurality of second insulating layers alternately stacked layer by layer; wherein, in a portion of the stacked body, the plurality of first insulating layers and the plurality of second insulating layers are processed into a stepped shape to form a first stepped portion; the first stepped portion having a plurality of first step surfaces formed by the plurality of first insulating layers and a plurality of first step surfaces connecting the plurality of first step surfaces to each other along the stacking direction of the stacked body, and extending in a first direction intersecting the stacking direction; wherein, in forming the first stepped portion, the bottommost second insulating layer of each of the plurality of second insulating layers is processed into a tapered portion, the tapered portion extending toward the first step surface connected to the corresponding first step surface on its lower side, and the width of the lower surface of the tapered portion in the first direction being greater than the thickness of the first insulating layer; the entire first stepped portion being covered by a third insulating layer common to the first insulating layer; and the portion of the third insulating layer covering the plurality of first step surfaces being removed.

4. A method of manufacturing a semiconductor memory device as claimed in claim 3, wherein, when forming the first stepped portion, a portion of the stacked body is formed by processing the plurality of first insulating layers and the plurality of second insulating layers into a stepped shape to form a second stepped portion, the second stepped portion having a plurality of second stepped surfaces formed by the plurality of second insulating layers and a plurality of second step surfaces connecting the plurality of second stepped surfaces to each other along the stacking direction of the stacked body and extending along the first direction, the second stepped portion is covered entirely by a fourth insulating layer common to the main component and the second insulating layers, and portions of the fourth insulating layer formed on the plurality of second stepped surfaces and portions of the plurality of second insulating layers formed on the plurality of second stepped surfaces are etched until the plurality of first stepped surfaces are exposed, thereby forming the tapered portion, the tapered portion comprising the second insulating layer and the fourth insulating layer, the bottommost second insulating layer of each of the plurality of first step surfaces.

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