Semiconductor device

Abstract

A semiconductor device includes an interposer and a plurality of memory chips. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a first bonding pad adjacent to the first surface. The plurality of memory chips are arranged in an array on the first surface of the interposer. Each of the plurality of memory chips includes a second bonding pad, and the second bonding pad is in direct contact with a corresponding first bonding pad.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a memory device. Prior Technology

[0002] With industrial development, the demand for larger memory capacities is increasing. To increase capacity, three-dimensional (3D) memory stacks have been developed, stacked in a direction perpendicular to the surface of the substrate. However, 3D memory stacks have limited input / output (I / O), which may limit the speed of signal transmission. Summary of the Invention

[0003] The present invention provides a semiconductor device having an increased number of I / Os.

[0004] The semiconductor device of the present invention includes an interposer and a plurality of memory chips. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a first bonding pad adjacent to the first surface. The plurality of memory chips are arranged in an array on the first surface of the interposer. Each of the plurality of memory chips includes a second bonding pad, and the second bonding pad directly contacts the corresponding first bonding pad.

[0005] In one embodiment of the semiconductor device of the present invention, the second bonding pad is bonded to a corresponding first bonding pad to form a conductive bonding structure.

[0006] In one embodiment of the semiconductor device of the present invention, the semiconductor device further includes an encapsulation layer disposed on an interposer and laterally encapsulating a plurality of memory chips.

[0007] In one embodiment of the semiconductor device of the present invention, a plurality of memory chips include first memory chips and second memory chips arranged side by side. An encapsulation layer is located in the gap between the first memory chips and the second memory chips.

[0008] In one embodiment of the semiconductor device of the present invention, each of a plurality of memory chips has a first region and a second region surrounding the first region. Each of the plurality of memory chips further includes a substrate, a plurality of memory cells, and logic circuitry. The plurality of memory cells are located on the substrate in the first region. The logic circuitry is located on the substrate in the second region. The plurality of memory cells are electrically connected to an interposer layer via the logic circuitry.

[0009] In one embodiment of the semiconductor device of the present invention, the second bonding pad is located in the second region and is electrically connected to the logic circuit.

[0010] In one embodiment of the semiconductor device of the present invention, the interposer further includes an interposer substrate, a redistribution structure, and a plurality of through-substrate vias. The redistribution structure is disposed on the interposer substrate. The plurality of through-substrate vias penetrate the interposer substrate and are electrically connected to the redistribution structure.

[0011] In one embodiment of the semiconductor device of the present invention, the semiconductor device further includes a packaging substrate and a plurality of conductive connectors. The packaging substrate is disposed on a second surface of an interposer. The plurality of conductive connectors are disposed between the interposer and the packaging substrate.

[0012] In one embodiment of the semiconductor device of the present invention, a plurality of memory chips are directly electrically connected to the packaging substrate through an interposer and a plurality of conductive connectors.

[0013] In one embodiment of the semiconductor device of the present invention, the interposer further includes a first bonding dielectric layer adjacent to a first surface, and a first bonding pad is located in the first bonding dielectric layer. Each of the plurality of memory chips further includes a second bonding dielectric layer facing the first bonding dielectric layer, a second bonding pad being located in the second bonding dielectric layer, and the first bonding dielectric layer directly contacting the second bonding dielectric layer.

[0014] Based on the above, the semiconductor device of this application includes a plurality of memory chips arranged in an array on the same plane of the interposer. Therefore, the semiconductor device has high memory capacity and also has an increased number of input / output (I / O) ports, thereby improving signal transmission speed.

[0015] To make the foregoing easier to understand, several embodiments are described in detail below with reference to the illustrations. Simple Explanation of the Diagram

[0016] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Figures 3 to 5 are schematic cross-sectional views of a semiconductor device manufacturing process according to an embodiment of the present invention. Implementation

[0017] The embodiments are described in detail below with reference to the accompanying drawings, but these embodiments are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be indicated by the same reference numerals in the following description.

[0018] In the text, terms such as "contains", "includes", "containing", and "have" are all open-ended terms, meaning "including but not limited to".

[0019] When terms such as "first" and "second" are used to describe elements, they are only used to distinguish elements and do not limit the order or importance of the devices. Therefore, in some cases, a first element may also be referred to as a second element, and a second element may also be referred to as a first element, which does not exceed the scope of this invention.

[0020] Furthermore, directional terms used in this document, such as "on," "above," "below," and "below," are used only to refer to the directions illustrated and are not intended to limit the invention.

[0021] Furthermore, the use of "from one value to another" to indicate a range is a general way of expressing the range to avoid listing all values ​​within that range in the specification. Therefore, a description of a specific numerical range includes any value within that range, as well as the smaller range of values ​​defined by any value within that range.

[0022] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Figure 1 may be a cross-sectional view taken along line A-A' shown in Figure 2. For clarity, Figure 2 only shows the interposer 100 and the memory die 200; other components are omitted.

[0023] Referring to Figures 1 and 2, the semiconductor device 10 includes an interposer 100 and a plurality of memory chips 200. The interposer 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. The plurality of memory chips 200 (including the first memory chip 200a and the second memory chip 200b) are arranged in an array on the first surface 100a of the interposer 100. In some embodiments, the semiconductor device 10 further includes a packaging substrate 300 disposed on the second surface 100b of the interposer 100.

[0024] In some embodiments, the interposer 100 includes an interposer substrate 110, a redistribution structure 120, a first bonding layer 130, and a through-substrate via 140. The redistribution structure 120 is disposed on the interposer substrate 110, and the first bonding layer 130 is disposed on the redistribution structure 120. The through-substrate via 140 penetrates the interposer substrate 110 and is electrically connected to the redistribution structure 120.

[0025] In some embodiments, the interposer substrate 110 is a semiconductor substrate. The material of the interposer substrate 110 includes silicon, germanium, or other suitable semiconductor materials. In some embodiments, the interposer substrate 110 is a silicon wafer.

[0026] In some embodiments, the redistribution structure 120 includes conductive layers 122 and dielectric layers 124 alternately stacked on an interposer substrate 110. In some embodiments, the redistribution structure 120 further includes conductive vias 126 electrically connected between adjacent conductive layers 122 in the z-direction. In some embodiments, the conductive layers 122 and conductive vias 126 are made of copper, titanium, combinations thereof, alloys thereof, or other suitable conductive materials. In some embodiments, the dielectric layer 124 is made of silicon oxide or other suitable dielectric materials.

[0027] In some embodiments, the first bonding layer 130 includes a first bonding dielectric layer 134 and a first bonding pad 132 located within the first bonding dielectric layer 134. The first bonding pad 132 is electrically connected to the conductive layer 122 of the redistribution structure 120. In some embodiments, the material of the first bonding pad 132 includes copper, titanium, combinations thereof, alloys thereof, or other suitable conductive materials. In some embodiments, the material of the first bonding dielectric layer 134 is the same as the material of the dielectric layer 124; for example, the material of the first bonding dielectric layer 134 includes silicon oxide. However, the invention is not limited thereto. In other embodiments, the material of the first bonding dielectric layer 134 is different from the material of the dielectric layer 124; for example, the material of the first bonding dielectric layer 134 may include polyimide or other suitable dielectric materials.

[0028] In some embodiments, the first bonding pad 132 is tapered. That is, the first bonding pad 132 has sloping sidewalls, and the width measured along the upper surface of the first bonding pad 132 (i.e., the surface of the first bonding pad 132 near the first surface 100a) is greater than the width measured along the lower surface of the first bonding pad 132 (i.e., the surface of the first bonding pad 132 away from the first surface 100a).

[0029] In some embodiments, the through-substrate via 140 also penetrates the dielectric layer 124 and directly contacts the conductive layer 122 for electrical connection. In some embodiments, the material of the through-substrate via 140 includes copper, titanium, combinations thereof, alloys thereof, or other suitable conductive materials.

[0030] In some embodiments, dielectric layer 144 is disposed on the side of the interposer substrate 110 opposite to the redistribution structure 120. In some embodiments, the material of dielectric layer 144 is similar to that of dielectric layer 124.

[0031] In some embodiments, the first bonding layer 130 is located near the first surface 100a, and the through-substrate via 140 is located near the second surface 100b. That is, the first bonding pad 132 is adjacent to the first surface 100a. In some embodiments, the first surface 100a is formed by the surfaces of the first bonding pad 132 and the first bonding dielectric layer 134. In some embodiments, the second surface 100b is formed by the surface of the dielectric layer 144.

[0032] In some embodiments, the interposer substrate 110 may also include passive components (such as capacitors, inductors, resistors, or similar components).

[0033] In some embodiments, as shown in FIG2, a plurality of memory chips 200 are arranged in a 4-column x 4-row array along the x and y directions, but the present invention is not limited thereto. The number of memory chips 200 is not limited and can be adjusted according to actual needs. In other embodiments, the plurality of memory chips 200 can be arranged in a 2x2 array, a 6x6 array, an 8x8 array, a 16x16 array, or other suitable arrangements. Here, the x, y, and z directions are perpendicular to each other.

[0034] In some embodiments, a plurality of memory chips 200 are located on the same layer and are not stacked perpendicularly to each other (i.e., not stacked in the z-direction).

[0035] In some embodiments, a plurality of memory chips 200 include a first memory chip 200a and a second memory chip 200b arranged side by side. Each of the plurality of memory chips 200 (including the first memory chip 200a and the second memory chip 200b) includes a substrate 210, an interconnect structure 220, a second bonding layer 230, and a plurality of memory cells 240. In some embodiments, each of the plurality of memory chips 200 has a first region R1 and a second region R2 surrounding the first region R1. The first region R1 may be a central region, and the second region R2 may be a peripheral region.

[0036] In some embodiments, substrate 210 is a semiconductor substrate. The material of substrate 210 includes silicon, germanium, or other suitable semiconductor materials. In some embodiments, substrate 210 has a front side 210a and a back side 210b. In some embodiments, a dielectric layer 244 is disposed on the back side 210b of substrate 210.

[0037] In some embodiments, a plurality of memory cells 240 are disposed on the front side 210a of the substrate 210 in the first region R1. Each of the plurality of memory cells 240 may be a dynamic random access memory (DRAM) cell, which includes a transistor-capacitor (ITIC) architecture. Note that, for clarity, the plurality of memory cells 240 are simplified to a single box in FIG1 to indicate their relative positions in the memory die 200, and the details of the memory cells are not drawn.

[0038] In some embodiments, an interconnect structure 220 is disposed on the front side 210a of a substrate 210 and electrically connected to a plurality of memory cells 240. In some embodiments, the interconnect structure includes conductive layers 222 and dielectric layers 224 alternately stacked on the substrate 210. In some embodiments, the conductive layers 222 constitute the logic circuitry of the memory die 200. The logic circuitry is located in a second region R2 and extends into a first region R1 to be electrically connected to the corresponding memory cells 240. In some embodiments, the material of the conductive layers 222 is similar to the material of the conductive layer 122, and the materials of the dielectric layers 224 and 244 are similar to the material of the dielectric layer 124.

[0039] In some embodiments, the second bonding layer 230 includes a second bonding dielectric layer 234 and a second bonding pad 232 located within the second bonding dielectric layer 234. The second bonding pad 232 is located in a second region R2 and is electrically connected to a conductive layer 222 of a logic circuit or interconnect structure 220. In some embodiments, the material of the second bonding pad 232 is the same as the material of the first bonding pad 132, and the material of the second bonding dielectric layer 234 is the same as the material of the first bonding dielectric layer 134.

[0040] In some embodiments, the second bonding pad 232 is tapered. That is, the second bonding pad 232 has sloping sidewalls, and the width measured along the upper surface of the second bonding pad 232 (i.e. the surface of the second bonding pad 232 near the interconnect structure 220) is smaller than the width measured along the lower surface of the second bonding pad 232 (i.e. the surface of the second bonding pad 232 away from the interconnect structure 220).

[0041] In some embodiments, the second bonding pad 232 directly contacts the corresponding first bonding pad 132, and the second bonding pad 232 is bonded to the corresponding first bonding pad 132 to form a conductive bonding structure, such that the logic circuit of the memory die 200 is electrically connected to the conductive layer 122 of the interposer 100. Therefore, a plurality of memory cells 240 in the memory die 200 are electrically connected to the interposer 100 through logic circuits. Note that in FIG1, for ease of description, the interface between the first bonding pad 132 and the second bonding pad 232 is clearly shown, but in reality, due to the fusion bonding between the first bonding pad 132 and the second bonding pad 232, the interface between the first bonding pad 132 and the second bonding pad 232 is almost invisible.

[0042] In some embodiments, the second bonding dielectric layer 234 directly contacts the first bonding dielectric layer 134, and the second bonding dielectric layer 234 is bonded to the first bonding dielectric layer 134 to form an insulating bonding structure. Note that in FIG1, for ease of description, the interface between the first bonding dielectric layer 134 and the second bonding dielectric layer 234 is clearly shown, but in reality, due to the fusion bonding between the first bonding dielectric layer 134 and the second bonding dielectric layer 234, the interface between the first bonding dielectric layer 134 and the second bonding dielectric layer 234 is almost invisible.

[0043] In some embodiments, the semiconductor device 10 further includes an encapsulation layer 202 disposed on the interposer 100 and laterally encapsulating a plurality of memory chips 200. In some embodiments, the encapsulation layer 202 is located in the gap between the first memory chip 200a and the second memory chip 200b. In some embodiments, the material of the encapsulation layer 202 includes epoxy resin, molding compound, or other suitable materials.

[0044] In some embodiments, the interposer 100 is electrically connected to the package substrate 300 via a plurality of conductive connectors 150. That is, the plurality of conductive connectors 150 are disposed between the interposer 100 and the package substrate 300. In some embodiments, the conductive connectors 150 include solder balls, metal bumps, or other suitable conductive materials.

[0045] In some embodiments, each of the plurality of memory chips 200 is directly electrically connected to the package substrate 300 through the interposer 100 and the conductive connector 150. This means that the electrical signals of the memory chip 200 reach the package substrate 300 only through the interposer 100 and the conductive connector 150, and do not reach the package substrate 300 through other chips or other components, and vice versa. In this embodiment, no logic chips are disposed between the memory chip 200 and the interposer 100.

[0046] In some embodiments, conductive terminals 310 are disposed on the surface of the package substrate 300 opposite to the interposer layer 100 to electrically connect the semiconductor device 10 to external components (such as printed circuit boards or the like). In some embodiments, conductive terminals 310 include solder balls, metal bumps, or other suitable conductive materials.

[0047] In this embodiment, the semiconductor device 10 includes a plurality of memory chips 200 arranged in an array along the x and y directions on the same plane of the interposer layer 100. Therefore, compared to a semiconductor device comprising a plurality of memory chips stacked along the z direction, the semiconductor device 10 has an increased number of input / output (I / O) operations while maintaining high memory capacity. Due to the increased number of I / O operations, signal transmission speed can be improved.

[0048] Figures 3 to 5 are cross-sectional schematic diagrams illustrating the manufacturing process of a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiments in Figures 3 to 5 continue to use the reference numerals and partial contents of the components in the embodiments of Figures 1 and 2, wherein the same or similar reference numerals are used to indicate the same or similar components, and descriptions of the same technical content are omitted. For the descriptions of the omitted parts, please refer to the foregoing embodiments; they will not be repeated here.

[0049] Referring to FIG3, an interposer 100 and a first memory die 200a are provided. The interposer 100 and the first memory die 200a are similar to the interposer 100 and memory die 200 described in the previous embodiments.

[0050] Referring to Figure 4, the first memory die 200a is bonded to the interposer 100 via hybrid bonding. For example, the second bonding layer 230 of the first memory die 200a faces the first bonding layer 130 of the interposer 100, and the second bonding pad 232 is aligned with the corresponding first bonding pad 132. Then, metal-to-metal bonding is performed between the second bonding pad 232 and the first bonding pad 132, and dielectric-to-dielectric bonding is performed between the second bonding dielectric layer 234 and the first bonding dielectric layer 134. Because the first memory die 200a is bonded to the interposer 100 via hybrid bonding, no micro-bumps or underfills are sandwiched between the first memory die 200a and the interposer 100. The first memory die 200a is in direct contact with the interposer 100, thus minimizing the distance between the first memory die 200a and the interposer 100, thereby improving the signal transmission speed between the first memory die 200a and the interposer 100. Furthermore, since no underfill is formed between the first memory die 200a and the interposer 100, the heat dissipation of the first memory die 200a is improved.

[0051] Referring to Figure 5, similarly, the second memory die 200b and more memory dies (not shown) are bonded to the interposer 100 by hybrid bonding. Then, an encapsulation layer 202 is formed on the interposer 100 by molding or other suitable methods to laterally encapsulate the memory die 200.

[0052] In some embodiments, a conductive connector 150 is formed on the second surface 100b of the interposer 100 and electrically connected to a corresponding through-substrate via 140. The conductive connector 150 may be formed before or after the memory die 200 is bonded to the interposer 100, which is not limited.

[0053] Referring back to Figure 1, the structure shown in Figure 5 is mounted on the packaging substrate 300. Conductive terminals are formed on the packaging substrate 300 by screen printing or other suitable methods. Based on the above, the manufacturing of the semiconductor device 10 is substantially completed.

[0054] Based on the above, the semiconductor device of this application includes a plurality of memory chips arranged in an array on the same plane of an interposer. Therefore, the semiconductor device has high memory capacity and also has an increased number of input / output (I / O) ports, thereby improving signal transmission speed.

[0055] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0056] 10: Semiconductor devices 100: Intermediary layer 100a: First surface 100b: Second surface 110: Intermediate layer substrate 120: Rewiring Structure 122, 222: Conductive layers 124, 144, 224, 244: Dielectric layers 126: Conductive via 130: First bonding layer 132: First joint pad 134: First bonding dielectric layer 140: Through-substrate via 150: Conductive connector 200: Memory chip 200a: First memory chip 200b: Second memory chip 202: Encapsulation layer 210: Base 210a: Front 210b: Back 220: Interconnection Structure 230: Second bonding layer 232: Second joint pad 234: Second bonding dielectric layer 240: Memory Unit 300: Packaging substrate 310: Conductive terminal R1: First Region R2: Second Region x, y, z: direction

Claims

1. A semiconductor device, comprising: An intermediary layer having a first surface and a second surface opposite to the first surface, wherein the intermediary layer includes a first bonding pad adjacent to the first surface; The interposer includes a plurality of memory chips arranged in an array on the first surface of the interposer, each of the plurality of memory chips having a first region and a second region surrounding the first region, each of the plurality of memory chips including: a substrate; a plurality of memory cells located on the substrate in the first region; and a logic circuit located on the substrate in the second region, wherein the plurality of memory cells are electrically connected to the interposer through the logic circuit; and a second bonding pad, wherein the second bonding pad directly contacts the corresponding first bonding pad.

2. The semiconductor device of claim 1, wherein the second bonding pad is bonded to a corresponding first bonding pad to form a conductive bonding structure.

3. The semiconductor device as claimed in claim 1, further comprising: An encapsulation layer is disposed on the intermediary layer and laterally encapsulates the plurality of memory chips.

4. The semiconductor device of claim 3, wherein the plurality of memory chips includes a first memory chip and a second memory chip arranged side by side, wherein the encapsulation layer is located in the gap between the first memory chip and the second memory chip.

5. The semiconductor device of claim 1, wherein the second bonding pad is located in the second region and is electrically connected to the logic circuit.

6. The semiconductor device as claimed in claim 1, wherein the interposer further comprises: Intermediate layer substrate; A redistribution structure is disposed on the interposer substrate; And multiple through-substrate vias that penetrate the interposer substrate and are electrically connected to the redistribution structure.

7. The semiconductor device as claimed in claim 1, further comprising: A packaging substrate is disposed on the second surface of the interposer layer; And a plurality of conductive connectors are disposed between the interposer and the encapsulation substrate.

8. The semiconductor device of claim 7, wherein the plurality of memory dies are directly electrically connected to the package substrate through the interposer and the plurality of conductive connectors.

9. The semiconductor device of claim 1, wherein the interposer further includes a first bonding dielectric layer adjacent to the first surface and the first bonding pad is located in the first bonding dielectric layer, wherein each of the plurality of memory chips further includes a second bonding dielectric layer facing the first bonding dielectric layer, the second bonding pad is located in the second bonding dielectric layer, and the first bonding dielectric layer directly contacts the second bonding dielectric layer.

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