Image sensor pixel and methods of forming the same

Abstract

An image sensor pixel includes a photosensor disposed in a semiconductor substrate. To provide isolation to reduce inter-pixel crosstalk and increase modulation transfer function (MTF), an etch stop layer is disposed on a first surface of the semiconductor substrate, and a deep trench is etched on a second surface opposite the etch stop layer disposed on the first surface. Etching stops at the etch stop layer, and the bottom surface of the etch trench is the surface of the etch stop layer. At least one dielectric layer may be deposited on the sidewalls and bottom surface of the deep trench, and the remainder of the deep trench is filled with metal or other opaque material. The image sensor pixel includes a semiconductor substrate and a photodiode disposed therein, and a metal barrier through the semiconductor substrate and arranged to provide optical isolation for the photodiode.

Description

Technical Field

[0001] The embodiments of the present invention relate to an image sensor pixel and a method for forming the same. Prior Technology

[0002] The following content covers image sensors, image sensor manufacturing, CMOS image sensor (CIS) technology, etc.

[0003] An image sensor includes an array of image sensor pixels, each pixel including a photodiode or other light sensor. In some designs, the wafer may be thinned to match the light absorption profile, and a (selectively thinned) wafer containing a CIS may be bonded to a second wafer on which related electronic components are fabricated.

[0004] Image sensor resolution is controlled by the size of the image sensor pixels; that is, smaller image sensor pixels allow for a higher number and density of pixels to be configured in the active image sensor region. However, as image sensor pixels become smaller, (optical and / or electrical) crosstalk between neighboring image sensor pixels becomes an increasingly challenging problem. The modulation transfer function (MTF) is a commonly used metric for evaluating image sensor performance. MTF characterizes how well the image captured by the image sensor maintains the contrast of an object. For an image sensor with a given pixel resolution, the modulation transfer function (MTF) can be considered as an indicator of the degree of crosstalk between neighboring image sensor pixels; a higher MTF is desirable because it indicates reduced crosstalk. Summary of the Invention

[0005] In a non-limiting example embodiment, a method of forming an image sensor pixel includes: disposing an etch stop layer on a first surface of a semiconductor substrate; etching a deep trench from a second surface opposite to the first surface of the semiconductor substrate to the etch stop layer disposed on the first surface, wherein the etching stops at the etch stop layer and the bottom surface of the etch trench is the surface of the etch stop layer; depositing at least one dielectric layer on the sidewalls and bottom surface of the etch trench, the at least one dielectric layer leaving an unfilled portion of the etch trench; and filling the unfilled portion of the etch trench with metal.

[0006] In a non-limiting example embodiment, a method of forming an image sensor pixel includes forming an etch stop layer grid on the surface of a semiconductor substrate, using the etch stop layer grid to stop etching, etching a deep trench grid through the entire thickness of the semiconductor substrate, the cells of the deep trench grid surrounding the individual image sensor pixels of the image sensor pixel array, and configuring an opaque material in the etched deep trench grid.

[0007] In a non-limiting example embodiment, the image sensor pixel includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photodiode disposed in the semiconductor substrate; and a metal barrier passing through the semiconductor substrate and configured to provide optical isolation of the photodiode. Simple Explanation of the Diagram

[0008] The various aspects of this disclosure are best understood by reading the following detailed description of the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for the purpose of discussing clarity. Figure 1A schematically illustrates a pixel cross-sectional view of an image sensor according to one embodiment. Figure 1B schematically illustrates a pixel cross-sectional view of an image sensor according to one embodiment. Figures 2A, 2B, 2C, 2D, 2E, 2F, and 2G schematically illustrate a method for manufacturing image sensor pixels using sequential cross-sectional views. Figure 3 schematically illustrates a pixel cross-sectional view of an image sensor according to another embodiment. Figure 4 schematically illustrates a pixel cross-sectional view of an image sensor according to another embodiment. Figure 5 schematically illustrates a top view and a cross-sectional view of the image sensor pixels of Figures 1 and 2G in the context of a dual-wafer stack according to an embodiment. Figure 6 schematically illustrates a top view and a cross-sectional view of the image sensor pixels of Figures 1 and 2G in the context of a dual-wafer stack according to an embodiment. Figures 7A, 7B, 7C, 7D and 7E schematically illustrate a method for fabricating the dual-wafer stack of Figure 6. Figure 8 schematically illustrates a top view and a cross-sectional view of the image sensor pixels of Figures 1 and 2G in a three-wafer stacking context according to an embodiment. Implementation

[0009] The following disclosure provides numerous different embodiments or examples to achieve different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, spatial relative terms such as "below," "lower," "lower," "upper," and "higher" are used herein to facilitate the description of the relationship between one element or feature and another element or feature shown in the figure. These spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figure. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0011] Referring to FIG1A, a cross-sectional view of an image sensor pixel 2 according to an embodiment is schematically shown, which is formed in and / or on a semiconductor substrate 12 having a first surface 14 and a second surface 16 on opposite sides. The first surface 14 is sometimes also referred to herein as the front surface or front side 14, and the second surface 16 is sometimes referred to herein as the back surface or back side 16. In a non-limiting example, the image sensor pixel 2 is designed for back-side illumination, wherein light L illuminates the back side 16. The semiconductor substrate 12 is made of a semiconductor material, such as silicon, gallium phosphide (GaP), gallium arsenide (GaAs), etc. The exemplary semiconductor substrate 12 is made of a single material, which is silicon in this example. However, as mentioned above, other semiconductor materials are also contemplated, and the semiconductor substrate may optionally contain multiple materials, for example (in a non-limiting example) containing a silicon wafer on which one or more heteroepitaxial semiconductor layers are disposed, such as one or more silicon-germanium alloy layers having a germanium composition of x (i.e., one or more Si1-xGex layers). The semiconductor material (or material) of the semiconductor substrate 12 is appropriately selected based on design factors, such as matching the bandgap or other absorption characteristics of the semiconductor material to the wavelength, wavelength band, or region of light to be detected by the image sensor pixel 2. As shown in FIG1A, the thickness of the semiconductor substrate 12 between surfaces 14 and 16 is DSub. In some non-limiting example embodiments, the semiconductor substrate 12 may comprise a silicon wafer that has been thinned to reduce its thickness, for example, in a non-limiting example Dsub = 5 to 8 micrometers, such that the substrate thickness DSub approximately matches the absorption depth of the light to be imaged and minimizes the thickness of the image sensor.

[0012] Image sensor pixel 2 is an example pixel in a two-dimensional pixel array forming an image sensor. In a non-limiting example, the image sensor can be fabricated using complementary metal-oxide-semiconductor (CMOS) technology, in which case it may be referred to as a CMOS image sensor (CIS). Each CIS pixel 2 includes an image sensing element 18 configured to receive incident light containing photons, and an electronic readout device or sub-circuit, such as including a CMOS transistor 20. An exemplary light sensor 18 is disposed in a semiconductor substrate 12. The light sensor 18 may be a photodiode, a photocapacitor, or other electronic device that converts light into an electrical signal. In a non-limiting example embodiment, the semiconductor substrate 12 is silicon, and the light sensor 18 is a silicon, germanium, and / or Si1-xGex photodiode formed by dopant implantation and / or diffusion to form a p / n junction, heteroepitaxial formation to form a hetero junction, and / or other fabrication techniques. The light sensor 18 is designed to detect light of a wavelength or wavelength band or region to be imaged by the image sensor pixel 2 array. Light of wavelengths or wavelength bands or regions may include part or all of the visible spectrum, part or all of the ultraviolet spectrum, part or all of the infrared spectrum, combinations thereof (e.g., in the case of a visible-near-infrared image sensor), etc. The exemplary image sensor pixel 2 of FIG1A also includes an electronic readout device or sub-circuit 20 operatively connected to the light sensor 18 to transmit and / or modify and / or convert electrical signals generated by the light sensor 18 in response to light to the output of the sensor pixel. In a non-limiting example embodiment, the electronic readout device or sub-circuit 20 includes a CMOS transistor, illustrated in FIG1A by gate dielectric 22 and gate 24 and an exemplary oxide / silicon nitride spacer 26. In a non-limiting example, the semiconductor substrate 12 is a silicon substrate, the electronic readout device or sub-circuit 20 is a MOSFET or a MOSFET-based readout sub-circuit, and the image sensor pixel is a CMOS image sensor (CIS) pixel.

[0013] Referring to FIG1B, a cross-sectional view of an image sensor pixel 10 according to another embodiment is illustrated. This pixel is again formed in and / or on a semiconductor substrate 12, having a first (e.g., front) surface 14 and a second (e.g., back) surface 16 as previously described in FIG1A. The image sensor pixel 10 is designed for back-side illumination, where light L is incident on the back side 16. The semiconductor substrate 12 again has a thickness DSub between surfaces 14 and 16, as shown in FIG1B. Similar to the embodiment of FIG1A, in some non-limiting example embodiments, the semiconductor substrate 12 may comprise a silicon wafer that has been thinned to a reduced thickness, for example, DSub = 5-8 micrometers in a non-limiting example, such that the substrate thickness DSub approximately matches the absorption depth of the light to be imaged and minimizes the thickness of the image sensor.

[0014] The image sensor pixel 10 in Figure 1B is an example pixel in a two-dimensional pixel array forming an image sensor. In a non-limiting example, the image sensor can be fabricated using CMOS technology and is referred to as a CMOS image sensor (CIS). Each CIS pixel 10 includes an image sensing element 18 (e.g., a photodiode, photocapacitor, or other electronic device that converts light into electrical signals) as previously described in the embodiment of Figure 1A, configured to receive incident light containing photons, and an electronic readout device or sub-circuit, such as including a CMOS transistor 20. In a non-limiting example embodiment, the semiconductor substrate 12 is silicon, and the photosensor 18 is a silicon, germanium, and / or Si1-xGex photodiode formed by dopant implantation and / or diffusion to form a p / n junction, heteroepitaxial formation to form a hetero junction, and / or other fabrication techniques. The photosensor 18 is designed to detect light of a wavelength or wavelength band or region to be imaged by the image sensor pixel 10 array. Light of wavelengths or wavelength bands or regions may include part or all of the visible spectrum, part or all of the ultraviolet spectrum, part or all of the infrared spectrum, combinations thereof (e.g., in the case of a visible-near-infrared image sensor), etc. The example image sensor pixel 10 of FIG1B again includes an electronic readout device or sub-circuit 20 operatively connected to a light sensor 18 to transmit and / or modify and / or convert electrical signals generated by the light sensor 18 in response to light to the output of the sensor pixel. In a non-limiting example embodiment of FIG1B, the electronic readout device or sub-circuit 20 is a CMOS transistor, represented in FIG1B by a gate dielectric 22 and a gate 24, and an example oxide / silicon nitride spacer 26. In a non-limiting example, the semiconductor substrate 12 is a silicon substrate, the electronic readout device or sub-circuit 20 is a MOSFET or a MOSFET-based readout sub-circuit, and the image sensor pixel is a CMOS image sensor (CIS) pixel.

[0015] Continuing with reference to Figures 1A and 1B, in a non-limiting example, the electronic readout device or sub-circuit 20 includes a transmission gate and associated circuitry (not shown). During the exposure interval for acquiring an image (e.g., set by the shutter speed in the case of a digital camera), photocharge accumulates in each pixel 2 or 10, and more specifically in the photodiode or other light sensor 18 of each pixel. At the end of the exposure, the photocharge accumulated in the light sensor 18 of each pixel 2 or 10 is transferred out through one or more transmission gates (i.e., readout). This should be understood as a non-limiting example, and various readout circuits may be employed in a CIS or other image sensor depending on design considerations. It should also be understood that portions of the readout circuitry may be configured on a second wafer or chip bonded to the semiconductor substrate 12. Some non-limiting examples of such multi-wafer CIS or other image sensor designs are described herein with reference to Figures 5, 6, and 8.

[0016] It should be understood that the two example image sensor pixels 2 and 10 shown in Figures 1A and 1B, respectively, are representative. In embodiments, the image sensor includes a two-dimensional array of image sensor pixels 2; or the image sensor includes a two-dimensional array of image sensor pixels 10. Although not shown in Figures 1A and 1B (but see Figures 5, 6, and 8 and the related description below), a metallization layer or stack may be configured on the front side 14 of the image sensor including the two-dimensional array of image sensor pixels to provide an electrical transmission path for the pixel output of the electronic readout device or sub-circuit 20 of the image sensor pixels. Taking a CMOS image sensor as an example, the electronic readout device or sub-circuit 20 of image sensor pixels 2 and 10, as well as the signal output metallization layer or stack, are suitable for fabrication using CMOS manufacturing techniques. Furthermore, the image sensor pixels may include other features not shown. For example, one or more light-coupling and / or light-shaping elements or features, such as lenses or microlenses, and / or color filters, may be configured on the light-receiving second surface 16, and / or an anti-reflective coating may be applied to the light-receiving second surface 16, and / or the light-receiving second surface 16 may be roughened and / or textured. Optional lenses or microlenses may be provided to focus light onto the photosensor 18. Optional color filters may be provided to allow light to pass through a specific wavelength band while blocking unwanted light outside that wavelength band. As a more specific, non-limiting example, in a red-green-blue (RGB) imaging array, image sensor pixels 2 or 10 may be grouped into color pixels, each color pixel including: an image sensor pixel 2 or 10 with a red filter; an image sensor pixel 2 or 10 with a blue filter; and an image sensor pixel 2 or 10 with a green filter. In some RGB imaging array designs, each color pixel may contain additional "color" elements, such as image sensor pixels 2 or 10 with or without a transparent filter. As another non-limiting example of a possible further element, a grid may be configured on the light-receiving surface 16, with grid lines extending between adjacent image sensor pixels 2 or 10 forming a two-dimensional array of image sensor pixels for CMOS image sensors or other image sensors. The grid comprises an opaque material and reduces optical crosstalk between adjacent image sensor pixels 2 or 10 in the two-dimensional array of image sensor pixels. In one non-limiting example, the grid lines extending between pixels can be formed by depositing and patterning a metal layer and / or a dielectric layer, thereby forming the grid.

[0017] As previously mentioned, the image sensor resolution is controlled by the size of the respective image sensor pixels 2 or 10 in Figure 1A or Figure 1B that make up the two-dimensional array. Smaller image sensor pixels allow for a greater number and higher density of image sensor pixels to be configured within a given effective image sensor area. However, as the image sensor pixels 2 or 10 become smaller, crosstalk (optical and / or electrical) between adjacent image sensor pixels becomes an increasingly challenging problem. Optical crosstalk refers to the leakage of light incident on one image sensor pixel into adjacent image sensor pixels, while electrical crosstalk refers to the leakage of photocharge (i.e., electrons or holes generated by incident light L) from the photosensor 18 in one image sensor pixel into adjacent image sensor pixels. Optical and / or electrical crosstalk can blur image content between pixels, thereby reducing the ability of the image sensor to maintain object contrast and thus decreasing the value of the modulation transfer function. Conversely, suppressing crosstalk can improve the ability of the image sensor to maintain object contrast, thereby increasing the modulation transfer function. As previously mentioned, arranging a grid (not shown) with grid lines extending between adjacent pixels on the light-receiving surface 16 is one way to reduce optical crosstalk. However, such a surface grid cannot block optical crosstalk caused by light propagating laterally through the semiconductor substrate 12.

[0018] Referring to Figures 1A and 1B, deep trench isolation can be formed in the semiconductor substrate 12 to reduce crosstalk caused by light propagating laterally through the semiconductor substrate 12. The example image sensor pixels 2 and 10 in Figures 1A and 1B respectively illustrate two alternative methods for providing deep trench isolation to suppress crosstalk between adjacent image sensor pixels. In the method for image sensor pixel 2 of Figure 1A, a shallow trench isolation region 4 (STI; i.e., STI region 4 or STI 4) is formed on the front surface 14 of the semiconductor substrate 12. To form the STI region 4, a shallow trench of depth DSTI is etched into the front surface 14 of the semiconductor substrate 12 (as shown in Figure 1A), followed by deposition of an oxide layer filling the shallow trench to form the STI region 4 of depth DSTI, and chemical mechanical polishing (CMP) to remove any excess oxide that may have deposited on the front surface 14 of the semiconductor substrate 12. The STI region 4 serves as an etch stop layer for forming the deep trench isolation (DTI) 6 with STI stop, thus isolating the image sensor pixel 2. To form the STI-stopped DTI 6, an STI-stopped deep trench is etched from the second (e.g., back side) surface 16 of the semiconductor substrate 12, for example using dry etching. The dry etching is stopped by STI 4 before reaching the first (e.g., front side) surface 14 of the semiconductor substrate 12; that is, STI 4 serves as an etch stop layer for forming the STI-stopped deep trench. The STI-stopped deep trench at this stage opens at the second (e.g., back side) surface 16 of the semiconductor substrate 12. The bottom and sidewalls of the STI-stopped deep trench are then coated with one or more dielectric layers (e.g., in a non-limiting example, one or more high-dielectric layers 30 and one oxide layer 32), which also coat the second surface 16 of the semiconductor substrate 12, and then filled with metal 34, such as electroplated copper or aluminum deposited by physical vapor deposition (PVD). The one or more high-dielectric layers 30 contain one or more dielectric materials with a dielectric constant higher than that of silicon dioxide. In some embodiments, the oxide layer 32 is formed by atomic layer deposition (ALD). In the example, an additional oxide layer 36 is deposited, for example, through low-temperature remote plasma-assisted oxidation (LRPO), to provide water resistance to the light-receiving surface 16.

[0019] One or more dielectric layers 30, 32 are typically thinner than the semiconductor substrate 12. In some non-limiting examples, the substrate thickness DSub is approximately 5–8 micrometers, while the thickness of the dielectric layers 30, 32 ranges from nanometers to tens of nanometers. As shown in Figure 1A, the depth of DTI 6 at the STI stop is D1, and the depth of STI region 4 is DSTI. Ignoring the thickness of the (typically thin) dielectric layers 30, 32, the thickness D1 of DTI 6 at the STI stop is the difference between the substrate thickness DSub and the STI depth DSTI, i.e., D1 ≅ DSub - DSTI. Although STI region 4 contains silicon dioxide and thus provides good electrical isolation, silicon dioxide is optically translucent or transparent in at least the visible, near-infrared, and near-ultraviolet spectral regions. Therefore, STI region 4 presents a gap of size DSTI in optical isolation. In some non-limiting examples of CMOS fabrication, the STI depth DSTI may be in the range of approximately 0.2 μm to 0.5 μm. If the substrate thickness DSub is approximately 5–8 μm, then the DSTI is approximately 2.5% to 10% of the total substrate thickness DSub. As recognized herein, this gap in the optical isolation provided by the deep trench isolation of image sensor pixel 2 reduces the effectiveness of optical isolation, leading to increased crosstalk between image sensor pixels and a decrease in the modulation transfer function (MTF) of the image sensor.

[0020] Referring to FIG1B, in the isolation method for image sensor pixel 10, the STI region 4 is replaced by an etch stop layer 40 disposed on the first surface 14 of the semiconductor substrate 12. The isolation method for image sensor pixel 10 does not involve etching trenches in the first surface 14 of the semiconductor substrate 12 (while the formation of the STI 4 for the isolation of image sensor pixel 2 does involve etching a shallow trench, which is then filled to form the STI 4). In the example of FIG1B, the etch stop layer 40 includes at least one dielectric layer on the first surface 14 of the semiconductor substrate 12 (in the non-limiting example of FIG1B, two dielectric layers 42 and 44). In the non-limiting example of FIG1B, these include an oxide layer 42 disposed on the first surface 14 of the semiconductor substrate 12, and a silicon nitride layer 44 deposited on the oxide layer 42. The etch stop layer 40 serves as an etch stop layer for forming the deep trench isolation (DTI) 50 for isolating the image sensor pixel 10. To form the DTI 50, a deep trench is etched from the second (e.g., back side) surface 16 of the semiconductor substrate 12, for example using dry etching. The dry etching is stopped by an etch stop layer 40 such that the bottom of the deep trench coincides (or nearly coincides) with the first (e.g., front side) surface 14 of the semiconductor substrate 12. In other words, the etch stop layer 40 serves as an etch stop layer for forming the deep trench. The deep trench extends completely from the second surface 16 through the semiconductor substrate 12 to the first surface 14. At this stage, the deep trench opens at the second (e.g., back side) surface 16 of the semiconductor substrate 12. The bottom and sidewalls of the deep trench are then coated with one or more dielectric layers (e.g., in a non-limiting example, one or more high-dielectric layers 30 and oxide layers 32), which also coat the second surface 16 of the semiconductor substrate 12. The deep trench is then filled with a metal 54, such as electroplated copper or aluminum deposited through PVD. As previously described, one or more high-dielectric layers 30 comprise one or more dielectric materials having a dielectric constant higher than that of SiO2. In some embodiments, oxide layer 32 is formed via ALD. In an example, an additional oxide layer 36 is deposited, for example via LRPO, to provide water resistance, for example, to the light-receiving surface 16.

[0021] As previously mentioned, one or more dielectric layers 30, 32 are typically thinner than the thickness DSub of the semiconductor substrate 12, and in some non-limiting example embodiments, this thickness is approximately 5-8 micrometers. As shown in Figure 1B, DTI 50 has a depth D2. Example DTI 50 extends completely from the second surface 16 through the semiconductor substrate 12 to the first surface 14, and in this example also includes a small additional portion overlapping the combined thickness of one or more dielectric layers 30, 32. Therefore, the depth D2 of DTI 50 is greater than or equal to the thickness DSub of the substrate 12. In other words, D2... [> ]DSub.

[0022] As previously described, the STI region 4 of image sensor pixel 2 presents a gap of size DSTI in optical isolation. The metal 34 of the STI-stopped DTI 6 has a depth D1, which is limited by the thickness DSTI of the STI region 4. In some non-limiting example embodiments, the STI depth DSTI is approximately between 2.5% and 10% of the total substrate thickness DSub. Accordingly, the depth D1 of the STI-stopped DTI 6 is limited to approximately 90% to approximately 98% of the semiconductor substrate thickness DSub. In contrast, the DTI 50 extends completely from the second surface 16 through the semiconductor substrate 12 to the first surface 14, advantageously providing improved isolation to suppress optical crosstalk between adjacent image sensor pixels and improving (i.e., increasing) the MTF of the image sensor.

[0023] The embodiment of Figure 1B does not use the STI region 4 in the embodiment of Figure 1A as a stop for forming the DTI 50. In some implementations of the embodiment of Figure 1B, the CMOS image sensor or other two-dimensional image sensor pixel array constituting the image sensor may not include an STI region at all. This may be advantageous because forming the STI region requires multiple manufacturing steps, such as photolithography-controlled dry etching to form a shallow trench on the front side 14, followed by thermal oxidation to fill the shallow trench with oxide material to form the STI region, and then chemical mechanical polishing (CMP) to remove excess thermal oxide from the front side 14. In other implementations of the embodiment of Figure 1B, the CMOS image sensor or other two-dimensional image sensor pixel array constituting the image sensor may include an STI region (not shown) for purposes other than as a stop for forming the deep trench isolation.

[0024] Figures 1A and 1B illustrate cross-sectional views of image sensor pixels 2 and 10, respectively, employing DTI 6 and DTI 50 with STI stops. It can be understood that in practical applications, all image sensor pixels constituting a two-dimensional image sensor pixel array typically employ the same type of DTI. For example, all image sensor pixels in a two-dimensional image sensor pixel array employ DTI 50 for image sensor pixel 10, where the metal 54 of the DTI 50 advantageously extends completely from the first surface 14 of the semiconductor substrate 12 to its second surface 16. Furthermore, the DTI 50 can be formed as a DTI grid 50 (e.g., see Figure 2F), where each image sensor pixel 10 (including the light sensor 18 of pixel 10) is substantially or completely surrounded or encircled by the surrounding portion of the DTI (grid) 50. This can be seen in the cross-sectional view of Figure 1B, where image sensor pixel 10 has DTI 50 on both sides.

[0025] Referring now to Figures 2A, 2B, 2C, 2D, 2E, 2F, and 2G, a method for manufacturing the image sensor pixel 10 of Figure 1B is illustrated through successive cross-sectional views. Note that Figure 2A illustrates two image sensor pixels being manufactured, while the remaining Figures 2B to 2G illustrate a single image sensor pixel being manufactured.

[0026] Figure 2A illustrates two image sensor pixels under fabrication after the formation of a photosensor 18 in a semiconductor substrate 12, and after the formation of gate oxide layers 22 and gates 24 of a CMOS transistor 20 on a first surface 14 of the semiconductor substrate 12. In a suitable method, continuous oxide and polysilicon layers corresponding to gate oxide layers 22 and 24, respectively, are deposited and patterned. As further shown in Figure 2A, a continuous oxide layer 42L is disposed on the first surface 14 of the semiconductor substrate 12, and a continuous silicon nitride layer 44L is deposited on the continuous oxide layer 42L. Subsequent etching removes these layers from the top of the gates 24.

[0027] Figure 2B illustrates an image sensor pixel being manufactured after etching a continuous oxide layer 42L and a continuous silicon nitride layer 44L to isolate the oxide / silicon nitride spacer 26 of the CMOS transistor 20. Further etching leaves a portion of the continuous oxide layer 42L and the continuous silicon nitride layer 44L, forming the oxide layer 42 and silicon nitride layer 44 of the etch stop layer 40 disposed on the first surface 14 of the semiconductor substrate 12.

[0028] The process described with reference to FIG2A and 2B is performed on the first surface (e.g., front side) 14 of the semiconductor substrate 12. As shown in FIG2A and 2B, no components or other fabricated features have been formed on the second surface (e.g., back side) 16 of the semiconductor substrate 12 so far.

[0029] Figure 2C illustrates an image sensor pixel under fabrication, after a deep trench 60 is etched starting from the second surface 16, the etching proceeds to an etch stop layer 40 disposed on the first surface 14, and then stops. The etching stops at the etch stop layer 40, the bottom surface 62 of which is the surface of the etch stop layer 40, specifically the surface of the silicon nitride layer 44 of the etch stop layer 40 in the example of Figure 2B. The deep trench 60 also has sidewalls 64 and an opening 66 at the second surface 16.

[0030] To further visualize the geometry of the deep trench 60, Figure 2C also shows a top view 70, viewed along the V1-V1 direction indicated in the cross-sectional view of Figure 2C. As shown in top view 70, the deep trench 60 forms a grid, with the photosensitive portion 72 of each image sensor pixel (including the pixel's light sensor 18) mostly or completely surrounded or encircled by the surrounding portion of the deep trench 60. In other words, the etch stop layer 40 is an etch stop layer grid 40, and the deep trench 60 is a deep trench grid 60, with cells of the deep trench grid 60 surrounding the individual image sensor pixels. In top view 70, the bottom surface 62 of the trench is visible. Therefore, when the deep trench grid 60 is filled with metal 54 (see Figure 2E), the metal 54, mostly or completely surrounding the deep trench isolation 50, forms a deep trench isolation grid 50, providing optical isolation to suppress crosstalk between adjacent image sensor pixels.

[0031] To allow trench 66 to be etched from the second (i.e., back) surface 16, the semiconductor substrate 12 is appropriately flipped. To provide structural support, the front surface 14 may be selectively bonded to a support wafer, secured by adhesive tape, or otherwise supported. Although not shown, it is conceivable to first form partial or complete metallization of the front surface 14, for example, comprising one or more patterned metallization layers spaced by an interlayer dielectric (IMD) material. For example, such metallization of the front surface 14 can provide electrical interconnections for the metal-oxide-semiconductor transistor 20 of the final image sensor.

[0032] By way of non-limiting example, the etching to form the deep trench 60 can employ dry etching, plasma etching, or similar methods, using an etchant that selectively etches the semiconductor material of the semiconductor substrate 12 without etching at least one layer of material in the etch stop layer 40 (e.g., in this example, the silicon nitride layer 44 is not etched). Lithography patterning is used to depict the lateral regions of the deep trench 60, for example, by coating a photoresist layer on a second (e.g., back side) surface 16, optically exposing the photoresist using a lithography mask to form a latent image of the deep trench 60 pattern in and / or on the photoresist, and developing the latent image to form openings in the photoresist corresponding to the deep trench 60 pattern. Etching is then performed through the openings in the photoresist. Alternatively, the lithography patterning may further employ one or more hard masks deposited prior to photoresist coating and patterned during development to provide sufficient mask resistance to the etchant.

[0033] Figure 2D illustrates the fabrication state of an image sensor pixel after the deposition of one or more dielectric layers 30, 32. In the example, these include one or more high-dielectric layers 30 having a dielectric constant higher than that of silicon dioxide, deposited in a non-limiting example by chemical vapor deposition (CVD); and an oxide layer 32, deposited in a non-limiting example by atomic layer deposition (ALD). As shown in Figure 2D, one or more dielectric layers 30, 32 are conformally deposited such that they are conformally coated on the second surface 16 of the semiconductor substrate 12 and the bottom surface 62 and sidewalls 64 of the deep trench 60. As previously mentioned, the one or more dielectric layers 30, 32 are relatively thin, for example, in some non-limiting example embodiments on the order of nanometers to tens of nanometers. Therefore, the conformally coated one or more dielectric layers 30, 32 leave a large portion of the internal volume of the deep trench 60 unfilled. That is, one or more dielectric layers 30, 32 leave unfilled portions in the etched deep trench 60.

[0034] Figure 2E illustrates the manufacturing state of an image sensor pixel after further filling the unfilled portions of the etched deep trench 60 with metal 54. In a non-limiting example embodiment, metal 54 is copper, and filling the unfilled portions of the etched deep trench 60 with metal (copper in this case) 54 is accomplished by electroplating, wherein a thin conformal copper seed layer is first applied by CVD or a similar method, followed by copper electroplating.

[0035] In another non-limiting example embodiment, the metal 54 is aluminum, and the filling of the unfilled portion of the etched deep trench 60 with the metal (here, aluminum) 54 is accomplished by physical vapor deposition (PVD).

[0036] In the example above, the etched deep trench 60 is filled with metal, namely copper or aluminum. More generally, the etched deep trench 60 is filled with an opaque material that is opaque to the wavelength or wavelength band or region of light that the image sensor pixel 10 is to image.

[0037] As shown in Figure 2E, whether by electroplating or PVD, the metal deposition is not limited to the deep trench 60; instead, excess metal 80 (e.g., excess electroplated copper 80 or excess aluminum 80 deposited through PVD in two non-limiting example embodiments) covers the second surface 16 of the semiconductor substrate 12 (or more precisely, covers one or more dielectric layers 30, 32 previously deposited on the second surface 16 of the semiconductor substrate 12 as described in Figure 2D).

[0038] Figure 2F illustrates the manufacturing state of an image sensor pixel after the removal of excess metal 80 in a subsequent chemical mechanical polishing (CMP) step. To further illustrate the geometry of this manufacturing stage, Figure 2C also shows a top view 82, viewed along the V2-V2 direction indicated in the cross-sectional view of Figure 2F. As shown in top view 82, the metal 54 filling the deep trench 60 forms a grid, and the photosensitive portion 72 of each image sensor pixel (including the pixel's photosensitive element 18) is mostly or completely surrounded or encircled by portions of the surrounding metal 54. In top view 82, the photosensitive portion 72 is covered by one or more dielectric layers 30, 32, with the uppermost dielectric layer 32 visible in top view 82. The surrounding metal 54 of the deep trench isolation 60 provides optical isolation to suppress crosstalk between adjacent image sensor pixels. Referring to the main cross-sectional view and top view 82, it can be seen that the deep trench isolation 50 includes a metal barrier 54 extending through the semiconductor substrate 12, configured to provide optical isolation for the photodiode 18 of the image sensor pixel 10.

[0039] Figure 2G illustrates the state of image sensor pixel 10 in Figure 1B after a final optional manufacturing step, which involves depositing an additional oxide layer 36, for example, via low-temperature remote plasma-assisted oxidation (LRPO), to provide water resistance or other protection against contaminant intrusion. The additional oxide layer 36 covers the ends of the metal 54 previously exposed on the second surface 16 to prevent oxidation or other degradation of the metal 54 and / or contaminant intrusion through the interface between the metal 54 and the oxide 32.

[0040] Referring now to FIG3, a cross-sectional view of an image sensor pixel 100 according to another embodiment is illustrated. The image sensor pixel 100 in FIG3 is similar to the image sensor pixel 10 in FIG1 and FIG2G, including a semiconductor substrate 12 having opposing first and second surfaces 14 and 16, a photosensor (e.g., a photodiode) 18, a metal-oxide-semiconductor transistor 20 having previously described elements 22, 24, 26, one or more dielectric layers 30, 32 and an additional oxide layer 36, and an etch stop layer 40 including an oxide layer 42 disposed on the first surface 14 of the semiconductor substrate 12 and a silicon nitride layer 44 deposited on the oxide layer 42. The image sensor pixel 100 differs from the image sensor pixel 10 in that the image sensor pixel 100 has a different deep trench isolation (DTI) 150 for isolating the image sensor pixel 100. Although the DTI 50 of image sensor pixel 10 in Figures 1 and 2G extends to the silicon nitride layer 44 of etch stop layer 40, the DTI 150 of image sensor pixel 100 in Figure 3 extends only to the oxide layer 42 of etch stop layer 40. To obtain the DTI 150 of image sensor pixel 100, the etchant forming the deep trench 66 (see Figure 2C) is selectively stopped at oxide layer 42. In other words, the etchant is selected to selectively etch the semiconductor material of semiconductor substrate 12 without etching the oxide material of oxide layer 42. Therefore, in image sensor pixel 100 of Figure 3, the bottom surface of the etched deep trench 60 is the surface of oxide layer 42 when manufacturing image sensor pixel 100 of Figure 3.

[0041] Figure 4 illustrates a cross-sectional view of an image sensor pixel 200 according to another embodiment. The image sensor pixel 200 in Figure 4 is similar to image sensor pixel 10 in Figures 1 and 2G and image sensor pixel 100 in Figure 3, again including a semiconductor substrate 12 having opposing first and second surfaces 14 and 16, a photosensor (e.g., a photodiode) 18, a metal-oxide-semiconductor transistor 20 having previously described elements 22, 24, 26, one or more dielectric layers 30, 32, and an additional oxide layer 36. The image sensor pixel 200 differs from image sensor pixels 10 and 100 in that it employs an etch stop layer 240 different from the etch stop layer 40 of image sensor pixels 10 and 100. The etch stop layer 240 is a metal via 240 formed on the first surface 14. For example, the metal via 240 may be a tungsten via metallized (not shown) on the front surface 14, for example comprising one or more patterned metallization layers spaced by an interlayer dielectric material. This metallization of the front surface 14 can, for example, provide electrical interconnects for the transistors 20 of the final image sensor. The metal via 240 shown is a non-functional metal via because it is not part of the electrical interconnects of the transistors 20 of the final image sensor. Instead, the metal via 240 serves as an etch stop layer 240 because the etching of the deep trench 60 (see FIG. 2C) stops at the metal via 240, and the bottom surface of the deep trench 60 is the surface of the metal via 240 when fabricating the image sensor pixel 200 of FIG. 4. However, it is also possible to connect the metal via 240 to electrical ground or a selected potential, for example, to provide electrical shielding for individual image sensor pixels, electrical manipulation of photocharge stored in the pixels, etc.

[0042] The advantage of the method in Figure 4 is that it may not require an additional process to provide the etch stop layer 240. Instead, the photolithographic mask used to form the metallized minimum layer (i.e., M0) via formed on the first surface 14 is modified to provide additional openings in the etch stop layer 240, and the via filling of the minimum layer (i.e., M0) via is therefore also filled with tungsten (or another metal selected for forming the M0 via) into the openings of the etch stop layer 240. The deep trench isolation 150 of the image sensor pixel 200 in Figure 4 is formed in the same manner as the deep trench isolation 50 of the image sensor pixel 10 in Figures 1 and 2G, except that the etching stops at the metal via 240.

[0043] Referring to FIG5, a top view and a cross-sectional view of the image sensor pixel 10 in FIG1 and FIG2G in a dual-wafer stack context are illustrated according to one embodiment. As previously described and as shown in FIG5, a metallization layer or stack 300 may be configured on the front side 14 of the image sensor containing a two-dimensional array of image sensor pixels 10 (one of which is shown in FIG5) to provide an electrical transmission path for the pixel output of the electronic readout device or sub-circuit 20 of the image sensor pixel 10. As shown in FIG5, the metallization layer or stack 300 includes one or more metallization layers (example metallization layers M1, ..., Mx, Mz) interconnected through vias 302, the metallization layers M1, ..., Mx, Mz and vias 302 being embedded in an interlayer dielectric (ILD) 304, other alternative names such as interlayer metal dielectric (IMD) material or the like are also known to those skilled in the art. The metallization layer or stack 300 is appropriately formed during the back-end process, for example, involving iteratively forming each successive metallization layer M1, ..., Mx, Mz and via 302 connecting the underlying metallization layer (or, for metallization layer M1, connecting to image sensor pixel 10).

[0044] In Figure 5, the resulting wafer is designated wafer T1, which includes image sensor pixels 10 fabricated in and / or on a semiconductor substrate 12, and a metallization layer or stack 300. An example in Figure 5 further illustrates the bonding of wafer T1 to a second wafer T2, which includes a (second) semiconductor substrate 12' with electronic components 310 fabricated thereon, and a (second) metallization layer or stack 300' containing a metallization layer embedded in an ILD 304' and connected via a via 302'. A bonding 320 joins the two wafers T1 and T2 together. Example bonding 320 does not use solder bonding for electrical connection, but instead employs copper (or other metal) pads 322 formed directly on the bonding surfaces of the respective metallization layers or stacks 300 and 300' (specifically contacting the topmost Mz metallization layer). Other wafer bonding methods are also contemplated, including those using solder. The electronic components 310 of the second wafer T2 may be transistors (such as planar, fin field-effect transistors (FinFETs), gate all-loop (GAA) transistors, etc.) or other electronic components, forming integrated circuit (IC) back-end logic to realize image sensor data storage, analog-to-digital (A / D) conversion circuits, digital image processing (DSP), and various combinations thereof and / or other functions.

[0045] In the example of Figure 5, the DTI grille 50 is aligned with a portion of the patterned M1 metal layer, and the metal does not extend beyond the M1 metal layer into the metallization stack 300. This achieves a trench-type contact window 234, as shown in the top view of Figure 5, forming a trench-type contact window grille 234 around the image sensor pixel (where the top view shows a portion of the trench-type contact window grille 234 around the example photosensor 18). The trench-type contact window grille 234 provides adequate light isolation for the photosensor 18 of the image sensor pixel if the light penetration depth does not significantly extend into the metallization layer or stack 300 of the first wafer T1.

[0046] Referring to FIG6, top and cross-sectional views of the image sensor pixel 10 in FIG1 and FIG2G are shown in the context of a two-wafer stack, which is a variant embodiment compared to FIG5. As previously shown in FIG5, this embodiment also includes a metallization layer or stack 300 on the front side 14 of the image sensor, which includes a two-dimensional array of image sensor pixels 10 (one of which is shown in FIG6). The metallization layer or stack 300 includes one or more metallization layers M1, ..., Mx, Mz, which are interconnected through vias 302 and embedded in an interlayer dielectric (ILD) 304, as previously described with reference to FIG5. As shown in Figure 5, the obtained wafer T1 is bonded to the second wafer T2. The second wafer T2 includes a (second) semiconductor substrate 12' in which and / or on which electronic components 310 are fabricated, and a (second) metallization layer or stack 300', which includes a metallization layer embedded in an ILD 304' and connected through a via 302'. A bonding 320 bonds the two wafers T1 and T2 together. Electrical contact windows are achieved by direct bonding through metal pads 322 formed on the bonding surfaces of the respective metallization layers or stacks 300 and 300'.

[0047] In the example of Figure 6, the DTI grid 50 is aligned with a portion of the patterned M1 metal layer, and the metal extends beyond the M1 metal layer into the metallization stack 300, through subsequent patterned metal layers Mx, ..., Mz to the metal pad 322, where it connects with further metallization in the metallization stack 300' of the second wafer T2, which extends through the patterned metal layers Mz, ..., Mx, ..., M1 of the metallization stack 300' of the second wafer T2. Thus, this achieves a grid-type contact window 236 extending through the two metallization stacks 300 and 300' formed during the back-end processes of the respective two wafers T1 and T2. As seen in the top view of Figure 6, this forms a grid-type contact window 236 surrounding the photosensor pixel (where the top view of Figure 6 shows a portion of the grid-type contact window 236 surrounding the example photosensor 18). The grid-type contact window 236 provides adequate optical isolation for the photosensitive element 18 of the image sensor pixel, even if the light penetration depth extends significantly into the metallization layer or stack 300 of the first wafer T1, and even if the light penetrates significantly into the metallization layer or stack 300' of the second wafer T2. The grid-type contact window 236 may be electrically non-functional because it has no electrical bias. Instead, the grid-type contact window 236 serves only as an optical crosstalk barrier as just described. However, it is also possible to connect the grid-type contact window 236 to an electrical bias circuit (not shown) in the second wafer T2, such as electrically grounding the grid-type contact window 236, or applying a selected potential to the grid-type contact window 236, for example, to provide electrical shielding for individual image sensor pixels, to electrically manipulate the photocharge stored in the pixels, or for similar purposes.

[0048] Referring to Figures 7A, 7B, 7C, 7D, and 7E, a method for fabricating the two wafer stacks of Figure 6 is illustrated. Figure 7A illustrates the fabricated image sensor pixel 10. This corresponds to Figure 2B in the process sequence of Figures 2A, 2B, 2C, 2D, 2E, 2F, and 2G, and includes sidewalls (SW) 26 formed by oxide and silicon nitride layers 42 and 44, which also form an etch stop layer 40.

[0049] Figure 7B illustrates the initial stage of back-end processing on the front side 14 of the image sensor to form a first portion of the interlayer dielectric 304 and a patterned M1 metallization layer connected to the image sensor pixels through vias. This layer also forms contact windows 330 on the etch stop layer 40. Figure 7C illustrates further back-end processing on the front side 14 of the image sensor to form subsequent metallization layers Mx, ..., Mz. Figure 7D illustrates wafer T1 being bonded to a second wafer T2 via bonding 320.

[0050] It is worth noting that in the manufacturing stage shown in FIG. 7D, the back side 16 of the semiconductor substrate 12 of the image sensor pixel is exposed, and wafer T1 (which may be selectively thinned during the fabrication of the image sensor pixel) is supported on a second wafer T2. Therefore, the back side 16 is exposed to perform the remaining back-side processes previously described with reference to FIGS. 2C, 2D, 2E, 2F, and 2G. To illustrate this, FIG. 7E illustrates the image sensor pixel under fabrication, where a deep trench 60 is etched starting from the second surface 16 (i.e., the back side 16), and the etching continues until an etch stop layer 40 disposed on the first surface 14 (i.e., the front side 14) is reached and then stopped. Therefore, FIG. 7E corresponds to FIG. 2C. By performing the further back-side processes previously described with reference to FIGS. 2D to 2G, the final image sensor pixel shown in FIG. 6 is obtained.

[0051] Figures 5 and 6 illustrate an example of a two-wafer stack including wafer T1, which contains an image sensor bonded to a second wafer T2. The second wafer T2 may provide image sensor driving circuitry or similar components, including element 310 formed in and / or on the semiconductor substrate 12' of the second wafer T2. It is understood that such a wafer stack can be extended to three (or more) wafers, with wafer T1 containing the image sensor being the top layer of the stack to receive light.

[0052] Referring to Figures 8, 1, and 2G, the top and cross-sectional views of the image sensor pixels are illustrated in the context of a three-wafer stack comprising a wafer T1 containing the image sensor, a second wafer T2, and a third wafer T3. This example differs from Figures 5 and 6 in that the wafer T1 containing the image sensor is bonded to the back side of the second wafer T2, i.e., to the back side of the semiconductor substrate 12', which is opposite to the metallization stack 300 formed in the back-end process of the first wafer T1. Therefore, a bonding 420 is formed between the metallization stack 300 of the first wafer T1 and the back side of the semiconductor substrate 12' of the second wafer T2. A further bonding 422 is formed between the metallization stack 300' formed on the front side of the second wafer T2 and the metallization stack 300'' formed on the front side of the third wafer T3 (wherein the metallization stack 300'' is again formed on the semiconductor substrate 12'' of the third wafer T3 during the back-end process of the third wafer T3). The second wafer T2 includes through-silicon vias (TSVs) 424 through the semiconductor substrate 12' to achieve electrical connection between the metallization stack 300 of the first wafer T1 and the metallization stack 300' formed on the front side of the second wafer T2. If the semiconductor substrate 12' is a silicon wafer, then the TSVs 424 can be considered as through-silicon vias (TSVs).

[0053] In the example of Figure 8, the deep trench isolation grid 50 is aligned with a portion of the patterned M1 metal layer, and the metal extends beyond the M1 metal layer into the metallization stack 300 through subsequent patterned metal layers Mx, ..., Mz to the metal pad 322, where it connects with further metallization in the metallization stack 300' of the second wafer T2, which extends through the patterned metal layers Mz, ..., Mx, ..., M1 of the metallization stack 300' of the second wafer T2. In this example, the contact window grid is further connected with more metallization in the metallization stack 300'' of the third wafer T3, which extends through the patterned metal layers Mz, ..., Mx, ..., M1 of the metallization stack 300'' of the third wafer T3. Thus, this achieves a grid-type contact window 236 extending through all three metallization stacks 300, 300', and 300'' formed during the back-end processes of the respective three wafers T1, T2, and T3. As shown in the top view of Figure 8, this forms a grid-type contact window 436 surrounding the image sensor pixel (where the top view of Figure 8 shows a portion of the grid-type contact window 436 surrounding the example photosensor 18). Even if the light penetration depth extends into the metallization layer or stack 300'' of the third wafer T3, the grid-type contact window 436 provides adequate optical isolation for the photosensor 18 of the image sensor pixel. The grid-type contact window 436 may be electrically non-functional, as it has no electrical bias. Instead, the grid-type contact window 436 serves only as an optical crosstalk barrier as just described. However, it is also contemplated to connect the grid-type contact window 436 to an electrical bias circuit (not shown) in the third wafer T3, for example, to electrically ground the grid-type contact window 436, or to apply a selected potential to the grid-type contact window 436, for example, to provide electrical shielding for individual image sensor pixels, manipulate the photocharge stored in the pixels, or for other purposes.

[0054] Further embodiments are described below.

[0055] In one non-limiting example embodiment, a method of forming an image sensor pixel includes: disposing an etch stop layer on a first surface of a semiconductor substrate; etching a deep trench from a second surface opposite to the first surface of the semiconductor substrate to the etch stop layer disposed on the first surface, wherein the etching stops at the etch stop layer, and the bottom surface of the etch trench is the surface of the etch stop layer; depositing at least one dielectric layer on the sidewalls and bottom surface of the etch trench, the at least one dielectric layer leaving unfilled portions of the etch trench; and filling the unfilled portions of the etch trench with metal. In some embodiments, the method is performed to isolate an image sensor pixel comprising a light sensor disposed in a semiconductor substrate.

[0056] In one non-limiting example embodiment, a method for isolating image sensor pixels in an image sensor pixel array is disclosed, each image sensor pixel comprising a light sensor disposed in a semiconductor substrate. The method includes forming an etch stop layer grid on the surface of the semiconductor substrate, using the etch stop layer grid to stop etching, etching a deep trench grid through the entire thickness of the semiconductor substrate, and disposing an opaque material within the etched deep trench grid.

[0057] In a non-limiting example embodiment, a method of forming an image sensor pixel includes forming an etch stop layer grid on the surface of a semiconductor substrate, using the etch stop layer grid to stop etching, etching a deep trench grid through the entire thickness of the semiconductor substrate, the cells of the deep trench grid surrounding the individual image sensor pixels of the image sensor pixel array, and configuring an opaque material in the etched deep trench grid.

[0058] In a non-limiting example embodiment, the image sensor pixel includes: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photodiode disposed in the semiconductor substrate; and a metal barrier passing through the semiconductor substrate and configured to provide optical isolation of the photodiode.

[0059] In one non-limiting example embodiment, the image sensor pixel includes a photosensor disposed in a semiconductor substrate. To provide isolation to reduce inter-pixel crosstalk and improve the modulation transfer function (MTF), an etch stop layer is disposed on a first surface of the semiconductor substrate, and a deep trench is etched from an opposing second surface to the etch stop layer disposed on the first surface. Etching stops at the etch stop layer, and the bottom surface of the etch trench is the surface of the etch stop layer. At least one dielectric layer is deposited on the sidewalls and bottom surface of the etch trench, and the remaining portion of the etch trench is filled with metal, for example, by copper plating or aluminum physical vapor deposition.

[0060] In one non-limiting example embodiment, the image sensor pixel includes a photosensor disposed in a semiconductor substrate. To provide isolation to reduce inter-pixel crosstalk and improve the modulation transfer function (MTF), an etch stop layer is disposed on a first surface of the semiconductor substrate, and a deep trench is etched from an opposing second surface to the etch stop layer disposed on the first surface. Etching stops at the etch stop layer, and the bottom surface of the etch trench is the surface of the etch stop layer. At least one dielectric layer may be deposited on the sidewalls and bottom surface of the deep trench, and the remainder of the deep trench is filled with a metal or other opaque material. The image sensor pixel includes a semiconductor substrate and a photodiode disposed therein, as well as a metal barrier through the semiconductor substrate and configured to provide optical isolation for the photodiode.

[0061] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0062] 2, 10, 100, 200: Image sensor pixels 12, 12', 12'': Semiconductor substrate 14: First surface, front side 16: Second surface, back side 18: Image sensing element, light sensor, photodiode 20: Transistors, electronic reading devices, or sub-circuits 22: Gate dielectric, gate oxide layer 24: Gate 26: Oxide / Silicon Nitride Interstitial Walls and Sidewalls 30: High dielectric layer, dielectric layer 32: Oxide layer, dielectric layer 34: Metal 36: Additional oxide layer 40: Etching Stop Layer 42: Dielectric layer, oxide layer 44: Dielectric layer, silicon nitride layer 42L: Continuous oxide layer 44L: Continuous silicon nitride layer 50: Deep trench isolation 54: Metals, Metal Barriers 60: Deep groove, deep groove bar 62: Bottom surface 64: Sidewall 66: Openings, grooves, deep grooves 70, 82: Top View 72: Photosensitive area 80: Excess Metal 150: Deep trench isolation 234: Grooved contact window 236, 436: Grid-type contact window 240: Etching stop layer, metal via 300, 300', 300'': Metallized stack 302, 302', 302'': Through holes 304, 304', 304'': Interlayer dielectric 310: Electronic components 320, 420, 422: Join 322: Copper pads, metal pads 330: Contact Window 424: Silicon perforation L: Light D1, D2, DSTI: Depth DSub: Thickness V1-V1, V2-V2: Direction T1: Wafer, First Wafer T2: Second wafer T3: Third wafer

Claims

1. A method for forming image sensor pixels, comprising: An etch stop layer and an electronic readout device are disposed on the first surface of a semiconductor substrate; A metallization stack is formed on the first surface of the semiconductor substrate, wherein the metallization stack includes a contact window connecting the etch stop layer and a via electrically connected to the electronic reading device; a deep trench is etched from a second surface located on the opposite side of the semiconductor substrate relative to the first surface, etching to the etch stop layer disposed on the first surface, wherein the etching stops at the etch stop layer and the bottom surface of the etch deep trench is the surface of the etch stop layer; at least one dielectric layer is deposited on the sidewalls of the etch deep trench and the bottom surface, the at least one dielectric layer leaving an unfilled portion in the etch deep trench; and the unfilled portion of the etch deep trench is filled with metal.

2. The method as described in claim 1, wherein configuring the etch stop layer includes: At least one dielectric layer is deposited on the first surface of the semiconductor substrate.

3. The method of claim 2, wherein the at least one dielectric layer comprises a silicon nitride layer deposited on the first surface of the semiconductor substrate, and the etching stops at the silicon nitride layer, and the bottom surface of the etched deep trench is the surface of the silicon nitride layer; or wherein the at least one dielectric layer comprises an oxide layer disposed on the first surface of the semiconductor substrate, and a silicon nitride layer deposited on the oxide layer, and the bottom surface of the etched deep trench is the surface of the oxide layer.

4. The method of claim 1, wherein forming the metallization stack on the first surface of the semiconductor substrate comprises: The contact window is formed to extend into the etch stop layer and to contact the at least one dielectric layer.

5. A method for forming image sensor pixels, comprising: An etch stop grid and an electronic readout device are formed on the surface of a semiconductor substrate; A metallization stack is formed on the surface of the semiconductor substrate, wherein the metallization stack includes a contact window connecting the etch stop grid and a via electrically connected to the electronic reading device; a deep trench grid is etched over the entire thickness of the semiconductor substrate, and the etch stop grid is used to stop the etching, wherein the cells of the deep trench grid surround the individual image sensor pixels of the image sensor pixel array; and an opaque material is disposed in the etched deep trench grid.

6. The method of claim 5, wherein forming the etch stop grid comprises: At least one dielectric layer is deposited on the surface of the semiconductor substrate, and the deposited at least one dielectric layer serves as an etch stop layer to stop the etching.

7. The method of claim 5, wherein forming the etch stop grid comprises: A metal through-hole grid is formed on the surface of the semiconductor substrate, and the metal through-hole grid serves as an etch stop layer to stop the etching.

8. An image sensor pixel, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A photodiode is disposed in the semiconductor substrate; An etch stop layer is disposed on the first surface of the semiconductor substrate; an electronic readout device is disposed on the first surface of the semiconductor substrate; a metallization stack is disposed on the first surface of the semiconductor substrate and includes a contact window connecting the etch stop layer and a via electrically connected to the electronic readout device; and a metal barrier is disposed through the semiconductor substrate, the metal barrier and the contact window providing optical isolation for the photodiode.

9. The image sensor pixel as claimed in claim 8, wherein the contact window is a grid-type contact window, and the photodiode is surrounded by the grid-type contact window in a top view.

10. The image sensor pixel as claimed in claim 8, wherein the thickness of the metal barrier is equal to or greater than the thickness of the semiconductor substrate.

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