Bandgap reference circuit

Abstract

The bandgap reference circuit includes first, second, and third current sources, first and second amplifiers, a temperature coefficient adjustment unit, and resistors. Each of the first, second, and third current sources contains two stacked PMOS transistors to reduce the voltage applied to each PMOS transistor when receiving a high supply voltage. The first amplifier controls the PMOS transistors in the first and second current sources to ensure sufficient margin when receiving low supply voltages. The second amplifier provides a gain boost loop to prevent mismatch between the PMOS transistors in the first, second, and third current sources. The temperature coefficient adjustment unit introduces positive and negative temperature coefficients into the currents generated by the first and second current sources, while the resistors generate a reference voltage based on the current replicated by the third current source.

Description

Technical Field

[0001] This disclosure relates to a bandgap reference circuit, and more particularly to a bandgap reference circuit capable of operating over a wide voltage range. Prior Technology

[0002] A bandgap reference circuit is a voltage reference circuit that provides a stable and accurate reference voltage for use in various electronic systems. It is designed to produce a relatively constant output voltage that is unaffected by changes in temperature, supply voltage, and other environmental factors.

[0003] One of the main challenges facing bandgap reference circuits is achieving high accuracy and stability over a wide range of operating conditions. For example, a bandgap reference circuit may need to operate from a supply voltage of 1.5V to 0.9V to meet the requirements of various applications. However, to enable the bandgap reference circuit to operate at higher voltages (e.g., 1.5V), additional protection measures may be required to ensure that the core components of the bandgap reference circuit remain within the safe operating area (SOA). However, these protection measures may cause the bandgap reference circuit to malfunction at lower voltages (e.g., 0.9V). Therefore, designing a bandgap reference circuit that supports different voltage ranges and outputs a stable reference voltage has become an urgent problem to be solved.

[0004] This prior art section provides background information only. The statements in this prior art section are not an admission that the subject matter disclosed in this section constitutes prior art to this disclosure, and no part of this prior art section should be used as an admission that any part of this application (including this prior art section) constitutes prior art to this disclosure. Summary of the Invention

[0005] This disclosure presents a bandgap reference circuit for generating a reference voltage and outputting the reference voltage via an output node. The bandgap reference circuit includes a first current source, a second current source, a third current source, a first amplifier, a second amplifier, resistors, and a temperature coefficient adjustment unit. The first current source outputs a first current flowing through the first node and includes a first P-channel metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor connected in a stacked configuration between the power supply voltage terminal and the first node. The second current source outputs a second current flowing through the second node and includes a third PMOS transistor and a fourth PMOS transistor connected in a stacked configuration between the power supply voltage terminal and the second node. The third current source outputs a third current flowing through the output node and includes a fifth PMOS transistor and a sixth PMOS transistor connected in a stacked configuration between the power supply voltage terminal and the output node. The first amplifier has a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the control terminals of the first and third PMOS transistors. The second amplifier has a first input terminal coupled to a third node connecting a fifth PMOS transistor and a sixth PMOS transistor, a second input terminal coupled to a fourth node connecting a first PMOS transistor and a second PMOS transistor, and an output terminal coupled to a control terminal of the sixth PMOS transistor. A resistor is coupled to the output node and used to receive a third current. The temperature coefficient adjustment unit includes a first bipolar junction transistor (BJT) to receive the first current and a second BJT to receive the second current. Simple Explanation of the Diagram

[0006] This disclosure can be understood more fully by referring to the accompanying illustrations, detailed description, and claims. Similar element symbols in different illustrations refer to similar elements.

[0007] Figure 1 illustrates a bandgap reference circuit according to a comparative example of this disclosure.

[0008] Figure 2 illustrates a bandgap reference circuit according to an embodiment of the present disclosure.

[0009] Figure 3 illustrates a bandgap reference circuit according to another embodiment of this disclosure.

[0010] Figure 4 illustrates a bandgap reference circuit according to another embodiment of this disclosure.

[0011] Figure 5 illustrates an amplifier according to an embodiment of the present disclosure. Implementation

[0012] This application claims priority and benefits from U.S. formal application No. 63 / 554,164, filed February 16, 2024, the contents of which are incorporated herein by reference in their entirety.

[0013] Figure 1 illustrates a bandgap reference circuit 100 according to a comparative example of the present disclosure. The bandgap reference circuit 100 includes P-type metal-oxide-semiconductor (PMOS) transistors P1A, P2A, and P3A, an amplifier 110, resistors R1A, R2A, R3A, and R4A, and bipolar junction transistors (BJTs) B1A and B2A.

[0014] PMOS transistor P1A includes a first terminal and a second terminal coupled to a power supply voltage terminal to receive a power supply voltage VDD, and a control terminal. PMOS transistor P2A includes a first terminal and a second terminal coupled to a power supply voltage terminal to receive a power supply voltage VDD, and a control terminal coupled to the control terminal of PMOS transistor P1A. PMOS transistor P3A includes a first terminal and a second terminal coupled to a power supply voltage terminal to receive a power supply voltage VDD, and a control terminal coupled to the control terminal of PMOS transistor P1A.

[0015] Amplifier 110 has a first input terminal coupled to the second terminal of PMOS transistor P1A, a second input terminal coupled to the second terminal of PMOS transistor P2A, and an output terminal coupled to the control terminal of PMOS transistor P1A and the control terminal of PMOS transistor P2A.

[0016] BJT B1A has an emitter coupled to the second terminal of PMOS transistor P1A, a collector coupled to ground, and a base coupled to the collector of BJT B1A. BJT B2A has an emitter, a collector coupled to ground, and a base coupled to the collector of BJT B2A.

[0017] Resistor R1A has a first terminal coupled to the second terminal of PMOS transistor P1A and a second terminal coupled to ground. Resistor R2A has a first terminal coupled to the second terminal of PMOS transistor P2A and a second terminal coupled to the emitter of BJT B2A. Resistor R3A has a first terminal coupled to the second terminal of PMOS transistor P2A and a second terminal coupled to ground. Resistor R4A has a first terminal coupled to the second terminal of PMOS transistor P3A and a second terminal coupled to ground.

[0018] The bandgap reference circuit 100 can output a reference voltage VBGR through the second terminal of the PMOS transistor P3A, and the reference voltage VBGR can be expressed as I3∙R4A, where I3 is the current conducted by the PMOS transistor P3A and flowing through the resistor R4A.

[0019] Furthermore, since PMOS transistors P1A, P2A, and P3A can be connected to form a current mirror, the current I3 conducted by transistor P3A should be equal to the current I1 conducted by transistor P1A and the current I2 conducted by transistor P2A (when the aspect ratios of PMOS transistors P1A, P2A, and P3A are the same). In addition, current I1 is equal to the sum of the current I1A flowing through resistor R1A and the current I1B flowing through BJT B1A. Current I1A is proportional to the base-emitter voltage VBE of BJT B1A and has a negative temperature coefficient, while current I1B is proportional to absolute temperature and therefore has a positive temperature coefficient. Therefore, by appropriately selecting resistor R1A, current I1 can be made essentially unaffected by temperature changes, and thus the reference voltage VBGR provided by the bandgap reference circuit 100 can also be made unaffected by temperature changes.

[0020] However, as temperature increases, the voltage VC at the second terminal of PMOS transistor P3A may become different from the voltage VA at the second terminal of PMOS transistor P1A and the voltage VB at the second terminal of PMOS transistor P2A. In other words, a mismatch may occur between PMOS transistors P1A, P2A, and P3A as temperature increases. This problem may become more severe when the bandgap reference circuit 100 operates at low supply voltages. For example, in some cases, the bandgap reference circuit 100 may be used to provide a reference voltage VBGR below 1V, while the supply voltage VDD may range from 0.9V to 1.5V. In this case, when the supply voltage VDD is approximately 0.9V, the mismatch may become more pronounced and unacceptable.

[0021] Furthermore, when the bandgap reference circuit 100 operates at a high supply voltage (e.g., 1.5V), the PMOS transistors P1A, P2A, and P3A may need to withstand higher voltages. Therefore, the PMOS transistors P1A, P2A, and P3A may not be suitable for manufacturing using advanced processes for thin gate oxide fabrication, thus hindering the application of advanced processes.

[0022] Figure 2 illustrates a bandgap reference circuit 200 according to an embodiment of the present disclosure. The bandgap reference circuit 200 includes current sources 210, 220, and 230, amplifiers 240 and 250, a temperature coefficient adjustment unit 260, and a resistor R1B.

[0023] Current source 210 generates an output current I1 that flows through node N1. Current source 210 includes PMOS transistors P1B and P2B, which are cascaded between the power supply voltage terminal and node N1. Current source 220 generates an output current I2 that flows through node N2. Current source 220 includes PMOS transistors P3B and P4B, which are cascaded between the power supply voltage terminal and node N2. Current source 230 generates an output current I3 that flows through node NO1 (i.e., the output node of the bandgap reference circuit 200). Current source 230 includes PMOS transistors P5B and P6B, which are cascaded between the power supply voltage terminal and node NO1. In some embodiments, when the power supply voltage VDD is relatively high, the stacked structure of current sources 210, 220 and 230 helps to reduce the voltage applied to each PMOS transistor, thus enabling the application of advanced process nodes for thin gate oxide devices and ensuring that PMOS transistors P1B, P2B, P3B, P4B, P5B and P6B ​​are operable in SOA.

[0024] As shown in Figure 2, PMOS transistor P1B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal coupled to the second terminal coupled to node N1, and a control terminal. PMOS transistor P3B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal coupled to node N1, and a control terminal. PMOS transistor P4B has a first terminal coupled to the second terminal coupled to the second terminal coupled to node N2, and a control terminal. PMOS transistor P5B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal coupled to the second terminal coupled to node N1, and a control terminal. PMOS transistor P6B has a first terminal coupled to the second terminal coupled to the second terminal coupled to node N1, and a control terminal.

[0025] Amplifier 240 has a first input terminal coupled to node N1, a second input terminal coupled to node N2, and an output terminal coupled to the control terminals of PMOS transistor P1B and a third PMOS transistor P3B. In some embodiments, the first input terminal of amplifier 240 is a negative input terminal, and the second input terminal of amplifier 240 is a positive input terminal. However, this disclosure is not limited thereto. The output of amplifier 240 can be used to control current sources 210 and 220 to make the voltages of nodes N1 and N2 equal.

[0026] In this embodiment, the bandgap reference circuit 200 may further include a capacitor C1B having a first terminal coupled to a power supply voltage terminal and a second terminal coupled to the output terminal of the amplifier 240. The capacitor C1B helps stabilize the output of the amplifier 240. However, this disclosure is not limited thereto. In some embodiments, the capacitor C1B may be omitted.

[0027] Amplifier 250 has a first input terminal coupled to node N3, a second input terminal coupled to node N4, and an output terminal coupled to a control terminal of PMOS transistor P6B, wherein node N3 is connected to PMOS transistors P5B and PMOS transistor P6B, and node N4 is connected to PMOS transistors P1B and PMOS transistor P2B. In some embodiments, the first input terminal of amplifier 250 is a negative input terminal, and the second input terminal of amplifier 250 is a positive input terminal. However, this disclosure is not limited thereto. In some embodiments, the second input terminal of amplifier 250 may be coupled to another node connected to PMOS transistors P3B and PMOS transistor P4B.

[0028] In this embodiment, amplifier 250 can function as a source follower and maintain the voltage at node N3 (connected to the second terminal of PMOS transistor P5B and the first terminal of PMOS transistor P6B) equal to the voltage at node N4 (connected to the second terminal of PMOS transistor P1B and the first terminal of PMOS transistor P2B). Therefore, the drain-source voltages of PMOS transistors P1B, P3B, and P5B are identical, and they can operate under the same conditions without being affected by temperature changes, thus significantly reducing mismatch. Furthermore, the gain boost provided by amplifier 250 also helps increase the output resistance, thereby improving the performance of the bandgap reference circuit 200.

[0029] The temperature coefficient adjustment unit 260 includes BJTs B1B and B2B. BJT B1B receives at least a portion of the current I1 generated by current source 210, and BJT B2B receives at least a portion of the current I2 generated by current source 220. BJT B1B has an emitter coupled to node N1 to receive at least a portion of the current I1, a collector coupled to ground, and a base coupled to ground. In this embodiment, the temperature coefficient adjustment unit 260 further includes a resistor R2B. Resistor R2B has a first end coupled to the first node N1 and a second end coupled to ground.

[0030] The BJT B2B has an emitter for receiving at least a portion of the current I2, a collector coupled to ground, and a base coupled to ground. Furthermore, the temperature coefficient adjustment unit 260 also includes resistors R3B and R4B. Resistor R3B has a first terminal coupled to node N2 and a second terminal coupled to the emitter of the BJT B2B. Resistor R4B has a first terminal coupled to node N2 and a second terminal coupled to ground.

[0031] By appropriately selecting resistors R2B, R3B, and R4B, the temperature coefficient adjustment unit 260 can adjust the temperature coefficients of currents I1 and I2 to reduce the impact of temperature changes. Since current sources 210, 220, and 230 can be connected to form a current mirror, currents I1 and I2 can be mirrored to generate current I3, and resistor R1B can receive current I3 to generate a reference voltage VBGR. In this embodiment, resistor R1B has a first terminal coupled to node NO1 and a second terminal coupled to ground. In this case, the reference voltage VBGR can be output via node NO1.

[0032] Furthermore, in this embodiment, the bandgap reference circuit 200 may further include a capacitor C2B. The capacitor C2B has a first terminal coupled to node NO1 and a second terminal coupled to ground. The capacitor C2B can be used to stabilize the output of the reference voltage VBGR. However, this disclosure is not limited thereto. In some embodiments, the capacitor C2B may be omitted.

[0033] In this embodiment, the temperature coefficient adjustment unit 260 may include resistors R2B, R3B, and R4B to adjust the temperature coefficient. However, this disclosure is not limited thereto. In some embodiments, certain resistors may be omitted or other resistors may be added.

[0034] Figure 3 illustrates a bandgap reference circuit 300 according to an embodiment of the present disclosure. The difference between the bandgap reference circuit 300 and the bandgap reference circuit 200 is that the temperature coefficient adjustment unit 360 of the bandgap reference circuit 300 omits the resistor R2B.

[0035] Figure 4 illustrates a bandgap reference circuit 400 according to an embodiment of the present disclosure. The bandgap reference circuit 400 differs from the bandgap reference circuit 300 in that the temperature coefficient adjustment unit 460 of the bandgap reference circuit 400 further includes a resistor R5B. Resistor R5B has a first terminal coupled to a second terminal of the PMOS transistor P4B and a second input terminal of the amplifier 250, and a second terminal coupled to a first terminal of resistor R3B and the first terminal of resistor R4B.

[0036] In the bandgap reference circuits 200, 300, and 400, when receiving a high supply voltage VDD (e.g., 1.5V), the stacked structure of current sources 210, 220, and 230 can disperse the high voltage experienced by the PMOS transistors, thus enabling PMOS transistors P1B, P2B, P3B, P4B, P5B, and P6B ​​to operate within their SOA. However, when receiving a low supply voltage VDD (e.g., 0.9V), PMOS transistors P2B and P4B will require appropriate bias to provide sufficient voltage margin for PMOS transistors P1B and P3B to operate normally.

[0037] In some embodiments, the control terminals of PMOS transistors P2B and P4B can receive the same bias voltage VBP. In some embodiments, the bias voltage VBP can be substantially equal to VDD - 2Vt, where VDD is the power supply voltage and Vt is the threshold voltage of PMOS transistor P1B. In this case, when the power supply voltage VDD is high (e.g., greater than the threshold voltage of 1.2V or 1.5V), PMOS transistors P1B, P2B, P3B, and P4B can operate in saturation mode. Furthermore, when the power supply voltage VDD is low (e.g., less than the threshold voltage of 0.9V), PMOS transistors P2B and P4B can be fully turned on and operate in linear mode, thus facilitating the operation of PMOS transistors P1B and P3B.

[0038] In some embodiments, the bandgap reference circuits 200, 300, and 400 may further include a voltage generator specifically for providing a bias voltage VBP for PMOS transistors P2B and P4B. However, this disclosure is not limited thereto. In some embodiments, the bias voltage VBP used to control PMOS transistors P2B and P4B may be the same as the bias voltage used by amplifier 240. That is, the bias voltage VBP used by amplifier 240 can be used to control both PMOS transistors P2B and P4B simultaneously.

[0039] Figure 5 illustrates an amplifier 240 according to an embodiment of the present disclosure. In this embodiment, the amplifier 240 is a folded stacked amplifier, which includes NMOS transistors N1B, N2B and N3B, PMOS transistors P7B, P8B, P9B and P10B, and load cells 242 and 244.

[0040] NMOS transistor N1B has a first terminal, a second terminal, and a control terminal coupled to the first input terminal of amplifier 240, i.e., coupled to node N1 of bandgap reference circuit 200, 300, or 400. NMOS transistor N2B has a first terminal, a second terminal, and a control terminal coupled to the second input terminal of amplifier 240, i.e., coupled to node N2 of bandgap reference circuit 200, 300, or 400. NMOS transistor N3B has a first terminal coupled to the second terminals of NMOS transistor N1B and NMOS transistor N2B, a second terminal coupled to ground, and a control terminal for receiving bias voltage VBN1.

[0041] PMOS transistor P7B has a first terminal coupled to a power supply voltage terminal, a second terminal coupled to a first terminal of NMOS transistor N1B, and a control terminal. PMOS transistor P8B has a first terminal coupled to the second terminal of PMOS transistor P7B, a second terminal coupled to the output terminal AO of amplifier 240, and a control terminal for receiving bias voltage VBP.

[0042] PMOS transistor P9B has a first terminal coupled to a power supply voltage terminal, a second terminal coupled to a first terminal of NMOS transistor N2B, and a control terminal coupled to a control terminal of PMOS transistor P7B. PMOS transistor P10B has a first terminal coupled to a second terminal of PMOS transistor P9B, a second terminal coupled to a control terminal of PMOS transistor P9B, and a control terminal coupled to a control terminal of PMOS transistor P8B.

[0043] Load unit 242 is coupled to the second terminal of PMOS transistor P8B, and load unit 244 is coupled to the second terminal of PMOS transistor P10B. In this embodiment, load unit 242 includes NMOS transistors N4B and N5B, and load unit 244 includes NMOS transistors N6B and N7B.

[0044] NMOS transistor N4B has a first terminal coupled to the second terminal of PMOS transistor P8B, a second terminal, and a control terminal for receiving bias voltage VBN2. NMOS transistor N5B has a first terminal coupled to the second terminal of NMOS transistor N4B, a second terminal coupled to ground, and a control terminal for receiving bias voltage VBN1.

[0045] NMOS transistor N6B has a first terminal coupled to the second terminal of PMOS transistor P10B, a second terminal, and a control terminal for receiving bias voltage VBN2. NMOS transistor N7B has a first terminal coupled to the second terminal of NMOS transistor N6B, a second terminal coupled to ground, and a control terminal for receiving bias voltage VBN1.

[0046] In this embodiment, since the connection methods of PMOS transistors P7B, P8B, P9B, and P10 are the same as those of PMOS transistors P1B, P2B, P3B, and P4B, the bias voltage VBP received by PMOS transistors P8B and P10B can also be provided to the control terminals of PMOS transistors P2B and P4B. That is, the control terminals of PMOS transistors P2B and P4B can be coupled to the control terminal of PMOS transistor P8B. In some embodiments, to further ensure that the bias voltage VBP can be applied to both amplifier 240 and current sources 210 and 220 simultaneously, PMOS transistors P7B, P8B, P9B, and P10B may have the same size factor as PMOS transistors P1B, P2B, P3B, and P4B, such that the current I4 flowing through PMOS transistors P7B and P8B is equal to currents I1 and I2 (i.e., I1 = I2 = I4), and the current I5 flowing through PMOS transistors P9B and P10B is equal to currents I1 and I2 (i.e., I1 = I2 = I5). Specifically, PMOS transistors P1B, P3B, P5B, P7B, and P9B may all have the same size factor. Furthermore, PMOS transistors P2B, P4B, P6B, P8B, and P10B may all have the same size factor.

[0047] Furthermore, in some embodiments, PMOS transistors P1B, P3B, P5B, P7B, and P9B may have different size factors than PMOS transistors P2B, P4B, P6B, P8B, and P10B. For example, the aspect ratio of PMOS transistor P2B may be greater than that of PMOS transistor P1B. However, this disclosure is not limited thereto.

[0048] By making PMOS transistors P7B, P8B, P9B, and P10B have the same size factor and the same interconnection as PMOS transistors P1B, P2B, P3B, and P4B, the bias voltage VBP ensures that PMOS transistors P2B and P4B operate in linear mode when the supply voltage VDD is low (e.g., below the threshold). Therefore, the drain-source voltage of PMOS transistors P2B and P4B can be reduced, and PMOS transistors P2B and P4B can be considered as pass gates, thus providing more voltage margin for PMOS transistors P1B and P3B. In this way, the bandgap reference circuits 200, 300, and 400 can provide a stable reference voltage VBGR regardless of whether a low or high supply voltage is received.

[0049] In summary, the bandgap reference circuit provided by the embodiments of this disclosure employs a stacked structure in the current source to mitigate the voltage applied to the transistors therein when receiving high supply voltages. Furthermore, the bandgap reference circuit further includes an amplifier acting as a source follower to avoid transistor mismatch in the current source. In this way, the bandgap reference circuit of this disclosure can generate a stable and accurate reference voltage over a wide supply voltage range.

[0050] 100, 200, 300, 400: Bandgap reference circuits 110: Amplifier 210, 220, 230: Current source 240, 250: Amplifiers 242, 244: Load Units 260, 360, 460: Temperature coefficient adjustment unit AO: Output end B1A, B2A:BJT B1B, B2B:BJT C1B, C2B: Capacitors I1, I2, I3, I1A, I1B: Current N1, N2, N3, N4, NO1: Nodes N1B, N2B, N3B, N4B, N5B, N6B, N7B: NMOS transistors P1A, P2A, P3A: PMOS transistors P1B, P2B, P3B, P4B, P5B, P6B: PMOS transistors P7B, P8B, P9B, P10B: PMOS transistors R1A, R2A, R3A, R4A: Resistors R1B, R2B, R3B, R4B, R5B: Resistors VA, VB, VC: Voltage VBE: Base-emitter voltage VBGR: Reference Voltage VBN1, VBN2, VBP: Bias voltage VBP: Bias voltage VDD: Power supply voltage

Claims

1. A bandgap reference circuit for generating a reference voltage and outputting the reference voltage via an output node, the bandgap reference circuit comprising: a first current source for generating a first current flowing through a first node, the first current source comprising a first P-channel metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor cascaded between a power supply voltage terminal and the first node; a second current source for generating a second current flowing through a second node, the second current source comprising a third PMOS transistor and a fourth PMOS transistor cascaded between the power supply voltage terminal and the second node; and a third current source for generating a third current flowing through the output node, the third current source comprising a fifth PMOS transistor and a sixth PMOS transistor cascaded between the power supply voltage terminal and the output node. A first amplifier having a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal coupled to a control terminal of the first PMOS transistor and a control terminal of the third PMOS transistor; a second amplifier having a first input terminal coupled to a third node, a second input terminal coupled to a fourth node, and an output terminal coupled to a control terminal of the sixth PMOS transistor, wherein the third node connects the fifth PMOS transistor and the sixth PMOS transistor, and the fourth node connects the first PMOS transistor and the second PMOS transistor; a first resistor coupled to the output node and used to receive the third current, the first resistor having a first terminal coupled to the output node and a second terminal coupled to a ground terminal; and a temperature coefficient adjustment unit comprising a first bipolar junction transistor (BJT) for receiving the first current and a second BJT for receiving the second current; The control terminals of the second PMOS transistor and the fourth PMOS transistor are used to receive a first bias voltage; the control terminal of the fifth PMOS transistor is coupled to the control terminal of the first PMOS transistor and the control terminal of the third PMOS transistor; the first bias voltage is set according to the potential of a power supply voltage received from the power supply voltage terminal, so that when the power supply voltage is lower than a threshold, the second PMOS transistor operates in a linear mode, and when the power supply voltage is higher than the threshold, the second PMOS transistor operates in a saturation mode.

2. The bandgap reference circuit as claimed in claim 1, wherein the first bias voltage is equal to a power supply voltage received from the power supply voltage terminal minus twice a threshold voltage of the first PMOS transistor.

3. The bandgap reference circuit as claimed in claim 1, wherein the first amplifier comprises: a first NMOS transistor having a first terminal, a second terminal, and a control terminal coupled to the first input terminal of the first amplifier; a second NMOS transistor having a first terminal, a second terminal, and a control terminal coupled to the second input terminal of the first amplifier; a third NMOS transistor having a first terminal coupled to the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor, a second terminal coupled to a ground terminal, and a control terminal for receiving a second bias voltage; a seventh PMOS transistor having a first terminal coupled to the power supply voltage terminal, a second terminal coupled to the first terminal of the first NMOS transistor, and a control terminal; and an eighth PMOS transistor having a first terminal coupled to the second terminal of the seventh PMOS transistor, a second terminal coupled to the output terminal of the first amplifier, and a control terminal for receiving the first bias voltage. A ninth PMOS transistor having a first terminal coupled to the power supply voltage terminal, a second terminal coupled to the first terminal of the second NMOS transistor, and a control terminal coupled to the control terminal of the seventh PMOS transistor; a tenth PMOS transistor having a first terminal coupled to the second terminal of the ninth PMOS transistor, a second terminal coupled to the control terminal of the ninth PMOS transistor, and a control terminal coupled to the control terminal of the eighth PMOS transistor; a first load unit having a first terminal coupled to the second terminal of the eighth PMOS transistor and a second terminal coupled to the ground terminal; and a second load unit having a first terminal coupled to the second terminal of the tenth PMOS transistor and a second terminal coupled to the ground terminal.

4. The bandgap reference circuit as claimed in claim 3, wherein a control terminal of the second PMOS transistor and a control terminal of the fourth PMOS transistor are coupled to the control terminal of the eighth PMOS transistor.

5. The bandgap reference circuit as claimed in claim 3, wherein the first PMOS transistor, the third PMOS transistor, the fifth PMOS transistor, the seventh PMOS transistor, and the ninth PMOS transistor have the same size factor, and the second PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, the eighth PMOS transistor, and the tenth PMOS transistor have the same size factor.

6. The bandgap reference circuit as claimed in claim 1, wherein a first end of the first PMOS transistor is coupled to the power supply voltage terminal, a second end of the first PMOS transistor is coupled to the fourth node, a first end of the second PMOS transistor is coupled to the fourth node, and a second end of the second PMOS transistor is coupled to the first node.

7. The bandgap reference circuit as claimed in claim 1, wherein a first terminal of the fifth PMOS transistor is coupled to the power supply voltage terminal, a second terminal of the fifth PMOS transistor is coupled to the third node, a first terminal of the sixth PMOS transistor is coupled to the third node, and a second terminal of the sixth PMOS transistor is coupled to the output node.

8. The bandgap reference circuit as claimed in claim 1, wherein the first input terminal of the first amplifier is a negative input terminal and the second input terminal of the first amplifier is a positive input terminal.

9. The bandgap reference circuit as claimed in claim 1, wherein the first input terminal of the second amplifier is a negative input terminal, and the second input terminal of the second amplifier is a positive input terminal.

10. The bandgap reference circuit as claimed in claim 1 further includes a first capacitor having a first terminal coupled to the power supply voltage terminal and a second terminal coupled to the output terminal of the first amplifier.

11. The bandgap reference circuit as claimed in claim 1 further includes a second capacitor having a first end coupled to the output node and a second end coupled to a ground terminal.

12. The bandgap reference circuit as claimed in claim 1, wherein the first BJT has an emitter for receiving at least a portion of the first current, a collector coupled to a ground terminal, and a base coupled to the ground terminal.

13. The bandgap reference circuit as claimed in claim 12, wherein the temperature coefficient adjustment unit further includes a second resistor having a first end coupled to the first node and a second end coupled to the ground terminal.

14. The bandgap reference circuit as claimed in claim 1, wherein the second BJT has an emitter for receiving at least a portion of the second current, a collector coupled to a ground terminal, and a base coupled to the ground terminal.

15. The bandgap reference circuit as claimed in claim 14, wherein the temperature coefficient adjustment unit further includes a third resistor having a first end coupled to the second node and a second end coupled to the emitter of the second BJT.

16. The bandgap reference circuit as claimed in claim 14, wherein the temperature coefficient adjustment unit further includes a fourth resistor having a first end coupled to the second node and a second end coupled to the ground terminal.

17. The bandgap reference circuit as claimed in claim 1, wherein the aspect ratio of the second PMOS transistor is greater than the aspect ratio of the first PMOS transistor.

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