Forming method of semiconductor structure

Abstract

This disclosure provides a method for forming a semiconductor structure. The method includes the following operations: forming a first hard mask stack on a dielectric layer, wherein the dielectric layer includes an array region; etching the first hard mask stack to form a second hard mask stack and a first trench, the first trench extending along a first direction above the array region and within the second hard mask stack; forming a second trench in the second hard mask stack, the second trench extending along a second direction different from the first direction, wherein the first trench and the second trench intersect each other to form an intersection; etching the second hard mask stack and dielectric layer directly below the intersection to form a via; and forming a first landing pad in the via.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor structure. Prior Technology

[0002] In pursuit of lower costs, higher efficiency, and higher component density, the size of semiconductor structures and components is generally becoming smaller. However, the miniaturization of semiconductor structures and components increases the difficulty and complexity of semiconductor structure fabrication processes. Therefore, forming reliable and intact semiconductor structures at smaller dimensions remains a challenge. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor structure. The method includes the following operations: forming a first hard mask stack on a dielectric layer, wherein the first hard mask stack includes alternating stacked carbon layers and a plurality of antireflective coatings, and the dielectric layer includes an array region. Etching the first hard mask stack to form a second hard mask stack and a first trench, the first trench extending along a first direction above the array region and within the second hard mask stack, wherein the bottom surface of the first trench is within one layer of the antireflective coatings. Forming photoresist on the second hard mask stack and within the first trench. Etching the photoresist and the second hard mask stack to form a second trench, the second trench extending along a second direction different from the first direction, wherein the first trench and the second trench intersect each other to form an intersection. Removing the photoresist. Etching the second hard mask stack directly below the intersection to form a hole to expose the dielectric layer. Etching the dielectric layer exposed from the hole to form a first via. Forming a first landing pad in the first via.

[0004] In some implementations, the k-value of the dielectric layer is less than or equal to 4.

[0005] In some embodiments, forming a first hard mask stack on a dielectric layer includes sequentially depositing a first carbon layer, a first anti-reflective coating, a second carbon layer, and a second anti-reflective coating on the dielectric layer.

[0006] In some embodiments, the bottom surface of the first trench is in the first anti-reflective coating.

[0007] In some embodiments, forming photoresist on the second hard mask stack and in the first trench includes sequentially depositing a photoresist underlayer, an anti-reflection structure, and a photoresist layer on the second hard mask stack and in the first trench.

[0008] In some implementations, the angle between the first direction and the second direction is between 60 degrees and 120 degrees.

[0009] In some embodiments, forming a first landing pad in a first via includes the following operations: depositing a metal layer in the first via and on a dielectric layer; planarizing the metal layer to form the first landing pad in the first via.

[0010] In some embodiments, this method further includes the following operation: After forming the first landing pad in the first through-hole, a capacitor structure is formed on the first landing pad.

[0011] In some embodiments, after etching the dielectric layer exposed from the hole to form the first via, the method further includes the following operations: etching a peripheral region of the dielectric layer to form a second via; and forming a second landing pad in the second via.

[0012] In some implementations, the formation of the first landing pad in the first through-hole and the formation of the second landing pad in the second through-hole are performed simultaneously.

[0013] This disclosure provides a method for forming a semiconductor structure. The method includes the following operations: Sequentially depositing a first hard mask layer, a second hard mask layer, a third hard mask layer, and a fourth hard mask layer on a dielectric layer, wherein the first and third hard mask layers have high etch selectivity relative to the second and fourth hard mask layers, and the dielectric layer includes an array region. Etching the second, third, and fourth hard mask layers to form a first trench extending over the array region along a first direction and removing the third and fourth hard mask layers. Forming a second trench in the second hard mask layer, extending along a second direction different from the first direction, wherein the first and second trenches intersect to form an intersection and expose the first hard mask layer. Forming a first via penetrating the first hard mask layer and the dielectric layer below the intersection. Removing the first and second hard mask layers. Forming a first landing pad in the first via.

[0014] In some embodiments, the first and third hard mask layers are carbon layers, and the second and fourth hard mask layers are anti-reflective coatings.

[0015] In some embodiments, this method further includes the following operation: After forming the first landing pad in the first through-hole, a capacitor structure is formed on the first landing pad.

[0016] In some embodiments, before etching the second, third, and fourth hard mask layers to form a first trench extending along a first direction above the array region and removing the third and fourth hard mask layers, the method further includes the following operations: forming a patterned photoresist layer with a first opening on the fourth hard mask layer and exposing the fourth hard mask layer; conformally forming a spacer layer to cover the patterned photoresist layer and the first opening; and etching a horizontal portion of the spacer layer to expose the patterned photoresist layer and the fourth hard mask layer.

[0017] In some embodiments, after removing the first hard mask layer and the second hard mask layer, the method further includes the following operations: etching the peripheral region of the dielectric layer to form a second via; forming a second landing pad in the second via.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are intended to provide further explanation of the claimed content of this disclosure. Simple Explanation of the Diagram

[0019] This disclosure can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings. Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments. Figures 2A and 2B are flowcharts of methods for forming semiconductor structures according to some embodiments. Figures 3A to 3C are cross-sectional views illustrating intermediate stages of forming a semiconductor structure according to various embodiments of this disclosure. Figure 3D is a top view of the semiconductor structure in Figure 3C. Figures 3E to 3I are cross-sectional views illustrating intermediate stages of forming a semiconductor structure according to various embodiments of this disclosure. Figure 3J is a top view of the semiconductor structure in Figure 3I. Figures 3K through 3M are cross-sectional views illustrating intermediate stages in the formation of a semiconductor structure according to various embodiments of this disclosure. Figure 3N is a top view of the semiconductor structure in Figure 3M. Figures 30 through 6 are cross-sectional views illustrating intermediate stages of forming a semiconductor structure according to various embodiments of this disclosure. Implementation

[0020] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0021] It should be understood that while the terms "first," "second," "third," etc., may be used in this document to describe different elements, parts, regions, and / or layers, such elements, parts, regions, and / or layers should not be limited by these terms. These terms are used only to distinguish an element, part, region, or layer from another element, part, region, or layer. Therefore, without departing from the teachings of this document, "first element," "element," "region," or "layer" discussed below may be referred to as a second element, element, region, or layer.

[0022] Additionally, spatial relative terms, such as "above," "up," and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0023] This disclosure relates to structures composed of different layers. When the term "on" is used to refer to two different layers (including a substrate), it simply means that one layer is on top of another or one layer is on top of another. These terms do not require that the two layers be in direct contact and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate.

[0024] This disclosure provides a method for forming a semiconductor structure. In this method, a hard mask stack having alternatingly stacked carbon layers and alternatingly stacked anti-reflective coatings is formed on a dielectric layer to serve as a mask for subsequent etching processes of the dielectric layer. The hard mask stack having alternatingly stacked carbon layers and anti-reflective coatings achieves a good pattern transfer effect, enabling the formation of precise patterns in the dielectric layer.

[0025] Figure 1 is a cross-sectional view of a semiconductor structure 100 according to some embodiments. Referring to Figure 1, the semiconductor structure 100 includes a dielectric layer 110, a first landing pad 120, a second landing pad 130, a capacitor structure 140, a dielectric layer 150, and a conductive line 152. In some embodiments, the dielectric layer 110 is a low-k dielectric layer having a k value less than or equal to 4, such as 1.5, 2, 2.5, 3, 3.5, or 4. In some embodiments, the dielectric layer 110 comprises silicon hydroxide (SiCOH), SiLK (Dow Chemical, Midland, Michigan), flowable oxide, methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), fluorosilicate glass (FSG), organosilicate glass (OSG), or combinations thereof, but this disclosure is not limited thereto. A dielectric layer 110 having a k value of less than or equal to 4 can reduce parasitic capacitance between the first landing pads 120, thereby improving the reliability and integrity of the semiconductor structure 100. In some embodiments, the thickness T1 of the dielectric layer 110 is between 40 nm and 100 nm, for example, 40, 50, 60, 70, 80, 90, or 100 nm.

[0026] As shown in Figure 1, the first landing pad 120 is embedded in the array region AR of the dielectric layer 110. In some embodiments, the first landing pad 120 comprises a metal, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), ruthenium (Ru), molybdenum (Mo), or copper (Cu), but this disclosure is not limited thereto. In some embodiments, the thickness T2 of the first landing pad 120 is between 40 nm and 100 nm, for example, 40, 50, 60, 70, 80, 90, or 100 nm. In some embodiments, the spacing S1 between the first landing pads 120 is 10 nm to 20 nm, for example, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 nm. The spacing S1 between the first landing pads 120 is 10nm~20nm. This results in a small parasitic capacitance between the first landing pads 120 despite the reduction in the size of the semiconductor structure, thereby improving the reliability and integrity of the semiconductor structure. In some embodiments, the top surface of the first landing pads 120 is substantially coplanar with the top surface of the dielectric layer 110. The semiconductor structure 100 can implement any number of first landing pads 120, such as 1, 2, 3, 4, 5, etc.

[0027] As shown in Figure 1, the second landing pad 130 is embedded in the peripheral region PR of the dielectric layer 110. In some embodiments, the second landing pad 130 comprises a metal, such as Al, W, Ti, Ta, Au, Ru, Mo, or Cu, but this disclosure is not limited thereto. In some embodiments, the thickness T3 of the second landing pad 130 is between 40 nm and 100 nm, for example, 40, 50, 60, 70, 80, 90, or 100 nm. In some embodiments, the top surface of the second landing pad 130 is substantially coplanar with the top surface of the dielectric layer 110. Any number of second landing pads 130 can be implemented in the semiconductor structure, for example, 1, 2, 3, 4, 5, etc.

[0028] As shown in Figure 1, capacitor structures 140 are formed in the array region AR of dielectric layer 110 and on the first landing pad 120. As shown in Figure 1, capacitor structures 140 extend vertically above the first landing pad 120. In some embodiments, the bottom of each capacitor structure 140 contacts the top of each first landing pad 120. In some embodiments, capacitor structures 140 are cylindrical. In some embodiments, each capacitor structure 140 includes an outer dielectric layer 140o, a first electrode layer 140f, a capacitor dielectric layer 140d, and a second electrode layer 140s. In some embodiments, the first electrode layer 140f contacts the first landing pad 120. In some embodiments, the outer dielectric layer 140o is formed on the outer sidewall of the first electrode layer 140f, and the capacitor dielectric layer 140d is conformally formed on the inner sidewall and bottom of the first electrode layer 140f. In some embodiments, the second electrode layer 140s is formed in the capacitor dielectric layer 140d. In some embodiments, the first electrode layer 140f and the second electrode layer 140s independently comprise TiN, TaN, Ti, Ta, W, Au, Ag, Mo, Al, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the outer dielectric layer 140o and the capacitor dielectric layer 140d independently comprise zirconium oxide (ZrO2), titanium oxide (TiO2), hafnium oxide (HfO2), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof, but this disclosure is not limited thereto. It is worth noting that the number of capacitor structures 140 depends on the number of first landing pads 120.

[0029] As shown in Figure 1, dielectric layer 150 is disposed on the peripheral region PR of dielectric layer 110. In some embodiments, dielectric layer 150 includes SiO2, Si3N4, SiON, other oxides, other nitrides, or combinations thereof, but this disclosure is not limited thereto. As shown in Figure 1, wire 152 is embedded in dielectric layer 150. In some embodiments, wire 152 contacts second landing pad 130. In some embodiments, wire 152 includes metals such as Ti, Ru, Al, W, Cu, Au, Ag, Mo, but this disclosure is not limited thereto. In some embodiments, the top surface of wire 152 is substantially coplanar with the top surface of dielectric layer 150. Semiconductor structure 100 may implement any number of wires 152, such as 1, 2, 3, 4, 5, etc.

[0030] Figures 2A and 2B are flowcharts of a method 200 for forming a semiconductor structure 100 according to some embodiments. Method 200 includes operations 203, 206, 209, 212, 215, 218, 221, 224, 227a, and 227b. Figures 3A-3C, 3E-3I, 3K-3M, and 3O-6 are cross-sectional views illustrating intermediate stages of forming the semiconductor structure 100 according to various embodiments of this disclosure. Although the method 200 disclosed herein is described using a series of operations or steps, the order of these operations or steps should not be construed as a limitation of this disclosure. For example, some operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, it is not necessary to perform all illustrated operations, steps, and / or features to achieve the embodiments of this disclosure. Additionally, each operation or step described herein may comprise several sub-steps or actions.

[0031] Referring to Figures 2A and 3A, method 200 begins at operation 203 by receiving a dielectric layer 302. The dielectric layer 302 includes an array region AR and a peripheral region PR. In some embodiments, the k-value of the dielectric layer 302 is less than or equal to 4, for example, 1.5, 2, 2.5, 3, 3.5, or 4. A k-value less than or equal to 4 for the dielectric layer 302 can reduce parasitic capacitance between subsequently formed first landing pads. In some embodiments, the thickness T4 of the dielectric layer 302 is between 40 nm and 100 nm, for example, 40, 50, 60, 70, 80, 90, or 100 nm. Referring to Figures 2A and 3B, in operation 206, a first hard mask stack 310 is formed on the dielectric layer 302, wherein the first hard mask stack 310 includes alternating stacks of a plurality of carbon layers and a plurality of anti-reflective coatings. In some embodiments, the first hard mask stack 310 includes a first hard mask layer 312, a second hard mask layer 314, a third hard mask layer 316, and a fourth hard mask layer 318. The first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are sequentially deposited on the dielectric layer 302, wherein the first hard mask layer 312 and the third hard mask layer 316 have high etch selectivity relative to the second hard mask layer 314 and the fourth hard mask layer 318. That is, the third hard mask layer 316 and the first hard mask layer 312 have a faster etch rate relative to the fourth hard mask layer 318 and the second hard mask layer 314. In some embodiments, the first hard mask layer 312 has high etch selectivity relative to the dielectric layer 302. That is, the first hard mask layer 312 has a faster etch rate relative to the dielectric layer 302. In some embodiments, the thickness T5 of the first hard mask layer 312 and the thickness T6 of the third hard mask layer 316 are each between 60 nm and 120 nm, for example, 60, 70, 80, 90, 100, 110, or 120 nm. In some embodiments, the thickness T7 of the second hard mask layer 314 and the thickness T8 of the fourth hard mask layer 318 are each between 20 nm and 60 nm, for example, 20, 25, 30, 35, 40, 45, 50, 55, or 60 nm. In some embodiments, the first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure CVD (LPCVD), another deposition process, or any suitable combination thereof.In some embodiments, the first hard mask layer 312 and the third hard mask layer 316 comprise the same material, such as a carbon layer (the first hard mask layer 312 and the third hard mask layer 316 may also be referred to as the first carbon layer and the second carbon layer, respectively), and the second hard mask layer 314 and the fourth hard mask layer 318 comprise the same material, such as an anti-reflective coating (the second hard mask layer 314 and the fourth hard mask layer 318 may also be referred to as the first anti-reflective coating and the second anti-reflective coating, respectively). In some embodiments, the anti-reflective coating is a dielectric anti-reflection coating (DARC) layer. In some embodiments, the anti-reflective coating comprises SiO2, SiON, Si3N4, combinations thereof, or any suitable material. The second hard mask layer 314 and the fourth hard mask layer 318, including the anti-reflective coating, can advantageously absorb light during subsequent exposures, thereby reducing or minimizing light reaching the layers below the second hard mask layer 314 and the fourth hard mask layer 318, and thus reducing light reflection from the layers below the second hard mask layer 314 and the fourth hard mask layer 318. For the advantages of the dielectric layer 302, please refer to the aforementioned advantages of the dielectric layer 110.

[0032] Figure 3C is a cross-sectional view of the semiconductor structure 300a along section line A-A' in Figure 3D. Figure 3D is a top view of the semiconductor structure 300a in Figure 3C. Referring to Figures 2A, 3C, 3D, and 3G, in operation 209, a first hard mask stack 310 is etched to form a second hard mask stack 330 and a first trench 328, the first trench 328 extending along a first direction D1 above the array region AR of the dielectric layer 302 and within the second hard mask stack 330, wherein the bottom surface of the first trench 328 is in one of the anti-reflective coatings. In some embodiments, the second hard mask stack 330 includes a first hard mask layer 312 and a second hard mask layer 332. Specifically, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are etched to form the second hard mask layer 332 and a first trench 328 extending along a first direction D1, and the third hard mask layer 316 and the fourth hard mask layer 318 are removed. The first trench 328 is located above the array region AR of the dielectric layer 302. In some embodiments, the bottom surface of the first trench 328 is within the second hard mask layer 332 or the first anti-reflective coating. In some embodiments, the bottom surface of the first trench 328 is at half the height of the second hard mask layer 332. In some embodiments, the depth d1 of the first trench 328 is between 10 nm and 30 nm, for example, 10, 15, 20, 25, or 30 nm. In some embodiments, the first hard mask stack 310 is etched using a dry etching process. The etching process details for Operation 209 will be described further later.

[0033] Referring to Figures 2A and 3C-3G, in some embodiments, before etching the first hard mask stack 310 to form the second hard mask stack 330 and extending along the first direction D1 above the array region AR of the dielectric layer 302 and into the second hard mask stack 330, method 200 further includes the following operations. As shown in Figure 3C, a patterned photoresist layer 320 having a first opening 322 is formed on the first hard mask stack 310 to expose the first hard mask stack 310. In some embodiments, the number of first openings 322 may be, for example, one, three, four, five, etc. As shown in Figure 3C, in some embodiments, a patterned photoresist layer 320 having a first opening 322 is formed on a fourth hard mask layer 318 to expose the fourth hard mask layer 318. In some embodiments, the patterned photoresist layer 320 is formed by deposition and patterning of photoresist (not shown). In other words, photoresist can be deposited, and then selectively exposed to visible light, ultraviolet light, etc., via a mask (not shown), followed by development of the exposed photoresist to obtain a patterned photoresist layer 320. In some embodiments, the photoresist is deposited by, for example, but not limited to, CVD, PVD, ALD, sputtering, LPCVD, other deposition processes, or any suitable combination thereof. As shown in Figures 3C and 3D, in some embodiments, the first opening 322 extends along a first direction D1 above the array region AR of the dielectric layer 302.

[0034] As shown in Figures 3C and 3E, after forming a patterned photoresist layer 320 with a first opening 322 on and exposing the first hard mask stack 310, a spacer layer 324 is conformally formed to cover the patterned photoresist layer 320 and conformally formed in the first opening 322. In some embodiments, the spacer layer 324 is formed by a deposition process, such as CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the spacer layer 324 comprises a silicon (Si) and oxygen (O) containing material, such as SiO2.

[0035] As shown in Figures 3E and 3F, after conformally forming a spacer layer 324 to cover the patterned photoresist layer 320 and conformally forming it in the first opening 322, a horizontal portion of the spacer layer 324 is etched to expose the patterned photoresist layer 320 and the first hard mask stack 310 to form a spacer 326. As shown in Figure 3F, in some embodiments, the horizontal portion of the spacer layer 324 is etched to expose a fourth hard mask layer 318. In some embodiments, the horizontal portion of the spacer layer 324 is etched by a dry etching process. In some embodiments, the spacer 326 includes a vertical portion of the spacer layer 324 and is located on the sidewall of the first opening 322 of the patterned photoresist layer 320. In some embodiments, the spacer 326 and the patterned photoresist layer 320 act as an etching mask for subsequent etching of the first hard mask stack 310. The spacer 326 is formed on the sidewall of the first opening 322 of the patterned photoresist layer 320, which can reduce the line width roughness of the subsequently formed pattern, thereby further enhancing the integrity and reliability of the semiconductor structure.

[0036] As shown in Figures 3F and 3G, operation 209 is performed after etching the horizontal portion of spacer layer 324 to expose patterned photoresist layer 320 and first hard mask stack 310 to form spacer 326. In some embodiments, the etching process details of operation 209 include the following steps: Etching the exposed portion of fourth hard mask layer 318 to form a second opening (not shown) to expose third hard mask layer 316. Etching the third hard mask layer 316 exposed from the second opening, and removing patterned photoresist layer 320 to form third opening (not shown) and expose second hard mask layer 314. Etching the second hard mask layer 314 exposed from the third opening, and removing fourth hard mask layer 318 and spacer 326 to form fourth opening (not shown). As shown in Figure 3G, removing third hard mask layer 316 to form first trench 328. In some embodiments, the fourth hard mask layer 318, the third hard mask layer 316, the patterned photoresist layer 320, the second hard mask layer 314, and the spacer 326 are etched and / or removed by an anisotropic etching process (e.g., dry etching). The third hard mask layer 316 has high etching selectivity relative to the fourth hard mask layer 318, which avoids damage to the pattern of the fourth hard mask layer 318 when the third hard mask layer 316 is etched. This results in better pattern migration and more precise patterns, thereby improving the reliability and integrity of the semiconductor structure.

[0037] As shown in Figures 2A and 3G-3H, in operation 212, photoresist 340 is formed on the second hard mask stack 330 and in the first trench 328. In some embodiments, photoresist 340 is formed on the second hard mask layer 332 and in the first trench 328. In some embodiments, photoresist 340 is a three-layer photoresist. In some embodiments, photoresist 340 includes a photoresist underlayer 342, an anti-reflection structure 344, and a photoresist layer 346. In some embodiments, forming photoresist 340 on the second hard mask stack 330 and in the first trench 328 includes sequentially depositing a photoresist underlayer 342, an anti-reflection structure 344, and a photoresist layer 346 on the second hard mask stack 330 and in the first trench 328. In some embodiments, the materials of the photoresist underlayer 342 and the photoresist layer 346 are similar to those of the first hard mask layer 312 and the third hard mask layer 316. In some embodiments, the anti-reflective structure 344 is a DARC layer. In some embodiments, the photoresist underlayer 342, the anti-reflective structure 344, and the photoresist layer 346 are deposited by, for example, CVD, PVD, ALD, sputtering, LPCVD, other deposition processes, or any suitable combination thereof.

[0038] Figure 3I is a cross-sectional view of semiconductor structure 300b along section line B-B' in Figure 3J. Figure 3J is a top view of semiconductor structure 300b in Figure 3I. Figure 3M is a cross-sectional view of semiconductor structure 300c along section line C-C' in Figure 3N. Figure 3N is a top view of semiconductor structure 300c in Figure 3M. As shown in Figures 2A, 3H, 3M, and 3N, in operation 215, photoresist 340 and a second hard mask stack 330 are etched to form a second hard mask stack 362 and a second trench 358, the second trench 358 extending along a second direction D2 different from the first direction D1, wherein the first trench 328 and the second trench 358 intersect each other to form an intersection 360. In some embodiments, the second hard mask stack 362 includes a first hard mask layer 312 and a second hard mask layer 356. In some embodiments, photoresist 340 and a second hard mask layer 332 are etched to form a second hard mask layer 356 and a second trench 358. The second trench 358 extends along a second direction D2 different from the first direction D1, wherein the first trench 328 and the second trench 358 intersect each other to form an intersection 360. As shown in Figure 3N, in some embodiments, the angle A1 between the first direction D1 and the second direction D2 is between 60 degrees and 120 degrees, for example, 60, 70, 80, 90, 100, 110, or 120 degrees. In some embodiments, the depth of the second trench 358 is the same as the depth d1 of the first trench 328, i.e., 10 nm to 30 nm, for example, 10, 15, 20, 25, or 30 nm. In some embodiments, the first hard mask layer 312 is exposed from the intersection 360. In some embodiments, the photoresist 340, the second hard mask stack 330 and the second hard mask layer 332 are etched by an anisotropic etching process (e.g., dry etching process).

[0039] As shown in Figures 2A and 3H-3N, prior to operation 215, method 200 further includes the following steps. As shown in Figures 3H-3J, photoresist layer 346 is patterned to form patterned photoresist layer 348 and a first opening 350, the first opening 350 extending along a second direction D2. As shown in Figures 3I and 3K, spacer layer 352 is conformally formed to cover patterned photoresist layer 348 and conformally formed in the first opening 350. As shown in Figures 3K-3L, horizontal portions of spacer layer 352 are etched to expose patterned photoresist layer 348 and anti-reflective structure 344 to form spacer 354. For the patterned photoresist layer 348, first opening 350, spacer layer 352, and spacer 354, please refer to the aforementioned embodiments of patterned photoresist layer 320, first opening 322, spacer layer 324, and spacer 326. The etching process details of operation 215 are similar to those of operation 209. For the implementation details and advantages of the etching process details of operation 215, please refer to the aforementioned implementation details and advantages of the etching process details of operation 209. As shown in Figures 3H and 3M, after operation 215, the photoresist 340 is removed.

[0040] As shown in Figures 2A, 3M, and 3O, in operation 218, the second hard mask stack 362 directly below the intersection 360 is etched to form a hole 364 to expose the dielectric layer 302. As shown in Figures 3M and 3O, in some embodiments, the first hard mask layer 312 below the intersection 360 is etched to form a first hard mask layer 366 and a hole 364 to expose the dielectric layer 302. In some embodiments, the second hard mask stack 362 and the first hard mask layer 312 directly below the intersection 360 are etched using an anisotropic etching process (e.g., a dry etching process). The first hard mask layer 312 has high etch selectivity relative to the second hard mask layer 356, which prevents damage to the pattern of the second hard mask layer 356 when the first hard mask layer 312 is etched. This results in better pattern migration and more precise patterns, thereby improving the reliability and integrity of the semiconductor structure. As shown in Figures 2A, 3O, and 3P, in operation 221, the dielectric layer 302 exposed from the via 364 is etched to form a first via 368 and a dielectric layer 370. In some embodiments, a second hard mask layer 356 is removed during the etching of the dielectric layer 302 to form the first via 368. In some embodiments, the dielectric layer 302 is etched by an anisotropic etching process (e.g., a dry etching process). As shown in Figures 2A, 3P, and 3Q, after operation 221, the first hard mask layer 366 is removed to form the first via 372. In some embodiments, the first hard mask layer 366 is removed by a dry etching process, wherein the gas used in the dry etching process is O2. The first hard mask layer 366 has high etch selectivity relative to the dielectric layer 370, which allows for easy removal of the first hard mask layer 366 without damaging the dielectric layer 370, thereby enhancing the reliability and integrity of the semiconductor structure.

[0041] In some embodiments, after etching the dielectric layer 302 exposed from the hole 364 to form the first via 368 (operation 221) and removing the first hard mask layer 366 to form the first via 372, method 200 further includes operations 224 and 227a. As shown in Figures 4A-4F, in operation 224, the peripheral region PR of the dielectric layer 370 is etched to form the second via 468. As shown in Figures 5A-5B, in operation 227a, a second landing pad 130 is formed in the second via 468. Operations 224 and 227a will be further described below.

[0042] Referring to Figures 2A and 4A-4F, in operation 224, the peripheral region PR of the dielectric layer 370 is etched to form a second via 468. In some embodiments, the peripheral region PR of the dielectric layer 370 is etched by a dry etching process. In some embodiments, operation 224 includes operations 224a-224f. As shown in Figures 2B, 3Q and 4A, in operation 224a, a first hard mask stack 410 is formed in the first via 372 and on the dielectric layer 370, and a photoresist (not shown) is formed on the first hard mask stack 410. The photoresist is then patterned to form a photoresist 420 and a first opening 426 extending along a third direction (not shown). In some embodiments, the first hard mask stack 410 includes a first hard mask layer 412, a second hard mask layer 414, a third hard mask layer 416 and a fourth hard mask layer 418. For embodiments of the first hard mask layer 412, the second hard mask layer 414, the third hard mask layer 416, and the fourth hard mask layer 418, please refer to the aforementioned embodiments of the first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318. In some embodiments, the first hard mask layer 412 is deposited in the first via 372. In some embodiments, the fourth hard mask layer 418 comprises an oxide-rich DARC having an oxide content of 15 atomic% to 30 atomic% such that the oxide content is, for example, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 atoms. A fourth hard mask layer 418, comprising an oxide-rich DARC layer with an oxide content of 15 to 30 atomic percent, can advantageously absorb light during subsequent exposures, thereby reducing or minimizing light reaching the layers below the fourth hard mask layer 418, and thus reducing light reflection from the layers below the fourth hard mask layer 418. Other advantages of the fourth hard mask layer 418 will be described below. In some embodiments, the photoresist 420 is a double-layer photoresist. In some embodiments, the photoresist 420 comprises an anti-reflection structure 422 and a photoresist layer 424. In some embodiments, the anti-reflection structure 422 is a bottom anti-reflection coating (BAC) layer. The anti-reflection structure 422, including the BARC layer, can advantageously absorb light during subsequent exposures, thereby reducing or minimizing light reaching the layers below the anti-reflection structure 422, and thus reducing light reflection from the layers below the anti-reflection structure 422. In some embodiments, the photoresist layer (not shown) is patterned to form a first opening 426 to expose the anti-reflection structure 422.

[0043] As shown in Figures 2B, 4A, and 4B, in operation 224b, a first hard mask stack 410 and photoresist 420 exposed from the first opening 426 are etched to form a second hard mask stack 430 and a first trench 432 extending along a third direction (not shown). In some embodiments, the first trench 432 is in the second hard mask layer 428. In some embodiments, an anti-reflective structure 422 exposed from the first opening 426 is etched to expose a fourth hard mask layer 418. For details of the etching process of the first hard mask stack 410, please refer to the embodiment of the etching process details of operation 209. In some embodiments, the second hard mask layer 414 and the fourth hard mask layer 418 are etched by a wet etching process. Because the fourth hard mask layer 418 includes oxide-rich DARC with an oxide content of 15 to 30 atoms, the etch selectivity between the fourth hard mask layer 418 and the third hard mask layer 416 is improved compared to the fourth hard mask layer 318 and the third hard mask layer 316. This results in better pattern migration and more accurate patterns during the etching process of the fourth hard mask layer 418 and the third hard mask layer 416, thereby enhancing the reliability and integrity of the semiconductor structure.

[0044] As shown in Figures 2B, 4B, and 4C, in operation 224c, a third hard mask stack 440 is formed in the first trench 432 on top of the second hard mask stack 430, and a photoresist (not shown) is formed on the third hard mask stack 440. The photoresist is then patterned to form a photoresist 450 and a second opening 456, the second opening 456 extending along a fourth direction (not shown) different from the third direction. In some embodiments, the number of second openings 456 may be more than one, such as two, three, four, five, etc. In some embodiments, the third hard mask stack 440 includes a first hard mask layer 442, a second hard mask layer 444, a third hard mask layer 446, and a fourth hard mask layer 448. In some embodiments, the photoresist 450 includes an anti-reflective structure 452 and a photoresist layer 454. For embodiments of the first hard mask layer 442, the second hard mask layer 444, the third hard mask layer 446, the fourth hard mask layer 448, the photoresist 450, the anti-reflection structure 452, and the photoresist layer 454, please refer to the foregoing embodiments of the first hard mask layer 412, the second hard mask layer 414, the third hard mask layer 416, the fourth hard mask layer 418, the photoresist 420, the anti-reflection structure 422, and the photoresist layer 424. In some embodiments, the second hard mask layer 444 includes a silicon-rich DARC layer having a silicon content of 60 atomic% to 80 atomic% (e.g., 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, or 80 atoms). In some embodiments, the fourth hard mask layer 448 includes an oxide-rich DARC layer having an oxide content of 15 to 30 atomic percent, such as 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 atomic percent. For the advantages of the second hard mask layer 444 and the fourth hard mask layer 448, please refer to the advantages of the aforementioned fourth hard mask layer 418.

[0045] As shown in Figures 2B, 4C, and 4D, in operation 224d, the third hard mask stack 440 and photoresist 450 exposed from the second opening 456 are etched to form a second trench 462. The second trench 462 extends in a fourth direction (not shown) different from the third direction, and is located within the second hard mask stack 460. In some embodiments, the second hard mask stack 460 includes a first hard mask layer 412 and a second hard mask layer 458. In some embodiments, the second trench 462 is located within the second hard mask layer 458. For an embodiment of the etching process in operation 224d, please refer to an embodiment of the etching process in operation 224b. Because the second hard mask layer 444 comprises a silicon-rich DARC layer with a silicon content of 60 to 80 atomic percent, the etch selectivity between the second hard mask layer 444 and the first hard mask layer 442 is improved compared to the second hard mask layer 314 and the first hard mask layer 312. This results in better pattern migration and more precise patterns during the etching process of the second hard mask layer 444 and the first hard mask layer 442, thereby improving the reliability and integrity of the semiconductor structure. Similarly, because the fourth hard mask layer 448 comprises an oxide-rich DARC layer with an oxide content of 15 to 30 atomic percent, the etch selectivity between the fourth hard mask layer 448 and the third hard mask layer 446 is improved compared to the fourth hard mask layer 318 and the third hard mask layer 316. This results in better pattern migration and more precise patterns during the etching process of the fourth hard mask layer 448 and the third hard mask layer 446, thereby improving the reliability and integrity of the semiconductor structure.

[0046] As shown in Figures 2B, 4D, and 4E, in operation 224e, a second hard mask stack 460 and dielectric layer 370 are etched directly beneath the first trench 432 and the second trench 462 to form a first hard mask layer 464, dielectric layer 110, and via 466, and a portion of the second hard mask stack 460 is removed. In some embodiments, a portion of the second hard mask stack 460 refers to the second hard mask layer 458. In some embodiments, the second hard mask stack 460 and dielectric layer 370 directly beneath the first trench 432 and the second trench 462 are etched using a dry etching process. As shown in Figures 2B, 4D, and 4F, in operation 224f, the remaining portion of the second hard mask stack 460 is removed to form a dielectric layer 110 having a second via 468 and a first via 372. In some embodiments, the remainder of the second hard mask stack 460 is removed by a dry etching process, wherein the gas used in the dry etching process is O2. In some embodiments, the first hard mask layer 464 is removed to form a dielectric layer 110 having a second via 468 and a first via 372. The first hard mask layer 464 has high etch selectivity relative to the dielectric layer 110, which allows the first hard mask layer 464 to be easily removed without damaging the dielectric layer 110, thereby improving the reliability and integrity of the semiconductor structure.

[0047] Referring to Figures 2A, 4F, 5A, and 5B, in operation 227a, a second landing pad 130 is formed in the second via 468. As shown in Figures 2A, 4F, 5A, and 5B, in operation 227b, a first landing pad 120 is formed in the first via 372. As shown in Figures 5A-5B, in some embodiments, forming the first landing pad 120 in the first via 372 and forming the second landing pad 130 in the second via 468 are performed simultaneously. In some embodiments, forming the first landing pad 120 in the first via 372 and forming the second landing pad 130 in the second via 468 constitutes the formation of a semiconductor structure 500. In some embodiments, forming the first landing pad 120 in the first via 372 and forming the second landing pad 130 in the second via 468 includes the following steps. As shown in Figures 4F and 5A, a metal layer 502 is deposited in the first via 372 and the second via 468, and on the dielectric layer 110. As shown in Figures 4F-5B, the metal layer 502 is planarized to form a first landing pad 120 in the first via 372 and a second landing pad 130 in the second via 468. In some embodiments, the metal layer 502 is deposited by, for example, but not limited to, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof. In some embodiments, the metal layer 502 is planarized by a chemical mechanical polishing (CMP) process. By using CMP planarization of the metal layer 502, the step height of the array region AR and the peripheral region PR of the dielectric layer 110 can be reduced, thereby improving the reliability and integrity of the semiconductor structure. The step height is formed because the pattern density of the layers above the array region AR and the peripheral region PR of the dielectric layer 110 differs during the formation of the semiconductor structure 500, resulting in different etching amounts between these layers. It is worth noting that the semiconductor structure 500 is formed using a damascene process.

[0048] Figure 6 is a cross-sectional view of semiconductor structure 100. As shown in Figures 5B and 6, after forming the first landing pad 120 in the first via 372 (operation 227b), a capacitor structure 140 is formed on the first landing pad 120. In some embodiments, forming the capacitor structure 140 includes the following operations. As shown in Figure 6, a stacked structure (not shown) with holes (not shown) is formed on semiconductor structure 500, wherein the holes expose each first landing pad 120, the stacked structure including a plurality of layers (not shown) having oxide layers and nitride layers, and photoresist (not shown) on these layers. The formation of the stacked structure with holes is described above in the formation of the dielectric layer 370 having the first via 372. In some embodiments, the photoresist includes two or three layers of photoresist, such as photoresist 340, photoresist 420, and photoresist 450. As shown in Figure 6, a first electrode layer 140f is conformally formed over the vias, and an etching process is subsequently performed on the stacked structure with the vias to remove the stacked structure. In some embodiments, the etching process includes a wet etching process. As shown in Figure 6, a capacitor dielectric layer 140d is conformally formed on the inner sidewalls and bottom of the first electrode layer 140f, and an outer dielectric layer 140o is formed on the outer sidewalls of the first electrode layer 140f. As shown in Figure 6, a second electrode layer 140s is formed within the capacitor dielectric layer 140d within the first electrode layer 140f.

[0049] As shown in Figure 6, a dielectric layer 150 with holes (not shown) is formed above the peripheral region PR of the semiconductor structure 500, with a portion of the holes exposing the second landing pad 130. The formation of the dielectric layer 150 with holes is described above in the formation of the dielectric layer 110 with the second via 468. As shown in Figure 6, conductive lines 152 are formed within the holes. The formation of the conductive lines 152 is described above in the formation of the first landing pad 120 and the second landing pad 130. In some embodiments, the capacitor structure 140, the dielectric layer 150, and the conductive lines 152 are formed by, for example, but not limited to, CVD, PVD, ALD, sputtering, LPCVD, another deposition process, or any suitable combination thereof.

[0050] In summary, this disclosure provides a method for forming a semiconductor structure. The method includes forming a hard mask stack on a dielectric layer as a mask for subsequent etching processes of the dielectric layer. The hard mask stack includes different etch selectivity among multiple layers, resulting in better pattern migration and thus more precise patterns formed in the dielectric layer. Furthermore, a damascene process is performed when forming the semiconductor structure having a dielectric layer and landing pads embedded in the dielectric layer, reducing the step height between the array region and the surrounding region of the dielectric layer. Therefore, these features improve the reliability and integrity of the semiconductor structure.

[0051] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0052] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended patent applications.

[0053] 100, 300a, 300b, 300c, 500: Semiconductor Structure 110, 150, 302, 370: Dielectric layer 120: First landing pad 130: Second landing pad 140: Capacitor Structure 140d: Capacitor dielectric layer 140°: Outer dielectric layer 140f: First electrode layer 140s: Second electrode layer 152: Conductor 200: Method 203, 206, 209, 212, 215, 218, 221, 224, 224a, 224b, 224c, 224d, 224e, 224f, 227a, 227b: Operations 310, 410: First hard mask layer 312, 366, 412, 442, 464: First hard mask layer 314, 332, 356, 414, 428, 444, 458: Second hard mask layer 316, 416, 446: Third hard mask layer 318, 418, 448: Fourth hard mask layer 320, 348: Patterned photoresist layer 322, 350, 426: First opening 324, 352: Spacing layer 326, 354: Spacers 328, 432: First trench 330, 362, 430, 460: Second hard mask stack 340, 420, 450: Optical Resist 342: Photoresist bottom layer 344, 422, 452: Anti-reflective structure 346, 424, 454: Photoresist layer 358, 462: Second trench 360: Intersection 364, 466: Holes 368, 372: First through hole 440: Third Hard Mask Layer 456: Second opening 468: Second through hole 502: Metallic layer AR: Array Area PR: Surrounding Area T1, T2, T3, T4, T5, T6, T7, T8: Thickness d1: Depth S1: Spacing D1: First Direction D2: Second Direction A1:Angle A-A', B-B', C-C': Section lines

[0054] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor structure, comprising: A first hard mask stack is formed on a dielectric layer, wherein the first hard mask stack includes a plurality of alternately stacked carbon layers and a plurality of antireflective coatings, and the dielectric layer includes an array region; the first hard mask stack is etched to form a second hard mask stack and a first trench, the first trench extending above the array region and within the second hard mask stack along a first direction, wherein a bottom surface of the first trench is in one of the antireflective coatings; a photoresist is formed on the second hard mask stack and within the first trench; the photoresist and the second hard mask stack are etched to form a second trench, the second trench extending along a second direction different from the first direction, wherein the first trench and the second trench intersect each other to form an intersection; the photoresist is removed; the second hard mask stack directly below the intersection is etched to form a hole to expose the dielectric layer; the dielectric layer exposed from the hole is etched to form a first via; And to form a first landing pad in the first through hole.

2. The method as described in claim 1, wherein a k value of the dielectric layer is less than or equal to 4.

3. The method as described in claim 1, wherein forming the first hard mask stack on the dielectric layer comprises sequentially depositing a first carbon layer, a first anti-reflective coating, a second carbon layer and a second anti-reflective coating on the dielectric layer.

4. The method as described in claim 3, wherein the bottom surface of the first trench is in the first antireflective coating.

5. The method as described in claim 1, wherein forming the photoresist on the second hard mask stack and in the first trench comprises sequentially depositing a photoresist underlayer, an anti-reflection structure and a photoresist layer on the second hard mask stack and in the first trench.

6. The method as described in claim 1, wherein an angle between the first direction and the second direction is between 60 degrees and 120 degrees.

7. The method as described in claim 1, wherein forming the first landing pad in the first through-hole comprises: A metal layer is deposited in the first via and on the dielectric layer; And planarize the metal layer to form the first landing pad in the first through-hole.

8. The method as described in claim 1, further comprising: After the first landing pad is formed in the first through hole, a capacitor structure is formed on the first landing pad.

9. The method as described in claim 1, further comprising: After etching the dielectric layer exposed from the hole to form the first via, a peripheral area of ​​the dielectric layer is etched to form a second via; And to form a second landing pad in the second through hole.

10. The method as described in claim 9, wherein forming the first landing pad in the first through-hole and forming the second landing pad in the second through-hole are performed simultaneously.

11. A method for forming a semiconductor structure, comprising: A first hard mask layer, a second hard mask layer, a third hard mask layer, and a fourth hard mask layer are sequentially deposited on a dielectric layer, wherein the first hard mask layer and the third hard mask layer have high etch selectivity relative to the second hard mask layer and the fourth hard mask layer, and the dielectric layer includes an array region; the second hard mask layer, the third hard mask layer, and the fourth hard mask layer are etched to form a first trench, the first trench extending above the array region along a first direction and removing the third hard mask layer and the fourth hard mask layer; a second trench is formed in the second hard mask layer, the second trench extending along a second direction different from the first direction, wherein the first trench and the second trench intersect each other to form an intersection and expose the first hard mask layer; a first via is formed through the first hard mask layer and the dielectric layer below the intersection. Remove the first hard masking layer and the second hard masking layer; and form a first landing pad in the first through-hole.

12. The method as described in claim 11, wherein the first hard mask layer and the third hard mask layer are carbon layers, and the second hard mask layer and the fourth hard mask layer are anti-reflective coatings.

13. The method as described in claim 11 further includes: After the first landing pad is formed in the first through hole, a capacitor structure is formed on the first landing pad.

14. The method of claim 11, further comprising, before etching the second hard mask layer, the third hard mask layer, and the fourth hard mask layer to form the first trench, the first trench extending over the array region along the first direction, and removing the third hard mask layer and the fourth hard mask layer: A patterned photoresist layer with a first opening is formed on the fourth hard mask layer and the fourth hard mask layer is exposed. A spacer layer is conformally formed to cover the patterned photoresist layer and the first opening; And etch a horizontal portion of the spacer layer to expose the patterned photoresist layer and the fourth hard mask layer.

15. The method as described in claim 11, further comprising: After removing the first hard mask layer and the second hard mask layer, a peripheral area of ​​the dielectric layer is etched to form a second via. And to form a second landing pad in the second through hole.

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