Semiconductor integrated circuits

Abstract

According to an embodiment, a semiconductor integrated circuit is provided, comprising a switch, a first control circuit, and a second control circuit. The switch is connected between a first power supply and a second power supply. The switch is turned off (OFF) when a first level is received at a control terminal. The first control circuit has an input node and an output node. The output node is connected to the control terminal of the switch. The second control circuit has an output node and an input node. The input node is connected to the control terminal of the switch. The semiconductor integrated circuit satisfies at least one of the following: in the first control circuit, the driving force toward the first level is greater than the driving force toward the second level; and in the second control circuit, the driving force toward the second level is greater than the driving force toward the first level.

Description

Technical Field

[0001] This embodiment relates to semiconductor integrated circuits. [Citation of relevant applications]

[0002] This case asserts priority to Japanese Patent Application No. 2024-162424, filed on September 19, 2024, the entire contents of which will be incorporated into this case. Prior Technology

[0003] Semiconductor integrated circuits such as power switches receive power and can supply or disconnect the power to circuits at connection points. In semiconductor integrated circuits, it is best to appropriately disconnect the power supply to connection points. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] [Figure 1] is a plan view showing the configuration of the semiconductor integrated circuit in the first embodiment.

[0006] [Figure 2] is a circuit diagram showing the configuration of the semiconductor integrated circuit in the first embodiment.

[0007] [Figure 3] is a circuit diagram showing the configuration of the power switch in the first embodiment.

[0008] [Figure 4] is a circuit diagram showing the detailed configuration of the power switch in the first embodiment.

[0009] [Figure 5A] and [Figure 5B] are diagrams showing the critical voltage distribution of the SVT and LVT in the first embodiment.

[0010] Figures 6A to 6D are waveform diagrams showing the operation of the power switch in the first embodiment.

[0011] [Figure 7] is a circuit diagram showing the configuration of the power switch in the second embodiment.

[0012] [Figure 8] is a circuit diagram showing the detailed configuration of the power switch in the second embodiment.

[0013] Figures 9A to 9D are diagrams showing the leakage current path in the second embodiment.

[0014] [Figure 10] is a circuit diagram showing the configuration of the power switch in the third embodiment.

[0015] [Figure 11] is a circuit diagram showing the detailed configuration of the power switch in the third embodiment.

[0016] [Figure 12A] and [Figure 12B] are diagrams showing the adjustment of the voltage division ratio by the auxiliary circuit in the third embodiment.

[0017] [Figure 13] is a circuit diagram showing the detailed configuration of the power switch in the fourth embodiment. Implementation

[0018] According to this embodiment, a semiconductor integrated circuit is provided, comprising a switch, a first control circuit, and a second control circuit. The switch is connected between a first power supply and a second power supply. The switch is turned off (OFF) on time when a first bit is received at the control terminal. The first control circuit has an input node and an output node. The output node is connected to the control terminal of the switch. The second control circuit has an output node and an input node. The input node is connected to the control terminal of the switch. Semiconductor integrated circuits satisfy at least one of the following: In the first control circuit, the driving force towards the first level is greater than the driving force towards the second level; and In the second control circuit, the driving force toward the second level is greater than the driving force toward the first level.

[0019] The semiconductor integrated circuit of each embodiment is described in detail below with reference to the accompanying drawings. However, these embodiments are not intended to limit the scope of the invention.

[0020] (First Implementation) The semiconductor integrated circuit in the first embodiment is a power receiving circuit that can supply or cut off the power to the circuit at the connection point, but is designed to properly cut off the power to the connection point.

[0021] As shown in Figure 1, the semiconductor integrated circuit 1 has a power supply terminal TM1, a control terminal TM2, a power supply circuit 2, multiple circuit blocks 3A to 3C, and a control circuit 4. Figure 1 is a plan view showing the structure of the semiconductor integrated circuit.

[0022] Power supply circuit 2 is connected to power supply terminal TM1, control circuit 4, and multiple circuit blocks 3A-3C. Control circuit 4 is connected to control terminal TM2 and power supply circuit 2. Multiple circuit blocks 3A-3C are each connected to power supply circuit 2.

[0023] Control circuit 4 receives control signal CTR from an external source (e.g., a controller) via control terminal TM2. Control circuit 4 generates control signals CNTA, CNTB, and CNTC according to control signal CTR and supplies them to power circuit 2.

[0024] Power supply circuit 2 receives power supply voltage TVDD from an external source (e.g., a controller) via power supply terminal TM1. Power supply circuit 2 uses power supply voltage TVDD to generate power supply voltages VDD_A, VDD_B, and VDD_C. Power supply circuit 2 supplies or cuts off power supply voltages VDD_A, VDD_B, and VDD_C to circuit blocks 3A, 3B, and 3C respectively according to control signals CNTA, CNTB, and CNTC.

[0025] As shown in Figure 2, the power supply circuit 2 is configured to supply and cut off power to the complex circuit blocks 3A, 3B, and 3C respectively. Figure 2 is a circuit diagram showing the configuration of the power supply circuit 2.

[0026] Power supply circuit 2 consists of a complex group of power switches 2A, 2B, and 2C. These power switch groups 2A, 2B, and 2C correspond to complex circuit blocks 3A, 3B, and 3C, and to complex control lines CNTA, CNTB, and CNTC. Each power switch group 2 is connected between power terminal TM1 and its corresponding circuit block 3.

[0027] The power switch group 2A is connected to the power terminal TM1 via the global power line TVDD, to the circuit block 3A via the local power line VDD_A, and to the control circuit 4 via the control line CNTA.

[0028] Let n be any integer greater than or equal to 2. Power switch group 2A is configured to supply and disconnect power to circuit block 3A respectively. Power switch group 2A consists of n power switches (PSWs) 21_1 to 21_n. The n PSWs 21_1 to 21_n are connected in parallel between the global power line TVDD and the local power line VDD_A, and in series with respect to the control line CNTA.

[0029] Each PSW21 has an input node IN connected to the control line CNTA or the PSW21 of the front end, an output node OUT connected to the PSW21 of the secondary end, a power node TVDD connected to the global power line TVDD, and a power node VDD connected to the corresponding circuit block 3A via the local power line VDD_A.

[0030] n PSWs 21_1~21_n are serially transmitted control signals CNTA. Each PSW 21 supplies or cuts off power to circuit block 3A according to the control signal CNTA.

[0031] PSW group 2B is connected to power terminal TM1 via global power line TVDD, to circuit block 3B via local power line VDD_B, and to control circuit 4 via control line CNTB.

[0032] PSW group 2B is configured to supply and cut off power to circuit block 3B respectively. PSW group 2B has n PSWs 22_1 to 22_n. The n PSWs 22_1 to 22_n are connected in parallel between the global power line TVDD and the local power line VDD_B, and connected in series for the control line CNTB.

[0033] Each PSW22 has an input node IN connected to the control line CNTB or the front-end PSW22, an output node OUT connected to the secondary PSW22, a power node TVDD connected to the global power line TVDD, and a power node VDD connected to circuit block 3B via the local power line VDD_B.

[0034] n PSWs 22_1~22_n are serially transmitted control signals CNTB. Each PSW 22 supplies or cuts off power to circuit block 3B according to the control signal CNTB.

[0035] PSW group 2C is connected to power terminal TM1 via global power line TVDD, to circuit block 3C via local power line VDD_C, and to control circuit 4 via control line CNTC.

[0036] PSW group 2C is configured to supply and cut off power to circuit block 3C respectively. PSW group 2C has n PSWs 23_1 to 23_n. The n PSWs 23_1 to 23_n are connected in parallel between the global power line TVDD and the local power line VDD_C, and connected in series for the control line CNTC.

[0037] Each PSW23 has an input node IN connected to the control line CNTC or the front-end PSW23, an output node OUT connected to the secondary PSW23, a power node TVDD connected to the global power line TVDD, and a power node VDD connected to circuit block 3C via the local power line VDD_C.

[0038] n PSWs 23_1~23_n are serially transmitted control signals CNTC. Each PSW 23 supplies or cuts off power to circuit block 3C according to the control signal CNTC.

[0039] Next, the configuration of each PSW21 will be explained using Figure 3. Figure 3 is a circuit diagram showing the configuration of the PSW21. In Figure 3, the configuration of the PSW21 is shown as an example, but the configurations of PSW22 and PSW23 are the same as those of PSW21.

[0040] PSW21 has a switch 213, a control circuit 211, and a control circuit 212.

[0041] Switch 213 is connected between power node TVDD and power node VDD. One end 213a of switch 213 is connected to power node TVDD, and the other end 213b is connected to power node VDD. Control terminal 213c is connected to node N1. Switch 213 is turned off when the control terminal 213c receives the H position.

[0042] Switch 213 may also include transistor PM1. Transistor PM1 is, for example, a PMOS transistor. Transistor PM1 has its source connected to power node TVDD, its drain connected to power node VDD, and its gate connected to node N1. Transistor PM1 is turned off (OFF) when the gate receives a bit H.

[0043] The control circuit 211 is connected between the input node IN and node N1 of the PSW 21. The input node 211a of the control circuit 211 is connected to the input node IN, the output node 211b is connected to the control terminal 213c of the switch 213 via node N1, and the power node 211c is connected to the power node TVDD.

[0044] The control circuit 211 may also include an inverter INV1. The inverter INV1 has its input node connected to the input node IN and its output node connected to node N1.

[0045] Control circuit 212 is connected between node N1 and output node OUT of PSW 21. Input node 211a of control circuit 212 is connected to control terminal 213c of switch 213 via node N1, output node 212b is connected to output node OUT, and power node 212c is connected to power node TVDD.

[0046] The control circuit 212 may also include an inverter INV2. The inverter INV2 has its input node connected to node N1 and its output node connected to the output node OUT.

[0047] PSW21 is configured such that the driving force toward the H level in control circuit 211 is greater than the driving force toward the L level, and the driving force toward the L level in control circuit 212 is greater than the driving force toward the H level.

[0048] The PSW21 can also be configured as shown in Figure 4. Figure 4 is a circuit diagram showing the detailed configuration of the PSW21.

[0049] The inverter INV1 of control circuit 211 has transistors PM11 and NM11. Transistors PM11 and NM11 are connected in reverse order. Transistor PM11 can also be a PMOS transistor. Transistor NM11 can also be an NMOS transistor. Transistors PM11 and NM11 have a common gate connection and are connected to the input node IN, and a common drain connection and are connected to node N1. The source of transistor PM11 is connected to the power supply node TVDD. The source of transistor NM11 is connected to the ground node VSS.

[0050] The threshold voltage of transistor PM11 is lower than that of transistor NM11. For example, the difference between the center voltage of the threshold voltage distribution of transistor PM11 and the center voltage of the threshold voltage distribution of transistor NM11 is more than half the width of the threshold voltage distribution of transistor PM11 (see Figure 5B). Therefore, the driving force towards the H level in control circuit 211 will be greater than the driving force towards the L level.

[0051] Transistor PM11 can be constructed from LVT (Low Threshold Voltage Transistor). Transistor NM11 can be constructed from SVT (Standard Threshold Voltage Transistor).

[0052] The inverter INV1 is composed of transistor PM11 of the LVT and transistor NM11 of the SVT. Therefore, when the input is at the L level, the output easily becomes at the H level. The critical voltage distribution of the LVT's PMOS is shown as a solid line in Figure 5B, and the critical voltage distribution of the SVT's NMOS is shown as a dashed line in Figure 5B. Figure 5 is a diagram showing the critical voltage distribution of the SVT and LVT. In Figure 5B, the vertical axis represents the number of transistors, and the horizontal axis represents the voltage.

[0053] The critical voltage distribution of the LVT's PMOS is shifted to a lower voltage side than that of the SVT's NMOS. The center voltage Vcp of the LVT's PMOS critical voltage distribution is lower than the center voltage Vcn of the SVT's NMOS critical voltage distribution. The difference between the center voltage Vcp and the center voltage Vcn is more than half the half-width (HWp) of the LVT's PMOS critical voltage distribution.

[0054] As shown in Figure 5B, even if the threshold voltage of the PMOS of the LVT becomes higher as ● due to the deviation, and the threshold voltage of the NMOS of the SVT becomes lower as ○, when the L level (e.g., V1) is supplied to the input node of the inverter, the NMOS will be turned off and the PMOS will be turned on, so that the H level can be output from the output node of the inverter.

[0055] The inverter INV2 of control circuit 212 has transistors PM12 and NM12. Transistors PM12 and NM12 are connected in reverse order. Transistor PM12 can also be a PMOS transistor. Transistor NM12 can also be an NMOS transistor. Transistors PM12 and NM12 are connected with their gates in common connection to node N1, and with their drains in common connection to the output node OUT. The source of transistor PM12 is connected to the power supply node TVDD. The source of transistor NM12 is connected to the ground node VSS.

[0056] The threshold voltage of transistor NM12 is lower than that of transistor PM12. For example, the difference between the center voltage of the threshold voltage distribution of transistor NM12 and the center voltage of the threshold voltage distribution of transistor PM12 is more than half the width of the threshold voltage distribution of transistor NM12. Therefore, the driving force towards the L level in control circuit 212 will be greater than the driving force towards the H level.

[0057] The NM12 transistor can be constructed from an LVT (Low Threshold Voltage Transistor). The PM12 transistor can be constructed from an SVT (Standard Threshold Voltage Transistor).

[0058] The inverter INV2 is composed of the LVT transistor NM12 and the SVT transistor PM12. Therefore, when the input is at the H level, the output is likely to become the L level.

[0059] The threshold voltage distribution of the LVT's NMOS is shifted to a lower voltage side than that of the SVT's PMOS. The center voltage of the LVT's NMOS threshold voltage distribution is lower than that of the SVT's PMOS threshold voltage distribution. The difference between the center voltage of the LVT's NMOS threshold voltage distribution and that of the SVT's PMOS threshold voltage distribution is more than half the width at half maximum (WHM) of the LVT's NMOS threshold voltage distribution.

[0060] Even if the threshold voltage of the NMOS in the LVT becomes high and the threshold voltage of the PMOS in the SVT becomes low due to the deviation, when the H level is supplied to the input node of the inverter, the PMOS will be turned off and the NMOS will be turned on, so that the L level can be output from the output node of the inverter.

[0061] For example, as shown in Figure 6B, when the potential of the control signal CNTA supplied to the input node IN of the initial stage PSW21_1 is maintained at the L level, as shown in Figure 6A, at time t1, the potential of the power line TVDD starts to rise from the L level. Figures 6A to 6D are waveform diagrams showing the operation of PSW21.

[0062] At this time, transistor PM1 of switch 213 is turned off.

[0063] Immediately after time t1, in the inverter INV1 of PSW21_1, although the gate-source voltage of transistor PM11 is relatively small, it is turned on (ON) because it is constructed as an LVT. Therefore, as shown by the dashed line in Figure 6C, the potential of node N1 begins to follow at a level close to the potential of the power supply line TVDD (H level). As a result, transistor PM1 of switch 213 is maintained in the OFF state.

[0064] Therefore, in the inverter INV2 of PSW21_1, although the gate-source voltage of transistor NM12 is relatively small, it is turned on because it is constructed as an LVT. As a result, as shown by the dotted line in Figure 6D, the potentials of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained near the L level.

[0065] At time t2, in the inverter INV1 of PSW21_1, although the gate-source voltage of transistor PM11 is relatively small, it can remain ON because it is constructed as an LVT. Therefore, the potential of node N1, as shown by the dashed line in Figure 6C, can continue to follow the potential at a level close to that of the power supply line TVDD. As a result, transistor PM1 of switch 213 is maintained in the OFF state.

[0066] Correspondingly, in the inverter INV2 of PSW21_1, although the gate-source voltage of transistor NM12 is relatively small, it can remain ON because it is constructed as an LVT. Therefore, the potentials of the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained near the L level, as shown in Figure 6D.

[0067] If time becomes t3, then in the inverter INV1 of PSW21_1, transistor PM11 remains ON due to the relatively large gate-source voltage. Therefore, the potential of node N1, as shown by the dashed line in Figure 6C, can continue to follow the potential at a level close to that of the power supply line TVDD. As a result, transistor PM1 of switch 213 is maintained in the OFF state.

[0068] Correspondingly, in the inverter INV2 of PSW21_1, transistor NM12 remains ON due to the relatively large gate-source voltage. Thus, as shown in Figure 6D, the output node OUT of PSW21_1 and the input node IN of the next stage PSW21_2 are maintained at the L level.

[0069] After time t3, in the inverter INV1 of PSW21_1, transistor PM11 is stably turned on (ON), and the potential of node N1, as shown by the dashed line in Figure 6C, is stably tracked at a level close to the potential of the power line TVDD (H). As a result, transistor PM1 of switch 213 is stably maintained in the OFF state.

[0070] Correspondingly, in the inverter INV2 of PSW21_1, the transistor NM12 is stably turned on (ON), and the potentials of the output node OUT of PSW21_1 and the input node IN of the secondary segment PSW21_2 are stably maintained at the L level as shown in Figure 6D.

[0071] As described above, in the first embodiment, in the semiconductor integrated circuit 1, the PSW 21 is configured such that the driving force towards the H level in the control circuit 211 is greater than the driving force towards the L level. This suppresses leakage when the switch 213, which should be turned off, is powered on, reducing power consumption in standby mode. Therefore, power disconnection from the connection point of the PSW 21 can be appropriately performed.

[0072] Furthermore, in the first embodiment, in the semiconductor integrated circuit 1, the PSW21 is configured such that the driving force towards the L level in the control circuit 212 is greater than the driving force towards the H level. This allows the signal transmitted to the secondary PSW21 to be easily suppressed at the L level, suppressing leakage caused by the influence of the preceding stage when the power supply to the switch 213, which should be turned off, is started, thus reducing power consumption in standby mode. Therefore, the power supply to the connection point can also be appropriately cut off via the secondary PSW21.

[0073] For example, if an inverter is constructed using the PMOS and NMOS of the SVT, the output will be at the L level when the input is at the L level. The critical voltage distribution of the SVT's PMOS is shown as a solid line in Figure 5A, and the critical voltage distribution of the SVT's NMOS is shown as a dashed line in Figure 5A. Figure 5 shows the critical voltage distributions of the SVT and LVT. In Figure 5A, the vertical axis represents the number of transistors, and the horizontal axis represents the voltage. The critical voltage distributions of the SVT's PMOS and NMOS almost overlap. The center voltage Vcp of the critical voltage distribution of the SVT's PMOS is almost equal to the center voltage Vcn of the critical voltage distribution of the SVT's NMOS.

[0074] As shown in Figure 5A, due to the deviation, if the threshold voltage of the PMOS of the SVT becomes higher as ● and the threshold voltage of the NMOS of the SVT becomes lower as ○, then when the L level (e.g., V1) is supplied to the input node of the inverter, the NMOS will be turned on and the PMOS will be turned off, and the L level can be output from the output node of the inverter.

[0075] For example, compared to the PSW21 shown in Figure 4, one can consider a PSW21 whose configuration is changed to include SVT transistors PM11s and NM11 in the inverter INV1s of the control circuit 211s, and SVT transistors PM12 and NM12 in the inverter INV2s of the control circuit 212s.

[0076] As shown in Figure 6B, when the potential of the control signal CNTS supplied to the input node IN of the initial PSW21s_1 is maintained at the L level, as shown in Figure 6A, at time t1, the potential of the power line TVDD starts to rise from the L level.

[0077] At this time, transistor PM1 of switch 213 is turned off.

[0078] Immediately after time t1, in the inverter INV1s of PSW21s_1, transistor PM11s is turned off due to the relatively small gate-source voltage and its SVT configuration. Consequently, as shown by the dotted line in Figure 6C, the potential of node N1 dissociates from the potential of the power supply line TVDD to level L. As a result, transistor PM1 of switch 213 begins to enter a half-on state.

[0079] Correspondingly, in the inverter INV2s of PSW21s_1, the transistor NM12s is turned off due to its relatively small gate-source voltage and its SVT configuration. Consequently, the potentials of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21s_2, as shown by the dotted line in Figure 6D, begin to follow at a level H close to the potential of the power supply line TVDD.

[0080] At time t2, in the inverter INV1s of PSW21s_1, transistor PM11s is off due to the relatively small gate-source voltage and its SVT configuration. Consequently, the potential of node N1 continues to dissociate from the potential of the power line TVDD to level L, as shown by the dotted line in Figure 6C. As a result, transistor PM1 of switch 213 forms a stronger half-open state.

[0081] Correspondingly, in the inverter INV2s of PSW21s_1, the transistor NM12s remains off due to its relatively small gate-source voltage and its SVT configuration. Consequently, the potentials of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21s_2, as shown by the dotted line in Figure 6D, continue to follow the H level, which is close to the potential of the power supply line TVDD.

[0082] If time t3 is reached, then in the inverter INV1s of PSW21s_1, transistor PM11s is turned on (ON) due to the relatively large gate-source voltage. Consequently, the potential of node N1, as shown by the dotted line in Figure 6C, begins to follow the potential at a level close to the power line TVDD (H level). As a result, transistor PM1 of switch 213 transitions from the half-on state to the OFF state and is maintained in the OFF state.

[0083] Correspondingly, in the inverter INV2s of PSW21s_1, the transistor NM12s is turned on (ON) because the gate-source voltage is relatively large. As a result, the potentials of the output node OUT of PSW21s_1 and the input node IN of the next stage PSW21_2 form the L level as shown by the dotted line in Figure 6D, and are initially maintained at the L level.

[0084] That is, in PSW21s, at times t1~t3, since the transistor PM1 of switch 213 is in a half-open state, the power consumption in the standby state will easily increase due to the leakage of transistor PM1.

[0085] On the other hand, in this embodiment, the PSW21 is configured as an inverter INV1 in the control circuit 211, which includes an LVT transistor PM11 and an SVT transistor NM11, and an inverter INV1 in the control circuit 212, which includes an SVT transistor PM12 and an LVT transistor NM12. This suppresses leakage when the switch 213, which should be OFF, is started, thus reducing power consumption in standby mode.

[0086] Alternatively, PSW21' can be configured such that the driving force towards the H level in control circuit 211 is greater than the driving force towards the L level, and the driving force towards the L level and the driving force towards the H level are equal in control circuit 212s. PSW21' can also be modified relative to the inverter INV2 shown in FIG4 by replacing it with an SVT transistor PM12 and an SVT transistor NM12s to form the inverter INV2s of control circuit 212s. In this case, since the driving force towards the H level is greater than the driving force towards the L level in control circuit 211 of PSW21', node N1 can be easily set to the H level during power-on. This suppresses leakage during power-on when the switch 213, which should be OFF, is turned off.

[0087] Alternatively, PSW21" can be configured such that the driving force towards the H level and the driving force towards the L level are equal in the control circuit 211s, and the driving force towards the L level is greater than the driving force towards the H level in the control circuit 212. PSW21" can also be modified relative to the inverter INV1 shown in FIG4, by including SVT transistors PM11s and NM11 to form the inverter INV1s of the control circuit 211s. In this case, since the driving force towards the L level is greater than the driving force towards the H level in the control circuit 212 of PSW21", the output node OUT can be easily set to the L level during power-on. This suppresses leakage caused by the influence of the front end of the switch 213, which should be turned off, during power-on.

[0088] (Second Implementation) Next, the semiconductor integrated circuit 1i of the second embodiment will be explained. Hereinafter, the explanation will focus on the parts that are different from the first embodiment.

[0089] In the first embodiment, an example is given of a configuration that reduces leakage of switch 213 by adjusting the driving force of the control circuit of PSW. However, in the second embodiment, an example is given of a configuration that reduces leakage of switch 213 by adding an auxiliary circuit of PSW.

[0090] In the semiconductor integrated circuit 1i, PSW21i (or 22i, 23i) can be configured as shown in FIG7. FIG7 is a circuit diagram showing the configuration of PSW21i in the second embodiment. In FIG7, the configuration of PSW21i is shown as an example, but the configurations of PSW22i and PSW23i are the same as those of PSW21i.

[0091] PSW21i replaces control circuits 211 and 212 (see Figure 3) and has control circuits 211s and 212s, and further has auxiliary circuits 214i and 215i.

[0092] The driving force of the control circuit 211s towards the H level and the driving force towards the L level can also be equal. As shown in Figure 8, the inverter INV1s of the control circuit 211s can also include SVT transistor PM11s and SVT transistor NM11. Figure 8 is a circuit diagram showing the detailed configuration of the PSW21i in the second embodiment.

[0093] The control circuit 212s shown in Figure 7 can have equal driving force towards the H level and driving force towards the L level. As shown in Figure 8, the inverter INV2s of the control circuit 212s can also include SVT transistors PM11s and NM11.

[0094] The auxiliary circuit 214i shown in Figure 7 is connected between the control circuit 211s and the switch 213. The auxiliary circuit 214i can also be connected between the control circuit 211s and node N1. The auxiliary circuit 214i is connected between the power supply potential TVDD and the ground potential VSS at the location between the control circuit 211s and the switch 213. The auxiliary circuit 214i can also be connected between the power supply potential TVDD and the ground potential VSS at the location between the control circuit 211s and node N1. Thus, when the switch 213 is kept in the OFF state and the L level is input to the input node of the control circuit 211s, the auxiliary H level of the auxiliary circuit 214i appears at the output node of the control circuit 211s.

[0095] As shown in Figure 8, the auxiliary circuit 214i includes at least one of transistor PM21 or transistor NM21. In Figure 8, an example of the auxiliary circuit 214i including transistor PM21 and transistor NM21 is given. Transistor PM21 and transistor NM21 are respectively connected as inverting diodes. Transistor PM21 can also be a PMOS transistor. Transistor NM21 can also be an NMOS transistor.

[0096] Transistors PM21 and NM21 are connected with a common drain and are connected to node N1. Transistor PM21 has its gate, source, and back gate connected to the power node TVDD. Transistor NM21 has its source connected to the power node TVDD, and its gate and back gate connected to the ground node VSS.

[0097] In transistor PM21, as shown in Figure 9B, the gate is maintained in the OFF state because it is connected to the power node TVDD, but the drain is in a floating state because the source is connected to the power node TVDD, so leakage current flows from the source to the drain. In this way, although little by little, charge is charged to the drain, and the potential can be raised to the H-side.

[0098] In the NM21 transistor, as shown in Figure 9A, the gate is maintained in the OFF state because it is connected to the ground node VSS, but the drain is in a floating state because the source is connected to the power node TVDD. Therefore, leakage current flows from the source to the drain. In this way, although little by little, charge is charged to the drain, and the potential can be raised to the H-side.

[0099] Therefore, when switch 213 is kept in the OFF state and the L level is input to the input node of control circuit 211s, the H level can be assisted to appear at the output node of control circuit 211s.

[0100] The auxiliary circuit 215i shown in Figure 7 is connected between the control circuit 212s and the output node OUT. The auxiliary circuit 215i is connected between the power supply potential TVDD and the ground potential VSS at the location between the control circuit 212s and the output node OUT. Therefore, when switch 213 is kept in the OFF state and the H level is input to the input node of the control circuit 212s, the auxiliary L level of the auxiliary circuit 215i appears at the output node of the control circuit 212s.

[0101] As shown in Figure 8, the auxiliary circuit 215i includes at least one of transistor PM22 or transistor NM22. In Figure 8, an example of the auxiliary circuit 215i including transistor PM22 and transistor NM22 is given. Transistor PM22 and transistor NM22 are respectively connected as inverting diodes. Transistor PM22 can also be a PMOS transistor. Transistor NM22 can also be an NMOS transistor.

[0102] Transistors PM22 and NM22 have a common drain connection and are connected to the output node OUT. Transistor PM22 has its source connected to the ground node VSS, and its gate and back gate connected to the power node TVDD. Transistor NM22 has its source, gate, and back gate connected to the ground node VSS.

[0103] In the PM22 transistor, as shown in Figure 9D, the gate is maintained in the OFF state because it is connected to the power node TVDD, but the drain is in a floating state because the source is connected to the ground node VSS. Therefore, leakage current flows from the drain to the source. In this way, although little by little, the charge will discharge from the drain, and the potential can be pulled towards the L-level side.

[0104] In the NM22 transistor, as shown in Figure 9C, the gate is maintained in the OFF state because it is connected to the ground node VSS, but the drain is in a floating state because the source is connected to the ground node VSS. Therefore, leakage current flows from the drain to the source. In this way, although little by little, the charge will discharge from the drain, and the potential can be pulled towards the L-level side.

[0105] Therefore, when switch 213 is kept in the OFF state and the H level is input to the input node of control circuit 212s, the L level can be assisted to appear at the output node of control circuit 212s.

[0106] As described above, in the second embodiment, in the PSW21i of the semiconductor integrated circuit 1i, when the switch 213 is kept in the OFF state and the L level is input to the input node of the control circuit 211s, the auxiliary circuit 214i assists the H level at the output node of the control circuit 211s. This suppresses leakage during power-on of the switch 213, which should be OFF, and reduces power consumption in standby mode. Therefore, power disconnection from the connection point of the PSW21i can be appropriately performed.

[0107] Furthermore, in the second embodiment, in the PSW21i of the semiconductor integrated circuit 1i, when the switch 213 is maintained in the OFF state and the H level is input to the input node of the control circuit 212s, the auxiliary circuit 215i assists the L level to appear at the output node of the control circuit 212s. This allows the signal transmitted to the secondary PSW21i to be easily suppressed at the L level, suppressing leakage caused by the influence of the preceding stage when the power supply to the OFF switch 213 is turned on, and reducing power consumption in standby mode. Therefore, the power supply to the connection point can also be appropriately cut off regarding the secondary PSW21i.

[0108] Alternatively, PSW21i' can be configured such that the auxiliary circuit 214i is omitted. In this case, in PSW21i', when switch 213 is maintained in the OFF state and level H is input to the input node of control circuit 212s, auxiliary circuit 215i assists in level L at the output node of control circuit 212s. This allows the signal transmitted to the next stage of PSW21i to be easily suppressed at level L, thus suppressing leakage caused by the influence of the preceding stage when the power supply to switch 213, which should be OFF, is turned on.

[0109] Alternatively, PSW21i" can be configured such that auxiliary circuit 215i is omitted. In this case, in PSW21i", when switch 213 is kept in the OFF state and the L level is input to the input node of control circuit 211s, auxiliary circuit 214i assists the H level at the output node of control circuit 211s. This suppresses leakage when the power supply to switch 213, which should be OFF, is turned on.

[0110] (Third Implementation) Next, the semiconductor integrated circuit 1j of the third embodiment will be described. Hereinafter, the description will focus on the parts that are different from the first and second embodiments.

[0111] In the second embodiment, an auxiliary circuit utilizing leakage is exemplified, but in the third embodiment, an auxiliary circuit utilizing a capacitor is exemplified.

[0112] In the semiconductor integrated circuit 1j, PSW21j (or 22j, 23j) can be configured as shown in FIG10. FIG10 is a circuit diagram showing the configuration of PSW21j in the third embodiment. In FIG10, the configuration of PSW21j is shown as an example, but the configurations of PSW22j and PSW23j are the same as those of PSW21j.

[0113] PSW21j replaces auxiliary circuits 214i and 215i (see Figure 7) and has auxiliary circuits 214j and 215j.

[0114] The auxiliary circuit 214j shown in Figure 10 is connected between the control circuit 211s and the switch 213. The auxiliary circuit 214j can also be connected between the control circuit 211s and node N1. The auxiliary circuit 214j is connected between the power supply potential TVDD and node N1 at the location between the control circuit 211s and the switch 213. Alternatively, the auxiliary circuit 214j can be connected between the power supply potential TVDD and node N1 at the location between the control circuit 211s and node N1. Thus, when the switch 213 is kept in the OFF state and the L level is input to the input node of the control circuit 211s, the auxiliary H level of the auxiliary circuit 214j appears at the output node of the control circuit 211s.

[0115] The auxiliary circuit 214j includes a capacitor C1. One end of capacitor C1 is connected to the control terminal of switch 213, and the other end is connected to the power supply node TVDD.

[0116] As shown in Figure 11, the auxiliary circuit 214j includes a transistor PM31. The transistor PM31 is connected by a capacitor. The transistor PM31 can also be a PMOS transistor.

[0117] The source and drain of transistor PM31 are connected to the power supply node TVDD, and the gate is connected to node N1. Therefore, transistor PM31 can function as a capacitor C1.

[0118] For example, the gate-drain capacitance CGD and the gate-source capacitance CGS of transistor PM1 are both equal at C. When the auxiliary circuit 214j is omitted, as shown in Figure 12A, the area near node N1 is configured such that capacitor CGD, node N1, and capacitor CGS are connected in series between power supply node TVDD and power supply node VDD.

[0119] The voltage division ratio of V11 between power node VDD and node N1 and V12 between node N1 and power node TVDD is V11:V12=1 / C:1 / C=1:1. During power startup, since power node VDD is almost at ground potential (≒0V), the potential of node N1 is approximately TVDD×1 / 2.

[0120] On the other hand, the gate capacitor of transistor PM31 is set as CMOS, and the capacitance of CMOS is equal to C. When auxiliary circuit 214j is provided, as shown in Figure 12B, near node N1, the configuration is formed by connecting capacitor CMOS and capacitor CGD in parallel between power node TVDD and node N1, and capacitor CGD is connected between node N1 and power node VDD.

[0121] The voltage division ratio of V1 between power node VDD and node N1 and V2 between node N1 and power node TVDD is V1:V2=1 / (C+C):1 / C=1:2. During power startup, power node VDD is almost at ground potential (≒0V), therefore the potential of node N1 is approximately TVDD×2 / 3.

[0122] That is, by setting up the auxiliary circuit 214j, the voltage division ratio of node N1 can be adjusted, so that the potential of node N1 is higher when the power is started.

[0123] Therefore, when switch 213 is kept in the OFF state and the L level is input to the input node of control circuit 211s, the H level can be assisted to appear at the output node of control circuit 211s.

[0124] The auxiliary circuit 215j shown in Figure 10 is connected between the control circuit 212s and the output node OUT. The auxiliary circuit 215j is connected between the output node OUT and the ground potential VSS at the location between the control circuit 212s and the output node OUT. Thus, when switch 213 is kept in the OFF state and the H level is input to the input node of the control circuit 212s, the auxiliary circuit 215j assists the L level at the output node of the control circuit 212s.

[0125] The auxiliary circuit 215j has a capacitor C2. One end of the capacitor C2 is connected to the output node of the control circuit 212s, and the other end is connected to the power supply node VDD.

[0126] As shown in Figure 11, the auxiliary circuit 215j includes a transistor NM32. The transistor NM32 is connected by a capacitor. The transistor NM32 can also be an NMOS transistor.

[0127] The NM32 transistor has its source and drain connected to the power supply node VDD, and its gate connected to the output node OUT. Therefore, the NM32 transistor can function as a capacitor, C2.

[0128] For example, if the auxiliary circuit 215j is omitted, when the power is started, the potential of node N1 does not rise sufficiently and is near the L level. The transistor PM12 is half-open, and the drain current flows in, which can easily charge the parasitic capacitance Cp of the line near the output node OUT, and the potential of the output node OUT can easily rise.

[0129] On the other hand, when the auxiliary circuit 215j is set, the potential of node N1 does not rise sufficiently when the power is started, and is near the L level. The transistor PM12 is half open, and the drain current flows in. However, in addition to the parasitic capacitance Cp of the line, the capacitor element C2 is also charged. Therefore, the potential of the output node OUT does not rise easily.

[0130] That is, by setting the auxiliary circuit 215j, the capacitor load near the output node OUT can be adjusted, so that the potential of the output node OUT is lower when the power is started.

[0131] Therefore, when switch 213 is kept in the OFF state and the H level is input to the input node of control circuit 212s, the L level can be assisted to appear at the output node of control circuit 212s.

[0132] As described above, in the third embodiment, in the PSW21j of the semiconductor integrated circuit 1j, when the switch 213 is kept in the OFF state and the L level is input to the input node of the control circuit 211s, the auxiliary H level of the auxiliary circuit 214j appears at the output node of the control circuit 211s. This suppresses leakage during power-on of the switch 213, which should be OFF, and reduces power consumption in standby mode. Therefore, power disconnection from the connection point of the PSW21j can be appropriately performed.

[0133] Furthermore, in the third embodiment, in the PSW21j of the semiconductor integrated circuit 1j, when the switch 213 is maintained in the OFF state and the H level is input to the input node of the control circuit 212s, the auxiliary circuit 215j assists the L level to appear at the output node of the control circuit 212s. This allows the signal transmitted to the secondary PSW21j to be easily suppressed at the L level, suppressing leakage caused by the influence of the preceding stage when the power supply to the OFF switch 213 is turned on, and reducing power consumption in standby mode. Therefore, the power supply to the connection point can also be appropriately cut off regarding the secondary PSW21j.

[0134] Alternatively, PSW21j' can be configured such that auxiliary circuit 214j is omitted. In this case, in PSW21j', when switch 213 is maintained in the OFF state and level H is input to the input node of control circuit 212s, auxiliary circuit 215j assists in level L at the output node of control circuit 212s. This allows the signal transmitted to the next stage of PSW21j to be easily suppressed at level L, thus suppressing leakage caused by the influence of the preceding stage when the power supply to switch 213, which should be OFF, is turned on.

[0135] Alternatively, PSW21j” can be configured such that auxiliary circuit 215j is omitted. In this case, in PSW21j”, when switch 213 is kept in the OFF state and the L level is input to the input node of control circuit 211s, auxiliary circuit 214j assists the H level at the output node of control circuit 211s. This suppresses leakage when the power supply to switch 213, which should be OFF, is turned on.

[0136] Alternatively, the auxiliary circuit 214j can replace the capacitor element C1, and be implemented by adding coupling capacitors to the lines between the control circuit 211s and the switch 213 and other lines. For example, such a configuration can be achieved by arranging the lines between the control circuit 211s and the switch 213 parallel to other lines.

[0137] Alternatively, the auxiliary circuit 215j can replace the capacitor element C2, and be implemented by adding coupling capacitors to other lines in the line between the control circuit 212s and the output node OUT. For example, such a configuration can be achieved by arranging the line between the control circuit 212s and the output node OUT parallel to other lines.

[0138] (Fourth Implementation) Next, the semiconductor integrated circuit 1k of the fourth embodiment will be explained. Hereinafter, the explanation will focus on the parts that are different from the first to third embodiments.

[0139] In the first embodiment, the driving force of the control circuit 211 towards the H level is greater than the driving force towards the L level, and the driving force of the control circuit 212 towards the L level is greater than the driving force towards the H level. This is exemplified by a configuration that adjusts the threshold value of the transistor. In the fourth embodiment, the configuration that adjusts the gate width relative to the gate length of the transistor is exemplified by a configuration that adjusts the threshold value of the transistor.

[0140] In the semiconductor integrated circuit 1k, PSW21k can also be configured as shown in Figure 13. Figure 13 is a circuit diagram showing the detailed configuration of PSW21k. Figure 13 is an example of the configuration of PSW21k, but the configurations of PSW22k and PSW23k are the same as those of PSW21k.

[0141] The inverter INV1k in control circuit 211k is configured such that the ratio of the gate width to the gate length of a P-type transistor is greater than the ratio of the gate width to the gate length of an N-type transistor. Alternatively, the inverter INV1k can be configured such that the ratio of the gate width to the gate length of a single P-type transistor is greater than the ratio of the gate width to the gate length of a single N-type transistor. Alternatively, the inverter INV1k can be configured such that multiple transistors are connected in parallel at the power node TVDD and multiple transistors are connected in series at the ground node VSS.

[0142] The inverter INV1k has transistors PM111, PM112, NM111, and NM112.

[0143] Transistors PM111 and PM112 are connected in parallel between the power supply node TVDD and the output node of the inverter INV1k. Transistors NM111 and NM112 are connected in series between the output node of the inverter INV1k and the ground node VSS. The parallel connection of transistors PM111 and PM112 is an anti-phase connection compared to the series connection of transistors NM111 and NM112.

[0144] Transistors PM111 and PM112 can also be PMOS transistors. Transistors NM111 and NM112 can also be NMOS transistors.

[0145] Transistors PM111, PM112, NM111, and NM112 are gate-connected and connected to the input node IN. Transistors PM111, PM112, and NM112 are drain-connected and connected to node N1. Transistor NM112's source is connected to transistor NM111. Transistor NM111's drain is connected to transistor NM112. Transistors PM111 and PM112's sources are connected to the power node TVDD. Transistor NM111's source is connected to the ground node VSS.

[0146] In inverter INV1k, assuming all transistors are of the same size, with their gate length set to L and gate width set to W, the ratio of the gate width to the gate length of the combined transistors PM111 and PM112 is 2×W / L, which is greater than the ratio of the gate width to the gate length of the combined transistors NM111 and NM112, W / (2×L). Therefore, the driving force towards the H level can be made greater than the driving force towards the L level in control circuit 211k.

[0147] In addition, in the inverter INV1k, the number of transistors connected in parallel on the power supply node TVDD side can be more than three, and the number of transistors connected in series on the ground node VSS side can also be more than three.

[0148] The inverter INV2k in the control circuit 212k is configured such that the ratio of the gate width to the gate length of the N-type transistor is greater than that of the P-type transistor. Alternatively, the inverter INV2k can be configured such that the ratio of the gate width to the gate length of one N-type transistor is greater than that of one P-type transistor. Alternatively, the inverter INV2k can be configured such that multiple transistors are connected in series at the power node TVDD and multiple transistors are connected in parallel at the ground node VSS.

[0149] The inverter INV2k has transistors PM121, PM122, NM121, and NM122.

[0150] Transistors PM121 and PM122 are connected in series between the power supply node TVDD and the output node of the inverter INV2k. Transistors NM121 and NM122 are connected in series between the output node of the inverter INV2k and the ground node VSS. The series connection of transistors PM121 and PM122 and the parallel connection of transistors NM121 and NM122 are reverse connections.

[0151] Transistors PM121 and PM122 can also be PMOS transistors. Transistors NM121 and NM122 can also be NMOS transistors.

[0152] Transistors PM121, PM122, NM121, and NM122 are gate-connected and connected to node N1. Transistors PM122, NM121, and NM122 are drain-connected and connected to output node OUT. Transistor PM122's source is connected to transistor PM121. Transistor PM121's drain is connected to transistor PM122. Transistors NM121 and NM122's sources are respectively connected to ground node VSS. Transistor PM121's source is connected to power node TVDD.

[0153] In inverter INV2k, assuming all transistors are of the same size, with their gate length set to L and gate width set to W, the ratio of the gate width to the gate length of the combined transistors NM121 and NM122 is 2×W / L, which is greater than the ratio of the gate width to the gate length of the combined transistors PM121 and PM122, W / (2×L). Therefore, the driving force towards the L level can be made greater than the driving force towards the H level in control circuit 212k.

[0154] In addition, in the inverter INV2k, the number of transistors connected in series on the power node TVDD side can be more than three, and the number of transistors connected in parallel on the ground node VSS side can also be more than three.

[0155] Furthermore, the operation of PSW21k (or PSW22k, PSW23k) is the same as that of the first implementation mode.

[0156] As described above, in the fourth embodiment, in the semiconductor integrated circuit 1k, the PSW 21k is configured such that the driving force towards the H level in the control circuit 211k is greater than the driving force towards the L level. This suppresses leakage when the switch 213, which should be turned off, is powered on, reducing power consumption in standby mode. Therefore, the power supply to the connection point of the PSW 21k can be appropriately cut off.

[0157] Furthermore, in the fourth embodiment, in the semiconductor integrated circuit 1k, the PSW21k is configured such that the driving force towards the L level in the control circuit 212k is greater than the driving force towards the H level. This allows the signal transmitted to the secondary PSW21k to be easily suppressed at the L level, suppressing leakage caused by the influence of the preceding stage when the power supply to the switch 213, which should be turned off, is started, thus reducing power consumption in standby mode. Therefore, the power supply to the connection point can also be appropriately cut off regarding the secondary PSW21k.

[0158] Alternatively, PSW21k' can be configured such that the driving force towards the H level in control circuit 211k is greater than the driving force towards the L level, and the driving force towards the L level and the driving force towards the H level are equal in control circuit 212s. PSW21k' can also be configured as an inverter INV2s in control circuit 212s by omitting transistors PM121 and NM121, relative to the inverter INV2k shown in FIG13. In this case, since the driving force towards the H level is greater than the driving force towards the L level in control circuit 211 of PSW21k', node N1 can be easily set to the H level during power-on. This suppresses leakage during power-on when the switch 213, which should be OFF, is turned off.

[0159] Alternatively, PSW21k” can also be configured such that the driving force towards the H level and the driving force towards the L level are equal in the control circuit 211s, and the driving force towards the L level is greater than the driving force towards the H level in the control circuit 212k. PSW21k” can also be configured as the inverter INV1s of the control circuit 211s by omitting transistors PM111 and NM111 relative to the inverter INV1k shown in FIG13. In this case, since the driving force towards the L level is greater than the driving force towards the H level in the control circuit 212 of PSW21k”, the output node OUT can be easily set to the L level during power-on. This suppresses leakage caused by the influence of the front end of the switch 213, which should be turned off, during power-on.

[0160] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit and scope of the invention. These embodiments or variations thereof are included within the scope and spirit of the present invention, as well as within the scope of the claims and their equivalents.

[0161] 1: Semiconductor integrated circuits 1i: Semiconductor integrated circuits 1k: Semiconductor integrated circuits 2: Power supply circuit 2A, 2B, 2C: Power switch group 3A~3C: Circuit Blocks 4: Control Circuit 211: Control Circuit 211a: Input node 211b: Output node 211c: Power Node 211s: Control Circuit 211k: Control circuit 212k: Control circuit 212: Control Circuit 212s: Control circuit 213: Switch 213c: Control terminal 214i: Auxiliary Circuit 215i: Auxiliary Circuit 214j: Auxiliary circuit 215j: Auxiliary circuit TM1: Power terminal TM2: Control Terminal CTR: Control Signal CNTA, CNTB, CNTC: Control signals TVDD: Power supply voltage VDD_A, VDD_B, VDD_C: Power supply voltage CNTA, CNTB, CNTC: Control lines TVDD: All-Area Power Cord VDD_A: Local power line VDD_B: Local power line VDD_C: Local power line IN: Input node OUT: Output node TVDD: Power Node VDD: Power Node PM1: Transistor PM11: Transistor NM11: Transistor PM11s: Transistor PM12: Transistor NM12: Transistor NM12s: Transistor PM21: Transistor NM21: Transistor PM22: Transistor NM22: Transistor PM31: Transistor NM32: Transistor N1: Node INV1: Inverter INV2: Inverter INV1s: Inverter INV2s: Inverter INV2k: Inverter VSS: Grounding node C1: Capacitor element C2: Capacitor element Cp: ​​Parasitic capacitance

Claims

1. A semiconductor integrated circuit, characterized by comprising: a switch connected between a first power node and a second power node, which is turned off (OFF) upon receiving a first bit at a control terminal; a first control circuit having an input node and an output node connected to the control terminal of the aforementioned switch; and a second control circuit having an output node and an input node connected to the control terminal of the aforementioned switch, satisfying at least one of the following: in the aforementioned first control circuit, the driving force toward the aforementioned first bit is greater than the driving force toward the aforementioned second bit; and in the aforementioned second control circuit, the driving force toward the aforementioned second bit is greater than the driving force toward the aforementioned first bit.

2. The semiconductor integrated circuit as described in claim 1, wherein, The aforementioned semiconductor integrated circuit satisfies the following: in the aforementioned first control circuit, the driving force toward the aforementioned first level is greater than the driving force toward the aforementioned second level; the aforementioned first control circuit has a first P-type transistor and a first N-type transistor connected in reverse phase; and the threshold voltage of the aforementioned first P-type transistor is lower than the threshold voltage of the aforementioned first N-type transistor.

3. The semiconductor integrated circuit as described in claim 1, wherein, The aforementioned semiconductor integrated circuit satisfies the following: in the aforementioned second control circuit, the driving force toward the aforementioned second level is greater than the driving force toward the aforementioned first level; the aforementioned second control circuit has a second P-type transistor and a second N-type transistor connected in reverse phase; and the threshold voltage of the aforementioned second N-type transistor is lower than the threshold voltage of the aforementioned second P-type transistor.

4. The semiconductor integrated circuit as described in claim 1, wherein, The aforementioned semiconductor integrated circuit satisfies the following: in the aforementioned first control circuit, the driving force toward the aforementioned first level is greater than the driving force toward the aforementioned second level; the aforementioned first control circuit has a complex number of first P-type transistors and a complex number of first N-type transistors connected in reverse phase; the complex number of first P-type transistors are connected in parallel; and the complex number of first N-type transistors are connected in series.

5. The semiconductor integrated circuit as described in claim 1, wherein, The aforementioned semiconductor integrated circuit satisfies the following: in the aforementioned second control circuit, the driving force toward the aforementioned second level is greater than the driving force toward the aforementioned first level; the aforementioned second control circuit has a complex number of second P-type transistors and a complex number of second N-type transistors connected in reverse phase; the complex number of second N-type transistors are connected in parallel; and the complex number of second P-type transistors are connected in series.

6. A semiconductor integrated circuit, characterized by comprising: a switch connected between a first power supply node and a second power supply node, which is turned off (OFF) upon receiving a first bit at a control terminal; a first control circuit having an input node and an output node connected to the control terminal of the aforementioned switch; and a second control circuit having an output node and an input node connected to the control terminal of the aforementioned switch, further comprising at least one of the following: a first auxiliary circuit that, when the aforementioned switch is maintained in the OFF state and the first bit is input to the input node of the aforementioned first control circuit, assists the appearance of a second bit, after logical inversion of the aforementioned first bit, at the output node of the aforementioned first control circuit; and a second auxiliary circuit that, when the aforementioned switch is maintained in the OFF state and the aforementioned second bit is input to the input node of the aforementioned second control circuit, assists the appearance of the aforementioned first bit at the output node of the aforementioned second control circuit.

7. The semiconductor integrated circuit as described in claim 6, wherein, The aforementioned semiconductor integrated circuit includes the aforementioned first auxiliary circuit. The aforementioned first auxiliary circuit includes at least one of a 3P-type transistor or a 3N-type transistor, whose drain is commonly connected to the control terminal of the aforementioned switch and whose source is commonly connected to the power supply potential. The aforementioned 3P-type transistor has a gate and a back gate respectively connected to the power supply potential. The aforementioned 3N-type transistor has a gate and a back gate respectively connected to the ground potential.

8. The semiconductor integrated circuit as described in claim 6, wherein, The aforementioned semiconductor integrated circuit includes the aforementioned second auxiliary circuit. The aforementioned second auxiliary circuit has at least one of a 4P-type transistor or a 4N-type transistor, whose drain is commonly connected to the control terminal of the aforementioned switch and whose source is commonly connected to the ground potential. The aforementioned 4P-type transistor has a gate and a back gate respectively connected to the power supply potential. The aforementioned 4N-type transistor has a gate and a back gate respectively connected to the ground potential.

9. The semiconductor integrated circuit as described in claim 6, wherein, The aforementioned semiconductor integrated circuit includes the aforementioned first auxiliary circuit, which has a first capacitor element with one end connected to the control terminal of the aforementioned switch and the other end connected to the aforementioned first power supply node.

10. The semiconductor integrated circuit as described in claim 6, wherein, The aforementioned semiconductor integrated circuit includes the aforementioned second auxiliary circuit, which has a second capacitor element with one end connected to the output node of the aforementioned second control circuit and the other end connected to the aforementioned second power supply node.

Images