Semiconductor device comprising a contact structur

Abstract

This application provides a contact structure, a semiconductor device including the contact structure, and a method for manufacturing the semiconductor device. The contact structure includes a body portion and an extension portion extending downward from the body portion, and the extension portion includes a trench. The trench is recessed into a bottom surface of the extension portion, the trench is recessed toward the body portion, and the body portion is exposed.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 825,237 (i.e., priority date "September 5, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a contact structure, a semiconductor device having the contact structure, and a method for manufacturing the semiconductor device. In particular, it relates to a contact structure having an extension. Prior Technology

[0003] Semiconductor devices are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demand for computing power, the size of semiconductor devices continues to shrink. However, this shrinkage also brings increasingly frequent and impactful challenges. Therefore, while reducing complexity, challenges in improving quality, yield, performance, and reliability must still be overcome.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0005] This disclosure provides a semiconductor device including a substrate; a word line structure including a word line electrode; an impurity region including an upper portion adjacent to the word line structure and a lower portion below the upper portion; and a contact structure including a body portion on the impurity region and an extension portion below the body portion. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region, and the upper portion of the impurity region has a tapered cross-sectional profile.

[0006] Another aspect of this disclosure provides a semiconductor device including a substrate having an isolation layer disposed therein; a plurality of impurity regions disposed within an active region defined by the isolation layer; a plurality of first word line structures disposed within the isolation layer; and a plurality of second word line structures disposed within the active region.

[0007] Another aspect of this disclosure provides a semiconductor device including a substrate; a word line structure disposed within the substrate; an impurity region including an upper portion adjacent to the word line structure and a lower portion disposed below the upper portion; a bit line contact disposed within the substrate and protruding from the substrate; and a bit line disposed on the bit line contact. The word line structure includes a word line dielectric layer contacting the lower portion of the impurity region, a word line electrode disposed on the word line dielectric layer, and a word line capping layer disposed on the word line electrode. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region. The upper portion of the impurity region has a tapered cross-sectional profile.

[0008] Due to the design of the semiconductor device disclosed herein, the extension can increase the contact area of ​​the contact structure. As a result, the performance of the semiconductor device can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When referring to the drawings in conjunction with the embodiments and the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. According to an embodiment of the present disclosure, FIG1 shows a method for manufacturing a semiconductor device in the form of a flowchart. According to one embodiment of the present disclosure, Figures 2 to 10 show cross-sectional schematic diagrams of a process for manufacturing a semiconductor device. According to one embodiment of the present disclosure, FIG11 shows a top view schematic diagram of an intermediate semiconductor device. Figure 12 is a cross-sectional view along line A-A' in Figure 11. According to one embodiment of the present disclosure, FIG13 shows a top view schematic diagram of an intermediate semiconductor device. Figure 14 is a cross-sectional view along line A-A' in Figure 13. According to one embodiment of the present disclosure, FIG15 shows a top view schematic diagram of an intermediate semiconductor device. According to one embodiment of the present disclosure, Figures 16 and 17 are schematic cross-sectional views along line A-A' of Figure 15, showing the process of manufacturing a semiconductor device. According to one embodiment of the present disclosure, FIG18 shows a top view schematic diagram of an intermediate semiconductor device. Figure 19 is a cross-sectional view along line A-A' in Figure 18. According to one embodiment of the present disclosure, FIG20 shows a top view schematic diagram of an intermediate semiconductor device. Figure 21 is a cross-sectional view along line A-A' in Figure 20. According to one embodiment of the present disclosure, FIG22 shows a top view schematic diagram of an intermediate semiconductor device. According to one embodiment of the present disclosure, Figures 23 to 26 are schematic cross-sectional views along line A-A' of Figure 22, showing the process of manufacturing a semiconductor device. Figure 27 is a schematic cross-sectional view along lines B-B' and C-C' in Figure 26. According to some embodiments disclosed herein, Figures 28 and 29 show cross-sectional schematic diagrams of the body and extension of a semiconductor device. According to another embodiment of this disclosure, FIG30 shows a schematic cross-sectional view of a semiconductor device. According to various embodiments disclosed herein, FIG31 shows a schematic cross-sectional view of a semiconductor device. According to various embodiments disclosed herein, Figures 32 and 33 show cross-sectional schematic diagrams of a process for manufacturing a semiconductor device. Implementation

[0011] The following disclosure provides many different embodiments or examples to achieve different features of the provided technical content. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, when the description refers to a first feature being formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or designations may be repeated in various examples in this disclosure. This repetition is for simplification and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms such as "below," "under," "down," "above," and "above," and similar terms are used here to facilitate the description of the relationship between one element or feature shown in the diagram and one or more other elements or features. These spatially related terms are used to cover different orientations of the device in use or operation, in addition to the orientation depicted in the diagram. The instrument may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used therein can be interpreted accordingly.

[0013] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be a component or layer in between.

[0014] It should be understood that although terms such as "first," "second," etc., are used herein to describe various elements, these elements are not limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from other elements. Thus, for example, the first element, first component, or first segment discussed below may be referred to as the second element, second component, or second segment, without departing from the teachings of this disclosure.

[0015] Unless the context otherwise specifies, the terms used here, such as “same,” “equal,” “plane,” or “coplanar,” when referring to orientation, layout, location, shape, size, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure. Rather, they mean that these orientations, layouts, locations, shapes, sizes, quantities, or other measures are substantially the same within acceptable variations, for example, variations that may arise from the manufacturing process. The term “generally” may be used here to express this meaning. For example, items described as “generally the same,” “generally equal,” or “generally plane” may be exactly the same, equal, or plane, or the same, equal, or plane within acceptable variations that may arise from the manufacturing process.

[0016] In this disclosure, semiconductor devices generally refer to devices that can operate using the characteristics of semiconductors, and optoelectronic devices, light-emitting display devices, semiconductor circuits and electronic devices all fall under the category of semiconductor devices.

[0017] It should be noted that in the description disclosed herein, "above" corresponds to the direction of the Z-direction arrow, and "below" corresponds to the opposite direction of the Z-direction arrow.

[0018] According to one embodiment of the present disclosure, FIG1 shows a semiconductor device manufacturing method 10 in the form of a flowchart. According to one embodiment of the present disclosure, FIGS. 2 to 10 show cross-sectional schematic diagrams of the process for manufacturing a semiconductor device. According to one embodiment of the present disclosure, FIG11 shows a top schematic diagram of an intermediate semiconductor device. FIG12 is a cross-sectional schematic diagram along line A-A' of FIG11.

[0019] Referring to Figures 1 to 10, in step S11, a substrate 101 is provided, a plurality of word line structures 200 are formed in the substrate 101, a bottom dielectric layer 111 is formed on the substrate 101, a bit line contact 301 is formed on the substrate 101, an intermediate dielectric layer 113 and a top dielectric layer 115 are sequentially formed on the bottom dielectric layer 111, a bit line 303 is formed on the bit line contact 301, and a plurality of unit contact openings 401O are formed in the top dielectric layer 115, the intermediate dielectric layer 113 and the bottom dielectric layer 111 to expose the substrate 101.

[0020] Referring to Figure 2, substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may be formed of an elemental semiconductor such as silicon or germanium; it may be formed of a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors, or combinations thereof.

[0021] Referring to Figure 2, an isolation layer 103 can be formed within substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on substrate 101. Optical lithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide and pad nitride layers and extend into substrate 101. An insulating material can be deposited within the trenches, followed by a planarization process, such as chemical mechanical polishing, until the top surface 101TS of substrate 101 is exposed to remove excess filler material, providing a generally flat surface for subsequent process steps, and simultaneously forming isolation layer 103. For example, the insulating material can be silicon oxide or other suitable insulating materials. In some embodiments, isolation layer 103 can define an active region AA within substrate 101.

[0022] Referring to Figure 2, an impurity region 105 can be formed within the active region AA. In some embodiments, the impurity region 105 can be formed by using a planting process with P-type or N-type dopants. The impurity region 105 can serve as the source and / or drain of the semiconductor device 1A.

[0023] The term "P-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, create valence electron vacancies. Examples of P-type dopants in silicon-containing semiconductors include, but are not limited to, boron, aluminum, gallium, and indium. The term "N-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, contribute free electrons to the intrinsic semiconductor material. Examples of N-type dopants in silicon-containing materials include, but are not limited to, antimony, arsenic, and phosphorus.

[0024] Referring to Figure 2, a first masking layer 811 may be formed on the substrate 101. In some embodiments, the first masking layer 811 may be a photoresist layer and may contain a pattern of a plurality of character line structures 200.

[0025] Referring to Figure 3, a first masking layer 811 can be used as a mask to perform a trench etching process to remove a portion of the isolation layer 103 and a portion of the substrate 101, while simultaneously forming a plurality of trenches TR1 and TR2. In some embodiments, the plurality of trenches TR2 formed in the substrate 101 are shallower than the plurality of trenches TR1 formed in the isolation layer 103. After forming the plurality of trenches TR1 and TR2, the first masking layer 811 can be removed.

[0026] Referring to Figure 4, a first insulating material 611 can be compliantly formed on the substrate 101, the insulating layer 103, and in the plurality of trenches TR1, TR2. The layer of the first insulating material 611 may have a U-shaped cross-sectional profile in the plurality of trenches TR1, TR2. In some embodiments, the layer of the first insulating material 611 may have a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0027] In some embodiments, the layer of the first insulating material 611 may be formed by a thermal oxidation process. For example, the layer of the first insulating material 611 may be formed by oxidizing the surfaces of a plurality of trenches TR1, TR2. In some embodiments, the layer of the first insulating material 611 may be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating material 611 may comprise a dielectric material with a high dielectric constant, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing an inner polycrystalline silicon liner (not shown), the layer of the first insulating material 611 may be formed by radical oxidation of the inner polycrystalline silicon liner. In some embodiments, after forming an inner silicon nitride liner (not shown), the layer of the first insulating material 611 may be formed by radical oxidation of the inner silicon nitride liner.

[0028] In some embodiments, the high dielectric constant dielectric material may comprise a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. For example, in some embodiments, the high dielectric constant dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof.

[0029] Referring to Figure 4, a plurality of character line bottom conductive layers 203 can be formed respectively and correspondingly in a plurality of trenches TR1 and TR2. For example, conductive material (not shown) can be formed to fill the plurality of trenches TR1 and TR2. Subsequently, an etch-back process can be performed to partially remove the conductive material formed in the plurality of trenches TR1 and TR2, while simultaneously forming the plurality of character line bottom conductive layers 203. In some embodiments, the conductive material can be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to a vacuum level. For example, in one embodiment, the conductive material is titanium nitride, and it can be formed by chemical vapor deposition.

[0030] Referring to Figure 4, a plurality of character line top conductive layers 205 can be formed within a plurality of trenches TR1 and TR2. For example, in some embodiments, the plurality of character line top conductive layers 205 can be formed from polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the plurality of character line top conductive layers 205 can be doped with P-type or N-type dopants. In some embodiments, conductive materials, such as polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium, can be deposited within the plurality of trenches TR1 and TR2. A subsequent etch-back process can be performed to remove portions of the conductive material to form the plurality of character line top conductive layers 205. In some embodiments, dopants can be added during the deposition process of the conductive material. In some embodiments, dopants can be implanted using a placement process after the etch-back process.

[0031] Referring to Figure 4, a character line capping layer 207 can be formed to completely fill the plurality of trenches TR1, TR2. For example, in some embodiments, the character line capping layer 207 can be formed from silicon nitride, silicon oxynitride, silicon nitride oxide, or other suitable dielectric materials. For example, in some embodiments, the character line capping layer 207 can be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0032] It should be noted that, in this disclosure, silicon nitride refers to a substance containing silicon, nitrogen, and oxygen, with oxygen comprising a greater proportion than nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, with nitrogen comprising a greater proportion than oxygen.

[0033] Referring to Figure 5, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 101TS of the substrate 101 is exposed to remove excess material and provide a generally flat surface for subsequent process steps. After the planarization process, the layers of the first insulating material 611 can be converted into multiple character line dielectric layers 201 within multiple trenches TR1 and TR2, respectively and accordingly. The character line capping layer 207 can be converted into multiple segments and formed on the multiple character line top conductive layers 205, respectively and accordingly. The multiple character line dielectric layers 201, multiple character line bottom conductive layers 203, multiple character line top conductive layers 205, and multiple character line capping layers 207 together constitute multiple character line structures 200. It should be noted that although the character line structures 200 in trench TR1 and the character line structures 200 in trench TR2 differ in size, their layer composition remains the same.

[0034] Referring to Figure 6, a bottom dielectric layer 111 may be formed on substrate 101. For example, in some embodiments, the bottom dielectric layer 111 may be composed of silicon oxide, undoped silicate glass, fluorosilicate glass, borosilicate silicate glass, spin-coated low-dielectric-constant dielectric layer, chemical vapor deposition low-dielectric-constant dielectric layer, or a combination thereof. As used in this disclosure, "low-dielectric-constant" refers to a dielectric material with a dielectric constant less than that of silicon oxide. In some embodiments, the bottom dielectric layer 111 may comprise a self-planarizing material, such as spin-coated glass or spin-coated low-dielectric-constant dielectric material, such as SiLKTM. The use of a self-planarizing dielectric material eliminates the need for a subsequent planarization step. In some embodiments, the bottom dielectric layer 111 may be formed by a deposition process, including chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0035] Referring to Figure 6, a second masking layer 813 may be formed on the bottom dielectric layer 111. In some embodiments, the second masking layer 813 may be a photoresist layer and may contain a pattern of bit line contacts 301.

[0036] Referring to Figure 7, a second masking layer 813 can be used as a mask to perform a bit line contact etching process to remove a portion of the bottom dielectric layer 111 and a portion of the impurity region 105, while simultaneously forming a bit line contact opening 301O. The bit line contact opening 301O can extend into the impurity region 105 and can be located between the word line structures 200 in the trench TR2. After forming the bit line contact opening 301O, the second masking layer 813 can be removed.

[0037] Referring to Figure 8, bit line contacts 301 can be formed within bit line contact openings 301O by depositing a conductive material and performing a planarization process such as chemical mechanical polishing. For example, in some embodiments, the conductive material may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. Bit line contacts 301 may be electrically connected to impurity regions 105.

[0038] Referring to Figure 9, an intermediate dielectric layer 113 may be formed on the bottom dielectric layer 111. In some embodiments, the intermediate dielectric layer 113 may be formed of the same material as the bottom dielectric layer 111, but is not limited thereto. In some embodiments, bit lines 303 may be formed within the intermediate dielectric layer 113 and may be formed on bit line contacts 301. Bit lines 303 may be electrically coupled to impurity regions 105 via bit line contacts 301. For example, in some embodiments, bit lines 303 may be formed of tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0039] Referring to Figure 9, a top dielectric layer 115 may be formed on the intermediate dielectric layer 113. In some embodiments, the top dielectric layer 115 may be formed of the same material as the bottom dielectric layer 111, but this is not a limitation. A third masking layer 815 may be formed on the top dielectric layer 115. In some embodiments, the third masking layer 815 may be a photoresist layer and may contain a pattern of a plurality of unit contact openings 401O.

[0040] Referring to Figure 10, a third masking layer 815 can be used as a mask to perform a cell contact etching process to remove portions of the top dielectric layer 115, the intermediate dielectric layer 113, and the bottom dielectric layer 111. After performing the cell contact etching process, a plurality of cell contact openings 401O can be formed through the top dielectric layer 115, the intermediate dielectric layer 113, and the bottom dielectric layer 111.

[0041] For the sake of brevity, clarity, and ease of description, only one unit contact opening 401O will be described.

[0042] Referring to Figures 11 and 12, the third masking layer 815 is removed by an ashing process or other suitable semiconductor process. A portion of the impurity region 105 and a portion of the isolation layer 103 are exposed through the cell contact opening 401O. In some embodiments, the cell contact opening 401O may have a square cross-sectional profile in a top view. In some embodiments, the cell contact opening 401O may have a rectangular cross-sectional profile (not shown).

[0043] According to one embodiment of the present disclosure, FIG13 shows a top view of an intermediate semiconductor device. FIG14 is a cross-sectional view along line A-A' of FIG13. According to one embodiment of the present disclosure, FIG15 shows a top view of an intermediate semiconductor device. According to one embodiment of the present disclosure, FIGS16 and 17 are cross-sectional views along line A-A' of FIG15, showing the manufacturing process of the semiconductor device. According to one embodiment of the present disclosure, FIG18 shows a top view of an intermediate semiconductor device. FIG19 is a cross-sectional view along line A-A' of FIG18.

[0044] Referring to Figures 1 and 13 to 19, in step S13, a first sacrificial layer 711 and a second sacrificial layer 713 are sequentially formed to partially fill a plurality of unit contact openings 4010, and a plurality of first intermediate openings 7110 and a plurality of second intermediate openings 7130 are sequentially formed to expose the impurity region 105.

[0045] An opening adjustment process can be implemented to adjust the exposed portion within the cell contact opening 401O. In some embodiments, the opening adjustment process may include a deposition operation followed by an etching operation. The deposition operation and the subsequent etching operation can be referred to as a cycle. Multiple cycles may be performed during the opening adjustment process. During the deposition operation, a sacrificial material may be deposited to completely fill the cell contact opening 401O. The subsequent etching operation may remove a portion of the sacrificial material, leaving an intermediate opening inside the cell contact opening 401O. This effectively reduces the size of the exposed portion of the cell contact opening 401O, such that the cell contact opening 401O is only partially filled. For a visual representation of this process, see Figures 13 to 19, which show an exemplary opening adjustment process comprising two cycles.

[0046] Referring to Figures 13 and 14, during the deposition operation of the first cycle of the aperture adjustment process, a first sacrificial layer 711 may be deposited to completely fill the cell contact opening 401O. The first sacrificial layer 711 may be formed of a sacrificial material. For example, in some embodiments, the first sacrificial layer 711 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. A planarization process may be performed until the top surface of the top dielectric layer 115 is exposed to provide a generally flat surface for subsequent semiconductor processes. In some embodiments, the planarization process is optional.

[0047] In some embodiments, the sacrificial material may be a material that exhibits etch selectivity towards the top dielectric layer 115 and the impurity region 105 (or the substrate 101). For example, in some embodiments, the sacrificial material may be formed of silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, boron carbide silicon nitride, or a combination thereof. For example, in some embodiments, the sacrificial material may be formed of boron nitride, boron silicon nitride, boron phosphorus nitride, boron carbide silicon nitride, or a combination thereof.

[0048] Referring to Figures 15 and 16, during the etching operation of the first cycle of the aperture adjustment process, an etching process may be performed to remove a portion of the first sacrificial layer 711, forming a first intermediate opening 711O. The remaining first sacrificial layer 711 is primarily attached to the sidewalls of the cell contact opening 401O. At this stage, the exposed portion of the cell contact opening 401O may still contain the isolation layer 103 and the impurity region 105. In some embodiments, the first intermediate opening 711O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the first intermediate opening 711O may have a diameter (or size) D1.

[0049] Referring to Figure 17, during the deposition operation of the second cycle of the opening adjustment process, additional sacrificial material can be compliantly deposited on the top dielectric layer 115 to transform the first sacrificial layer 711 into the second sacrificial layer 713. At this stage, the substrate of the first intermediate opening 711O can be filled, and the sidewalls and bottom of the cell contact opening 401O can be completely covered.

[0050] Referring to Figures 18 and 19, during the etching operation of the second cycle of the aperture adjustment process, an etching process may be performed to remove a portion of the second sacrificial layer 713, thereby forming the second intermediate opening 713O. The remaining second sacrificial layer 713 is primarily attached to the sidewalls of the cell contact opening 401O. The remaining second sacrificial layer 713 may be thicker than the remaining first sacrificial layer 711. At this stage, the exposed portion of the cell contact opening 401O may contain only the impurity region 105. In some embodiments, the second intermediate opening 713O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the second intermediate opening 713O may have a diameter (or size) D2. The diameter D2 of the second intermediate opening 713O may be smaller than the diameter D1 of the first intermediate opening 711O.

[0051] Alternatively, in some embodiments, after the second intermediate opening 713O (not shown) is formed, the exposed portion of the cell contact opening 401O may include both the impurity region 105 and the isolation layer 103. However, after the second intermediate opening 713O is formed, the area of ​​the exposed portion within the cell contact opening 401O may be smaller than the area of ​​the exposed portion within the cell contact opening 401O after the first intermediate opening 711O is formed.

[0052] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surface of the top dielectric layer 115 is exposed to remove excess material and provide a generally flat surface for subsequent process steps. In some embodiments, the planarization process is optional.

[0053] In some embodiments, additional cycles of the aperture adjustment process may be performed until the desired intermediate aperture diameter (or size) is achieved. In other embodiments, the aperture adjustment process achieves the desired intermediate aperture diameter in only one cycle.

[0054] According to one embodiment of the present disclosure, FIG20 shows a top view of an intermediate semiconductor device. FIG21 is a cross-sectional view along line A-A' of FIG20. According to one embodiment of the present disclosure, FIG22 shows a top view of an intermediate semiconductor device. According to one embodiment of the present disclosure, FIGS23 to 26 are cross-sectional views along line A-A' of FIG22, showing the manufacturing process of the semiconductor device. FIG27 is a cross-sectional view along lines B-B' and C-C' of FIG26.

[0055] Referring to Figures 1 and 20 to 27, in step S15, a plurality of barrier layers 817 are formed within the plurality of second intermediate openings 713O, the second sacrificial layer 713 is removed, the plurality of unit contact openings 401O are deepened to form a plurality of extended unit contact openings 403E, the plurality of barrier layers 817 are removed, and a plurality of contact structures 400 are formed within the plurality of extended unit contact openings 403E.

[0056] For the sake of brevity, clarity, and ease of description, only one barrier layer 817 will be described.

[0057] Referring to Figures 20 and 21, the barrier layer 817 may completely fill the second intermediate opening 713O. In some embodiments, the top surfaces of the second sacrificial layer 713 and the barrier layer 817, as well as the top surface of the top dielectric layer 115, are substantially coplanar. In some embodiments, the barrier layer 817 may be formed of a material that is etch-selective to the second sacrificial layer 713 and the top dielectric layer 115. In some embodiments, the barrier layer 817 may be a photoresist layer.

[0058] Alternatively, in some embodiments, the top surface of the barrier layer 817 may be lower than the top surface of the second sacrificial layer 713 or the top surface of the top dielectric layer 115 (not shown).

[0059] Referring to Figures 22 and 23, the second sacrificial layer 713 can be removed. In some embodiments, the removal of the second sacrificial layer 713 can be achieved by an etching process such as a wet etching process. In some embodiments, during the wet etching process, the ratio of the etching rate of the second sacrificial layer 713 to the etching rate of the barrier layer 817 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the wet etching process, the ratio of the etching rate of the second sacrificial layer 713 to the etching rate of the top dielectric layer 115 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0060] Referring to Figure 24, an etching process such as an anisotropic dry etching process can be used to deepen the cell contact opening 401O toward the substrate 101. The anisotropic dry etching process can use a barrier layer 817 as a mask. After performing the anisotropic dry etching process, the cell contact opening 401O can be extended to form an extended cell contact opening 403E. The lower section of the extended cell contact opening 403E can surround the protrusion 101P of the impurity region 105 that is shielded by the barrier layer 817.

[0061] Referring to Figure 25, the barrier layer 817 can be removed, for example, using an ashing or etching process. In some embodiments, the top surface 101PT of the protrusion 101P and the top surface 101TS of the substrate 101 may be substantially coplanar. In some embodiments, since the protrusion 101P is consumed during the removal of the barrier layer 817, the top surface 101PT of the protrusion 101P may be slightly lower than the top surface 101TS (not shown) of the substrate 101.

[0062] Referring to Figures 26 and 27, conductive material can be deposited to completely fill the extended cell contact opening 403E. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the top dielectric layer 115 is exposed to remove excess material, providing a generally flat surface for subsequent process steps and simultaneously forming a plurality of contact structures 400. For example, in some embodiments, the conductive material may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or tantalum-magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0063] For the sake of brevity, clarity, and ease of description, only one contact structure 400 will be described.

[0064] In some embodiments, the contact structure 400 may include a body portion 401 and an extension portion 403. The extension portion 403 may be disposed within the lower section of the extended unit contact opening 403E and surround the protrusion 101P of the impurity region 105. In some embodiments, the top surface 403TS of the extension portion 403, the top surface 101PT of the protrusion 101P, and the top surface 101TS of the base 101 may be substantially coplanar. In some embodiments, the bottom surface 403BS of the extension portion 403 may be substantially flat. In some embodiments, the extension portion 403 may have a square annular cross-sectional profile when viewed from above.

[0065] The body portion 401 may be formed on the extension portion 403 and the protrusion portion 101P. In some embodiments, the body portion 401 may have a square cross-sectional profile in a top view. In some embodiments, the body portion 401 may have a rectangular cross-sectional profile (not shown) in a top view. In some embodiments, the ratio of the height H1 of the extension portion 403 to the height H2 of the contact structure 400 may be between about 0.05 and about 0.30, between about 0.1 and about 0.30, or between about 0.15 and about 0.20.

[0066] The extension 403 may extend from the body portion 401 toward the base 101. The groove 403R may be recessed into the bottom surface 403BS of the extension 403 and recessed toward the body portion 401. The groove 403R may accommodate the protrusion 101P, and the protrusion 101P may directly contact the body portion 401. In some embodiments, in a top view, the center point CP1 of the body portion 401 (shown as a crosshair) may be aligned with the center point CP2 of the groove (shown as a crosshair). The center point CP2 of the groove may be referred to as the center point CP2 of the protrusion 101P.

[0067] In the description of this disclosure, the xyz coordinate system is used, where x and y represent directions in a plane parallel to the main surface of the structure, and z represents a direction perpendicular to that plane; when one feature is aligned with another feature, these features have substantially the same (x, y) coordinates.

[0068] The contact area of ​​the contact structure 400 can be increased by using the extension portion 403. This improves the performance of the semiconductor device 1A.

[0069] According to another embodiment of this disclosure, FIG28 shows a schematic cross-sectional view of the body portion 401 and the extension portion 403 of the semiconductor device 1B.

[0070] Referring to Figure 28, semiconductor device 1B may have a structure similar to that shown in Figure 27. Components in Figure 28 that are the same as or similar to those in Figure 27 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0071] In semiconductor device 1B, the main body 401 may have a circular cross-sectional profile when viewed from above. The extension 403 may have an annular cross-sectional profile when viewed from above.

[0072] According to another embodiment of the present disclosure, FIG29 shows a schematic cross-sectional view of the body portion 401 and the extension portion 403 of the semiconductor device 1C.

[0073] Referring to Figure 29, the semiconductor device 1C may have a structure similar to that shown in Figure 27. Components in Figure 29 that are the same as or similar to those in Figure 27 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0074] In some embodiments, from a top view of the semiconductor device 1C, the center point CP1 of the body portion 401 is not aligned with the center point CP2 of the trench (or the center point CP2 of the protrusion 101P).

[0075] According to another embodiment of the present disclosure, FIG30 shows a schematic cross-sectional view of a semiconductor device 1D.

[0076] Referring to Figure 30, the semiconductor device 1D may have a structure similar to that shown in Figure 27. Components in Figure 30 that are the same as or similar to those in Figure 27 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0077] In the semiconductor device 1D, the bottom surface 403BS of the extension 403 is inclined relative to the top surface 101TS of the substrate 101. In some embodiments, the bottom surface 403BS near the character line structure 200 disposed in the trench TR2 may be higher than the bottom surface 403BS near the character line structure 200 disposed in the trench TR1.

[0078] According to various embodiments disclosed herein, FIG31 shows a schematic cross-sectional view of a semiconductor device 1E. The semiconductor device 1E in FIG31 may have a structure similar to that shown in FIG26. Elements in FIG31 that are the same as or similar to those in FIG26 are labeled with similar reference numerals, and repeated descriptions are omitted.

[0079] Referring to FIG. 31, the semiconductor device 1E may include a plurality of first word line structures 200 and a plurality of second word line structures 200' within a substrate 101, wherein the plurality of first word line structures 200 are disposed within a plurality of first trenches TR1 in an isolation layer 103, and the plurality of second word line structures 200' are disposed within a plurality of second trenches TR2 in an impurity region 105 defined by the isolation layer 103. The first word line structure 200 includes a first word line dielectric layer 201, a first word line bottom conductive layer 203, a first word line top conductive layer 205, and a first word line capping layer 207, which are the same as the word line structure 200 within the trenches TR1 in FIG. 26. The second word line structure 200' includes a second word line dielectric layer 201', a second word line bottom conductive layer 203', a second word line top conductive layer 205', and a second word line capping layer 207'. The second character line bottom conductive layer 203' and the second character line top conductive layer 205' of the second character line structure 200' are the same as the character line bottom conductive layer 203 and the character line top conductive layer 205 of the character line structure 200 in the trench TR2 in Figure 26, respectively. Compared with the character line dielectric layer 201 and the character line capping layer 207 in the trench TR2 in Figure 26, the second character line dielectric layer 201' includes two inclined top surfaces T1 and T2 that are opposite to each other, and the second character line capping layer 207' includes two conical sidewalls S1 and S2 that are opposite to each other.

[0080] Furthermore, referring to FIG31, the semiconductor device 1E further includes a plurality of impurity regions 107B and 107C disposed within the substrate 101. Each of the plurality of impurity regions 107B and 107C may include an upper portion 107B-1 / 107C-1 disposed within the top surface 101TS of the substrate 101, and a lower portion 107B-2 / 107C-2 disposed below the upper portion 107B-1 / 107C-1. In some embodiments, the top surface 107TS of the upper portions 107B-1 and 107C-1 is substantially coplanar with the top surface 101TS of the substrate 101. The upper portions 107B-1 and 107C-1 may be separated by a plurality of second character line structures 200', while the lower portions 107B-2 and 107C-2 may be connected to each other, wherein the lower portions 107B-2 and 107C-2 are the remaining portions after the impurity region 105 has been etched. The upper portion 107B-1 / 107C-1 may have two opposing conical sidewalls 107S1 and 107S2. The horizontal distance between the two conical sidewalls 107S1 and 107S2 may gradually decrease along the Z direction from the top surface 107TS of the upper portion 107B-1 and 107C-1 to the bottom surface 107BS of the upper portion 107B-1 and 107C-1. The angle α between either of the conical sidewalls S1 / S2 and the principal plane (i.e., the XY plane) of the base 101 may be between approximately 45 degrees and approximately 60 degrees. In some embodiments, the top surface 107TS of the upper portion 107B-1 and 107C-1 is substantially parallel to the principal plane (i.e., the XY plane) of the base 101. In some embodiments, the top surface 205'TS of the second character line top conductive layer 205' of the second character line structure 200' is lower than the top surface 107TS of the upper 107B-1 and 107C-1, and the upper 107B-1 / 107C-1 of the impurity region 107B / 107C has a tapered profile.

[0081] According to various embodiments disclosed herein, Figures 32 and 33 show cross-sectional schematic diagrams of the process for manufacturing the semiconductor device 1E.

[0082] Referring to Figure 32, an etching process can be performed on the intermediate structure shown in Figure 5 to remove a portion of the impurity region 105 in the substrate 101 and a portion of the word line dielectric layer 201 and a portion of the word line capping layer 207 in the trench TR2. As a result, a plurality of recesses 901, a plurality of first word line structures 200 (i.e., the word line structures 200 in the trench TR1 in Figure 5), a plurality of second word line structures 200' in the trench TR2, and the lower portions 107B-2 and 107C-2 of a plurality of impurity regions 107B and 107C (i.e., the remaining portions of the impurity region 105 after the etching process) are formed within the substrate 101. The recess 901 may have two opposing tapered sidewalls 901S1 and 901S2. The recess 901 may have a bottom surface 901BS, wherein the vertical position of the bottom surface 901BS is defined by the intersection point 901P of the tapered sidewalls 901S1 / 901S2 and the outer surface of the trench TR2. The horizontal distance between the two tapered sidewalls 901S1, 901S2 may gradually decrease along the Z direction from the top surface 101TS of the substrate 101 to the bottom surface 901BS of the recess 901. The angle α between either of the tapered sidewalls 901S1 / 901S2 and the principal plane (i.e., the XY plane) of the substrate 101 may be between approximately 45 degrees and approximately 60 degrees. In some embodiments, the etching process may be an isotropic plasma dry etching process. In some embodiments, the etching process may be a wet etching process. In some embodiments, the top surface 101TS of the substrate 101 is substantially parallel to the principal plane (i.e., the XY plane) of the substrate 101.

[0083] Referring to Figure 33, an epitaxial growth process can be implemented to fill a plurality of recesses 901 and simultaneously form the upper portions 107B-1 and 107C-1 of a plurality of impurity regions 107B and 107C. The epitaxial growth process can be chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, a planarization process such as chemical mechanical polishing can be selectively implemented to provide a generally flat surface for subsequent process steps.

[0084] The shape (or structure) of the upper portions 107B-1 and 107C-1 of the plurality of impurity regions 107B and 107C can be determined by the plurality of recesses 901. The upper portion 107B-1 may be located between two second character line structures 200'. In some embodiments, the upper portion 107C-1 may be located on opposite sides of the upper portion 107B-1, with the two character line structures 200' interposed between them. In other words, the upper portions 107B-1 and 107C-1 may be separated by the second character line structures 200'. In some embodiments, the upper portions 107B-1 and 107C-1 may have a top surface 107TS that is substantially coplanar with the top surface 101TS of the substrate 101, and a bottom surface 107BS that is substantially coplanar with the bottom surface 901BS of the recess 901.

[0085] For example, in some embodiments, the upper parts 107B-1 and 107C-1 may be made of silicon phosphide (SiP), phosphorus-doped silicon carbide (SiCP), silicon carbide (SiC), silicon germanium (SiGe), silicon germanium tin alloy (SiGeSn), silicon germanium boron alloy (SiGeB), or other suitable semiconductor materials.

[0086] In some embodiments, the upper 107B-1 / 107C-1 may be doped with a dopant such as phosphorus or boron. The dopant concentration of the upper 107B-1 / 107C-1 may be uniform. In some embodiments, the dopant concentration of the upper 107B-1 / 107C-1 may gradually increase from the bottom surface 107BS to the top surface 107TS. In some embodiments, the dopant concentration of the upper 107B-1 and 107C-1 may be greater than the dopant concentration of the lower 107B-2 and 107C-2.

[0087] The top surface 205'TS of the second character line top conductive layer 205' of the second character line structure 200' is lower than the top surface 107TS of the upper 107B-1 and 107C-1 of the impurity regions 107B and 107C, and the impurity regions 107B / 107C have a tapered cross-sectional profile. In some embodiments, the vertical position of the top surface 205'TS of the second character line top conductive layer 205' may be higher than the vertical position of the bottom surface 107BS of the upper 107B-1 and 107C-1. In some embodiments, the top surface 205'TS of the second character line top conductive layer 205' and the bottom surface 107BS of the upper 107B-1 and 107C-1 may be at the same vertical position.

[0088] This disclosure provides a semiconductor device including a substrate; a word line structure including a word line electrode; an impurity region including an upper portion adjacent to the word line structure and a lower portion below the upper portion; and a contact structure including a body portion on the impurity region and an extension portion below the body portion. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region, and the upper portion of the impurity region has a tapered cross-sectional profile.

[0089] Another aspect of this disclosure provides a semiconductor device including a substrate having an isolation layer disposed therein; a plurality of impurity regions disposed within an active region defined by the isolation layer; a plurality of first word line structures disposed within the isolation layer; and a plurality of second word line structures disposed within the active region.

[0090] Another aspect of this disclosure provides a semiconductor device including a substrate; a word line structure disposed within the substrate; an impurity region including an upper portion adjacent to the word line structure and a lower portion disposed below the upper portion; a bit line contact disposed within the substrate and protruding from the substrate; and a bit line disposed on the bit line contact. The word line structure includes a word line dielectric layer contacting the lower portion of the impurity region, a word line electrode disposed on the word line dielectric layer, and a word line capping layer disposed on the word line electrode. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region. The upper portion of the impurity region has a tapered cross-sectional profile.

[0091] Due to the design of the semiconductor device disclosed herein, the extension can increase the contact area between the contact structure and the impurity region. Therefore, the performance of the semiconductor device 1A can be improved.

[0092] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0093] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0094] 1A: Semiconductor Device 1B: Semiconductor Devices 1C: Semiconductor Device 1D: Semiconductor Device 1E: Semiconductor Devices 10: Method 101: Base 101P: Protrusion 101PT: Top Surface 101TS: Top surface 103: Isolation layer 105: Impurity Zone 107B: Impurity Region 107B-1: Upper part 107B-2: Lower part 107BS: Bottom 107C: Impurity Region 107C-1: Upper part 107C-2: Lower part 107TS: Top surface 107S1: Sidewall 107S2: Sidewall 111: Bottom Dielectric Layer 113: Intermediate dielectric layer 115: Top Dielectric Layer 200: Character Line Structure 200': Character line structure 201: Character line dielectric layer 201': Character line dielectric layer 203: Conductive layer at the bottom of the character line 203': Bottom conductive layer of character line 205: Top conductive layer of character line 205': Top conductive layer of character line 205'TS: Top surface 207: Character Line Cover Layer 207': Character line capping 301: Bit line contact 301O: Bit line contact opening 303: Bitline 400: Contact Structure 401: Ontology Department 401O: Unit contact opening 403: Extension Section 403BS: Bottom surface 403E: Extended unit contact opening 403R: Groove 403TS: Top surface 611: First insulating material 711: First Sacrifice Layer 711O: First middle opening 713: Second Sacrificial Layer 713O: Second middle opening 811: First masking layer 813: Second masking layer 815: Third masking layer 817: Barrier Layer 901: Depression 901BS: Bottom 901P: Intersection 901S1: Sidewall 901S2: Sidewall AA: Active Zone CP1: Center point CP2: Center point D1: Diameter D2: Diameter H1: Height H2: Height S1: Sidewall S2: Sidewall S11: Steps S13: Steps S15: Steps T1: Top surface T2: Top surface TR1: Trench TR2: Trench Z: Direction α: Angle

Claims

1. A semiconductor device, comprising: One base; A character line structure includes a character line electrode; an impurity region including an upper portion adjacent to the character line structure and a lower portion below the upper portion; and a contact structure including a body portion on the impurity region and an extension portion below the body portion, wherein a top surface of the character line electrode of the character line structure is lower than a top surface of the upper portion of the impurity region, and the upper portion of the impurity region has a tapered profile.

2. The semiconductor device as claimed in claim 1, wherein the top surface of the upper portion is substantially coplanar with a top surface of the substrate.

3. The semiconductor device as claimed in claim 2, wherein the impurity region includes two conical sidewalls connected to the top surface of the upper portion of the impurity region.

4. The semiconductor device as claimed in claim 3, wherein the angle between one of the two conical sidewalls and the top surface of the upper portion of the impurity region is between about 45 degrees and about 60 degrees.

5. The semiconductor device as claimed in claim 1, wherein the dopant concentration of the upper portion is greater than the dopant concentration of the lower portion.

6. The semiconductor device as claimed in claim 5, wherein the dopant concentration of the upper portion gradually increases from a bottom surface of the upper portion to a top surface of the upper portion.

7. The semiconductor device as claimed in claim 1, wherein the word line structure further includes a word line dielectric layer contacting the lower portion of the impurity region, and a word line capping layer disposed on the word line electrode.

8. The semiconductor device as claimed in claim 7, wherein the character line dielectric layer includes two tilted top surfaces facing each other.

9. The semiconductor device as claimed in claim 7, wherein the character line capping layer includes two tapered sidewalls opposite to each other.

10. The semiconductor device as claimed in claim 7, wherein a character line electrode surrounded by the character line dielectric layer is disposed on the character line dielectric layer.

11. The semiconductor device as claimed in claim 10, wherein the word line electrode includes a top word line conductive layer and a bottom word line conductive layer below the top word line conductive layer.

12. The semiconductor device of claim 1, wherein the extension of the contact structure extends from the body portion, and the extension of the contact structure includes a trench, wherein the trench is recessed into a bottom surface of the extension, the trench is recessed toward the body portion, and the body portion is exposed.

13. The semiconductor device as claimed in claim 1, wherein the ratio between a height of the extension and a height of the contact structure is between about 0.05 and about 0.

3.

14. The semiconductor device as claimed in claim 12, wherein the body portion has a square cross-sectional profile in a top view.

15. The semiconductor device as claimed in claim 12, wherein, in a top view, the extension has an annular cross-sectional profile.

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