Memory circuits, voltage provision circuits and methods for operating the same

Abstract

This disclosure provides a memory circuit including a memory array and a voltage supply circuit. The memory array includes a plurality of memory cells. The voltage supply circuit provides an operating voltage to one or more of the plurality of memory cells, the operating voltage being shifted from a first voltage domain to a second voltage domain. The voltage supply circuit includes a voltage detector for receiving a first supply voltage in the first voltage domain, powered by a second supply voltage in the second voltage domain, and providing a first control signal. The first control signal is used to determine whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

Description

Technical Field

[0001] This disclosure relates to a memory circuit, a voltage supply circuit, and a method of operation thereof. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). The improvement in integrated density is mainly due to the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. Summary of the Invention

[0003] This disclosure provides a memory circuit including a memory array and a voltage supply circuit. The memory array includes a plurality of memory cells. The voltage supply circuit provides an operating voltage to one or more of the plurality of memory cells, the operation of which is shifted from a first voltage domain to a second voltage domain. The voltage supply circuit includes a voltage detector for receiving a first supply voltage in the first voltage domain, powered by a second supply voltage in the second voltage domain, and providing a first control signal. The first control signal is used to determine whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

[0004] This disclosure provides a voltage supply circuit including a voltage detector, a logic gate, and a first n-type transistor. The voltage detector is powered by a first supply voltage in a first voltage domain and is used to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is higher than the second supply voltage in a logic high state. The logic gate is used to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the first voltage domain. The first n-type transistor has a gate terminal for receiving the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to ground. When the first supply voltage is in a logic high state and the second supply voltage is in a logic low state, the second control signal is output in a logic low state via the logic gate.

[0005] This disclosure provides an operational method for providing an operating voltage to a memory circuit, comprising the following steps: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different from the second voltage domain; after identifying a memory circuit configured in a first operating mode, providing an operating voltage equal to the second supply voltage having a first logic state; after identifying a memory circuit configured in a second operating mode, providing an operating voltage equal to the second supply voltage having a second logic state; and after identifying a memory circuit configured in a third operating mode, providing an operating voltage equal to the second supply voltage having a first logic state. In the first operating mode, the first supply voltage and the second supply voltage each have a second logic state; in the second operating mode, the first supply voltage and the second supply voltage each have a second logic state; and in the third operating mode, the first supply voltage and the second supply voltage each have a first logic state and a second logic state, respectively. Simple Explanation of the Diagram

[0006] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation. Figure 1 illustrates an exemplary block diagram of a memory circuit according to some embodiments; Figure 2 illustrates an exemplary schematic diagram of a memory cell of the memory circuit of Figure 1 according to some embodiments; Figure 3 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 4 illustrates an exemplary circuit diagram of a voltage detector included in the voltage supply circuit of Figure 3 according to some embodiments; Figure 5 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 6 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 7 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 8 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 9 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 10 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; Figure 11 illustrates an exemplary circuit diagram of a voltage supply circuit coupled to or integrated with the memory circuitry of Figure 1, according to some embodiments; and Figure 12 illustrates an exemplary flowchart of a method for providing an operating voltage to a memory circuit according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, this document uses spatially relative terms (such as "below," "below," "lower," "above," "upper," "top," "bottom," and similar) to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein can be interpreted similarly.

[0009] As we move faster and faster toward next-generation technology nodes, system input / output (I / O) requirements typically involve transmitting signals between integrated circuit chips and components with large capacitances, such as connections associated with printed circuit board traces and cables. These connections require greater drive power and voltage than the communication occurring within the integrated circuit chip. I / O devices interface faster, smaller signals from the main chip to these other, higher-capacitance components, and typically transmit signals at higher voltages. As a non-limiting example, memory circuits (e.g., fuse memory circuits or other one-time programmable (OTP) memory circuits) often rely on I / O circuits to provide high voltages for the operation of the memory circuits (e.g., programming, erasing, etc.).

[0010] A voltage supply circuit is one of many such I / O circuits operatively coupled to a memory circuit and capable of providing a desired operating voltage (e.g., a relatively high operating voltage). Such a voltage supply circuit typically includes a level shifter that shifts the level of the supply voltage from one voltage domain to another. For example, when the memory cells of the memory circuit are configured in programmable mode, the voltage supply circuit typically provides the memory cells with an operating voltage shifted from a first (e.g., lower) voltage domain to a second (e.g., higher) voltage domain. The voltage supply circuit can receive a first supply voltage and a second supply voltage, both of which are logic high but located in the first and second voltage domains respectively, and provides the memory cells with an operating (e.g., programmable) voltage equal to the second supply voltage in the logic high state.

[0011] However, in some situations, the first supply voltage may be incorrectly provided in a logic low state, while the second supply voltage is provided in a logic high state. Therefore, existing voltage supply circuitry may provide an operating voltage equal to the same second supply voltage in a logic high state, causing memory circuitry malfunction. For example, if the first supply voltage is in a logic low state, various circuit elements powered by the first supply voltage (e.g., control circuitry) may fail to function properly. By providing a high operating voltage to the memory cells when these control circuits are malfunctioning, the memory cells may be incorrectly programmed. Therefore, existing voltage supply circuitry for memory circuitry is not entirely satisfactory in certain scenarios.

[0012] This disclosure provides various embodiments of a voltage supply circuit operatively coupled to a memory array, for example, providing an operating voltage to the memory array based on a configured operating mode of the memory array. In some embodiments, the voltage supply circuit may include a voltage sensor for receiving a first supply voltage and being powered by a second supply voltage. When the first supply voltage is detected to be provided in a logic low state and the second supply voltage is provided in a logic high state, the voltage sensor may provide a control signal to a logic gate (e.g., a NOR gate) of the voltage supply circuit to force the output stage of the voltage supply circuit to provide an operating voltage (e.g., ground voltage) equal to the second supply voltage in a logic low state. Therefore, even if the first / second supply voltage has an erroneous logic state, as disclosed herein, the voltage supply circuit can force the operating voltage down to ground voltage, thereby preventing further failure of the coupled memory array.

[0013] Figure 1 illustrates a memory circuit 100 according to various embodiments. In the embodiment illustrated in Figure 1, the memory circuit 100 includes a memory array 102, a column decoder 104, a row decoder 106, input / output (I / O) circuitry 108, and logic control circuitry 110. Although not shown in Figure 1, the elements of the memory circuit 100 may be operatively coupled to each other and to the logic control circuitry 110. While in the embodiment illustrated in Figure 1, the individual elements are depicted as separate blocks for clarity, in some other embodiments, some or all of the elements depicted in Figure 1 may be integrated together. For example, the I / O circuitry 108 may be embedded (or integrated) within the memory array 102.

[0014] Memory array 102 is a hardware element for storing data. In one embodiment, memory array 102 is embodied as a semiconductor memory device. Memory array 102 includes a plurality of memory cells (or other storage cells) 103. Memory array 102 includes a plurality of columns R1~RM each extending in a first direction (e.g., the X direction) and a plurality of rows C1~CN each extending in a second direction (e.g., the Y direction). Each column / row may include one or more conductive structures. In some embodiments, each memory cell 103 is configured at the intersection of a corresponding column and a corresponding row and is operable according to the voltage or current passing through the individual conductive structures of the column and row.

[0015] According to various embodiments of this disclosure, each memory cell 103 can be implemented as a one-time-programmable (OTP) memory cell. For example, memory cell 103 can be a fuse cell, comprising at least a series-coupled fuse resistor and a transistor. However, it should be understood that memory cell 103 can be implemented as any of various other memory configurations, such as a static random access memory (SRAM) cell, a phase-change random access memory (PCRAM) cell, a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, or the like, while remaining within the scope of this disclosure. A detailed description of a memory cell 103 configured as a fuse cell will be described below with reference to Figure 2.

[0016] Column decoder 104 is a hardware element that receives column addresses of memory array 102 and asserts conductive structures (e.g., word lines) at those column addresses. Row decoder 106 is a hardware element that receives row addresses of memory array 102 and asserts one or more conductive structures (e.g., bit lines, source lines) at those row addresses. I / O circuitry 108 is a hardware element that can access (e.g., read, program) each memory cell 103 asserted via column decoder 104 and row decoder 106. Logic control circuitry 110 is a hardware element that can control coupled elements (e.g., memory array 102, column decoder 104, row decoder 106, I / O circuitry 108).

[0017] Figure 2 illustrates an exemplary configuration (hereinafter referred to as "fuse unit 103") of a memory unit 103 (Figure 1) configured as a fuse unit according to some embodiments. The fuse unit 103 is implemented as a 1T1R configuration, for example, a fuse resistor 202 connected in series to the access transistor 204. However, it should be understood that any other fuse configuration exhibiting fuse characteristics may be used by the fuse unit 103, such as a 2-diode-1-resistor (2D1R) configuration, a many-transistors-one-resistor (many-T1R) configuration, etc., while remaining within the scope of this disclosure.

[0018] The fuse resistor 202 is formed of one or more metal structures. For example, the fuse resistor 202 may be one of multiple interconnect structures in one of multiple metallization layers disposed above the access transistor 204. The access transistor 204 may be formed above the main surface of the semiconductor substrate; this configuration is sometimes referred to as part of the front-end-of-line (FEOL) process. During the FEOL process, multiple metallization layers are typically formed, each of which contains multiple interconnect (e.g., metal) structures; this configuration is sometimes referred to as part of the back-end-of-line (BEOL) process.

[0019] When the fuse resistor 202 (of fuse unit 103) is a metallic structure, it may exhibit, for example, an initial resistance value (or resistivity) at the time of manufacture. To program the fuse unit 103, the access transistor 204 (if embodied as an n-type transistor) is turned on by applying a signal corresponding to a logic high state (e.g., voltage) to the gate terminals of the access transistor 204 via a word line (WL). Simultaneously or subsequently, a sufficiently high voltage (e.g., a programming voltage) is applied via a bit line (BL) to one of the terminals of the fuse resistor 202. When access transistor 204 is turned on to provide (e.g., programmable) a path from BL through fuse resistor 202 and access transistor 204 to the source line (SL), such a high voltage signal can burn out a portion of the corresponding metal structure (fuse resistor 202), thereby changing fuse resistor 202 from a first state (e.g., short-circuited) to a second state (e.g., open-circuited). Therefore, the fuse unit 103 can irreversibly change from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1), which can be read by applying a relatively low voltage signal to BL and turning on access transistor 204 to provide (e.g., read) a path. In various embodiments of this disclosure, such a high programmable voltage shifted upward from the first voltage domain to the second voltage domain can be provided by the voltage supply circuitry of I / O circuitry 108, which will be discussed in further detail below.

[0020] Figure 3 illustrates an exemplary circuit diagram of a voltage supply circuit 300 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 300 provides an operating voltage VDDQ for a programmable fuse unit 103. The operation of the voltage supply circuit 300 can be shifted from a first voltage domain to a second voltage domain. The first voltage domain is within a range between a ground voltage and a first supply voltage VDD; and the second voltage domain is within a range between a ground voltage and a second supply voltage VQPS. The first supply voltage VDD is equal to 0 V when provided in a logic low state and is equal to approximately 0.75 V when provided in a logic high state; while the second supply voltage VQPS is equal to 0 V when provided in a logic low state and is equal to approximately 1.8 V when provided in a logic high state.

[0021] In some embodiments, the voltage supply circuit 300 may include a voltage detector (e.g., voltage detector 301 in Figure 4) for detecting whether a first supply voltage VDD has been correctly supplied. If the voltage detector identifies that the first supply voltage VDD is supplied in a logic low state and the second supply voltage VQPS is supplied in a logic high state (e.g., 0 V and 1.8 V, respectively), then the voltage detector 301 may provide a control signal to the logic gate of the voltage supply circuit 300 to forcibly pull the operating voltage VDDQ to 0 V. Details of the voltage detector 301 will be discussed below.

[0022] Referring first to Figure 3, the voltage supply circuit 300 includes an inverter 302, a NAND gate 304, an inverter 306, a level shifter 308, an inverter 310, a NOR gate 312, an inverter 314, a pull-up transistor 316, a pull-down transistor 318, and a voltage detector 301. In some embodiments, the inverter 302, NAND gate 304, and inverter 306 can operate in a first voltage domain (e.g., between 0 V and 0.75 V); and the inverter 310, NOR gate 312, inverter 314, pull-up transistor 316, pull-down transistor 318, and voltage detector 301 can operate in a second voltage domain (e.g., between 0 V and 1.8 V).

[0023] Inverter 302 can receive a control signal PD (e.g., via a first control pin) and provide the inverted control signal PD to one input of NAND gate 304. NAND gate 304 can receive another control signal PS (e.g., via a second control pin) and perform a NAND operation on the inverted control signal PD and the control signal PS to provide signal 305. In some embodiments, when the coupled fuse unit 103 is configured in read mode, both control signals PD and PS are in a logic low state (i.e., PD=0 and PS=0); and when the coupled fuse unit 103 is configured in program mode, control signals PD and PS are in a logic low state and a logic high state (i.e., PD=0 and PS=1), respectively. The control signals PD and PS, having individual logic states, can be provided in a first voltage domain. For example, when configured to a logic high state, the control signal PD / PS is provided at 0.75 V; and when configured to a logic low state, the control signal PD / PS is provided at 0 V.

[0024] Inverter 306 provides signal 307 to level shifter 308 by inverting signal 305, which has undergone logic NAND operation. Level shifter 308 shifts signal 307 (e.g., its voltage is 0 V when it is logic low, or its voltage is 0.75 V when it is logic high) to provide signal 309 (e.g., its voltage is 0 V when it is logic low, or its voltage is 1.8 V when it is logic high). For example, when signal 307 is received by level shifter 308 in a logic high state, level shifter 308 can provide signal 309 with a logic high state, where signal 307 and signal 309 are approximately 0.75 V and 1.8 V, respectively. Inverter 310 provides signal 311 to one input of NOR gate 312 by inverting signal 309. NOR gate 312 can receive another input signal (e.g., control signal VDD_OK) and perform a logic NOR operation on signal 311 and control signal VDD_OK to provide control signal DIS. Inverter 314 can provide signal 315 by inverting control signal DIS. The gate terminal of pull-up transistor 316 can receive signal 315, and the gate terminal of pull-down transistor 318 can receive signal 315. In addition, the source terminal of pull-up transistor 316 (which may be implemented as a p-type transistor) can be connected to a second supply voltage VQPS, and the source terminal of pull-down transistor 318 (which may be implemented as an n-type transistor) can be connected to ground voltage, wherein the respective drain terminals of pull-up transistor 316 and pull-down transistor 318 are connected to each other at the output node to provide operating voltage VDDQ.

[0025] Referring next to Figure 4, which illustrates an exemplary circuit diagram of a voltage detector 301 according to some embodiments, the voltage detector 301 includes an inverter 405 formed by a pull-up transistor 410, a pull-down transistor 420, a transistor 430, and a Schmitt trigger 440. The pull-up transistor 410 and the pull-down transistor 420 may be implemented as p-type and n-type transistors, respectively. The source terminal of the pull-up transistor 410 may be connected to a second supply voltage VQPS, and the source terminal of the pull-down transistor 420 may be connected to ground. The respective gate terminals of the pull-up transistor 410 and the pull-down transistor 420 are connected to each other to operably serve as inputs to the inverter 405, and the respective drain terminals of the pull-up transistor 410 and the pull-down transistor 420 are connected to each other to operably serve as outputs to the inverter 405. The input of inverter 405 receives the first supply voltage VDD and is coupled to ground via a transistor 430 gated by the control signal DIS. The output of inverter 405 is connected to the input of a Schmitt trigger 440, which is operatively configured as a power noise filter. The Schmitt trigger 440 provides the control signal VDD_OK by filtering the logic-inverted first supply voltage VDD. For example, the control signal VDD_OK may be in a logic high state when the first supply voltage VDD and the second supply voltage VQPS are in logic low and logic high states, respectively.

[0026] In operation, the voltage supply circuit 300 provides an operating voltage VDDQ equal to the second supply voltage VQPS (e.g., approximately 1.8 V) when the coupled memory cell 103 is being programmed; and provides an operating voltage VDDQ equal to the second supply voltage VQPS (e.g., approximately 0 V) ​​when the coupled memory cell 103 is being read. Furthermore, in read mode, both the first supply voltage VDD and the second supply voltage VQPS are in a logic high state (i.e., VDD=1 and VQPS=1), and both the control signal PD and the control signal PS are in a logic low state (i.e., PD=0 and PS=0). Therefore, the signal 307 input to the level shifter 308 is in a logic low state, and the signal 309 output from the level shifter 308 is also in a logic low state. Next, the NOR gate 312 can output a control signal DIS in a logic low state, causing the pull-up transistor 316 and pull-down transistor 318, which are operable as inverters, to output an operating voltage VDDQ equal to approximately 0 V. In program mode, the control signals PD and PS are in logic low and logic high states respectively (i.e., PD=0 and PS=1). Therefore, the signal 307 input to the level shifter 308 is in a logic high state, and the signal 309 output from the level shifter 308 is also in a logic high state. Next, the NOR gate 312 can output a control signal DIS in a logic high state, causing the pull-up transistor 316 and pull-down transistor 318, which are operable as inverters, to output an operating voltage VDDQ equal to approximately 1.8 V.

[0027] In some scenarios, the first supply voltage VDD and the second supply voltage VQPS may (e.g., incorrectly) be in logic low and logic high states respectively (i.e., VDD=0 and VQPS=1), while the control signals PD and PS can be in any arbitrary logic combination. When VDD=0, the inverter 405 of the voltage detector 301 can output a logic high control signal VDD_OK by inverting the first supply voltage VDD. Therefore, the NOR gate 312 can then output a logic low control signal DIS, regardless of the logic combination of the control signals PD and PS. Thus, the pull-up transistor 316 and pull-down transistor 318, which are operable as inverters, can output an operating voltage VDDQ equal to approximately 0 V.

[0028] Table 1 below summarizes the various combinations of the logic states of the first supply voltage VDD, the second supply voltage VQPS, the operating voltage VDDQ, the control signal VDD_OK, and the control signal DIS. For example, when the operating voltage VDDQ is in a logic low state, the operating voltage VDDQ is equal to the second supply voltage VQPS in a logic high state (e.g., approximately 1.8 V); and when the operating voltage VDDQ is in a logic low state, the operating voltage VDDQ is equal to the second supply voltage VQPS in a logic low state (e.g., approximately 0 V). VDD VQPS VDDQ VDD_OK DIS 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 Table 1.

[0029] Figure 5 illustrates an exemplary circuit diagram of a voltage supply circuit 500 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 500 provides an operating voltage VDDQ for the programmed fuse unit 103. Similar to voltage supply circuit 300 (Figure 3), the operation of voltage supply circuit 500 can be shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V), the difference being that voltage supply circuit 500 can arrange its elements (e.g., transistors) in a stacked structure to reduce the voltage drop between any terminals of each transistor. Therefore, the following discussion of voltage supply circuit 500 will focus on its differences.

[0030] Compared to voltage supply circuit 300 (Figure 3), voltage supply circuit 500 also includes elements 501, 502, 504, 506, 508, 510, and 512, which are similar to elements 301, 302, 304, 306, 308, 310, and 312, respectively, except for the following differences. For example, element 508 (e.g., a level shifter) is used to shift a first voltage domain in the range of 0 V to a first supply voltage VDD (e.g., about 0.75 V) to another (third) voltage domain in the range of 0 V to a mid-range supply voltage MVDD (e.g., about 0.9 V). In such embodiments, the mid-range supply voltage MVDD may be configured as 1 / 2 × VQPS. In another example, element 510 (e.g., an inverter), element 512 (e.g., a NOR gate), and element 501 (e.g., a voltage sensor) operate at the mid-range supply voltage MVDD. In other words, the inverter 510, the NOR gate 512, and the voltage detector 501 can operate in a third voltage range from 0 V to approximately 0.9 V.

[0031] For example, a voltage detector 501, which may include the elements shown in Figure 4, may couple its inverter between the mid-range supply voltage MVDD and the ground voltage. Therefore, the voltage detector 501 may receive a first supply voltage VDD in a first voltage domain (from 0 V to about 0.75 V) and output a control signal VDD_OK in a third voltage domain (from 0 V to about 0.9 V). For example, the voltage detector 501 may output a logic high control signal VDD_OK (e.g., about 0.9 V) when it detects that the first supply voltage VDD is in a logic low state and the mid-range supply voltage MVDD is in a logic high state.

[0032] The voltage supply circuit 500 may further include inverters 514, 516, and 518; a level shifter 520; inverters 522, 524, 526, and 528; a first pull-up transistor 530; a second pull-up transistor 532; a first pull-down transistor 534; and a second pull-down transistor 536. In some embodiments, inverters 514, 516, and 518 may operate in a third voltage domain. Inverter 514 may provide a control signal psvqb by inverting the control signal DIS provided by the NOR gate 512. Inverter 516 may provide signal 517 by inverting the control signal psvqb. Inverter 518 may provide signal 519 by inverting signal 517. As discussed above regarding voltage detector 301 (Figures 3 to 4), NOR gate 512 can receive the control signal VDD_OK, which is in a logic high state, when it detects that the first supply voltage VDD is in a logic low state and the intermediate supply voltage MVDD is in a logic high state.

[0033] Level shifter 520 can shift a third voltage domain in the range of 0 V to the mid-range supply voltage MVDD (approximately 0.9 V) to another (fourth) voltage domain in the range of the mid-range supply voltage MVDD (approximately 0.9 V) to the second supply voltage VQPS (approximately 1.8 V). For example, level shifter 520 can shift the control signal psvqb (e.g., between 0 V and approximately 0.9 V) and provide signal 521 (e.g., between approximately 0.9 V and approximately 1.8 V). Inverter 522 can provide signal 523 by inverting signal 521. Inverter 524 can provide signal 525 by inverting signal 523. Inverter 526 can provide signal 527 by inverting signal 525. Inverter 528 can provide signal 529 by inverting signal 527. Therefore, when the control signal psvqb is in a logic high state (e.g., about 0.9 V), the signal 529 can be in a logic high state (e.g., about 1.8 V).

[0034] The gate of the first pull-up transistor 530 can receive signal 529, the gate of the second pull-up transistor 532 can receive the intermediate supply voltage MVDD, the gate of the first pull-down transistor 534 can receive the intermediate supply voltage MVDD, and the gate of the second pull-down transistor 536 can receive signal 519. Furthermore, the source of the first pull-up transistor 530 (which may be a p-type transistor) can be connected to the second supply voltage VQPS, and its drain is connected to the source of the second pull-up transistor 532 (which may be a p-type transistor). The source of the second pull-down transistor 536 (which may be an n-type transistor) can be connected to ground, and its drain is connected to the source of the first pull-down transistor 534 (which may be an n-type transistor). The respective drains of the second pull-up transistor 532 and the first pull-down transistor 534 are connected to each other at the output node to provide the operating voltage VDDQ.

[0035] Figure 6 illustrates an exemplary circuit diagram of a voltage supply circuit 600 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 600 provides an operating voltage VDDQ for the programmable fuse unit 103. The voltage supply circuit 600 is substantially similar to the voltage supply circuit 500 (Figure 5), both providing an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V) via a stacked structure. The difference is that the voltage sensor (e.g., voltage sensor 601) of the voltage supply circuit 600 can be powered by another intermediate supply voltage HVDD. In such embodiments, the intermediate supply voltage HVDD can be configured as 2 / 3 × VQPS, while the intermediate supply voltage MVDD remains configured as 1 / 2 × VQPS. For brevity, the following discussion of the voltage supply circuit 600 will focus on its differences.

[0036] Compared to voltage supply circuit 500 (Figure 5), voltage supply circuit 600 also includes components 601, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, 634 and 636, which are similar to components 501, 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534 and 536, respectively. The difference is that voltage detector 601, which may include the components shown in Figure 4, can couple its inverter between the mid-range supply voltage HVDD (e.g., about 1.2 V) and the ground voltage. Therefore, voltage detector 601 can receive a first supply voltage VDD in a first voltage domain (from 0 V to about 0.75 V) and output a control signal VDD_OK in another voltage domain (from 0 V to about 1.2 V). For example, voltage detector 601 can output a control signal VDD_OK (e.g., about 1.2 V) in a logic high state when it detects that the first supply voltage VDD is in a logic low state and the intermediate supply voltage HVDD is in a logic high state.

[0037] Figure 7 illustrates an exemplary circuit diagram of a voltage supply circuit 700 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 700 provides an operating voltage VDDQ for the programmable fuse unit 103. The voltage supply circuit 700 is substantially similar to the voltage supply circuit 600 (Figure 6), both of which provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V) via a stacked structure. The difference is that the voltage supply circuit 700 may have fewer pull-up transistors and fewer pull-down transistors at its output stage. Therefore, the following discussion of the voltage supply circuit 700 will focus on these differences.

[0038] Compared to voltage supply circuit 600 (Figure 6), voltage supply circuit 700 also includes components 701, 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, 726, 728, 730, and 732, which are similar to components 601, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, and 636, respectively. It should be noted that voltage supply circuit 700 includes a pull-up transistor 730 and a pull-down transistor 732 at its output stage. These transistors are connected to each other via their drain terminals to provide the operating voltage VDDQ.

[0039] Figure 8 illustrates an exemplary circuit diagram of a voltage supply circuit 800 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 800 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 800 is substantially similar to the voltage supply circuit 500 (Figure 5), both providing an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V) via a stacked structure. The difference is that the components of the voltage supply circuit 800 can be powered by separate intermediate supply voltages LVDD and HVDD. Generally, the second supply voltage VQPS is higher than the intermediate supply voltage HVDD, which is higher than the intermediate supply voltage LVDD, which is higher than ground. For example, the intermediate supply voltage LVDD can be configured as 1 / 3 × VQPS, and the intermediate supply voltage HVDD can be configured as 2 / 3 × VQPS. For the sake of brevity, the following discussion of the voltage supply circuit 800 will focus on its differences.

[0040] Compared to voltage supply circuit 500 (Figure 5), voltage supply circuit 800 also includes elements 801, 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, and 828, which are similar to elements 501, 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, and 528, respectively, except for the following differences. For example, a voltage detector 801, which may include the elements shown in Figure 4, may couple its inverter between a first intermediate-range supply voltage LVDD (e.g., approximately 0.6 V) and ground voltage. Therefore, voltage detector 801 can receive a first supply voltage VDD in a first voltage domain (from 0 V to about 0.75 V) and output a control signal VDD_OK in another (third) voltage domain (from 0 V to about 0.6 V). Voltage detector 801 can output a logic high control signal VDD_OK (e.g., about 0.6 V) when it detects that the first supply voltage VDD is in a logic low state and the first mid-range supply voltage LVDD is in a logic high state. In another example, level shifter 820 is used to shift the control signal psvqb from a third voltage domain (e.g., from 0 V to about 0.6 V) to yet another (fourth) voltage domain. In some embodiments, the fourth voltage domain may range from the first mid-range supply voltage LVDD (e.g., about 0.6 V) to a second mid-range supply voltage HVDD of about 1.2 V. Therefore, inverters 822, 824, 826, and 828, which are coupled to the output of level shifter 820, can operate in the fourth voltage domain.

[0041] Additionally, the voltage supply circuit 800 includes level shifters 830, inverters 832, 834, 836, and 838, pull-up transistors 840, 842, and 844, and pull-down transistors 846, 848, and 850. Level shifter 830 can receive a control signal psvqb_i in a fourth voltage domain (approximately 0.6V to 1.2V) from inverter 822 and shift it to another (fifth) voltage domain. In some embodiments, the fifth voltage domain may range from a second mid-range supply voltage HVDD (e.g., approximately 1.2V) to a second supply voltage VQPS (e.g., approximately 1.8V). Therefore, inverters 832, 834, 836, and 838 coupled to the output of level shifter 830 can operate in the fifth voltage domain.

[0042] Pull-up transistors 840, 842, 844, 846, 848, and 850 can still be coupled between the second supply voltage VQPS and the ground voltage, wherein the drain terminals of pull-up transistors 844 and 846 are connected to each other to provide the operating voltage VDDQ. Specifically, the gate of pull-up transistor 840 can be used to receive the signal output from inverter 838 (from about 1.2 V to about 1.8 V in the fifth voltage domain); the gate of pull-up transistor 842 can be used to receive the second intermediate supply voltage HVDD (from about 0.6 V to about 1.2 V in the fourth voltage domain); the gates of pull-up transistor 844 and pull-down transistor 846 can be used to receive the signal output from inverter 828 (from about 0.6 V to about 1.2 V in the fourth voltage domain); the gate of pull-down transistor 848 can be used to receive the first intermediate supply voltage LVDD (from 0 V to about 0.6 V in the third voltage domain); and the gate of pull-down transistor 850 can be used to receive the signal output from inverter 818 (from 0 V to about 0.6 V in the third voltage domain).

[0043] Figure 9 illustrates an exemplary circuit diagram of a voltage supply circuit 900 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 900 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 900 is substantially similar to the voltage supply circuit 800 (Figure 8), both of which provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V) via a stacked structure. The difference is that the voltage sensor (e.g., voltage sensor 901) of the voltage supply circuit 900 can be powered by a third intermediate supply voltage MVDD. Generally, the second supply voltage VQPS is higher than the intermediate supply voltage HVDD, which is higher than the intermediate supply voltage MVDD, which is higher than the intermediate supply voltage LVDD, which is higher than the ground voltage. For example, the mid-range supply voltage LVDD can be configured to 1 / 3 × VQPS, the mid-range supply voltage MVDD can be configured to 1 / 2 × VQPS, and the mid-range supply voltage HVDD can be configured to 2 / 3 × VQPS. For the sake of brevity, the following discussion of the voltage supply circuit 900 will focus on these differences.

[0044] Compared to voltage supply circuit 800 (Figure 8), voltage supply circuit 900 also includes components 901, 902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936, 938, 940, 942, 944, 946, 948, and 950, which are similar to components 801 and 802, respectively. The differences between voltage detectors 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, 828, 830, 832, 834, 836, 838, 840, 842, 844, 846, 848, and 850 are that voltage detector 901, which may include the elements shown in Figure 4, may couple its inverter between the mid-range supply voltage MVDD (e.g., about 0.9 V) and the ground voltage. Therefore, voltage detector 901 may receive a first supply voltage VDD in a first voltage domain (from 0 V to about 0.75 V) and output a control signal VDD_OK in another voltage domain (from 0 V to about 0.9 V). For example, when the voltage detector 901 detects that the first supply voltage VDD is in a logic low state and the intermediate supply voltage MVDD is in a logic high state, it outputs a control signal VDD_OK (e.g., about 0.9 V) in a logic high state.

[0045] Figure 10 illustrates an exemplary circuit diagram of a voltage supply circuit 1000 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 1000 provides an operating voltage VDDQ for the programmable fuse unit 103. Similar to voltage supply circuit 300 (Figure 3), the operation of voltage supply circuit 1000 can be shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V), the difference being that voltage supply circuit 1000 can provide another control signal PS18 via another pin. Therefore, the following discussion of voltage supply circuit 1000 will focus on its differences.

[0046] As shown in the figure, the voltage supply circuit 1000 includes inverter 1002, NAND gate 1004, inverter 1006, inverter 1008, level shifter 1010, p-type transistor 1016, p-type transistor 1012, n-type transistor 1014, inverter 1018, inverter 1020, inverter 1022, inverter 1024, NAND gate 1026, and inverter 1028. In some embodiments, inverter 1002, NAND gate 1004, inverter 1006, and inverter 1008 can operate in a first voltage domain, and p-type transistor 1012, n-type transistor 1014, p-type transistor 1016, inverter 1018, inverter 1020, inverter 1022, inverter 1024, NAND gate 1026, and inverter 1028 can operate in a second voltage domain, wherein level shifter 1010 shifts the first voltage domain to the second voltage domain.

[0047] During operation (when the coupled memory cell 103 is configured in program mode), control signals PD, PS, and PS18 are provided in logic low, logic high, and logic high states, respectively (i.e., PD=0, PS=1, PS18=1). Therefore, input signals 1025A and 1025B received by NAND gate 1026 are both provided in a logic high state, causing inverter 1028 to output an operating voltage VDDQ equal to the second supply voltage VQPS in the logic high state (e.g., approximately 1.8 V). For example, when PD=0 and PS=1, NAND gate 1004 outputs a signal in a logic high state, causing level shifter 1010 to receive an input signal in a logic low state (e.g., 0 V in the first voltage domain) and provide an output signal also in a logic low state (e.g., 0 V in the second voltage domain). An inverter formed by p-type transistor 1012 and n-type transistor 1014 can output an input signal 1025B in a logic high state. On the other hand, when PS18=1, an inverter chain composed of inverters 1018, 1020, 1022, and 1024 can output an input signal 1025A in a logic high state. After receiving two input signals in a logic high state, NAND gate 1026 can output a signal in a logic low state, which is then inverted to a logic high state by inverter 1028.

[0048] In certain scenarios, when the coupled memory cell 103 is configured in program mode but PS18=1 and PS=0, the voltage supply circuit 1000 can output an operating voltage VDDQ equal to the second supply voltage VQPS (e.g., at 0 V) ​​which is in a logic low state. This scenario may occur when the first supply voltage VDD is not properly provided. For example, when PS=0, the input signal 1025B received by the NAND gate 1026 becomes logic low, causing the NAND gate 1026 to output a signal with a logic high state. Therefore, the inverter 1028 provides an operating voltage VDDQ (e.g., at 0 V) ​​in a logic low state.

[0049] Figure 11 shows an exemplary circuit diagram of a voltage supply circuit 1100 for an I / O circuit 108 according to some embodiments. The voltage supply circuit 1100 provides an operating voltage VDDQ for the programmable fuse unit 103. Similar to voltage supply circuit 500 (Figure 5), the operation of voltage supply circuit 1100 can be shifted from a first voltage domain (e.g., from 0 V to about 0.75 V) to a second voltage domain (e.g., from 0 V to about 1.8 V), the difference being that voltage supply circuit 1100 can receive another control signal PS18 via a different pin. Therefore, the following discussion of voltage supply circuit 1100 will focus on this difference.

[0050] Similar to voltage supply circuit 500, voltage supply circuit 1100 also includes components 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1124, 1126, 1128, 1130, 1132, 1134, and 1136, which are similar to components 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, and 536, respectively. Additionally, voltage supply circuit 1100 includes a NAND gate 1140 and inverters 1142, 1144, 1146, and 1148. NAND gate 1140 is used to receive input signals 1139A and 1139B via an inverter chain consisting of inverters 1142, 1144, 1146, and 1148, and via voltage detector 1101. It provides control signal psvqb by performing logic NAND operations on input signals 1139A and 1139B. For example, input signal 1139B can be the same as control signal DIS, but control signal DIS is only in a logic high state when both the first supply voltage VDD and the second supply voltage VQPS (or the mid-range supply voltage MVDD) are in a high logic state; and input signal 1139A can have the same logic state as the received control signal PS18.

[0051] Figure 12 illustrates a flowchart of an operation method 1200 for providing an operating voltage to a memory circuit according to some embodiments. The operation of operation method 1200 can be performed by the elements described above (e.g., Figures 3 through 11), and therefore, some of the reference numerals used above may be repeated in the following discussion of operation method 1200. Furthermore, it should be understood that operation method 1200 has been simplified, and therefore, additional operations may be provided before, during, and after operation method 1200 in Figure 12, and only some of these other operations are briefly described herein.

[0052] Operation method 1200 begins with operation 1210. In operation 1210, a first supply voltage that transitions in a first voltage domain and a second supply voltage that transitions in a second voltage domain are received, wherein the first voltage domain is different from the second voltage domain. Using voltage supply circuit 300 as a non-limiting example, voltage supply circuit 300 can receive a first supply voltage (e.g., a first supply voltage VDD) and a second supply voltage (e.g., a second supply voltage VQPS) having separate logic states. The first supply voltage can transition in a first voltage domain (e.g., from 0 V to a first supply voltage VDD that can be set to about 0.75 V), and the second supply voltage can transition in a second voltage domain different from the first voltage domain (e.g., from 0 V to a second supply voltage VQPS that can be set to about 1.8 V). For example, when supplied in a logic high state, voltage supply circuit 300 can receive a first supply voltage equal to 0.75 V; and when supplied in a logic low state, voltage supply circuit 300 can receive a first supply voltage equal to 0 V. Similarly, when provided in a logic high state, the voltage supply circuit 300 can receive a second supply voltage equal to 1.8 V; and when provided in a logic low state, the voltage supply circuit 300 can receive a second supply voltage equal to 0 V.

[0053] Operation method 1200 continues to operation 1220. In operation 1220, after identifying a memory circuit configured in a first operation mode, an operating voltage equal to a second supply voltage having a first logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in read mode, the voltage supply circuit 300 can provide an operating voltage VDDQ (e.g., 0 V) ​​equal to the second supply voltage in a logic low state. In some embodiments, the voltage supply circuit 300 can determine that the memory circuit is in read mode by identifying that both control signals PD and PS are configured in a logic low state and both the first supply voltage VDD and the second supply voltage VQPS are provided in a logic high state.

[0054] Operation method 1200 continues to operation 1230. In operation 1230, after identifying a memory circuit configured in a second operation mode, an operating voltage equal to a second supply voltage having a second logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in program mode, the voltage supply circuit 300 can provide an operating voltage VDDQ equal to the second supply voltage in a logic high state, for example, 1.8 V. In some embodiments, the voltage supply circuit 300 can determine that the memory circuit is in program mode by identifying that the control signal PD is configured in a logic low state, the control signal PS is configured in a logic high state, and both the first supply voltage VDD and the second supply voltage VQPS are provided in a logic high state.

[0055] Operation method 1200 continues to operation 1240. In operation 1240, after identifying a memory circuit configured in a third operation mode, an operating voltage equal to a second supply voltage having a first logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in a non-programmed mode or a non-read mode (sometimes referred to as a valid mode or transition mode), the voltage supply circuit 300 can provide an operating voltage VDDQ equal to the second supply voltage in a logic low state, for example, 0 V. For example, such a transition mode may occur during the switching between read mode and program mode, wherein the second supply voltage VQPS has reached a logic high state, but the first supply voltage VDD remains in a logic low state. In some embodiments, the voltage supply circuit 300 may determine that the memory circuit is in a valid state by identifying that control signals PD and PS are not configured, the first supply voltage VDD is provided in a logic low state, and the second supply voltage VQPS is provided in a logic high state.

[0056] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array and a voltage supply circuit. The memory array includes a plurality of memory cells. The voltage supply circuit provides an operating voltage to one or more of the plurality of memory cells, the operation of which is shifted from a first voltage domain to a second voltage domain. The voltage supply circuit includes a voltage detector, which receives a first supply voltage in the first voltage domain, is powered by a second supply voltage in the second voltage domain, and provides a first control signal. The first control signal determines whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

[0057] In some embodiments of the memory circuit, the voltage supply circuit further includes a NOR gate, a first inverter, and a second inverter. The NOR gate receives a first control signal and provides a second control signal. The first inverter receives the second control signal and provides a third control signal. The second inverter receives the third control signal and provides an operating voltage. Each of the NOR gate, the first inverter, and the second inverter is powered by a second supply voltage.

[0058] In some embodiments of the memory circuit, the voltage detector includes a third inverter powered by a second supply voltage, the third inverter being used to receive the first supply voltage and provide a first control signal.

[0059] In some embodiments of the memory circuit, when the first supply voltage and the second supply voltage are provided in the first logic state and the second logic state, respectively, the first control signal is provided in the second logic state, such that the voltage supply circuit provides an operating voltage equal to the second supply voltage in the first logic state.

[0060] In some embodiments of the memory circuit, the voltage detector further includes an n-type transistor coupled between the input of the third inverter and ground voltage. The gate of the n-type transistor is connected to a second control signal, which is determined based on a logic NOR operation performed on the first control signal.

[0061] In some embodiments of the memory circuit, when both the first supply voltage and the second supply voltage are provided in the second logic state, the second control signal remains in the second logic state.

[0062] In some embodiments of the memory circuit, the voltage detector further includes a Schmitt trigger coupled to the output of a third inverter.

[0063] In some embodiments of memory circuits, multiple memory cells each include a one-time programmable memory cell.

[0064] In another embodiment of this disclosure, a voltage supply circuit is disclosed. The voltage supply circuit includes a voltage detector, a logic gate, and a first n-type transistor. The voltage detector is powered by a first supply voltage in a first voltage domain and is used to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is higher than the second supply voltage in a logic high state. The logic gate is used to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the first voltage domain. The first n-type transistor has a gate terminal for receiving the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to ground. When the first supply voltage is in a logic high state and the second supply voltage is in a logic low state, the second control signal is output in a logic low state via the logic gate.

[0065] In some embodiments of the voltage supply circuit, the logic gate includes a NOR logic gate.

[0066] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a first p-type transistor. The first p-type transistor has a gate terminal for receiving a second control signal via a first inverter, a drain terminal connected to an output node, and a source terminal connected to a first supply voltage.

[0067] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a level shifter. The level shifter is used to shift the signal from the second voltage domain to the first voltage domain.

[0068] In some embodiments of the voltage supply circuit, depending on the logic state of the second control signal, the operating voltage supplied at the output node is equal to the first supply voltage in the logic high state or the first supply voltage in the logic low state.

[0069] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a second n-type transistor, a first p-type transistor, and a second p-type transistor. The second n-type transistor has a gate terminal for receiving a first supply voltage, a drain terminal connected to an output node, and a source terminal connected to the drain terminal of the first n-type transistor. The first p-type transistor has a gate terminal for receiving the first supply voltage, a drain terminal connected to an output node, and a source terminal coupled to a third supply voltage in a third voltage domain. The third supply voltage is higher than the first supply voltage. The second p-type transistor has a gate terminal for receiving a third control signal, a drain terminal connected to the source terminal of the first p-type transistor, and a source terminal connected to the third supply voltage.

[0070] In some embodiments of the voltage supply circuit, depending on the logic state of the second control signal and the logic state of the third control signal, the operating voltage provided at the output node is equal to the third supply voltage in the logic high state or the third supply voltage in the logic low state, and the third control signal is in the third voltage domain.

[0071] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a first quasi-shifter and a second quasi-shifter. The first quasi-shifter is used to shift the signal from a second voltage domain to a first voltage domain. The second quasi-shifter is used to shift the signal from the first voltage domain to a third voltage domain.

[0072] In some embodiments of the voltage supply circuit, the voltage detector includes an inverter powered by a first supply voltage. The inverter has an input for receiving a second supply voltage and an output for providing a first control signal.

[0073] In some embodiments of the voltage supply circuit, the voltage detector further includes a second n-type transistor coupled between the input of the inverter and the ground voltage. The gate of the second n-type transistor is used to receive a second control signal.

[0074] In another embodiment of this disclosure, an operational method for providing an operating voltage to a memory circuit is disclosed, comprising the following steps: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different from the second voltage domain; after identifying a memory circuit configured in a first operating mode, providing an operating voltage equal to the second supply voltage having a first logic state; after identifying a memory circuit configured in a second operating mode, providing an operating voltage equal to the second supply voltage having a second logic state; and after identifying a memory circuit configured in a third operating mode, providing an operating voltage equal to the second supply voltage having a first logic state. In the first operating mode, the first supply voltage and the second supply voltage each have a second logic state; in the second operating mode, the first supply voltage and the second supply voltage each have a second logic state; and in the third operating mode, the first supply voltage and the second supply voltage each have a first logic state and a second logic state, respectively.

[0075] In some embodiments of the operating method, the second supply voltage in the second logic state is higher than the first supply voltage in the second logic state.

[0076] As used herein, the terms "about" and "approximately" generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate, for example, the value of a given quantity that varies within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0077] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0078] 100: Memory Circuit 102: Memory Array 103: Memory Unit / Fuse Unit 104: Column Decoder 106: Line Decoder 108: Input / Output (I / O) Circuits 110: Logic control circuit 202: Fuse Resistor 204: Access Transistor 300: Voltage supply circuit 301: Voltage Detector / Component 302: Inverter / Component 304: NAND gate / component 305, 307, 309, 311, 315: Signals 306, 310: Inverters / Components 308: Level shifter / component 312: NOR gate / component 314: Inverter 316: Pull-up transistor 318: Pull-down transistor 405: Inverter 410: Pull-up transistor 420: Pull-down transistor 430: Transistor 440: Schmitt trigger 500: Voltage supply circuit 501: Voltage Detector / Component 502, 504, 506, 508: Components 510: Inverter / Component 512: NOR gate / component 514, 516, 518: Inverters / Components 517, 519, 521, 523, 525: Signals 520: Level shifter / component 522, 524, 526, 528: Inverters / Components 527, 529: Signal 530: First pull-up transistor / component 532: Second pull-up transistor / component 534: First pull-down transistor / component 536: Second pull-down transistor / component 600: Voltage supply circuit 601: Voltage Detector / Component 602, 604, 606, 608, 610: Components 612, 614, 616, 618, 620: Components 622, 624, 626, 628, 630: Components 632, 634, 636: Components 700: Voltage Supply Circuit 701: Component 702, 704, 706, 708, 710: Components 712, 714, 716, 718, 720: Components 722, 724, 726, 728: Components 730: Pull-up transistor / component 732: Pull-down transistor / component 800: Voltage Supply Circuit 801: Voltage Detector / Component 802, 804, 806, 808, 810: Components 812, 814, 816: Components 818: Inverter / Component 820: Level shifter / component 822, 824, 826, 828: Inverters / Components 830: Level shifter / component 832, 834, 836, 838: Inverters / Components 840, 842, 844: Pull-up transistors / components 846, 848, 850: Pull-down transistors / components 900: Voltage supply circuit 901: Voltage Detector / Component 902, 904, 906, 908, 910: Components 912, 914, 916, 918, 920: Components 922, 924, 926, 928, 930: Components 932, 934, 936, 938, 940: Components 942, 944, 946, 948, 950: Components 1000: Voltage supply circuit 1002: Inverter 1004: NAND gate 1006, 1008: Inverters 1010: Level shifter 1012: p-type transistor 1014: n-type transistor 1016: p-type transistor 1018, 1020, 1022, 1024: Inverters 1025A, 1025B: Input signal 1026: NAND gate 1028: Inverter 1100: Voltage supply circuit 1101: Voltage Detector 1102, 1104, 1106, 1108: Components 1110, 1112, 1114, 1116: Components 1118, 1120, 1122, 1124: Components 1126, 1128, 1130, 1132: Components 1134, 1136: Components 1139A, 1139B: Input signal 1140: NAND gate / inverter 1142, 1144, 1146, 1148: Inverters 1200: Operating Instructions 1210, 1220, 1230, 1240: Operations BL: Bitline C1~CN: rows DIS: Control Signal HVDD: Mid-range supply voltage / Second mid-range supply voltage LVDD: Mid-range supply voltage / First mid-range supply voltage MVDD: Mid-range supply voltage / Third mid-range supply voltage PD, PS, PS18: Control signals Psvqb, psvqb_i: Control signals R1~RM: Columns VDD: First supply voltage VDD_OK: Control signal VDDQ: Operating voltage VQPS: Second supply voltage WL: Character Line

[0079] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A memory circuit comprising: a memory array including a plurality of memory cells; and a voltage supply circuit for providing an operating voltage to one or more of the plurality of memory cells, the operation of the voltage supply circuit being shifted from a first voltage domain to a second voltage domain; wherein the voltage supply circuit includes a voltage detector, and wherein the voltage detector is configured to receive a first supply voltage in the first voltage domain, be powered by a second supply voltage in the second voltage domain, and provide a first control signal for determining whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

2. The memory circuit as claimed in claim 1, wherein the voltage supply circuit further comprises: a NOR gate for receiving the first control signal and providing a second control signal; and a first inverter for receiving the second control signal and providing a third control signal; And a second inverter for receiving the third control signal and providing the operating voltage; Each of the NOR gate, the first inverter, and the second inverter is powered by the second supply voltage.

3. The memory circuit as claimed in claim 1, wherein the voltage detector includes a third inverter powered by the second supply voltage, the third inverter being used to receive the first supply voltage and provide the first control signal.

4. The memory circuit as claimed in claim 3, wherein when the first supply voltage and the second supply voltage are provided in the first logic state and the second logic state respectively, the first control signal is provided in the second logic state, such that the voltage supply circuit provides the operating voltage equal to the second supply voltage in the first logic state.

5. The memory circuit as claimed in claim 3, wherein the voltage detector further includes an n-type transistor coupled between an input of the third inverter and a ground voltage, wherein a gate terminal of the n-type transistor is connected to a second control signal, the second control signal being determined based on a logic NOR operation performed on the first control signal.

6. The memory circuit as claimed in claim 5, wherein the second control signal remains in the second logic state when both the first supply voltage and the second supply voltage are provided in the second logic state.

7. The memory circuit as claimed in claim 5, wherein the voltage detector further includes a Schmitt trigger coupled to an output of the third inverter.

8. The memory circuitry as claimed in claim 1, wherein each of the plurality of memory cells comprises a one-time programmable memory cell.

9. A voltage supply circuit comprising: a voltage detector powered by a first supply voltage in a first voltage domain, the voltage detector being configured to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is lower than the second supply voltage in the logic high state; a logic gate being configured to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the second voltage domain; and a first n-type transistor having a gate terminal for receiving the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to a ground voltage; wherein when the first supply voltage has the logic high state and the second supply voltage has the logic low state, the second control signal is output in the logic low state via the logic gate.

10. A method of providing an operating voltage to a memory circuit, comprising the steps of: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different from the second voltage domain; after identifying a memory circuit configured in a first operating mode, in response to a control signal, providing an operating voltage equal to the second supply voltage having a first logic state; after identifying the memory circuit configured in a second operating mode, in response to the control signal, providing the operating voltage equal to the second supply voltage having a second logic state; and after identifying the memory circuit configured in a third operating mode, in response to the control signal, providing the operating voltage equal to the second supply voltage having the first logic state; wherein in the first operating mode, the first supply voltage and the second supply voltage each have the second logic state. In the second operating mode, the first supply voltage and the second supply voltage each have the second logic state, and in the third operating mode, the first supply voltage and the second supply voltage each have the first logic state and the second logic state, respectively.

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