Semiconductor device and methods of formation

Abstract

During the nanosheet release process, the nanostructure channels of the nanostructured transistor are etched to remove sacrificial nanostructure layers between the nanostructure channels. The nanostructure channels are etched such that their thickness at the edges is less than that at the center. This results in a sloping / tapered or curved cross-sectional profile between the center and the edges of the nanostructure channels. The resulting cross-sectional profile provides a larger opening between vertically adjacent nanostructure channels to allow for the deposition of gate structure material between the vertically adjacent nanostructure channels of the nanostructured transistor. The larger opening increases the gap-filling performance of the gate structure formation, which reduces the likelihood of seams and / or voids appearing in the gate structure between vertically adjacent nanostructure channels.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Prior Technology

[0002] With advancements in semiconductor device manufacturing and the shrinking of technology processing node sizes, transistors may be affected by the short-channel effect (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement. Furthermore, as transistor gate lengths decrease to accommodate smaller technology nodes, source / drain (S / D) electron tunneling increases, which raises the transistor's cutoff current (the current flowing through the transistor channel when the transistor is in the cutoff configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates to overcome the short-channel effect at smaller technology nodes. Nanostructure transistors offer high efficiency compared to other types of transistors, exhibiting reduced SCE and enhanced carrier mobility. Summary of the Invention

[0003] Some embodiments described herein provide a method for forming a semiconductor device. The method includes the steps of: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes the step of: performing a first etching operation to etch the nanostructured semiconductor layers and the sacrificial nanostructured layers to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructured channels and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes the step of: performing a second etching operation to remove the sacrificial nanostructured layers from the semiconductor device, wherein the second etching operation causes the nanostructured channels in the nanostructured channels to have a first cross-sectional thickness at the center of the nanostructured channel and a second cross-sectional thickness at the outer edge of the nanostructured channel, and wherein the second cross-sectional thickness is less than the first cross-sectional thickness.

[0004] Some embodiments described herein provide a method for forming a semiconductor device. The method includes the steps of: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes the steps of: performing a first etching operation to etch the nanostructured semiconductor layers and the sacrificial nanostructured layers to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructured channels and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes the steps of: performing a plurality of second etching operations to remove the sacrificial nanostructured layers from the semiconductor device, wherein the second etching operations cause the top and bottom surfaces of the nanostructured channels to have inclined sections between the center of the nanostructured channel and the outer edge of the nanostructured channel.

[0005] Some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device, wherein a first distance between the outer edges of perpendicularly adjacent nanostructured channels is greater than a second distance between the centers of perpendicularly adjacent nanostructured channels. The semiconductor device includes a gate structure surrounding the nanostructured channels. The semiconductor device includes a first source / drain region adjacent to a first side of the gate structure. The semiconductor device includes a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1A to 1C are schematic diagrams illustrating exemplary implementations of the fin boundary customization process described herein. Figure 2 is a schematic diagram of the fabrication process of the exemplary dummy gate structure described in this article. Figure 3 is a schematic diagram illustrating an exemplary implementation of the source / drain groove formation process described in this paper. Figures 4A and 4B are schematic diagrams illustrating exemplary implementations of the internal spacer formation process described herein. Figure 5 is a schematic diagram illustrating an exemplary implementation of the source / drain region formation process described in this paper. Figure 6 is a schematic diagram illustrating an exemplary implementation of the interlayer dielectric layer formation process described in this paper. Figures 7A to 7F are schematic diagrams illustrating exemplary implementations of the nanosheet release process described herein. Figures 8A to 8J are schematic diagrams illustrating exemplary implementations of the nanosheet release process described herein. Figures 9A to 9C are schematic diagrams illustrating exemplary implementations of the gate formation process described herein. Figure 10 is a schematic diagram of an example of the semiconductor device described in this article. Figure 11 is a schematic diagram of an example of the semiconductor device described in this article. Figures 12 and 13 are flowcharts of exemplary processes related to forming the semiconductor device described herein. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0009] Some nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors) include internal spacers between the source / drain regions and the gate structure. These internal spacers provide various process and / or performance advantages, such as electrical isolation between the source / drain regions and the gate structure, and / or protection of the source / drain regions from etching during gate replacement operations to replace the sacrificial nanostructure layer with the gate structure.

[0010] However, forming the gate structure around the nanostructure channels of a nanostructured transistor can be challenging in terms of fabrication processes, potentially leading to defects within the gate structure. For example, while vertically adjacent nanostructure channels in a nanostructured transistor can be separated by small spaces to achieve high channel density, this can make it difficult to fill the spaces between them. Consequently, due to poor gap-filling performance between vertically adjacent nanostructure channels, seams or voids may form in the gate structure between them. These seams / voids can increase gate resistance and / or gate capacitance, thereby degrading the performance of the nanostructured transistor.

[0011] In some embodiments described herein, the nanostructure channels of a nanostructured transistor are etched during a nanosheet release process to remove sacrificial nanostructure layers between the nanostructure channels. The nanostructure channels are etched such that the thickness of the nanostructure channels at their edges is less than the thickness at their center. This results in a sloping / tapered or curved cross-sectional profile between the center and edges of the nanostructure channels. The resulting cross-sectional profile provides a larger opening between vertically adjacent nanostructure channels for depositing material for the gate structure of the nanostructured transistor between these vertically adjacent channels. The larger opening increases the gap-filling performance of the gate structure, which reduces the likelihood (and / or size) of seams and / or voids in the gate structure between vertically adjacent nanostructure channels. Therefore, the techniques described herein can reduce the gate resistance and / or gate capacitance of the nanostructured transistor, thereby improving its performance.

[0012] Figures 1A through 1C are schematic diagrams illustrating an exemplary embodiment 100 of the fin-bound process described herein. Exemplary embodiment 100 includes examples of forming the fin-shaped structure and associated shallow trench isolation (STI) region of the semiconductor device 105 described herein. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes examples of forming the fin-shaped structure and associated STI region of the transistors in the semiconductor device 105.

[0013] Figures 1A through 1C illustrate perspective views and cross-sectional views along line AA in the perspective views, respectively. As shown in Figure 1A, the processing of the semiconductor device 105 is performed together with the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0014] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 located above the semiconductor substrate 110. The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in Figure 1A are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of this disclosure.

[0015] The sacrificial nanostructure layer 120 enables the definition of vertical distances between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a vacancy layer for the subsequently formed gate structure of the transistor of the semiconductor device 105, the vacancy layer being formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This enables the selective etching of the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 depending on the type of etchant used (e.g., the sacrificial nanostructure layer 120 can be etched without etching the nanostructure channel layer 125, and the nanostructure channel layer 125 can be etched without etching the sacrificial nanostructure layer 120).

[0016] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the layer stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be grown by epitaxial growth using deposition tools. Epitaxial growth can include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0017] As shown in a close-up view of a portion of layer stack 115 in Figure 1A, intermixing may occur between two or more nanostructure layers in layer stack 115. For example, intermixing may occur between sacrificial nanostructure layer 120 and a vertically adjacent nanostructure channel layer 125. Intermixing may cause silicon (Si) and / or germanium (Ge) to diffuse between sacrificial nanostructure layer 120 and nanostructure channel layer 125. Therefore, an intermixed layer 130 may be included between sacrificial nanostructure layer 120 and nanostructure channel layer 125. Intermixed layer 130 may include silicon-germanium (SiGe) regions where the silicon (Si) concentration (e.g., due to silicon diffusion from nanostructure channel layer 125 into sacrificial nanostructure layer 120) is higher than the germanium (Ge) concentration in intermixed layer 130.

[0018] One or more mask layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The mask layers may include a hard mask (HM) layer 135, a capping layer 140, an oxide layer 145, and / or a nitride layer 150. The mask layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0019] As shown in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 155 extending over the semiconductor substrate 110. The fin structure 155 may extend in the semiconductor device 105 along the x-direction and may be aligned in the semiconductor device 105 along the y-direction. The fin structure 155 includes a portion 160 of the layer stack 115, which is located above and / or on the fin portion 165 on the semiconductor substrate 110. The fin structure 155 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more masking layers. One or more masking layers may be patterned using lithography techniques (including dual patterning or multiple patterning techniques). The semiconductor substrate 110 may be etched using an etching tool based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0020] As further shown in Figure 1B, some fin structures 155 can be formed with different widths for different types of nanostructure transistors. For example, a first subset of fin structures 155a can be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 155b can be formed for n-type nanostructure transistors (e.g., n-type nanostructure transistor (NMOS) nanostructure transistors). As another example, the first subset of fin structures 155a can be formed for nanostructure transistors operating at lower voltages, and the second subset of fin structures 155b can be formed for nanostructure transistors operating at higher voltages.

[0021] As shown in Figure 1C, a pad 170 and an STI region 175 are formed between adjacent fin portions 165 of the fin structure 155. The pad 170 and the STI region 175 may each include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials.

[0022] A deposition tool can be used (e.g., using ALD or another conformal deposition technique) to conformally deposit the liner 170, and a dielectric layer can be deposited on the liner 170 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 155 and extends above the top of the fin structures 155. A planarization or polishing operation (e.g., chemical mechanical planarization, CMP) can then be performed using a planarization tool to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 150. The nitride layer 150 serves as a CMP termination layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 175 such that the top surface of the STI region 175 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0023] As described above, Figures 1A through 1C are provided as examples. Other examples may differ from those described for Figures 1A through 1C.

[0024] Figure 2 is a schematic diagram of an exemplary embodiment 200 of the dummy gate formation process described herein. Exemplary embodiment 200 includes an example of a dummy gate structure 205 forming a nanostructure transistor of a semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the processes described in conjunction with Figures 1A to 1C.

[0025] Figure 2 illustrates a perspective view of semiconductor device 105, in which a dummy gate structure 205 is formed on semiconductor device 105. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed above a portion of fin structure 155 and a portion of STI region 175. The dummy gate structure 205 extends in the x-direction and is aligned in the y-direction such that the dummy gate structure 205 is approximately perpendicular to fin structure 155. The dummy gate structure 205 is a sacrificial structure, which will be replaced by a replacement gate structure or replacement gate stack in subsequent processing stages of semiconductor device 105. The dummy gate structure 205 can also be used to define source / drain (S / D) recesses, in which the source / drain regions of the nanostructured transistor are formed in fin structure 155.

[0026] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 located above and / or on the gate electrode layer 210, a spacer layer 220 located on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 located below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polycrystalline silicon or PO) or other materials. The hard mask layer 215 includes one or more layers, such as an oxide layer formed above an oxide layer (e.g., a pad oxide layer of silicon dioxide (SiO2) or other materials) and a nitride layer (e.g., a pad nitride layer of silicon nitride such as Si3N4 or other materials). The spacer layer 220 includes silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiOx, such as SiO2), silicon nitride (e.g., SixNy, such as Si3N4), high dielectric constant (high k) dielectric material (e.g., dielectric material with a dielectric constant greater than about 3.9) and / or other suitable materials.

[0027] The layer of the dummy gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor processing techniques.

[0028] Figure 2 further illustrates the reference sections used in the subsequent figures described herein. Section AA lies in the xz plane (referred to as the y-section) and spans the fin structure 155 in the source / drain region of semiconductor device 105. Section BB lies in the yz plane perpendicular to section AA (referred to as the x-section) and spans the dummy gate structure 205 along the underlying fin structure 155. Section CC lies in the xz plane parallel to section AA and perpendicular to section BB, and along the dummy gate structure 205. For clarity, these reference sections will be referenced in subsequent figures. In some figures, for ease of depiction, component symbols for some components or features may be omitted to avoid obscuring other components or features.

[0029] As stated above, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2.

[0030] Figure 3 is a schematic diagram of an exemplary embodiment 300 of the source / drain trench formation process described herein. Exemplary embodiment 300 includes an example of a source / drain trench 305 forming a source / drain region for a nanostructured transistor in a semiconductor device 105. Figure 3 illustrates a plurality of angles shown in Figure 2, including the angle of section AA and section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 300 are performed after the processes described in conjunction with Figures 1A through 2.

[0031] As shown in sections AA and BB of Figure 3, the source / drain groove 305 is formed through portion 160 of the fin structure 155 during the etching operation. The source / drain groove 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using etching tools and may be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes the use of plasma etching technology, wet chemical etching technology, and / or another type of etching technology.

[0032] The source / drain grooves 305 also extend into a portion of the fin portion 165 of the fin structure 155. This results in the formation of a mesa region 310 in the fin structure 155. The sidewall of the portion of each source / drain groove 305 located below the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as the base) refers to the region of the fin portion 165 of the fin structure 155, which defines a nanostructure channel from the nanostructure channel layer 125 in the region. The nanostructure channel 315 extends between adjacent source / drain grooves 305 and is located below the dummy gate structure 205 between adjacent source / drain grooves 305.

[0033] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or nanowire) and serves as a semiconductor channel for the nanostructure transistor of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may include silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructure channel 315 is vertically aligned or stacked above the semiconductor substrate 110.

[0034] As stated above, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3.

[0035] Figures 4A and 4B are schematic diagrams of an exemplary embodiment 400 of the internal spacer formation process described herein. Exemplary embodiment 400 includes an example of forming internal spacers between the ends of nanostructure channels 315, the ends being exposed in source / drain recesses 305. Figures 4A and 4B are illustrated from the angle of section BB in Figure 2, respectively. In some embodiments, the operations described in conjunction with exemplary embodiment 400 are performed after the processes described in conjunction with Figures 1A through 3.

[0036] As shown in section BB of Figure 4A, in one or more first etch operations, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain grooves 305 are etched laterally (e.g., in the x-direction approximately parallel to the length of the sacrificial nanostructure layer 120) to form cavities 405 between the ends of the sacrificial nanostructure layer 120 exposed in the source / drain grooves 305. Specifically, the ends of the sacrificial nanostructure layer 120 located below the dummy gate structure 205 can be etched laterally via the source / drain grooves 305 using an etching tool to form cavities 405 between the ends of the nanostructure channels 315.

[0037] In embodiments where the sacrificial nanostructure layer 120 is silicon-germanium (SiGe) and the nanostructure channel 315 is silicon (Si), the sacrificial nanostructure layer 120 is etched in one or more first etch operations using a wet etchant (such as a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH), and / or hydrogen fluoride (HF)), followed by rinsing with water (H2O). The mixed solution and water can be provided to the source / drain recess 305 to etch the sacrificial nanostructure layer 120 in the source / drain recess 305. In some embodiments, the mixed solution etching and water rinsing are repeated multiple times to form the cavity 405.

[0038] As shown in Figure 4B, an internal spacer 410 is formed in the cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 410 serves to reduce parasitic capacitance in the nanostructure transistors and prevent the source / drain regions (subsequently formed in the source / drain recess 305) from being etched during a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacer 410 includes silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbide (SiOCN), and / or other dielectric materials.

[0039] To form the internal spacer 410, a dielectric material layer can be deposited in the cavity 405 and along the sidewalls and bottom surface of the source / drain recesses using a deposition tool. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. Excess material of the dielectric material layer is then removed from the source / drain recesses using an etching tool, leaving the remaining portion corresponding to the internal spacer 410 in the cavity 405. In some embodiments, the etching operation may cause the surface of the internal spacer 410 facing the source / drain recesses 305 to bend or recess. In some embodiments, the surface of the internal spacer 410 facing the source / drain recesses 305 is approximately flat, such that the surface of the internal spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0040] As described above, Figures 4A and 4B are provided as examples. Other examples may differ from those described with respect to Figures 4A and 4B.

[0041] Figure 5 is a schematic diagram of an exemplary embodiment 500 of the source / drain region formation process described herein. Exemplary embodiment 500 includes an example of forming the source / drain region of a nanostructured transistor for a semiconductor device 105. Figure 5 is illustrated from the plurality of angles shown in Figure 2, including the angle of section AA and section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 4B.

[0042] As shown in cross-sections AA and BB in Figure 5, the source / drain groove 305 is filled with one or more layers of material to form a source / drain region within the source / drain groove 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain groove 305, and the deposition tool can deposit a source / drain region 510 on the buffer region 505 in the source / drain groove 305. In some embodiments, a deposition tool can be used to deposit a capping layer 515 on the source / drain region 510 in the source / drain groove 305.

[0043] Buffer region 505 may include silicon (Si), boron-doped silicon (Si:B), or other dopants and / or other materials. Buffer region 505 may be located between source / drain region 510 and mesa region 310, which is adjacent to buffer region 505, to reduce, minimize, and / or prevent dopant migration and / or current leakage from source / drain region 510 to adjacent mesa region 310, which could otherwise lead to short-channel effects in semiconductor device 105. Therefore, buffer region 505 can improve the performance and / or yield of semiconductor device 105.

[0044] Depending on the context, "source / drain region" may refer to either the source or the drain individually, or collectively. The source / drain region 510 may be located on opposite sides of the dummy gate structure 205, such that the nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Therefore, the semiconductor device 105 may include a p-type metal-oxide semiconductor (PMOS) nanostructure transistor (including a p-type source / drain region 510), an n-type metal-oxide semiconductor (NMOS) nanostructure transistor (including an n-type source / drain region 510), and / or other types of nanostructure transistors.

[0045] One or more layers of the source / drain region 510 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over an associated buffer region 505 (referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 over the first layer. The first layer may include lightly doped silicon (e.g., boron (B), phosphorus (P), and / or another dopant) and may serve as a shielding layer to reduce short-channel effects in the semiconductor device 105 and reduce dopant extrusion or migration to the nanostructure channel 315. The second layer may include heavily doped silicon or heavily doped silicon-germanium. A second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0046] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or other materials. Prior to contact formation, during semiconductor processing operations of the semiconductor device 105, the capping layer 515 may be included to reduce dopant diffusion and protect the underlying source / drain regions 510. Furthermore, the capping layer 515 may facilitate the formation of metal-semiconductor (e.g., silicate) alloys.

[0047] As stated above, Figure 5 is provided as an example. Other examples may differ from those described for Figure 5.

[0048] Figure 6 is a schematic diagram of an exemplary embodiment 600 of the interlayer dielectric (ILD) formation process described herein. Figure 6 is illustrated from the plurality of angles shown in Figure 2, including the angle of section AA and the angle of section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 5.

[0049] As shown in cross-sections AA and BB in Figure 6, a dielectric layer 605 is formed above the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during the gate replacement process and / or to prevent damage to the source / drain region 510 to replace the dummy gate structure 205. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0050] In some implementations, a contact etch stop layer (CESL) is conformally deposited (e.g., using a deposition tool) over the source / drain region 510 before the dielectric layer 605 is formed. Alternatively, the capping layer 515 may be a CESL. The dielectric layer 605 is then formed on the CESL. The CESL provides a mechanism to terminate the etching process when forming contacts or vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (SixNy), silicon carbonitride (SiCN), carbonitride (CN), silicon oxynitride (SiON), silicon carbide (SiCO), or combinations thereof, etc. The CESL may be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0051] As stated above, Figure 6 is provided as an example. Other examples may differ from those described for Figure 6.

[0052] Figures 7A through 7F are schematic diagrams of an exemplary embodiment 700 of the nanosheet release process described herein. The nanosheet release process (e.g., a SiGe release process) is a process for removing the remaining portion of the sacrificial nanostructure layer 120 between the nanostructure channels 315 of the semiconductor device 105. The nanosheet release process may be performed as part of a replacement gate (RPG) process, which replaces the dummy gate structure 205 of the nanostructure transistor of the semiconductor device 105 with a high-k / metal gate structure (e.g., a replacement gate structure). Figures 7A through 7F are illustrated from the angle of section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the operations described in conjunction with Figures 1A through 6.

[0053] As shown in Figure 7A, a dummy gate removal operation can be performed prior to the nanosheet removal process. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or groove) between the dielectric layers 605 and provides a channel for the nanosheet removal process to access the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or another type of etching technique.

[0054] As further shown in Figure 7A, each of the nanostructure channels 315 may have a dimension D1 and a dimension D2. Dimension D1 corresponds to the z-direction (vertical) thickness at the center of the nanostructure channel 315 (e.g., the center of the width along the y-direction of the nanostructure channel 315), and dimension D2 corresponds to the z-direction (vertical) thickness at the edge of the nanostructure channel 315 (e.g., the outer edge of the width along the y-direction of the nanostructure channel 315). Before the nanosheet release process, the z-direction thickness at the center of the nanostructure channel 315 and the z-direction thickness at the edge of the nanostructure channel 315 are approximately equal (e.g., dimension D1 ≈ dimension D2).

[0055] As shown in Figures 7B through 7F, the nanosheet release process may include performing an etching operation to laterally etch the sacrificial nanostructure layer 120, thereby removing the sacrificial nanostructure layer 120 from between vertically adjacent nanostructure channels 315.

[0056] As shown in Figure 7B, the etching operation may include providing etchant 705 around the exposed portions of the sacrificial nanostructure layer 120 and laterally etching the sacrificial nanostructure layer 120 using the etchant 705. The semiconductor device 105 may be placed in the processing chamber of the etching tool, and the etchant 705 may be provided to the processing chamber as a mixture of process gases that react with each other and / or with the material of the sacrificial nanostructure layer 120 to etch the sacrificial nanostructure layer 120. In some embodiments, the pressure in the processing chamber may range from about 100 mTorr to about 2500 mTorr. However, other ranges and values ​​are also within the scope of this disclosure.

[0057] Etching agent 705 may include gas-based etchants, including combinations of fluorine-based etchants (e.g., F2 gas) and hydrofluoric acid etchants (e.g., HF gas). During the etching operation, other gases (such as purge gases, carrier gases, and / or other reactive gases) may also be supplied to the processing chamber. These gases may include argon (Ar), ammonia (NH3), chlorine trifluoride (ClF3), and / or nitrogen (N2), etc. In some embodiments, the total gas flow rate entering the processing chamber during the etching operation may be as high as approximately 1300 standard cubic centimeters per minute (sccm). However, other values ​​and / or ranges of the total gas flow rate during the etching operation are within the scope of this disclosure.

[0058] As shown in Figures 7C through 7E, etchant 705 can laterally etch the sacrificial nanostructure layer 120 during an etching operation, starting from the outer edge of the sacrificial nanostructure layer 120 and moving towards its center until the sacrificial nanostructure layer 120 is completely removed (or substantially completely removed). Etching agent 705 can also etch and remove the intermixed layer 130 from the nanostructure channel 315. In some embodiments, the etching operation lasts for approximately 20 seconds to approximately 150 seconds to ensure complete removal of the sacrificial nanostructure layer 120. However, other ranges and values ​​are within the scope of this disclosure.

[0059] Etching agent 705 can be used to etch the sacrificial nanostructure layer 120 and the intermixed layer 130 by removing silicon (Si) and germanium (Ge) from the sacrificial nanostructure layer 120 and the intermixed layer 130. The removal of silicon (Si) from the sacrificial nanostructure layer 120 and the intermixed layer 130 may result from a reaction between the fluorine-based etchant (e.g., F2 gas) in etching agent 705 and the silicon-germanium (SiGe) in the sacrificial nanostructure layer 120 and the intermixed layer 130. As shown in region 710 of Figure 7C, a fluorine-based etchant (e.g., F2 gas) in etchant 705 can adhere to silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130 to form germanium trifluoride (GeF3) and silicon trifluoride (SiF3), respectively. Fluorine migration (F-migration) may occur, in which fluorine (F) atoms migrate from germanium trifluoride molecules to silicon trifluoride molecules, thereby forming germanium difluoride (GeF2) and silicon tetrafluoride (SiF4) gases. Removal of silicon tetrafluoride gas from semiconductor device 105 removes silicon (Si) from sacrificial nanostructure layer 120 and intermixed layer 130. Fluorine (F) atom migration can occur at energies in the range of about 0.3 electron volts (eV) to about 0.35 eV. However, other values ​​and / or ranges of energy for fluorine (F) atom migration are within the scope of this disclosure. Fluorine (F) atom migration can be an exothermic process, where the enthalpy change (∆H) ranges from about -1.75 eV to about -2.0 eV. However, other values ​​and / or ranges of enthalpy change are within the scope of this disclosure.

[0060] The removal of germanium (Ge) from the self-sacrificing nanostructure layer 120 and the intermixed layer 130 may result from the reaction between the combination of fluorine-based etchant (e.g., F2 gas) and hydrofluoric acid etchant (e.g., HF gas) in etchant 705 and silicon-germanium (SiGe) in the self-sacrificing nanostructure layer 120 and the intermixed layer 130. As shown in region 715 of Figure 7C, fluorine (F) in fluorine-based etchants (e.g., F2 gas) and / or hydrofluoric acid etchants (e.g., HF gas) can adhere to silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130. Furthermore, hydrogen in the hydrofluoric acid etchant of etchant 705 can adhere to silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130. Fluorine and hydrogen react with germanium to form germanium hydrogen fluoride (GeH3F) and silicon hydrogen fluoride (SiHF2). Hydrogen migration (H migration) may occur, in which hydrogen (H) atoms migrate from silicon hydrogen fluoride molecules to germanium hydrogen fluoride molecules, thereby forming germanium trifluoride (GeH3F) gas and silicon difluoride (SiF2). The germanium trifluoride gas is removed from the semiconductor device 105, thereby removing germanium (Ge) from the sacrificial nanostructure layer 120 and the intermixed layer 130. Hydrogen (H) atom migration can occur at energies ranging from about 0.9 eV to about 1.0 eV. However, other values ​​and / or ranges of energy for fluorine (F) atom migration are within the scope of this disclosure. Hydrogen (H) atom migration can be an exothermic process, wherein the enthalpy change (∆H) is included in the range of about -0.75 eV to about -0.9 eV. However, other values ​​and / or ranges of enthalpy change are also within the scope of this disclosure.

[0061] In some implementations, during the etching operation, the gas flow rate of the fluorine-based etchant (e.g., F2 gas) entering the processing chamber can be as high as about 300 sccm to achieve sufficient etching rates for the silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130. However, other values ​​and ranges of the gas flow rate of the fluorine-based etchant are within the scope of this disclosure.

[0062] In some implementations, during the etching operation, the gas flow rate of the hydrofluoric acid etchant (e.g., HF gas) entering the processing chamber can be as high as about 50 sccm to achieve a sufficient etching rate for germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130. However, other values ​​and ranges of the hydrofluoric acid etchant gas flow rate are within the scope of this disclosure.

[0063] As further illustrated in Figures 7C to 7E, during the etching operation, portions of the nanostructure channel 315 are also etched to remove the sacrificial nanostructure layer 120. Material removal from the top and bottom of the nanostructure channel 315 results in the nanostructure channel 315 having a tapered or curved cross-sectional profile along its width (e.g., along the y-direction). As described above, the etchant 705 laterally etches the sacrificial nanostructure layer 120 starting from its edge and continuing to the center. Therefore, the etchant 705 is in contact with the edge of the nanostructure channel 315 for a longer period than it is in contact with the center of the nanostructure channel 315 along the y-direction. This varying exposure duration to the etchant 705 results in a greater amount of etching at the edge of the nanostructure channel 315 (and therefore, a greater amount of material removed from the edge) than at the center. This results in a tapered or curved cross-sectional profile along the width (e.g., along the y-direction) of the nanostructure channel 315.

[0064] As described above, the removal of silicon (Si) from the sacrificial nanostructure layer 120 and the intermixed layer 130 involves the migration of fluorine (F) between molecules formed by silicon (Si) and germanium (Ge) in the sacrificial nanostructure layer 120 and the intermixed layer 130. However, the nanostructure channel 315 may not include germanium (Ge) and may only include silicon (Si). To remove silicon (Si) from the nanostructure channel 315 in the absence of germanium (Ge), an etching operation can be performed at a high temperature to provide sufficient energy to remove silicon (Si) from the nanostructure channel 315 using a fluorine-based etchant (e.g., F2 gas) in the etchant 705.

[0065] For example, the temperature in the processing chamber can be raised to above 50 degrees Celsius and as high as about 75 degrees Celsius. The etching operation can be performed when the temperature in the processing chamber is within this range to achieve the following reaction between the fluorine-based etchant (e.g., F2 gas) in the etchant 705 and the silicon (Si) in the nanostructure channel 315: The fluorine-based etchant (e.g., F2 gas) in etchant 705 reacts with silicon (Si) in nanostructure channel 315 to form silicon tetrafluoride (SiF4) gas. The silicon tetrafluoride gas is removed from semiconductor device 105, resulting in the removal of silicon (Si) from nanostructure channel 315. The reaction can occur at energies in the range of about 1.1 electron volts (eV) to about 1.2 eV. However, other values ​​and / or ranges for the reaction are within the scope of this disclosure.

[0066] Figure 7F illustrates the cross-sectional profile of the nanostructure channel 315 after the etching operation. As shown in Figure 7F, the nanostructure channel 315 may each have a top inclined segment 720 and a bottom inclined segment 725. The top inclined segment 720 may correspond to a cross-sectional segment along the y-direction between the center 730 and the outer edge 735 of the nanostructure channel 315. The top inclined segment 720 is part of the top surface of the nanostructure channel 315 and is inclined or angled between the center 730 and the outer edge 735 of the nanostructure channel 315. Alternatively, the top inclined segment 720 may be a curved segment. The bottom inclined segment 725 may correspond to a cross-sectional segment along the y-direction between the center 730 and the outer edge 735 of the nanostructure channel 315. The bottom inclined segment 725 is part of the bottom surface of the nanostructure channel 315 and is inclined or angled between the center 730 and the outer edge 735 of the nanostructure channel 315. Alternatively, the bottom sloping section 725 can be a curved section.

[0067] As further shown in Figure 7F, the nanostructure channel 315 may have dimensions D3 and D4. Dimension D3 corresponds to the z-direction (vertical) thickness at the center 730 of the nanostructure channel 315 (e.g., the center of the width along the y-direction of the nanostructure channel 315), and dimension D4 corresponds to the z-direction (vertical) thickness at the outer edge 735 of the nanostructure channel 315 (e.g., the outer edge of the width along the y-direction of the nanostructure channel 315). Since the nanostructure channel 315 is etched during the etching operation of the wafer release process, the z-direction thickness at the outer edge 735 of the nanostructure channel 315 after the wafer release process (e.g., after the etching operation of the wafer release process) is less than the z-direction thickness at the outer edge 735 of the nanostructure channel 315 before the wafer release process (e.g., dimension D4 < dimension D2).

[0068] Furthermore, as described above, due to the different durations of exposure of the center 730 and the outer edge 735 to the etchant 705, the amount of etching at the outer edge 735 of the nanostructure channel 315 (and thus, the amount of material removed from the outer edge 735) is greater than the amount of etching at the center 730 of the nanostructure channel 315. Therefore, after the nanosheet release process, the z-direction thickness of the outer edge 735 of the nanostructure channel 315 is less than the z-direction thickness of the center 730 of the nanostructure channel 315 after the nanosheet release process (e.g., dimension D4 < dimension D3). Consequently, the z-direction thickness of the nanostructure channel 315 decreases in the y-direction from the center 730 to the outer edge 735 of the nanostructure channel 315 along the top inclined segment 720 and the bottom inclined segment 725. In some implementations, the transition may be a uniform linear transition (e.g., the top inclined segment 720 and the bottom inclined segment 725 are straight lines at an angle) or a non-uniform transition (e.g., the top inclined segment 720 and the bottom inclined segment 725 are curved).

[0069] Because the thickness in the z-direction differs between the center 730 and the outer edge 735 of the nanostructure channel 315, the vertical (z-direction) spacing between vertically adjacent (e.g., adjacent in the z-direction) nanostructure channels 315 may differ at the center 730 of the nanostructure channel 315 from that at the outer edge 735. Specifically, the vertical (z-direction) spacing at the center 730 of vertically adjacent nanostructure channels 315 (denoted as dimension D5 in Figure 7F) may be smaller than the vertical (z-direction) spacing at the outer edge 735 of vertically adjacent nanostructure channels 315 (denoted as dimension D6 in Figure 7F). The larger vertical spacing at the outer edge 735 of vertically adjacent nanostructure channels 315 provides a larger area for the gate structure material to flow into the space between the vertically adjacent nanostructure channels 315, thereby improving the gap filling performance when forming the gate structure. An exemplary embodiment of forming a gate structure of semiconductor device 105 is illustrated and described in conjunction with Figures 9A to 9C.

[0070] As further shown in Figure 7F, the top inclined segment 720 of the second nanostructure channel 315 may have an angle (denoted as dimension D7 in Figure 7F) relative to the center 730 of the top surface of the first nanostructure channel 315, and the bottom inclined segment 725 of the first nanostructure channel 315, which is perpendicular to the first nanostructure channel 315, may have an angle (denoted as dimension D8 in Figure 7F) relative to the center 730 of the bottom surface of the second nanostructure channel 315. These angles result in the angle between the outer edges 735 of the first and second nanostructure channels 315 (denoted as dimension D9 in Figure 7F) (relative to the center point between the first and second nanostructure channels 315) being larger than when the first and second nanostructure channels 315 have a uniform z-direction (vertical) thickness. The larger the angle between the outer edges 735, the larger the area of ​​the gate structure material that can flow into the space between the first and second nanostructure channels 315, thereby improving the gap filling performance when forming the gate structure.

[0071] As described above, Figures 7A through 7F are provided as examples. Other examples may differ from those described for Figures 7A through 7F.

[0072] Figures 8A to 8J are schematic diagrams of an exemplary embodiment 800 of the nanosheet release process described herein. The exemplary embodiment 800, illustrated and described in conjunction with Figures 8A to 8J, is an alternative to the nanosheet release process illustrated and described in conjunction with Figures 7A to 7F. Figures 8A to 8J are illustrated from the angle of section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the operations described in conjunction with Figures 1A to 6.

[0073] The nanosheet release process illustrated in Figures 8A to 8J is performed using a process at a lower temperature than the nanosheet release process described and illustrated in Figures 7A to 7F. The nanosheet release process described and illustrated in Figures 8A to 8J is a cyclic process comprising multiple etch-clear cycles performed at a temperature of about 50 degrees Celsius or lower, such as from about 30 degrees Celsius to about 50 degrees Celsius. However, other values ​​and ranges of temperature for the exemplary implementation 800 of the nanosheet release process described and illustrated in Figures 8A to 8J are within the scope of this disclosure. Performing the nanosheet release process at a temperature of about 50 degrees Celsius or lower reduces the likelihood that the gas etchant used in the nanosheet release process will etch the internal spacer 410 and damage the source / drain region 510 of the semiconductor device 105. However, as described in conjunction with Figures 7A through 7F, performing the nanosheet release process at temperatures above approximately 50 degrees Celsius allows for fewer process steps and less etchant to achieve the tapered or curved cross-sectional profile of the nanostructure channel 315, thereby reducing process complexity, time, and / or cost.

[0074] Figures 8A to 8C illustrate the first etch-clear cycle of the cyclic process, Figures 8D to 8F illustrate the second etch-clear cycle of the cyclic process, and Figures 8G to 8I illustrate the third etch-clear cycle of the cyclic process. However, the number of etch-clear cycles of the cyclic process illustrated in Figures 8A to 8I is an example, and other numbers are also within the scope of this disclosure. The etch-clear cycle of the cyclic process can be performed "in situ" because the semiconductor device 105 remains in the same processing chamber throughout the etch-clear cycle of the cyclic process (e.g., there is no need to remove the semiconductor device 105 from the processing chamber).

[0075] As shown in Figures 8A and 8B, the first etch-clear cycle of the cyclic process may include a first etch operation, wherein etchant 705 is used to remove a first portion of the sacrificial nanostructure layer 120. A portion of the intermixed layer 130 and / or a portion of the nanostructure channel 315 may also be removed in the first etch operation.

[0076] As shown in Figure 8C, during the first etch operation, byproduct 805 may be deposited onto the nanostructure channel 315. During the first etch operation, byproduct 805 may correspond to etching byproducts formed by material removal from the self-sacrificing nanostructure layer 120, the intermixed layer 130, and / or the nanostructure channel 315. These byproducts 805 may inhibit further etching of the nanostructure channel 315. Therefore, the first etch-clean cycle of the cycle process may further include a first clean operation, performing the first clean operation to remove the byproduct 805, so that the nanostructure channel 315 can be further etched using the etchant 705.

[0077] The first purging operation may include supplying a purging gas into the processing chamber and pumping the purging gas out of the processing chamber (e.g., the purging gas carries byproduct 805 out of the processing chamber). The purging gas may include one or more inert gases, such as argon (Ar) and / or nitrogen (N2), etc. In some embodiments, the flow rate of argon into the processing chamber may be up to about 500 sccm. However, other ranges and values ​​of argon flow rates are within the scope of this disclosure. In some embodiments, the flow rate of nitrogen into the processing chamber may be up to about 500 sccm. However, other ranges and values ​​of nitrogen flow rates are within the scope of this disclosure.

[0078] As shown in Figures 8D and 8E, the second etch-clean cycle of the cyclic process may include a second etch operation, wherein etchant 705 is used to remove a second portion of the sacrificial nanostructure layer 120. A portion of the intermixed layer 130 and / or a portion of the nanostructure channel 315 may also be removed in the second etch operation.

[0079] As shown in Figure 8F, during the second etch operation, byproduct 805 may be deposited onto the nanostructure channel 315. Therefore, the second etch-clean cycle of the cycle process may further include a second clean operation to remove byproduct 805, so that the nanostructure channel 315 can be further etched using etchant 705.

[0080] As shown in Figures 8G and 8H, the third etch-clean cycle of the cyclic process may include a third etch operation, in which etchant 705 is used to remove a third portion of the sacrificial nanostructure layer 120. A portion of the intermixed layer 130 and / or a portion of the nanostructure channel 315 may also be removed in the third etch operation.

[0081] As shown in Figure 8I, during the third etch operation, byproduct 805 may be deposited on the nanostructure channel 315. Therefore, the third etch-clean cycle of the cycle process may further include a third clean operation to remove byproduct 805, so that the nanostructure channel 315 can be further etched using etchant 705.

[0082] In some implementations, two or more etching operations in a cyclic process can be performed with the same process parameters, such as the same duration, the same chamber pressure, the same temperature, and / or the same etchant flow rate. In some implementations, two or more etching operations in a cyclic process can be performed with different process parameters to achieve a specific cross-sectional profile of the nanostructure channel 315. For example, two or more etching operations in a cyclic process can be performed under conditions such as different durations, different chamber pressures, different chamber temperatures, and / or different etchant flow rates.

[0083] Figure 8J illustrates the cross-sectional profile of the nanostructure channel 315 after the etching operation. As shown in Figure 8J, the nanostructure channel 315 may each have a top inclined segment 720 and a bottom inclined segment 725. The top inclined segment 720 may correspond to a cross-sectional segment along the y-direction between the center 730 and the outer edge 735 of the nanostructure channel 315. The top inclined segment 720 is part of the top surface of the nanostructure channel 315 and is inclined or angled between the center 730 and the outer edge 735 of the nanostructure channel 315. Alternatively, the top inclined segment 720 may be a curved segment. The bottom inclined segment 725 may correspond to a cross-sectional segment along the y-direction between the center 730 and the outer edge 735 of the nanostructure channel 315. The bottom inclined segment 725 is part of the bottom surface of the nanostructure channel 315 and is inclined or angled between the center 730 and the outer edge 735 of the nanostructure channel 315. Alternatively, the bottom sloping section 725 can be a curved section.

[0084] As described above, Figures 8A through 8J are provided as examples. Other examples may differ from those described for Figures 8A through 8J.

[0085] Figures 9A to 9C are schematic diagrams of an exemplary embodiment 900 of the gate formation process described herein. The gate formation process may be performed as part of a replacement gate process, which replaces the dummy gate structure 205 of the nanostructured transistor of the semiconductor device 105 with a gate structure 905 (e.g., a high-k / metal gate structure). Figures 9A to 9C are illustrated from the angle of section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 900 are performed after one or more operations described in conjunction with Figures 1A to 8J.

[0086] As shown in Figure 9A, the gate dielectric layer 910 of the gate structure 905 may be formed around the nanostructure channel 315. In some embodiments, the gate dielectric layer 910 is also formed on the mesa region 310. The gate dielectric layer 910 can be deposited using deposition tools employing PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, the gate dielectric layer 910 is a high-k gate dielectric layer, comprising one or more high-k materials (e.g., dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO2, dielectric constant approximately 3.9)). Examples include lanthanum oxide (LaxOy, such as La2O3), hafnium oxide (HfOx, such as HfO2), zirconium oxide (ZrOx, such as ZrO2), and / or aluminum oxide (AlxOy, such as Al2O3), etc. Alternatively and / or, silicon dioxide (SiO2) and / or another dielectric material may be used instead of a high-k dielectric material. In some embodiments, the thickness of the gate dielectric layer 910 may range from about 0.5 nanometers to about 3 nanometers. However, other values ​​in the range are also within the scope of this disclosure.

[0087] As shown in Figure 9B, a work function metal layer 915 of the gate structure 905 is formed on the gate dielectric layer 910. The work function metal layer 915 can be deposited using deposition tools with CVD, PVD, ALD, electroplating and / or other suitable deposition techniques.

[0088] A work function metal layer 915 may be included to tune the work function of the gate structure 905. In some embodiments, the gate structure 905 is a p-type gate structure for a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, and the work function metal layer 915 is a p-type work function metal layer. In these embodiments, the work function metal layer 915 may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals with a work function greater than about 4.7 eV, to tune the work function of the gate structure 905 such that the work function is adjusted to be close to the valence band (EV) of the material of the nanostructure channel 315. In some embodiments, the gate structure 905 is an n-type gate structure for an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor, and the work function metal layer 915 is an n-type work function metal layer. In these embodiments, the work function metal layer 915 may include one or more n-type metals, such as titanium aluminum (TiAl) and / or titanium aluminum carbon (TiAlC), to tune the work function of the gate structure 905 so that the work function is close to the conduction band (EC) of the material of the nanostructure channel 315.

[0089] A work function metal layer 915 can be formed such that the work function metal layer 915 surrounds one or more sides of the nanostructure channel 315. In some embodiments, the material of the work function metal layer 915 is deposited between vertically adjacent nanostructure channels 315. In some embodiments, the work function metal layer 915 is merged between vertically adjacent nanostructure channels 315. The tapered or curved cross-sectional profile achieved for the nanostructure channel 315 using the nanosheet release technique described in conjunction with Figures 7A to 7F and / or Figures 8A to 8J provides improved gap-filling performance for depositing the work function metal layer 915 between vertically adjacent nanostructure channels 315, which reduces the likelihood of seams / voids forming in the work function metal layer 915 between vertically adjacent nanostructure channels 315. Alternatively, the work function metal layers 915 are not merged, but spaced apart between vertically adjacent nanostructure channels 315, such that the work function metal layer 915 surrounding each nanostructure channel 315 is spaced apart from the work function metal layers 915 surrounding the vertically adjacent nanostructure channels 315.

[0090] As shown in Figure 9C, a gate electrode layer 920 of the gate structure 905 may be formed above the work function metal layer 915. The gate electrode layer 920 may be formed such that it surrounds one or more sides of the nanostructure channel 315. Material of the gate electrode layer 920 may be deposited between vertically adjacent nanostructure channels 315. The tapered or curved cross-sectional profile achieved for the nanostructure channel 315 using the nanosheet release technique described in conjunction with Figures 7A through 7F and / or Figures 8A through 8J provides improved gap-filling performance for depositing the gate electrode layer 920 between vertically adjacent nanostructure channels 315, reducing the likelihood of seams / voids forming in the gate electrode layer 920 between vertically adjacent nanostructure channels 315.

[0091] The gate electrode layer 920 comprises one or more conductive metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). The gate electrode layer 920 can be deposited using deposition tools employing CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The gate electrode layer 920 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then the gate electrode layer 920 is deposited on the seed layer. In some embodiments, after depositing the gate electrode layer 920, a planarization tool can be used to planarize the gate electrode layer 920.

[0092] Because the thickness in the z-direction differs between the center 730 and the outer edge 735 of the nanostructure channel 315, the z-direction (vertical) thickness of the gate structure 905 between vertically adjacent (e.g., adjacent in the z-direction) nanostructure channels 315 may also differ at the center 730 of the nanostructure channel 315 from that at the outer edge 735 of the nanostructure channel 315. Specifically, the z-direction (vertical) thickness of the gate structure 905 at the center 730 of the vertically adjacent nanostructure channel 315 (denoted as dimension D10 in Figure 9C) may be greater than the z-direction (vertical) thickness of the gate structure 905 at the outer edge 735 of the vertically adjacent nanostructure channel 315 (denoted as dimension D11 in Figure 9C).

[0093] As described above, Figures 9A through 9C are provided as examples. Other examples may differ from those described for Figures 9A through 9C.

[0094] Figure 10 is a schematic diagram of an exemplary embodiment 1000 of the semiconductor device 105 described herein. As shown in Figure 10, the semiconductor device 105 may include a plurality of nanostructure channels 315 (arranged along the z-direction) in the semiconductor device 105. The semiconductor device 105 includes a gate structure 905 surrounding the nanostructure channels 315 and a gate dielectric layer 910 located between the nanostructure channels 315 and the gate structure 905. The gate structure 905 may include a work function metal layer 915 and a gate electrode layer 920.

[0095] The z-direction thickness (dimension D3) at the center 730 of the nanostructure channel 315 may be greater than the z-direction thickness (dimension D4) at the outer edge 735 of the nanostructure channel 315. In some embodiments, the z-direction thickness at the center 730 of the nanostructure channel 315 is in the range of about 3 nanometers to about 8 nanometers, while the z-direction thickness at the outer edge 735 of the nanostructure channel 315 is in the range of about 2 nanometers to about 7 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0096] The z-direction distance or spacing (dimension D6) between the outer edges 735 of vertically adjacent nanostructure channels 315 may be greater than the z-direction distance or spacing (dimension D5) at the center 730 of vertically adjacent nanostructure channels 315. In some embodiments, the z-direction distance or spacing at the center 730 of vertically adjacent nanostructure channels 315 is in the range of about 8 nanometers to about 13 nanometers, while the z-direction distance or spacing at the outer edges 735 of vertically adjacent nanostructure channels 315 is in the range of about 9 nanometers to about 13 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0097] In some embodiments, the gate structure 905 is an n-type gate structure, and the nanostructure channel 315 may have a sheet width (denoted as dimension D12 in Figure 10), ranging from approximately 30 nanometers to approximately 80 nanometers. In these embodiments, the average z-direction thickness of the top nanostructure channel 315a, the average z-direction thickness of the middle nanostructure channel 315b, and the average z-direction thickness of the bottom nanostructure channel 315c may each range from approximately 3 nanometers to approximately 7 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0098] Furthermore, in these embodiments, the difference between the z-direction thickness (dimension D3) at the center 730 of the top nanostructure channel 315a and the z-direction thickness (dimension D4) at the outer edge 735 of the top nanostructure channel 315a can range from about 0 nanometers to about 1.5 nanometers. The difference between the z-direction thickness (dimension D3) at the center 730 of the middle nanostructure channel 315b and the z-direction thickness (dimension D4) at the outer edge 735 of the middle nanostructure channel 315b can range from about 1 nanometer to about 2.5 nanometers. The difference between the z-direction thickness (dimension D3) at the center 730 of the bottom nanostructure channel 315c and the z-direction thickness (dimension D4) at the outer edge 735 of the bottom nanostructure channel 315c can range from about 1 nanometer to about 2.5 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0099] Furthermore, in these embodiments, the average spacing or distance between the top nanostructure channel 315a and the middle nanostructure channel 315b, the average spacing or distance between the middle nanostructure channel 315b and the bottom nanostructure channel 315c, and the average spacing or distance between the bottom nanostructure channel 315c and the mesa region 310 can each be included in the range of about 8 nanometers to about 13 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0100] Furthermore, in these embodiments, the difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the top nanostructure channel 315a and the middle nanostructure channel 315b and the z-direction distance or spacing (dimension D5) at the center 730 of the top nanostructure channel 315a and the middle nanostructure channel 315b can range from about 0 nanometers to about 2 nanometers. The difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c and the z-direction distance or spacing (dimension D5) at the center 730 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c can range from about 0.5 nanometers to about 2.5 nanometers. The difference between the z-direction distance or spacing (dimension D6) at the outer edge 735 of the bottom nanostructure channel 315c and the mesa region 310 and the z-direction distance or spacing (dimension D5) at the center 730 of the bottom nanostructure channel 315c and the mesa region 310 can range from about 0 nanometers to about 2 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0101] Furthermore, in these embodiments, the angle (dimension D7) of the top inclined section 720 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, and the angle (dimension D8) of the bottom inclined section 725 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, can each be included in the range of about 1 degree to about 6 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0102] Furthermore, in these embodiments, the angle (dimension D9) between the outer edge 735 of the top nanostructure channel 315a and the outer edge 735 of the middle nanostructure channel 315b, the angle between the outer edge 735 of the middle nanostructure channel 315b and the outer edge 735 of the bottom nanostructure channel 315c, and the angle between the outer edge 735 of the bottom nanostructure channel 315c and the outer edge 735 of the mesa region 310 can each be included in the range of approximately 15 degrees to approximately 23 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0103] In some embodiments, the gate structure 905 is a p-type gate structure, and the nanostructure channel 315 may have a sheet width (size D12) ranging from about 30 nanometers to about 80 nanometers. In these embodiments, the average z-direction thickness of the top nanostructure channel 315a may range from about 4 nanometers to about 8 nanometers, while the average z-direction thickness of the middle nanostructure channel 315b and the average z-direction thickness of the bottom nanostructure channel 315c may each range from about 3.5 nanometers to about 7.5 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0104] Furthermore, in these embodiments, the difference between the z-direction thickness (dimension D3) at the center 730 of the top nanostructure channel 315a and the z-direction thickness (dimension D4) at the outer edge 735 of the top nanostructure channel 315a can range from about 0 nanometers to about 1.5 nanometers. The difference between the z-direction thickness (dimension D3) at the center 730 of the middle nanostructure channel 315b and the z-direction thickness (dimension D4) at the outer edge 735 of the middle nanostructure channel 315b can range from about 1 nanometer to about 2.5 nanometers. The difference between the z-direction thickness (dimension D3) at the center 730 of the bottom nanostructure channel 315c and the z-direction thickness (dimension D4) at the outer edge 735 of the bottom nanostructure channel 315c can range from about 1 nanometer to about 2.5 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0105] Furthermore, in these embodiments, the average spacing or distance between the top nanostructure channel 315a and the middle nanostructure channel 315b, the average spacing or distance between the middle nanostructure channel 315b and the bottom nanostructure channel 315c, and the average spacing or distance between the bottom nanostructure channel 315c and the mesa region 310 can each be included in the range of about 7 nanometers to about 12 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0106] Furthermore, in these embodiments, the difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the top nanostructure channel 315a and the middle nanostructure channel 315b and the z-direction distance or spacing (dimension D5) at the center 730 of the top nanostructure channel 315a and the middle nanostructure channel 315b can range from about 0 nanometers to about 2 nanometers. The difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c and the z-direction distance or spacing (dimension D5) at the center 730 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c can range from about 0.5 nanometers to about 2.5 nanometers. The difference between the z-direction distance or spacing (dimension D6) at the outer edge 735 of the bottom nanostructure channel 315c and the mesa region 310 and the z-direction distance or spacing (dimension D5) at the center 730 of the bottom nanostructure channel 315c and the mesa region 310 can range from about 0 nanometers to about 2 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0107] Furthermore, in these embodiments, the angle (dimension D7) of the top inclined section 720 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, and the angle (dimension D8) of the bottom inclined section 725 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, can each be included in the range of about 1 degree to about 6 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0108] Furthermore, in these embodiments, the angle (dimension D9) between the outer edge 735 of the top nanostructure channel 315a and the outer edge 735 of the middle nanostructure channel 315b, the angle between the outer edge 735 of the middle nanostructure channel 315b and the outer edge 735 of the bottom nanostructure channel 315c, and the angle between the outer edge 735 of the bottom nanostructure channel 315c and the outer edge 735 of the mesa region 310 can each be included in the range of approximately 15 degrees to approximately 23 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0109] In some embodiments, the gate structure 905 is a p-type gate structure or an n-type gate structure, and the nanostructure channel 315 may have a sheet width (size D12) ranging from about 5 nanometers to about 30 nanometers. In these embodiments, the average z-direction thickness of the top nanostructure channel 315a may range from about 3 nanometers to about 7 nanometers, while the average z-direction thickness of the middle nanostructure channel 315b and the average z-direction thickness of the bottom nanostructure channel 315c may each range from about 2 nanometers to about 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0110] Furthermore, in these embodiments, the difference between the z-direction thickness (dimension D3) at the center 730 of the top nanostructure channel 315a and the z-direction thickness (dimension D4) at the outer edge 735 of the top nanostructure channel 315a can range from about -0.5 nm to about 1 nm. The difference between the z-direction thickness (dimension D3) at the center 730 of the middle nanostructure channel 315b and the z-direction thickness (dimension D4) at the outer edge 735 of the middle nanostructure channel 315b can range from about -0.5 nm to about 0.5 nm. The difference between the z-direction thickness (dimension D3) at the center 730 of the bottom nanostructure channel 315c and the z-direction thickness (dimension D4) at the outer edge 735 of the bottom nanostructure channel 315c can range from about -0.5 nm to about 0.5 nm. However, other values ​​and ranges are also within the scope of this disclosure.

[0111] Furthermore, in these embodiments, the average spacing or distance between the top nanostructure channel 315a and the middle nanostructure channel 315b, the average spacing or distance between the middle nanostructure channel 315b and the bottom nanostructure channel 315c, and the average spacing or distance between the bottom nanostructure channel 315c and the mesa region 310 can each be included in the range of about 8 nanometers to about 13 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0112] Furthermore, in these embodiments, the difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the top nanostructure channel 315a and the middle nanostructure channel 315b and the z-direction distance or spacing (dimension D5) at the center 730 of the top nanostructure channel 315a and the middle nanostructure channel 315b can be in the range of approximately -0.5 nm to approximately 0.5 nm. The difference between the z-direction distance or spacing (dimension D6) at the outer edges 735 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c and the z-direction distance or spacing (dimension D5) at the center 730 of the middle nanostructure channel 315b and the bottom nanostructure channel 315c can be in the range of approximately -0.5 nm to approximately 0.5 nm. The difference between the z-direction distance or spacing (dimension D6) at the outer edge 735 of the bottom nanostructure channel 315c and the mesa region 310 and the z-direction distance or spacing (dimension D5) at the center 730 of the bottom nanostructure channel 315c and the mesa region 310 can be in the range of about -0.5 nanometers to about 0.5 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0113] Furthermore, in these embodiments, the angle (dimension D7) of the top inclined section 720 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, and the angle (dimension D8) of the bottom inclined section 725 of the top nanostructure channel 315a, the middle nanostructure channel 315b, and the bottom nanostructure channel 315c, can each be included in the range of about 0 degrees to about 2 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0114] Furthermore, in these embodiments, the angle (dimension D9) between the outer edge 735 of the top nanostructure channel 315a and the outer edge 735 of the middle nanostructure channel 315b, the angle between the outer edge 735 of the middle nanostructure channel 315b and the outer edge 735 of the bottom nanostructure channel 315c, and the angle between the outer edge 735 of the bottom nanostructure channel 315c and the outer edge 735 of the mesa region 310 can each be included in the range of approximately 35 degrees to approximately 50 degrees. Within this range, sufficient gap-filling performance can be achieved to reduce the likelihood of forming gaps / voids in the gate structure 905. However, other values ​​and ranges are also within the scope of this disclosure.

[0115] As described above, Figure 10 is provided as an example. Other examples may differ from those described with respect to Figure 10.

[0116] Figure 11 is a schematic diagram of an exemplary embodiment 1100 of the semiconductor device 105 described herein. As shown in Figure 11, the semiconductor device 105 may include a plurality of nanostructure channels 315 (arranged along the z-direction) within the semiconductor device 105. The top nanostructure channel 315a differs from the nanostructure channels 315 in Figures 7F and 8J in that the top nanostructure channel 315a in exemplary embodiment 1100 has a substantially flat top surface. Therefore, the angle of the top surface of the top nanostructure channel 315a in exemplary embodiment 1100 (denoted as dimension D13 in Figure 11) can be in the range of about 0 degrees to about 2 degrees. However, other ranges and values ​​are also within the scope of this disclosure.

[0117] As described above, Figure 11 is provided as an example. Other examples may differ from those described with respect to Figure 11.

[0118] Figure 12 is a flowchart of an exemplary process 1200 associated with forming the semiconductor structure described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 12.

[0119] As shown in Figure 12, process 1200 may include the following steps: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1210). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured semiconductor layers (e.g., nanostructured channel layer 125) and a plurality of sacrificial nanostructured layers (e.g., sacrificial nanostructured layer 120), such that the nanostructured semiconductor layers and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105) (e.g., the z-direction), as described herein.

[0120] As further shown in Figure 12, process 1200 may include the following steps: performing a first etch operation to etch a nanostructured semiconductor layer and a sacrificial nanostructured layer to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate (block 1220). For example, one or more semiconductor processing tools may be used to perform the first etch operation to etch the nanostructured semiconductor layer and the sacrificial nanostructured layer to define a plurality of nanostructured channels (e.g., nanostructured channel 315) arranged in a direction approximately perpendicular to the semiconductor substrate, as described herein. In some embodiments, the nanostructured channels and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate.

[0121] As further shown in Figure 12, process 1200 may include the following step: performing a second etch operation to remove a sacrificial nanostructure layer (block 1230) from the semiconductor device. For example, one or more semiconductor processing tools may be used to perform the second etch operation to remove the sacrificial nanostructure layer from the semiconductor device, as described herein. In some embodiments, the second etch operation results in a nanostructure channel having a first cross-sectional thickness (e.g., dimension D3) at the center of the nanostructure channel (e.g., center 730) and a second cross-sectional thickness (e.g., dimension D4) at the outer edge of the nanostructure channel (e.g., outer edge 735). In some embodiments, the second cross-sectional thickness is smaller than the first cross-sectional thickness.

[0122] Process 1200 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with other implementations described elsewhere in this document.

[0123] In the first embodiment, the second cross-sectional thickness (e.g., dimension D2) at the outer edge of the nanostructure channel is greater before the second etching operation than after the second etching operation (e.g., dimension D4).

[0124] In the second embodiment, the step of performing the second etching operation, either alone or in combination with the first embodiment, includes the following steps: performing the second etching operation at a temperature greater than about 50 degrees Celsius and less than or about 75 degrees Celsius.

[0125] In the third embodiment, the step of performing the second etching operation, either alone or in combination with one or more of the first and second embodiments, includes the following steps: performing the second etching operation using a fluorine-based etchant, wherein during the second etching operation, the fluorine-based etchant removes material from the nanostructure channels.

[0126] In the fourth embodiment, the step of performing the second etching operation, either alone or in combination with one or more of the first to third embodiments, includes the following steps: performing the second etching operation using a hydrofluoric acid etchant, wherein during the second etching operation, the hydrofluoric acid etchant removes material from the sacrificial nanostructure layer.

[0127] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, at least one of a fluorine-based etchant or a hydrofluoric acid etchant removes material from the intermixed layer (e.g., intermixed layer 130) between the nanostructure channel and the sacrificial nanostructure layer in the sacrificial nanostructure layer.

[0128] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the amount of material removed from the center (e.g., center 730) of the nanostructure channel during the second etching operation is greater than the amount of material removed from the outer edge (e.g., outer edge 735) of the nanostructure channel.

[0129] Although Figure 12 shows an exemplary block of process 1200, in some implementations, process 1200 includes more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 12. Alternatively, two or more blocks of process 1200 may be executed in parallel.

[0130] Figure 13 is a flowchart of an exemplary process 1300 associated with forming the semiconductor structure described herein. In some implementations, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 13.

[0131] As shown in Figure 13, process 1300 may include the following steps: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1310). For example, one or more semiconductor processing tools may be used to form a plurality of nanostructured semiconductor layers (e.g., nanostructured channel layer 125) and a plurality of sacrificial nanostructured layers (e.g., sacrificial nanostructured layer 120), such that the nanostructured semiconductor layers and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105) (e.g., the z-direction), as described herein.

[0132] As further shown in Figure 13, process 1300 may include the following steps: performing a first etch operation to etch a nanostructured semiconductor layer and a sacrificial nanostructured layer to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate (block 1320). For example, one or more semiconductor processing tools may be used to perform the first etch operation to etch the nanostructured semiconductor layer and the sacrificial nanostructured layer to define a plurality of nanostructured channels (e.g., nanostructured channel 315) arranged in a direction approximately perpendicular to the semiconductor substrate, as described herein. In some embodiments, the nanostructured channels and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate.

[0133] As further shown in Figure 13, process 1300 may include the following steps: performing a plurality of second etch operations to remove a sacrificial nanostructure layer (block 1330) from the semiconductor device. For example, one or more semiconductor processing tools may be used to perform the plurality of second etch operations to remove the sacrificial nanostructure layer from the semiconductor device, as described herein. In some embodiments, the second etch operations result in the top and bottom surfaces of the nanostructure channel having sloping segments (e.g., top sloping segment 720, bottom sloping segment 725) between the center (e.g., center 730) and the outer edge (e.g., outer edge 735) of the nanostructure channel.

[0134] Process 1300 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.

[0135] In the first embodiment, the step of performing the second etching operation includes the following steps: performing a third etching operation to remove a first portion of the sacrificial nanostructure layer; and performing a fourth etching operation to remove a second portion of the sacrificial nanostructure layer.

[0136] In the second embodiment, the step of performing the second etching operation, either alone or in combination with the first embodiment, includes the following steps: performing a cleaning operation before the fourth etching operation to remove byproducts generated by the third etching operation.

[0137] In the third embodiment, the step of performing the second etching operation, either alone or in combination with one or more of the first and second embodiments, includes the following steps: performing the third etching operation, the cleaning operation, and the fourth etching operation in the same processing chamber.

[0138] In the fourth embodiment, the step of performing the second etching operation, either alone or in combination with one or more of the first to third embodiments, includes the following steps: performing the second etching operation at a temperature in the range of about 30 degrees Celsius to about 50 degrees Celsius.

[0139] In the fifth embodiment, the step of performing the second etching operation, either alone or in combination with one or more of the first to fourth embodiments, includes the following steps: performing the second etching operation using a fluorine-based etchant and a hydrofluoric acid etchant.

[0140] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, the hydrofluoric acid etchant removes material from the sacrificial nanostructure layer during the second etching operation.

[0141] In the seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, a fluorine-based etchant removes material from the nanostructure channels during the second etching operation.

[0142] Although Figure 13 shows an exemplary block of process 1300, in some implementations, process 1300 includes more blocks, fewer blocks, different blocks, or blocks with different arrangements than those shown in Figure 13. Alternatively, two or more blocks of process 1300 may be executed in parallel.

[0143] In this manner, the nanostructure channels of a nanostructured transistor are etched during the nanosheet release process to remove sacrificial nanostructure layers between the nanostructure channels. The nanostructure channels are etched such that the thickness of the nanostructure channels at their edges is less than the thickness at their center. This results in a sloping / tapered or curved cross-sectional profile between the center and edges of the nanostructure channels. The resulting cross-sectional profile provides a larger opening between vertically adjacent nanostructure channels for depositing material for the gate structure of the nanostructured transistor between these vertically adjacent channels. The larger opening increases the gap-filling performance of the gate structure, which reduces the likelihood (and / or size) of seams and / or voids in the gate structure between vertically adjacent nanostructure channels. Therefore, the technique described herein can reduce the gate resistance and / or gate capacitance of nanostructured transistors, thereby improving their performance.

[0144] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method includes the steps of: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes the steps of: performing a first etching operation to etch the nanostructured semiconductor layers and the sacrificial nanostructured layers to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructured channels and the sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes the steps of: performing a second etching operation to remove the sacrificial nanostructured layers from the semiconductor device, wherein the second etching operation causes the nanostructured channels in the nanostructured channels to have a first cross-sectional thickness at the center of the nanostructured channel and a second cross-sectional thickness at the outer edge of the nanostructured channel, and wherein the second cross-sectional thickness is less than the first cross-sectional thickness.

[0145] In some embodiments, the second cross-sectional thickness at the outer edge of the nanostructure channel is greater before the second etching operation than after the second etching operation. In some embodiments, performing the second etching operation includes performing the second etching operation at a temperature greater than about 50 degrees Celsius and less than or about 75 degrees Celsius. In some embodiments, performing the second etching operation includes performing the second etching operation using a fluorine-based etchant, wherein the fluorine-based etchant removes material from the nanostructure channel during the second etching operation. In some embodiments, performing the second etching operation includes performing the second etching operation using a hydrofluoric acid etchant, wherein the hydrofluoric acid etchant removes material from the sacrificial nanostructure layer during the second etching operation. In some embodiments, at least one of the fluorine-based etchant or the hydrofluoric acid etchant removes material from the intermixed layer between the nanostructure channel and the sacrificial nanostructure layer in the sacrificial nanostructure layer. In some embodiments, the amount of material removed from the center of the nanostructure channel in the second etching operation is greater than the amount of material removed from the plurality of outer edges of the nanostructure channel.

[0146] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor device. The method includes the steps of: forming a plurality of nanostructured semiconductor layers and a plurality of sacrificial nanostructured layers, such that the nanostructured semiconductor layers and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The method includes the steps of: performing a first etching operation to etch the nanostructured semiconductor layers and sacrificial nanostructured layers to define a plurality of nanostructured channels arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructured channels and sacrificial nanostructured layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes the steps of: performing a plurality of second etching operations to remove the sacrificial nanostructured layers from the semiconductor device, wherein the second etching operations cause the top and bottom surfaces of the nanostructured channels to have inclined segments between the center of the nanostructured channel and the outer edge of the nanostructured channel.

[0147] In some embodiments, performing the second etching operation includes performing a third etching operation to remove a plurality of first portions of the sacrificial nanostructure layer, and performing a fourth etching operation to remove a plurality of second portions of the sacrificial nanostructure layer. In some embodiments, performing the second etching operation includes performing a cleaning operation prior to the fourth etching operation to remove a plurality of byproducts generated by the third etching operation. In some embodiments, performing the second etching operation includes performing the third etching operation, the cleaning operation, and the fourth etching operation in the same processing chamber. In some embodiments, performing the second etching operation includes performing the second etching operation at a temperature in the range of about 30 degrees Celsius to about 50 degrees Celsius. In some embodiments, performing the second etching operation includes performing the second etching operation using a fluorine-based etchant and a hydrofluoric acid etchant. In some embodiments, the hydrofluoric acid etchant removes material from the sacrificial nanostructure layer during the second etching operation. In some embodiments, the fluorine-based etchant removes material from the nanostructure channels during the second etching operation.

[0148] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device, wherein a first distance between the outer edges of perpendicularly adjacent nanostructured channels is greater than a second distance between the centers of perpendicularly adjacent nanostructured channels. The semiconductor device includes a gate structure surrounding the nanostructured channels. The semiconductor device includes a first source / drain region adjacent to a first side of the gate structure. The semiconductor device includes a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side.

[0149] In some embodiments, the first thickness of the gate structure between the outer edges of vertically adjacent nanostructure channels is greater than the second thickness of the gate structure between the centers of vertically adjacent nanostructure channels. In some embodiments, the first thickness of the outer edges of vertically adjacent nanostructure channels is greater than the second thickness of the centers of vertically adjacent nanostructure channels. In some embodiments, the angle between the center of the nanostructure channel and the inclined segment of the nanostructure channel is in the range of about 1 degree to about 6 degrees. In some embodiments, the first angle between the center of the nanostructure channel and the top inclined segment of the nanostructure channel and the second angle between the center of the nanostructure channel and the bottom inclined segment are different angles.

[0150] The terms "approximately" and "substantially" may indicate that the value of a given quantity varies within 5% of its value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, in accordance with this disclosure, the terms "approximately" and "substantially" may refer to a percentage of the value of a given quantity.

[0151] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to the equivalent constructions without departing from the spirit and scope of this disclosure.

[0152] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Nanostructure Layer 125: Nanostructured Channel Layer 130: Intermixed Layer 135: Hard mask layer 140: Overlay 145: Oxide layer 150: Nitride layer 155: Fin-shaped structure 155a: First fin-shaped structure subset 155b: Second fin-shaped structure subset 160: Part 165: Fin-shaped part 170: Padding 175: STI region 205: Virtual gate structure 210: Gate electrode layer 215: Hard mask layer 220: Spacer layer 225: Gate dielectric layer 305: Source / Drain Groove 310: Countertop area 315: Nanostructured Channel 315a: Top nanostructure channel 315b: Intermediate nanostructure channel 315c: Bottom nanostructure channel 405: Cavity 410: Internal spacers 505: Buffer Area 510: Source / Drain Region 515: Covering layer 605: Dielectric layer 705: Etching Agent 710, 715: Areas 720: Top sloping section 725: Bottom sloping section 730: Center 735: Outer edge 805: Byproduct 905: Gate structure 910: Gate dielectric layer 915: Work function metal layer 920: Gate electrode layer 1200, 1300: Process Blocks 1210, 1220, 1230, 1310, 1320, 1330: AA, BB, CC: Cross-sections D1~D13: Dimensions x, y, z: Direction

[0153] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure semiconductor layers and a plurality of sacrificial nanostructure layers, such that the nanostructure semiconductor layers and the sacrificial nanostructure layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; performing a first etching operation to etch the nanostructure semiconductor layers and the sacrificial nanostructure layers to define a plurality of nanostructure channels, the nanostructure channels being arranged in a direction approximately perpendicular to the semiconductor substrate, wherein the nanostructure channels and the sacrificial nanostructure layers are arranged alternately in a direction approximately perpendicular to the semiconductor substrate; and performing a second etching operation to remove the sacrificial nanostructure layers from the semiconductor device, wherein the second etching operation produces a nanostructure channel among the nanostructure channels, the nanostructure channel having a first cross-sectional thickness at a center of the nanostructure channel and a second cross-sectional thickness at a plurality of outer edges of the nanostructure channel, wherein the second cross-sectional thickness is smaller than the first cross-sectional thickness.

2. The method as described in claim 1, wherein the thickness of the second cross section at the outer edges of the nanostructure channel is greater before the second etching operation than after the second etching operation.

3. The method as described in claim 1, wherein the step of performing the second etching operation comprises the following steps: performing the second etching operation at a temperature greater than about 50 degrees Celsius and less than or about 75 degrees Celsius.

4. A method of forming a semiconductor device, comprising the steps of: forming a plurality of nanostructure semiconductor layers and a plurality of sacrificial nanostructure layers, such that the nanostructure semiconductor layers and the sacrificial nanostructure layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; performing a first etching operation to etch the nanostructure semiconductor layers and the sacrificial nanostructure layers to define a plurality of nanostructure channels arranged approximately perpendicular to the semiconductor substrate in the direction, wherein the nanostructure channels and the sacrificial nanostructure layers are arranged alternately in the direction approximately perpendicular to the semiconductor substrate; and performing a plurality of second etching operations to remove the sacrificial nanostructure layers from the semiconductor device, wherein the second etching operations cause a top surface and a bottom surface of a nanostructure channel of the nanostructure channels to have a plurality of inclined segments between a center of the nanostructure channel and a plurality of outer edges of the nanostructure channel.

5. The method as described in claim 4, wherein the step of performing the second etching operations comprises the following steps: performing the second etching operations using a fluorine-based etchant and a hydrofluoric acid etchant.

6. The method as described in claim 5, wherein the hydrofluoric acid etchant removes material from the sacrificial nanostructure layers during the second etching operations.

7. The method as described in claim 6, wherein the fluorine-based etchant removes material from the nanostructure channels during the second etching operations.

8. A semiconductor device comprising: a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device, wherein a first distance between a plurality of outer edges of a plurality of vertically adjacent nanostructure channels is greater than a second distance between a plurality of centers of the plurality of vertically adjacent nanostructure channels; a gate structure surrounding the nanostructure channels, wherein a first thickness of the gate structure between the outer edges of the vertically adjacent nanostructure channels is different from a second thickness of the gate structure between the centers of the vertically adjacent nanostructure channels; a first source / drain region adjacent to a first side of the gate structure; and a second source / drain region adjacent to a second side of the gate structure, the second side being opposite to the first side.

9. The semiconductor device as claimed in claim 8, wherein an angle between a center of a nanostructure channel and an inclined segment of the nanostructure channel is in the range of about 1 degree to about 6 degrees.

10. The semiconductor device as claimed in claim 8, wherein a first angle between a center of one nanostructure channel and a top inclined segment of the nanostructure channel and a second angle between the center of the nanostructure channel and a bottom inclined segment of the nanostructure channel are different angles.

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