Package structure including at least two dice

Abstract

A packaging structure, an assembly structure, and a manufacturing method are provided. The packaging structure includes a molding structure, a first top die, and a second top die. The molding structure includes a first electronic component, a second electronic component, and an encapsulant encapsulating the first electronic component and the second electronic component. The first top die is electrically connected to the first electronic component and the second electronic component. The second top die is electrically connected to the second electronic component.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113122008, filed on June 14, 2024, which claims priority and benefits over U.S. Official Application No. 18 / 640,229, filed on April 19, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a packaging structure, an assembly structure, and a method for manufacturing the same; more specifically, it relates to a packaging structure including at least one passive element, an assembly structure including the packaging structure, and a method for manufacturing the same. Prior Technology

[0003] Semiconductor electronic components are widely used in various electronic applications, and their size is constantly shrinking to meet current application requirements. However, shrinking the size of semiconductor electronic components brings challenges that affect their final electrical characteristics, quality, cost, and yield. As semiconductor electronic components become smaller, they require multifunctionality and high-capacity data processing capabilities. Therefore, the need to increase the integration of semiconductor components used in these electronic components is growing. However, due to limitations in semiconductor integration technology, meeting all functional requirements using only a single semiconductor wafer is challenging. To address this issue, semiconductor packages comprising multiple semiconductor wafers have been developed.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a packaging structure including: a molding structure, a first top die, and a second top die. The molding structure includes a first electronic component, a second electronic component, and an encapsulant. The first electronic component includes a plurality of first top pads. The second electronic component is disposed side-by-side with the first electronic component and includes a plurality of first top pads and a plurality of second top pads. The encapsulant encapsulates the first electronic component and the second electronic component. The first top die is disposed on the molding structure and includes a plurality of first bonding pads and a plurality of second bonding pads. The plurality of first bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first top pads of the first electronic component. The plurality of second bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first top pads of the second electronic component. The second top die is disposed on the molded structure and includes a plurality of bonding pads, wherein the plurality of bonding pads are substantially aligned with and electrically connected to the plurality of second top pads of the second electronic component.

[0006] Another aspect of this disclosure provides an assembly structure including: a substrate, a molding structure, a first top die, and a second top die. The molding structure is disposed on the substrate and electrically connected to the substrate. The molding structure includes a first electronic component, a second electronic component, and an encapsulant. The second electronic component is disposed side-by-side with the first electronic component. The function of the first electronic component is different from the function of the second electronic component. The encapsulant encapsulates the first electronic component and the second electronic component. A top surface of the first electronic component and a top surface of the second electronic component are substantially coplanar with a top surface of the encapsulant. A bottom surface of the first electronic component and a bottom surface of the second electronic component are substantially coplanar with a bottom surface of the encapsulant. The first top die is disposed on the molding structure and electrically connected to the first electronic component and the second electronic component, respectively. The second top die is disposed on the molding structure and electrically connected to the second electronic component.

[0007] Another aspect of this disclosure provides a manufacturing method. The manufacturing method includes: forming a molded structure, wherein the molded structure includes a first electronic component, a second electronic component disposed side-by-side with the first electronic component, and an encapsulant encapsulating the first electronic component and the second electronic component, wherein a function of the first electronic component is different from a function of the second electronic component; electrically connecting a first top die to the first electronic component and the second electronic component; and electrically connecting a second top die to the second electronic component, wherein the function of the first top die is different from the function of the second top die.

[0008] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0009] When referring to the drawings in conjunction with the embodiments and the scope of the claim, a more comprehensive understanding of the disclosure of this application can be obtained, wherein in all the drawings, the same element symbols represent similar elements, and: Figure 1 is a cross-sectional view illustrating the assembly structure of some embodiments of this disclosure; Figure 2 is an enlarged view, illustrating region "A" in Figure 1; Figure 3 is an enlarged view, illustrating region "B" in Figure 1; Figure 4 is an enlarged view, illustrating region "C" in Figure 1; Figure 5 is a cross-sectional view illustrating the assembly structure of some embodiments of this disclosure; Figure 6 is a cross-sectional view illustrating the assembly structure of some embodiments of this disclosure; Figures 7 to 15 are cross-sectional views illustrating various stages of a method for manufacturing an assembly structure according to some embodiments of this disclosure; Figures 16 to 18 are cross-sectional views illustrating various stages of a method for manufacturing an assembly structure according to some embodiments of this disclosure; Figure 19 is a top view illustrating the assembly structure of Figure 1; Figure 20 is a top view illustrating the assembly structure of some embodiments of this disclosure; Figure 21 is a flowchart illustrating a method for manufacturing an assembly structure according to some embodiments of this disclosure. Implementation

[0010] The embodiments or exemplary cases of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.

[0011] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0012] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context otherwise requires. It should be further understood that the terms "comprising" and "including," when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.

[0013] Figure 1 is a cross-sectional view illustrating the assembly structure 5 of some embodiments of this disclosure. Figure 2 is an enlarged view illustrating region "A" in Figure 1. Figure 3 is an enlarged view illustrating region "B" in Figure 1. Figure 4 is an enlarged view illustrating region "C" in Figure 1. In some embodiments, the assembly structure 5 may be a semiconductor electronic component, a semiconductor electronic structure, or a package structure. In some embodiments, the assembly structure 5 may include a package structure 9, a substrate 52, a plurality of bumps 56, and a plurality of external connectors 53.

[0014] The substrate 52 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 52 may include an insulator-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate 52 may include organic materials, glass, ceramic materials, or other similar materials. For example, substrate 52 may be made of a cured photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including a photoinitiator. For example, substrate 52 may include a homogeneous material. For example, the material of substrate 52 may include epoxy FR5, FR4, bismalleimide triazine (BT), printed circuit board (PCB) material, prepreg (PP), Ajinomoto build-up film (ABF), or other suitable materials.

[0015] The substrate 52 may have a first surface 521 (e.g., a top surface), a second surface 522 (e.g., a bottom surface), and a side surface 523. The second surface 522 (e.g., the bottom surface) may be opposite to the first surface 521 (e.g., the top surface). The side surface 523 may extend between the first surface 521 (e.g., the top surface) and the second surface 522 (e.g., the bottom surface). The substrate 52 may include a plurality of pads 524 exposed from the first surface 521 (e.g., the top surface) of the substrate 52.

[0016] An encapsulation structure 9 may be disposed on a first surface 521 of substrate 52 and may be attached to and electrically connected to a pad 524 exposed from the first surface 521 of substrate 52 via bumps 56. Each bump 56 may include a reflowable material, such as solder material comprising silver tin (AgSn). An external connector 53 may be disposed on a second surface 522 of substrate 52 to provide electrical connections to substrate 52, such as input / output (I / O) connections. Each external connector 53 may include a reflowable material, such as solder balls comprising silver tin (AgSn).

[0017] The package structure 9 can be a semiconductor package structure, a semiconductor electronic component, or a semiconductor electronic structure. The package structure 9 may include a molding structure 50, a first top die 6, a second top die 7, and a protective material 58.

[0018] A molding structure 50 may be disposed on and electrically connected to a substrate 52. The molding structure 50 may have a first surface 501 (e.g., a top surface), a second surface 502 (e.g., a bottom surface), and a side surface 503. The second surface 502 (e.g., the bottom surface) may be opposite to the first surface 501 (e.g., the top surface). The side surface 503 may extend between the first surface 501 (e.g., the top surface) and the second surface 502 (e.g., the bottom surface).

[0019] Referring to Figures 1 to 4, the molded structure 50 may include a first electronic component 1, a second electronic component 2, an intermediate electronic component 54, and an encapsulant 51. The functions, structures, and dimensions of the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 may differ from each other. For example, the first electronic component 1 may include a semiconductor device or an interposer. The second electronic component 2 may include a semiconductor bridging die, such as a logic die or a controller. The intermediate electronic component 54 may include a semiconductor die or wafer, such as a cache memory wafer (e.g., a dynamic random access memory (DRAM) wafer, or a static random access memory (SRAM) wafer, etc.).

[0020] The first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 are arranged side by side, and the encapsulant 51 encapsulates the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54. The first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 can be attached to and electrically connected to the pad 524 of the substrate 52 by means of bumps 56.

[0021] As shown in Figures 1 and 2, the first electronic component 1 may have a first surface 11 (e.g., a top surface or an active surface), a second surface 12 (e.g., a bottom surface or a back surface), and a side surface 13. The second surface 12 (e.g., a bottom surface) may be opposite to the first surface 11 (e.g., a top surface). The side surface 13 may extend between the first surface 11 (e.g., a top surface) and the second surface 12 (e.g., a bottom surface).

[0022] The first electronic component 1 may include a first main portion 10, a plurality of through holes 14, a first circuit structure 15, a plurality of first lower pads 18, and a plurality of second lower pads 19. The material of the first main portion 10 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0023] The through hole 14 may extend through the first main portion 10 and may include a plurality of first through holes 14a and a plurality of second through holes 14b.

[0024] A first circuit structure 15 may be disposed on the top surface 101 of the first main portion 10. The first circuit structure 15 may include a dielectric structure 151 (including a plurality of dielectric layers), at least one circuit layer 152, a plurality of first inner pads 153a, a plurality of second inner pads 153b, a plurality of first internal vias 154a, a plurality of second internal vias 154b, and a plurality of first upper pads 16. The circuit layer 152, the first inner pads 153a, the second inner pads 153b, the first internal vias 154a, the second internal vias 154b, and the first upper pads 16 are embedded in the dielectric structure 151. The top surface 161 of the first upper pads 16 may be exposed from the first surface 11 of the first electronic component 1. Each first upper pad 16 may be a hybrid bonding (HB) pad and may comprise copper or aluminum.

[0025] A first through hole 14a, a first internal pad 153a, a first internal through hole 154a, and a first lower pad 18 can be provided within the vertical projection of the first top die 6. A second through hole 14b, a second internal pad 153b, a second internal through hole 154b, and a second lower pad 19 can be provided outside the vertical projection of the first top die 6.

[0026] Circuit layer 152 can horizontally connect the first inner pad 153a and the second inner pad 153b. Circuit layer 152 can be a fan-out redistribution layer. First internal via 154a can vertically connect the first inner pad 153a and the first upper pad 16. The first inner pad 153a can be electrically connected to a plurality of upper endpoints of the first via 14a via the first internal via 154a. In some embodiments, the bottom dielectric layer and the bottom first internal via 154a can be omitted, and the first inner pad 153a can directly contact the first via 14a and the top surface 101 of the first main portion 10.

[0027] A first lower pad 18 may be disposed below the bottom surface 102 of the first main portion 10 and electrically connected to a plurality of lower endpoints of the first through hole 14a. In some embodiments, the first lower pad 18 may directly contact the first through hole 14a and the bottom surface 102 of the first main portion 10.

[0028] The second inner pad 153b can be electrically connected to a plurality of upper endpoints of the second through-hole 14b via the second inner through-hole 154b. In some embodiments, the bottommost dielectric layer and the bottommost second inner through-hole 154b can be omitted, and the second inner pad 153b can directly contact the second through-hole 14b and the top surface 101 of the first main portion 10. A second lower pad 19 can be disposed below the bottom surface 102 of the first main portion 10 and electrically connected to a plurality of lower endpoints of the second through-hole 14b. In some embodiments, the second lower pad 19 can directly contact the second through-hole 14b and the bottom surface 102 of the first main portion 10.

[0029] As shown in Figures 1 and 3, the second electronic component 2 may have a first surface 21 (e.g., a top surface or an active surface), a second surface 22 (e.g., a bottom surface or a back surface), and a side surface 23. The second surface 22 (e.g., the bottom surface) may be opposite to the first surface 21 (e.g., the top surface). The side surface 23 may extend between the first surface 21 (e.g., the top surface) and the second surface 22 (e.g., the bottom surface).

[0030] The second electronic component 2 may include a second main portion 20, a plurality of through holes 24, a second circuit structure 25, at least one first lower pad 28, and a plurality of second lower pads 29. The material of the second main portion 20 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. The thickness of the second main portion 20 may be equal to the thickness of the first main portion 10.

[0031] The through-hole 24 may extend through the second main portion 20 and may include at least one first through-hole 24a disposed below the first top grain 6 and a plurality of second through-holes 24b disposed below the second top grain 7.

[0032] A second circuit structure 25 can be disposed on the top surface 201 of the second main portion 20. The second circuit structure 25 may include a dielectric structure 251 (including a plurality of dielectric layers), at least one circuit layer 252, at least one bridging circuit 252a, at least one first internal pad 253a, a plurality of second internal pads 253b, a plurality of first internal vias 254a, a plurality of second internal vias 254b, a plurality of first upper pads 26, and a plurality of second upper pads 27. The circuit layer 252, bridging circuit 252a, first internal pad 253a, second internal pad 253b, first internal vias 254a, second internal vias 254b, first upper pads 26, and second upper pads 27 are embedded in the dielectric structure 251. The top surface 261 of the first upper pad 26 and the top surface 271 of the second upper pad 27 can be exposed from the first surface 21 of the second electronic component 2. Each of the first upper pad 26 and the second upper pad 27 may be a hybrid bonding (HB) pad and may include copper or aluminum.

[0033] A first through hole 24a, a first internal pad 253a, a first internal through hole 254a, and a first lower pad 28 can be provided within the vertical projection of the first top die 6. A second through hole 24b, a second internal pad 253b, a second internal through hole 254b, and a second lower pad 29 can be provided within the vertical projection of the second top die 7.

[0034] Circuit layer 252 may be horizontally connected to the first inner pad 253a and / or the second inner pad 253b. Bridging circuit 252a may be electrically connected to one of the first inner vias 254a and one of the second inner vias 254b. Bridging circuit 252a may be electrically connected to the first top die 6 and the second top die 7. Circuit layer 252 and bridging circuit 252a may be located on the same layer. Alternatively, bridging circuit 252a may be part of circuit layer 252.

[0035] The first internal through-hole 254a can vertically connect the first internal pad 253a and the first upper pad 26. The first internal pad 253a can be electrically connected to the upper end of the first through-hole 24a via the first internal through-hole 254a. In some embodiments, the bottom dielectric layer and the bottom first internal through-hole 254a can be omitted, and the first internal pad 253a can directly contact the first through-hole 24a and the top surface 201 of the second main portion 20.

[0036] A first lower pad 28 may be disposed below the bottom surface 202 of the second main portion 20 and electrically connected to the lower end of the first through hole 24a. In some embodiments, the first lower pad 28 may directly contact the first through hole 24a and the bottom surface 202 of the second main portion 20.

[0037] The second internal via 254b can vertically connect the second internal pad 253b and the second upper pad 27. The second internal pad 253b can be electrically connected to a plurality of upper endpoints of the second via 24b via the second internal via 254b. In some embodiments, the bottom dielectric layer and the bottom second internal via 254b can be omitted, and the second internal pad 253b can directly contact the second via 24b and the top surface 201 of the second main portion 20.

[0038] A second lower pad 29 may be disposed below the bottom surface 202 of the second main portion 20 and electrically connected to a plurality of lower endpoints of the second through hole 24b. In some embodiments, the second lower pad 19 may directly contact the second through hole 24b and the bottom surface 202 of the second main portion 20.

[0039] As shown in Figures 1 and 4, an intermediate electronic component 54 can be disposed between the first electronic component 1 and the second electronic component 2. The intermediate electronic component 54 may have a first surface 541 (e.g., a top surface) and a second surface 542 (e.g., a bottom surface) opposite to the first surface 541 (e.g., the top surface).

[0040] The encapsulant 51 may include a first portion 51a and a second portion 51b. The first portion 51a of the encapsulant 51 may be disposed between the intermediate electronic component 54 and the first electronic component 1. The second portion 51b of the encapsulant 51 may be disposed between the intermediate electronic component 54 and the second electronic component 2.

[0041] Intermediate electronic component 54 may include a third electronic component 3 stacked on the fourth electronic component 4. The third electronic component 3 may be electrically connected to the fourth electronic component 4 by means of hybrid bonding.

[0042] The third electronic component 3 may have a first surface 31 (e.g., a top surface or an active surface), a second surface 32 (e.g., a bottom surface or a back surface), and a side surface 33. The second surface 32 (e.g., a bottom surface) may be opposite to the first surface 31 (e.g., a top surface). The side surface 33 may extend between the first surface 31 (e.g., a top surface) and the second surface 32 (e.g., a bottom surface).

[0043] The third electronic component 3 may include a third main portion 30, a plurality of third vias 34, a third circuit structure 35, and a plurality of third lower pads 38. The material of the third main portion 30 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0044] A third via 34 may extend through the third main portion 30. A third circuit structure 35 may be disposed on the top surface 301 of the third main portion 30. The third circuit structure 35 may include a dielectric structure 351 (including a plurality of dielectric layers), at least one circuit layer 352, a plurality of third inner pads 353, a plurality of third inner vias 354, and a plurality of third upper pads 36. The circuit layer 352, the third inner pads 353, the third inner vias 354, and the third upper pads 36 are embedded in the dielectric structure 351. The top surface 361 of the third upper pads 36 may be exposed from the first surface 31 of the third electronic element 3 (i.e., the first surface 541 of the intermediate electronic element 54). Each third upper pad 36 may be a hybrid bonding (HB) pad and may comprise copper or aluminum.

[0045] A third through hole 34, a third inner pad 353, a third inner through hole 354 and a third lower pad 38 can be provided within the vertical projection of the first top grain 6.

[0046] The circuit layer 352 can be horizontally connected to the third inner pad 353. The third inner via 354 can be vertically connected to the third inner pad 353 via the third upper pad 36. The third inner pad 353 can be electrically connected to a plurality of upper endpoints of the third via 34 via the third inner via 354. In some embodiments, the bottom dielectric layer and the bottom third inner via 354 can be omitted, and the third inner pad 353 can directly contact the top surface 301 of the third via 34 and the third main portion 30.

[0047] A third lower pad 38 may be disposed below the bottom surface 302 of the third main portion 30 and electrically connected to a plurality of lower endpoints of the third through hole 34. In some embodiments, the third lower pad 38 may directly contact the third through hole 34 and the bottom surface 302 of the third main portion 30.

[0048] The fourth electronic component 4 may have a first surface 41 (e.g., a top surface or an active surface), a second surface 42 (e.g., a bottom surface or a back surface), and a side surface 43. The second surface 42 (e.g., a bottom surface) may be opposite to the first surface 41 (e.g., a top surface). The side surface 43 may extend between the first surface 41 (e.g., a top surface) and the second surface 42 (e.g., a bottom surface).

[0049] The fourth electronic component 4 may include a fourth main portion 40, a plurality of fourth vias 44, a fourth circuit structure 45, and a plurality of fourth lower pads 48. The material of the fourth main portion 40 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0050] A fourth via 44 may extend through the fourth main portion 40. A fourth circuit structure 45 may be disposed on the top surface 401 of the fourth main portion 40. The fourth circuit structure 45 may include a dielectric structure 451 (including a plurality of dielectric layers), at least one circuit layer 452, a plurality of fourth inner pads 453, a plurality of fourth inner vias 454, and a plurality of fourth upper pads 46. The circuit layer 452, the fourth inner pads 453, the fourth inner vias 454, and the fourth upper pads 46 are embedded in the dielectric structure 451. The top surface 461 of the fourth upper pads 46 may be exposed from the first surface 41 of the fourth electronic component 4. Each fourth upper pad 46 may be a hybrid bonding (HB) pad and may comprise copper or aluminum.

[0051] The fourth upper pad 46 of the fourth electronic component 4 can be attached to the third lower pad 38 of the third electronic component 3 by metal-to-metal bonding. Therefore, the fourth upper pad 46 of the fourth electronic component 4 can be substantially aligned and electrically connected to the third lower pad 38 of the third electronic component 3. The fourth through-hole 44, the fourth internal pad 453, the fourth internal through-hole 454, and the fourth lower pad 48 can be provided within the vertical projection of the first top die 6.

[0052] Circuit layer 452 can be horizontally connected to fourth inner pad 453. Fourth inner via 454 can be vertically connected to fourth inner pad 453 and fourth upper pad 46. Fourth inner pad 453 can be electrically connected to a plurality of upper endpoints of fourth via 44 via fourth inner via 454. In some embodiments, bottommost dielectric layer and bottommost fourth inner via 454 can be omitted, and fourth inner pad 453 can directly contact fourth via 44 and top surface 401 of fourth main portion 40.

[0053] A fourth lower pad 48 may be disposed below the bottom surface 402 of the fourth main portion 40 and electrically connected to a plurality of lower endpoints of the fourth through hole 44. In some embodiments, the fourth lower pad 48 may directly contact the fourth through hole 44 and the bottom surface 402 of the fourth main portion 40.

[0054] As shown in Figure 1, the encapsulant 51 may have a first surface 511 (or top surface) (e.g., the first surface 501 of the molded structure 50), a second surface 512 (or bottom surface) (e.g., the second surface 502 of the molded structure 50), and a side surface 513 (e.g., the side surface 503 of the molded structure 50). The second surface 512 may be opposite to the first surface 511. The side surface 513 may extend between the first surface 511 and the second surface 512. The material of the encapsulant 51 may include a molding compound with or without fillers.

[0055] The top surface 11 of the first electronic component 1 and the top surface 21 of the second electronic component 2 can be substantially coplanar with the first surface 511 of the encapsulant 51. Furthermore, the bottom surface 12 of the first electronic component 1 and the bottom surface 22 of the second electronic component 2 can be substantially coplanar with the second surface 512 of the encapsulant 51.

[0056] As shown in Figures 1 and 2, the first top grain 6 may have a first surface 61 (e.g., a top surface or a back surface), a second surface 62 (e.g., a bottom surface or an active surface), and a side surface 63. The second surface 62 (e.g., a bottom surface) may be opposite to the first surface 61 (e.g., a top surface). The side surface 63 may extend between the first surface 61 (e.g., a top surface) and the second surface 62 (e.g., a bottom surface).

[0057] The first top die 6 may include semiconductor dies or wafers, such as signal processing dies (e.g., digital signal processing (DSP) dies), logic dies (e.g., application processor (AP), system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC) dies, or microcontrollers), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, front-end dies (e.g., analog front-end (AFE) dies), or other active components.

[0058] The first top die 6 may include a main portion 60 and a circuit structure 65. The material of the main portion 60 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.

[0059] A circuit structure 65 may be provided on the main portion 60. The circuit structure 65 may include a dielectric structure 651 (including a plurality of dielectric layers), at least one circuit layer 652, a plurality of internal pads 653, a plurality of internal vias 654, a plurality of first bonding pads 66, a plurality of second bonding pads 67, and a plurality of third bonding pads 68. The circuit layer 652, internal pads 653, internal vias 654, first bonding pads 66, second bonding pads 67, and third bonding pads 68 are embedded in the dielectric structure 651. The bottom surface 661 of the first bonding pad 66, the bottom surface 671 of the second bonding pad 67, and the bottom surface 681 of the first bonding pad 66 may be exposed from the second surface 62 of the first top die 6. Each of the first bonding pad 66, the second bonding pad 67, and the third bonding pad 68 may be a hybrid bonding (HB) pad and may include copper or aluminum.

[0060] The circuit layer 652 can be horizontally connected to the inner pad 653. The internal via 654 can vertically connect the inner pad 653 to the first bonding pad 66, the second bonding pad 67, and the third bonding pad 68.

[0061] A first top die 6 can be disposed on the molded structure 50. The first top die 6 can be electrically connected to the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 of the molded structure 50 by hybrid bonding. As shown in FIG2, the first bonding pad 66 of the first top die 6 can be substantially aligned and electrically connected to the first upper pad 16 of the first electronic component 1, respectively. Therefore, the first bonding pad 66 of the first top die 6 can be attached to the first upper pad 16 of the first electronic component 1 by metal-to-metal bonding. The dielectric structure 651 of the circuit structure 65 of the first top die 6 can be directly attached to or can directly contact the dielectric structure 151 of the first circuit structure 15 of the first electronic component 1.

[0062] Therefore, the first top die 6 can be electrically connected to the first electronic component 1 via a plurality of first vertical electrical paths 81 (or conductive paths) extending directly from the first top die 6 to the first electronic component 1. No horizontal electrical path may exist between the first top die 6 and the first electronic component 1. Furthermore, the first top die 6 can be electrically connected to the substrate 52 via a plurality of fifth vertical paths 85 extending directly from the first top die 6 to the substrate 52. No horizontal electrical path may exist between the first top die 6 and the substrate 52.

[0063] As shown in Figure 3, the second bonding pad 67 of the first top die 6 can be substantially aligned and electrically connected to the first upper pad 26 of the second electronic component 2. Therefore, the second bonding pad 67 of the first top die 6 can be attached to the first upper pad 26 of the second electronic component 2 by metal-to-metal bonding. The dielectric structure 651 of the circuit structure 65 of the first top die 6 can be directly attached to or can directly contact the dielectric structure 251 of the second circuit structure 25 of the second electronic component 2.

[0064] Therefore, the first top die 6 can be electrically connected to the second electronic component 2 via a plurality of second vertical electrical paths 82 extending directly from the first top die 6 to the second electronic component 2. No horizontal electrical path may exist between the first top die 6 and the second electronic component 2.

[0065] As shown in Figure 4, the third bonding pad 68 of the first top die 6 can be substantially aligned and electrically connected to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3, respectively. Therefore, the third bonding pad 68 of the first top die 6 can be attached to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3 by metal-to-metal bonding. The dielectric structure 651 of the circuit structure 65 of the first top die 6 can be directly attached to or can directly contact the dielectric structure 351 of the third circuit structure 35 of the third electronic component 3.

[0066] Therefore, the first top die 6 can be electrically connected to the third electronic element 3 of the intermediate electronic element 54 via a plurality of fourth vertical electrical paths 84 extending directly from the first top die 6 to the third electronic element 3 of the intermediate electronic element 54. No horizontal electrical path is required between the first top die 6 and the third electronic element 3 of the intermediate electronic element 54. Furthermore, the first top die 6 can be electrically connected to the substrate 52 via a plurality of seventh vertical paths 87 extending directly from the first top die 6 through the intermediate electronic element 54 to the substrate 52. No horizontal circuit path is required between the first top die 6 and the substrate 52.

[0067] As shown in Figures 1 and 3, the second top grain 7 may have a first surface 71 (e.g., a top surface), a second surface 72 (e.g., a bottom surface), and a side surface 73. The second surface 72 (e.g., the bottom surface) may be opposite to the first surface 71 (e.g., the top surface). The side surface 73 may extend between the first surface 71 (e.g., the top surface) and the second surface 72 (e.g., the bottom surface).

[0068] The function of the first top die 6 may differ from the function of the second top die 7. The second top die 7 may include a semiconductor device or memory die, such as a high bandwidth memory (HBM) die. The second top die 7 may include a substrate carrier 75 (e.g., a substrate or logic die), a plurality of memory dies stacked on the substrate carrier 75, and an encapsulating agent (e.g., a molding compound) that encapsulates the memory dies and covers a portion of the top surface of the substrate carrier 75.

[0069] The substrate carrier 75 may include a dielectric structure 751 (including a plurality of dielectric layers) and a plurality of bonding pads 76. The bottom surface 761 of the bonding pads 76 may be exposed from the second surface 72 of the second top die 7. Each bonding pad 76 may be a hybrid bonding (HB) pad and may be coated with copper or aluminum.

[0070] A second top die 7 can be disposed on the molded structure 50. The second top die 7 can be electrically connected to the second electronic component 2 of the molded structure 50 by hybrid bonding. As shown in FIG3, the bonding pads 76 of the second top die 7 can be substantially aligned and electrically connected to the second upper pad 27 of the second electronic component 2. Therefore, the bonding pads 76 of the second top die 7 can be attached to the second upper pad 27 of the second electronic component 2 by metal-to-metal bonding. The dielectric structure 751 of the substrate carrier 75 of the second top die 7 can be directly attached to or can directly contact the dielectric structure 251 of the second circuit structure 25 of the second electronic component 2.

[0071] Therefore, the second top die 7 can be electrically connected to the second electronic component 2 via a plurality of third vertical electrical paths 83 extending directly from the second top die 7 to the second electronic component 2. No horizontal electrical path is required between the second top die 7 and the second electronic component 2. Furthermore, the second top die 7 can be electrically connected to the substrate 52 via a plurality of sixth vertical paths 86 extending directly from the second top die 7 to the substrate 52. No horizontal circuit path is required between the second top die 7 and the substrate 52.

[0072] As shown in Figures 1 to 4, the top surface 161 of the first upper pad 16 of the first electronic component 1, the top surface 261 of the first upper pad 26 of the second electronic component 2, the top surface 271 of the second upper pad 27 of the second electronic component 2, and the top surface 361 of the third upper pad 36 of the third electronic component 3 are substantially coplanar with the first surface 511 of the encapsulant 51. Furthermore, the top surface 11 of the first electronic component 1, the top surface 21 of the second electronic component 2, and the top surface 541 of the intermediate electronic component 54 (i.e., the top surface 31 of the third electronic component 3) are substantially coplanar with the first surface 511 of the encapsulant 51. The bottom surface 12 of the first electronic component 1, the bottom surface 22 of the second electronic component 2, and the bottom surface 542 of the intermediate electronic component 54 (i.e., the bottom surface 42 of the fourth electronic component 4) are substantially coplanar.

[0073] As shown in Figures 1 and 3, the bridging circuit 252a of the second electronic component 2 can be configured to electrically connect the second bonding pad 67 of the first top die 6 to the bonding pad 76 of the first top die 6. A portion 2a of the second electronic component 2 can be exposed in the gap g between the first top die 6 and the second top die 7. The side surface 63 of the first top die 6 and the side surface 73 of the second top die 7 can contact the top surface 21 of the second electronic component 2.

[0074] As shown in Figures 1 and 2, a portion 1a of the first electronic component 1 can extend beyond the vertical projection of the first top die 6. Therefore, the first top die 6 can partially overlap the first electronic component 1 vertically.

[0075] As shown in Figure 1, a protective material 58 (e.g., a molding compound with or without filler) can cover the first top grain 6, the second top grain 7, and the top surface 501 of the molding structure 50. Therefore, the protective material 58 can directly contact the top surface 11 of the first electronic component 1, the top surface 21 of the second electronic component 2, and the first surface 511 of the encapsulant 51.

[0076] In the embodiments shown in Figures 1 to 4, heterogeneous electronic components (e.g., semiconductor wafers or semiconductor dies) can be integrated into the assembly structure 5 and the package structure 9 without the need for redistribution structures or interposers. For example, the first top die 6 and the second top die 7 can communicate with each other via the second electronic component 2. Furthermore, the first top die 6 can communicate directly with the substrate 52 via the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54. Similarly, the second top die 7 can communicate directly with the substrate 52 via the second electronic component 2. Therefore, the assembly structure 5 and the package structure 9 can fulfill a variety of desired functions. This increases design flexibility and reduces manufacturing costs.

[0077] Figure 5 is a cross-sectional view illustrating an assembly structure 5a of some embodiments disclosed herein. Except for the structure of the encapsulation structure 9a, the assembly structure 5a can be similar to the assembly structure 5 of Figure 1. In the encapsulation structure 9a, the second surface 62 of the first top die 6 and the second surface 72 of the second top die 7 do not contact the top surface 501 of the molding structure 50. The protective material 58 can be omitted.

[0078] The first top die 6 can be electrically connected to the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 via, for example, a plurality of bumps made of solder material 59. The second top die 7 can be electrically connected to the second electronic component 2 via solder material 59. The solder material 59 may include a reflowable material, such as silver tin (AgSn). Therefore, the first top die 6 and the second top die 7 are electrically connected to the molded structure 50 by solder bonding rather than hybrid bonding.

[0079] The first upper pad 16 of the first electronic component 1, the first upper pad 26 of the second electronic component 2, the second upper pad 27 of the second electronic component 2, the third upper pad 36 of the third electronic component 3, the first bonding pad 66 of the first top die 6, the second bonding pad 67 and the third bonding pad 68, and the bonding pad 76 of the second top die 7 are solder pads.

[0080] Figure 6 is a cross-sectional view illustrating an assembly structure 5b of some embodiments disclosed herein. Except for the structure of the encapsulation structure 9b, the assembly structure 5b may be similar to the assembly structure 5 of Figure 1.

[0081] In the package structure 9b, the bump 56 and the protective material 58 can be omitted. Therefore, the molded structure 50 can be electrically connected to the substrate 52 by hybrid bonding. For example, the first electronic component 1, the fourth electronic component 4 of the intermediate electronic component 54, and the second electronic component 2 can be electrically connected to the substrate 52 by hybrid bonding instead of solder bonding.

[0082] The second surface 12 of the first electronic component 1, the second surface 42 of the fourth electronic component 4 (i.e., the second surface 542 of the intermediate electronic component 54) and the second surface 22 of the second electronic component 2 can directly contact the first surface 521 of the substrate 52.

[0083] The first lower pad 18 and the second lower pad 19 of the first electronic component 1, the first lower pad 28 and the second lower pad 29 of the second electronic component 2, the fourth lower pad 48 of the fourth electronic component 4, and the pad 524 of the substrate 52 can be hybrid bonding (HB) pads. Therefore, the first lower pad 18 and the second lower pad 19 of the first electronic component 1, the first lower pad 28 and the second lower pad 29 of the second electronic component 2, and the fourth lower pad 48 of the fourth electronic component 4 can be attached to and electrically connected to the pad 524 of the substrate 52 by metal-to-metal bonding.

[0084] Figures 7 to 15 are cross-sectional views illustrating various stages of the manufacturing method of the assembly structure 5 according to some embodiments of this disclosure.

[0085] Figures 7 to 9 show that a molded structure 50 can be formed on a first carrier 92. The first carrier 92 may include a first release layer 93 located thereon. Referring to Figure 7, a first carrier 92 having a first release layer 93 thereon can be provided. In addition, a first electronic component 1, a second electronic component 2, and an intermediate electronic component 54 can be provided.

[0086] In some embodiments, only known good wafers are used, such as known good first electronic component 1, known good second electronic component 2, and known good intermediate electronic component 54. In some embodiments, the size and function of the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 may differ from each other.

[0087] The first electronic component 1 may be the same as the first electronic component 1 in Figures 1 and 2. The first electronic component 1 may have a first surface 11, a second surface 12, and a side surface 13. The second surface 12 may be opposite to the first surface 11. The side surface 13 may extend between the first surface 11 and the second surface 12.

[0088] The first electronic component 1 may include a first main portion 10, a plurality of through holes 14, a first circuit structure 15, a plurality of first lower pads 18, and a plurality of second lower pads 19. The through holes 14 may extend through the first main portion 10 and may include a plurality of first through holes 14a and a plurality of second through holes 14b. The first circuit structure 15 may be disposed on the top surface 101 of the first main portion 10. The first circuit structure 15 may include a plurality of first upper pads 16. The top surface 161 of the first upper pads 16 may be exposed from the first surface 11 of the first electronic component 1.

[0089] A first lower pad 18 may be disposed below the bottom surface 102 of the first main portion 10 and electrically connected to a plurality of lower endpoints of the first through hole 14a. A second lower pad 19 may be disposed below the bottom surface 102 of the first main portion 10 and electrically connected to a plurality of lower endpoints of the second through hole 14b.

[0090] The second electronic component 2 may be the same as the second electronic component 2 in Figures 1 and 3. The second electronic component 2 may have a first surface 21, a second surface 22, and a side surface 23. The second surface 22 may be opposite to the first surface 21. The side surface 23 may extend between the first surface 21 and the second surface 22.

[0091] The second electronic component 2 may include a second main portion 20, a plurality of through holes 24, a second circuit structure 25, at least one first lower pad 28, and a plurality of second lower pads 29. The through holes 24 may extend through the second main portion 20 and may include at least one first through hole 24a and a plurality of second through holes 24b.

[0092] A second circuit structure 25 may be provided on the top surface 201 of the second main part 20. The second circuit structure 25 may include a plurality of first upper pads 26 and a plurality of second upper pads 27. The top surfaces 261 of the first upper pads 26 and the top surfaces 271 of the second upper pads 27 may be exposed from the first surface 21 of the second electronic component 2.

[0093] A first lower pad 28 may be provided below the bottom surface 202 of the second main portion 20 and electrically connected to the lower end point of the first through hole 24a. A second lower pad 29 may be provided below the bottom surface 202 of the second main portion 20 and electrically connected to a plurality of lower ends of the second through hole 24b.

[0094] Intermediate electronic component 54 may be the same as the intermediate electronic component 54 in Figures 1 and 4. Intermediate electronic component 54 may have a first surface 541 and a second surface 542 opposite to the first surface 541. Intermediate electronic component 54 may include a third electronic component 3 stacked on the fourth electronic component 4. The third electronic component 3 may be electrically connected to the fourth electronic component 4 by hybrid bonding.

[0095] The third electronic component 3 may have a first surface 31, a second surface 32, and a side surface 33. The second surface 32 may be opposite to the first surface 31. The side surface 33 may extend between the first surface 31 and the second surface 32.

[0096] The third electronic component 3 may include a third main portion 30, a plurality of third through holes 34, a third circuit structure 35, and a plurality of third lower pads 38. The third circuit structure 35 may be disposed on the top surface 301 of the third main portion 30. The top surface 361 of the third upper pad 36 may be exposed from the first surface 31 of the third electronic component 3. The third lower pads 38 may be disposed below the bottom surface 302 of the third main portion 30 and electrically connected to the plurality of lower endpoints of the third through holes 34.

[0097] The fourth electronic component 4 may have a first surface 41, a second surface 42, and a side surface 43. The second surface 42 may be opposite to the first surface 41. The side surface 43 may extend between the first surface 41 and the second surface 42.

[0098] The fourth electronic component 4 may include a fourth main portion 40, a plurality of fourth through holes 44, a fourth circuit structure 45, and a plurality of fourth lower pads 48. The fourth through holes 44 may extend through the fourth main portion 40. The fourth circuit structure 45 may be disposed on the top surface 401 of the fourth main portion 40. The fourth circuit structure 45 may include a plurality of fourth upper pads 46. The top surface 461 of the fourth upper pads 46 may be exposed from the first surface 41 of the fourth electronic component 4.

[0099] The fourth upper pad 46 of the fourth electronic component 4 can be attached to the third lower pad 38 of the third electronic component 3 by metal-to-metal bonding. Therefore, the fourth upper pad 46 of the fourth electronic component 4 can be substantially aligned and electrically connected to the third lower pad 38 of the third electronic component 3. The fourth lower pad 48 can be disposed below the bottom surface 402 of the fourth main portion 40 and electrically connected to a plurality of lower endpoints of the fourth through hole 44.

[0100] Referring to Figure 8, a first electronic component 1, a second electronic component 2, and an intermediate electronic component 54 can be arranged side-by-side on the first release layer 93 of the first carrier 92. In some embodiments, the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 can be reconfigured or rearranged on the first release layer 93 of the first carrier 92. The second surface 12 of the first electronic component 1, the second surface 22 of the second electronic component 2, and the second surface 542 of the intermediate electronic component 54 can contact the first release layer 93. The intermediate electronic component 54 can be disposed between the first electronic component 1 and the second electronic component 2.

[0101] Referring to Figure 9, an encapsulant 51 can be formed on the first release layer 93 of the first carrier 92 to encapsulate the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54. The encapsulant 51 can be the same as the encapsulant 51 in Figure 1.

[0102] Then, a polishing process can be performed to form a molded structure 50 on the first carrier 92. The molded structure 50 may include a first electronic component 1, a second electronic component 2, an intermediate electronic component 54, and an encapsulant 51. The molded structure 50 may have a first surface 501 and a second surface 502 opposite to the first surface 501.

[0103] The encapsulant 51 may have a first surface 511 and a second surface 512 opposite to the first surface 511. The first surface 511 of the encapsulant 51 may be substantially coplanar or aligned with the first surface 11 of the first electronic component 1, the first surface 21 of the second electronic component 2, and the first surface 541 of the intermediate electronic component 54. Therefore, the first surface 501 of the molded structure 50 may include the first surface 511 of the encapsulant 51, the first surface 11 of the first electronic component 1, the first surface 21 of the second electronic component 2, and the first surface 541 of the intermediate electronic component 54.

[0104] Furthermore, the second surface 512 of the encapsulant 51 may be substantially coplanar or aligned with the second surface 12 of the first electronic component 1, the second surface 22 of the second electronic component 2, and the second surface 542 of the intermediate electronic component 54. Therefore, the second surface 502 of the molded structure 50 may include the second surface 512 of the encapsulant 51, the second surface 12 of the first electronic component 1, the second surface 22 of the second electronic component 2, and the second surface 542 of the intermediate electronic component 54.

[0105] Referring to Figure 10, the first surface 501 of the molded structure 50 can be attached to the second release layer 95 of the second carrier 94. Then, the first carrier 92 and the first release layer 93 can be removed from the molded structure 50 to expose the second surface 502 of the molded structure 50.

[0106] Referring to Figure 11, a plurality of bumps 56 can be formed on the first lower pad 18 and the second lower pad 19 of the first electronic component 1 and on the first lower pad 28 and the second lower pad 29 of the second electronic component 2.

[0107] Referring to Figure 12, the bump 56 and the second surface 502 of the molding structure 50 can be attached to the third release layer 97 of the third carrier 96. Then, the second carrier 94 and the second release layer 95 can be removed from the molding structure 50 to expose the first surface 501 of the molding structure 50.

[0108] Referring to Figure 13, a first top grain 6 and a second top grain 7 can be provided. The function and size of the first top grain 6 may differ from the function and size of the second top grain 7. The first top grain 6 may be the same as the first top grain 6 in Figure 1. The first top grain 6 may have a first surface 61, a second surface 62, and a side surface 63. The second surface 62 may be opposite to the first surface 61. The side surface 63 may extend between the first surface 61 and the second surface 62.

[0109] The first top die 6 may include a main portion 60 and a circuit structure 65. The circuit structure 65 may be disposed on the main portion 60. The circuit structure 65 may include a plurality of first bonding pads 66, a plurality of second bonding pads 67, and a plurality of third bonding pads 68. The bottom surface 661 of the first bonding pads 66, the bottom surface 671 of the second bonding pads 67, and the bottom surface 681 of the first bonding pads 66 may be exposed from the second surface 62 of the first top die 6.

[0110] The second top grain 7 can be the same as the second top grain 7 in FIG1. ​​The second top grain 7 can have a first surface 71, a second surface 72, and a side surface 73. The second surface 72 can be opposite to the first surface 71. The side surface 73 can extend between the first surface 71 and the second surface 72.

[0111] The second top die 7 may include a substrate carrier 75 (e.g., a substrate or logic die), a plurality of memory dies stacked on the substrate carrier 75, and an encapsulating agent (e.g., a molding compound) that encapsulates the memory dies and covers a portion of the top surface of the substrate carrier 75. The substrate carrier 75 may include a plurality of bonding pads 76. The bottom surface 761 of the bonding pads 76 may be exposed from the second surface 72 of the second top die 7.

[0112] Referring to Figure 14, the first top die 6 can be electrically connected to the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 of the molded structure 50 by hybrid bonding. The first bonding pad 66 of the first top die 6 can be substantially aligned and electrically connected to the first upper pad 16 of the first electronic component 1. Therefore, the first bonding pad 66 of the first top die 6 can be attached to the first upper pad 16 of the first electronic component 1 by metal-to-metal bonding.

[0113] The second bonding pad 67 of the first top die 6 can be substantially aligned and electrically connected to the first top pad 26 of the second electronic component 2. Therefore, the second bonding pad 67 of the first top die 6 can be attached to the first top pad 26 of the second electronic component 2 by metal-to-metal bonding.

[0114] The third bonding pad 68 of the first top die 6 can be substantially aligned and electrically connected to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3, respectively. Therefore, the third bonding pad 68 of the first top die 6 can be attached to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3 by metal-to-metal bonding.

[0115] Furthermore, the second top die 7 can be electrically connected to the second electronic component 2 of the molded structure 50 by hybrid bonding. The bonding pads 76 of the second top die 7 can be substantially aligned and electrically connected to the second upper pad 27 of the second electronic component 2. Therefore, the bonding pads 76 of the second top die 7 can be attached to the second upper pad 27 of the second electronic component 2 by metal-to-metal bonding.

[0116] Then, a protective material 58 can be formed to cover and contact the first top die 6, the second top die 7, the top surface 11 of the first electronic component 1, the top surface 21 of the second electronic component 2, and the top surface 511 of the encapsulant 51.

[0117] Referring to Figure 15, a segmentation process can be performed to form a plurality of package structures 9. Package structure 9 can be the same as the package structure 9 in Figure 1.

[0118] Then, the package structure 9 can be electrically connected to a plurality of pads 524 exposed from the first surface 521 (e.g., the top surface) of the substrate 52 via bumps 56. For example, the molded structure 50 of the package structure 9 can be electrically connected to the pads 524 via bumps 56.

[0119] Then, a plurality of external connectors 53 can be formed or disposed on the second surface 522 (e.g., the bottom surface) of the substrate 52 to obtain the assembly structure 5 shown in FIG1.

[0120] Figures 16 to 18 illustrate various stages of a method for manufacturing an assembly structure 5b according to some embodiments of the present disclosure. The initial stages of the method corresponding to Figures 16 to 18 are the same as or at least similar to the stages shown in Figures 7 to 9. Figure 16 illustrates the stages following those shown in Figure 9.

[0121] Referring to Figure 16, the molding structure 50 is segmented, and the first carrier 92 and the first release layer 93 can be removed from the molding structure 50.

[0122] Referring to Figure 17, the segmented molded structure 50 can be electrically connected to the substrate 52 by hybrid bonding. For example, the first electronic component 1, the fourth electronic component 4 of the intermediate electronic component 54, and the second electronic component 2 can be electrically connected to the substrate 52 by hybrid bonding instead of solder bonding. Therefore, the second surface 12 of the first electronic component 1, the second surface 42 of the fourth electronic component 4 (i.e., the second surface 542 of the intermediate electronic component 54), and the second surface 22 of the second electronic component 2 can directly contact the first surface 521 of the substrate 52. The first lower pad 18 and the second lower pad 19 of the first electronic component 1, the first lower pad 28 and the second lower pad 29 of the second electronic component 2, and the fourth lower pad 48 of the fourth electronic component 4 can be attached to and electrically connected to the pad 524 of the substrate 52 by metal-to-metal bonding.

[0123] Referring to Figure 18, the first top die 6 can be electrically connected to the first electronic component 1, the second electronic component 2, and the intermediate electronic component 54 of the molded structure 50 by hybrid bonding. The first bonding pad 66 of the first top die 6 can be substantially aligned and electrically connected to the first upper pad 16 of the first electronic component 1. Therefore, the first bonding pad 66 of the first top die 6 can be attached to the first upper pad 16 of the first electronic component 1 by metal-to-metal bonding.

[0124] The second bonding pad 67 of the first top die 6 can be substantially aligned and electrically connected to the first top pad 26 of the second electronic component 2. Therefore, the second bonding pad 67 of the first top die 6 can be attached to the first top pad 26 of the second electronic component 2 by metal-to-metal bonding.

[0125] The third bonding pad 68 of the first top die 6 can be substantially aligned and electrically connected to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3, respectively. Therefore, the third bonding pad 68 of the first top die 6 can be attached to the third upper pad 36 of the intermediate electronic component 54 or the third electronic component 3 by metal-to-metal bonding.

[0126] Furthermore, the second top die 7 can be electrically connected to the second electronic component 2 of the molded structure 50 by hybrid bonding. The bonding pads 76 of the second top die 7 can be substantially aligned and electrically connected to the second upper pad 27 of the second electronic component 2. Therefore, the bonding pads 76 of the second top die 7 can be attached to the second upper pad 27 of the second electronic component 2 by metal-to-metal bonding.

[0127] Therefore, the assembly structure 5b shown in Figure 6 is obtained.

[0128] Figure 19 is a top view of the assembly structure 5 of Figure 1. The first top die 6 may overlap with the first electronic component 1, the intermediate electronic component 54, and the second electronic component 2. The second top die 7 may overlap only with the second electronic component 2.

[0129] Figure 20 is a top view of an assembly structure 5' according to some embodiments of the present disclosure. The assembly structure 5' may include two second top dies 7, two intermediate electronic components 54, and two second electronic components 2. A first top die 6 may overlap with a first electronic component 1, the two intermediate electronic components 54, and the two second electronic components 2. Each of the second top dies 7 may overlap only with each of the second electronic components 2.

[0130] Figure 21 is a flowchart illustrating a method 900 for manufacturing an assembly structure 5 according to some embodiments of the present disclosure.

[0131] In some embodiments, method 900 may include step S901, forming a molding structure including a first electronic component, a second electronic component arranged side-by-side with the first electronic component, and an encapsulant for encapsulating the first electronic component, wherein the function of the first electronic component is different from the function of the second electronic component. For example, as shown in FIG9, a molding structure 50 may be formed. The molding structure 50 may include a first electronic component 1 and a second electronic component 2 arranged side-by-side with the first electronic component 1. An encapsulant 51 may encapsulate the first electronic component 1 and the second electronic component 2. The function of the first electronic component 1 may be different from the function of the second electronic component 2.

[0132] In some embodiments, method 900 may include step S902, electrically connecting a first top die to a first electronic component and a second electronic component. For example, as shown in FIG14, the first top die 6 may be electrically connected to the first electronic component 1 and the second electronic component 2.

[0133] In some embodiments, method 900 may include step S903, electrically connecting a second top die to a second electronic component, wherein the function of the first top die is different from the function of the second top die. For example, as shown in FIG14, the second top die 7 may be electrically connected to the second electronic component 2. The function of the first top die 6 may be different from the function of the second top die 7.

[0134] One aspect of this disclosure provides a packaging structure including: a molding structure, a first top die, and a second top die. The molding structure includes a first electronic component, a second electronic component, and an encapsulant. The first electronic component includes a plurality of first top pads. The second electronic component is disposed side-by-side with the first electronic component and includes a plurality of first top pads and a plurality of second top pads. The encapsulant encapsulates the first electronic component and the second electronic component. The first top die is disposed on the molding structure and includes a plurality of first bonding pads and a plurality of second bonding pads. The plurality of first bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first top pads of the first electronic component. The plurality of second bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first top pads of the second electronic component. The second top die is disposed on the molded structure and includes a plurality of bonding pads, wherein the plurality of bonding pads are substantially aligned with and electrically connected to the plurality of second top pads of the second electronic component.

[0135] Another aspect of this disclosure provides an assembly structure including: a substrate, a molding structure, a first top die, and a second top die. The molding structure is disposed on the substrate and electrically connected to the substrate. The molding structure includes a first electronic component, a second electronic component, and an encapsulant. The second electronic component is disposed side-by-side with the first electronic component. The function of the first electronic component is different from the function of the second electronic component. The encapsulant encapsulates the first electronic component and the second electronic component. A top surface of the first electronic component and a top surface of the second electronic component are substantially coplanar with a top surface of the encapsulant. A bottom surface of the first electronic component and a bottom surface of the second electronic component are substantially coplanar with a bottom surface of the encapsulant. The first top die is disposed on the molding structure and electrically connected to the first electronic component and the second electronic component, respectively. The second top die is disposed on the molding structure and electrically connected to the second electronic component.

[0136] Another aspect of this disclosure provides a manufacturing method. The manufacturing method includes: forming a molded structure, wherein the molded structure includes a first electronic component, a second electronic component disposed side-by-side with the first electronic component, and an encapsulant encapsulating the first electronic component and the second electronic component, wherein a function of the first electronic component is different from a function of the second electronic component; electrically connecting a first top die to the first electronic component and the second electronic component; and electrically connecting a second top die to the second electronic component, wherein the function of the first top die is different from the function of the second top die.

[0137] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0138] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0139] 1: First electronic component 1a: Part 2: Second electronic component 2a: Part 3: Third electronic component 4: Fourth electronic component 5: Assembly Structure 5': Assembly structure 5a: Assembly structure 5b: Assembly Structure 6: First top grain 7: Second top grain 9: Packaging Structure 9a: Packaging structure 9b: Packaging structure 10: First Main Part 11: First Surface 12: Second Surface 13: Side surface 14: Through hole 14a: First through hole 14b: Second through hole 15: First Circuit Structure 16: First upper pad 18: First lower pad 19: Second lower pad 20: Second Main Part 21: First Surface 22: Second Surface 23: Side surface 24: Through hole 24a: First through hole 24b: Second through hole 25: Second Circuit Structure 26: First upper pad 27: Second upper pad 28: First lower pad 29: Second lower pad 30: The Third Main Part 31: First Surface 32: Second surface 33: Side surface 34: Third through hole 35: Third Circuit Structure 36: Third upper pad 38: Third lower pad 40: Fourth Main Part 41: First Surface 42: Second surface 43: Side surface 44: Fourth through hole 45: Fourth Circuit Structure 46: Fourth upper pad 48: Fourth lower pad 50: Molded structure 51: Encapsulant 51a: Part 1 51b: Part Two 52:Substrate 53: External connector 54: Intermediate electronic components 56: Bump 58: Protective Materials 59: Solder materials 60: Main Part 61: First Surface 62: Second surface 63: Side surface 65: Circuit Structure 66: First joint pad 67: Second joint pad 68: Third joint pad 71: First Surface 72: Second Surface 73: Side surface 75: Substrate carrier 76: Joint Pad 81: First vertical electrical path 82: Second vertical electrical path 83: Third vertical electrical path 84: Four vertical electrical paths 85: Fifth Vertical Path 86: Sixth Vertical Path 87: Seventh Vertical Path 92: The First Carrier 93: First Release Layer 94: Second Carrier 95: Second Release Layer 96: The Third Carrier 97: Third Release Layer 101: Top surface 102: Bottom surface 151: Dielectric Structure 152: Circuit Layer 153a: First internal pad 153b: Second internal pad 154a: First internal through hole 154b: Second internal through hole 161: Top surface 201: Top surface 202: Bottom surface 251: Dielectric Structure 252: Circuit Layer 252a: Bridge circuit 253a: First internal pad 253b: Second internal pad 254a: First internal through hole 254b: Second internal through hole 261: Top surface 271: Top surface 301: Top surface 302: Bottom surface 351: Dielectric Structure 352: Circuit Layer 353: Third internal pad 354: Third internal through hole 361: Top surface 401: Top surface 402: Bottom surface 451: Dielectric Structure 452: Circuit Layer 453: Fourth internal pad 461: Top surface 454: Fourth internal through hole 501: First Surface 502: Second Surface 503: Side surface 511: First Surface 512: Second Surface 513: Side surface 521: First Surface 522: Second Surface 523: Side surface 524: Pad 541: First Surface 542: Second Surface 651: Dielectric Structure 652: Circuit Layer 653: Internal pad 654:Inner through hole 661: Bottom surface 671: Bottom surface 681: Bottom surface 751: Dielectric Structure 761: Bottom surface 900: Method S901: Steps S902: Steps S903: Steps A: Area B: Area C: Area g: gap

Claims

1. A packaging structure, comprising: A molded structure includes: a first electronic component including a plurality of first upper pads; a second electronic component disposed side-by-side with the first electronic component and including a plurality of first upper pads and a plurality of second upper pads; and an encapsulant for encapsulating the first electronic component and the second electronic component; a first top die disposed on the molded structure and including a plurality of first bonding pads and a plurality of second bonding pads, wherein the plurality of first bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first upper pads of the first electronic component, and wherein the plurality of second bonding pads of the first top die are substantially aligned with and electrically connected to the plurality of first upper pads of the second electronic component; and a second top die disposed on the molded structure and including a plurality of bonding pads, wherein the plurality of bonding pads are substantially aligned with and electrically connected to the plurality of second upper pads of the second electronic component. A protective material covers the first top die, the second top die, and a top surface of the encapsulation structure; and an intermediate electronic component is disposed between the first electronic component and the second electronic component, and includes a plurality of third upper pads, wherein the protective material directly contacts a top surface of the first electronic component, a top surface of the second electronic component, and a top surface of the encapsulant, wherein the encapsulant further encapsulates the intermediate electronic component, wherein the first top die also includes a plurality of third bonding pads, wherein the plurality of third bonding pads are substantially aligned with and electrically connected to the plurality of third upper pads of the intermediate electronic component.

2. The packaging structure as claimed in claim 1, wherein the plurality of top surfaces of the plurality of first upper pads of the first electronic component, the plurality of top surfaces of the plurality of first upper pads of the second electronic component, and the plurality of top surfaces of the plurality of second upper pads of the second electronic component are substantially coplanar with the top surface of the encapsulant.

3. The packaging structure as claimed in claim 1, wherein the top surface of the first electronic component and the top surface of the second electronic component are substantially coplanar with the top surface of the encapsulant, and wherein a bottom surface of the first electronic component and a bottom surface of the second electronic component are substantially coplanar with the bottom surface of the encapsulant.

4. The packaging structure as claimed in claim 1, wherein the first top die is electrically connected to the first electronic component and the second electronic component by hybrid bonding, wherein the second top die is electrically connected to the second electronic component by hybrid bonding.

5. The packaging structure as claimed in claim 1, wherein the first top die is electrically connected to the first electronic component and the second electronic component by a plurality of solder materials, wherein the second top die is electrically connected to the second electronic component by a plurality of solder materials.

6. The packaging structure as claimed in claim 1, wherein the second electronic component further includes a bridging circuit configured to electrically connect the plurality of second bonding pads of the first top die and the plurality of bonding pads of the second top die.

7. The packaging structure as claimed in claim 1, wherein a portion of the second electronic component is exposed in a gap between the first top die and the second top die.

8. The packaging structure as claimed in claim 1, wherein one side surface of the first top die and one side surface of the second top die contact the top surface of the second electronic component.

9. The packaging structure as claimed in claim 1, wherein the first electronic component further comprises: a first main portion; a plurality of first through-holes extending through the first main portion; a first circuit structure disposed on a top surface of the first main portion and including a circuit layer, a plurality of first inner pads, a plurality of first inner through-holes, and a plurality of first upper pads, wherein the circuit layer is horizontally connected to the plurality of first inner pads, wherein the plurality of first inner through-holes are vertically connected to the plurality of first inner pads and the plurality of first upper pads, wherein the plurality of first inner pads are electrically connected to a plurality of upper endpoints of the plurality of first through-holes; and a plurality of first lower pads disposed below a bottom surface of the first main portion and electrically connected to a plurality of lower endpoints of the plurality of first through-holes.

10. The packaging structure as claimed in claim 9, wherein the second electronic component further comprises: a second main portion; at least one first via disposed below the first top die and extending through the second main portion; a plurality of second vias disposed below the two top dies and extending through the second main portion; a second circuit structure disposed on a top surface of the second main portion and comprising a circuit layer, a bridging circuit, at least one first inner pad, a plurality of second inner pads, a plurality of second inner vias, a plurality of second inner pads, a plurality of first upper pads, and a plurality of second upper pads, wherein the circuit layer horizontally connects the at least one first inner pad and / or the plurality of second inner pads, and the bridging circuit is electrically connected to one of the plurality of first inner vias and one of the plurality of second inner vias, wherein the plurality of first inner vias vertically connects the at least one first inner pad and the plurality of first upper pads. The at least one first inner pad is electrically connected to an upper end of the at least one first through hole, wherein the plurality of second inner through holes vertically connect the plurality of second inner pads and the plurality of second upper pads, wherein the plurality of second inner pads are electrically connected to an upper end of the plurality of second through holes; and at least one first lower pad is disposed below a bottom surface of the first main portion and electrically connected to a lower end of the at least one first through hole; and a plurality of second lower pads are disposed below a bottom surface of the second main portion and electrically connected to a plurality of lower ends of the plurality of second through holes.

11. The packaging structure as claimed in claim 1, wherein a first portion of the encapsulant is disposed between the intermediate electronic component and the first electronic component, and a second portion of the encapsulant is disposed between the intermediate electronic component and the second electronic component.

12. The packaging structure as described in claim 1, wherein the intermediate electronic component further includes a third electronic component, wherein the third electronic component is stacked on a fourth electronic component.

13. The packaging structure as described in claim 12, wherein the third electronic component is electrically connected to the fourth electronic component by hybrid bonding.

14. The packaging structure as claimed in claim 12, wherein the third electronic component comprises: a third main portion; a plurality of third through-holes extending through the third main portion; a third circuit structure disposed on a top surface of the third main portion and comprising a circuit layer, a plurality of third inner pads, a plurality of third inner through-holes, and a plurality of third upper pads, wherein the circuit layer is horizontally connected to the plurality of third inner pads, wherein the plurality of third inner through-holes are vertically connected to the plurality of third inner pads and the plurality of third upper pads, wherein the plurality of third inner pads are electrically connected to a plurality of upper endpoints of the plurality of third through-holes; and a plurality of third lower pads disposed below a bottom surface of the third main portion and electrically connected to a plurality of lower endpoints of the plurality of third through-holes.

15. The packaging structure as claimed in claim 14, wherein the fourth electronic component comprises: a fourth main portion; a plurality of fourth vias extending through the fourth main portion; a fourth circuit structure disposed on a top surface of the fourth main portion and comprising a circuit layer, a plurality of fourth inner pads, a plurality of fourth inner vias, and a plurality of fourth upper pads, wherein the plurality of fourth upper pads are substantially aligned with and electrically connected to the plurality of third lower pads of the third electronic component, wherein the circuit layer is horizontally connected to the plurality of fourth inner pads, wherein the plurality of fourth inner vias are vertically connected to the plurality of fourth inner pads and the plurality of fourth upper pads, wherein the plurality of fourth inner pads are electrically connected to a plurality of upper endpoints of the plurality of fourth vias; and a plurality of fourth lower pads disposed below a bottom surface of the fourth main portion and electrically connected to a plurality of lower endpoints of the plurality of fourth vias, wherein the intermediate electronic component comprises a cache memory chip.

16. The packaging structure as described in claim 1, wherein a function of the first top die is different from a function of the second top die.

17. The packaging structure as described in claim 16, wherein the first top die includes a logic die and the second top die includes a memory die.

18. The packaging structure as described in claim 1, wherein the second electronic component includes a logic die, and the first electronic component includes an interposer.

19. The packaging structure as claimed in claim 1, wherein a portion of the first electronic component extends on a vertical projection of the first top die.

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