Semiconductor memory devices and methods for manufacturing semiconductor memory devices

Abstract

The objective of this invention is to obtain a charge storage layer with a shape that can effectively improve the characteristics of memory cells. A pillar of a semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a stacking direction within a stacked body; first and second insulating layers sequentially covering the sidewalls of the semiconductor layer from the semiconductor layer side; and a plurality of segment layers, which are respectively disposed between the third insulating layer and the first and second insulating layers such that a third insulating layer containing a material different from the first and second insulating layers is dispersed at the height positions of the plurality of conductive layers; the first insulating layer has a first portion at a height position facing each of the plurality of segment layers, the external shape of which at the first height position is a first distance along a first direction of the plurality of conductive layers, the first height position being located between the two ends in the thickness direction of each of the plurality of conductive layers; and a second portion, the external shape of which at a second height position is a second distance greater than the first distance in the first direction, the second height position being located between the height positions of the two ends of the plurality of conductive layers and the first height position.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Prior Technology

[0002] To increase the memory capacity of semiconductor memory devices such as three-dimensional non-volatile memory, attempts are being made to reduce the thickness of multiple conductive layers and increase the number of layers. As the thickness of multiple conductive layers decreases, in order to suppress interference between memory cells formed at different heights of the multiple conductive layers, it is more effective to divide the charge storage layer, which stores data by storing charge, for each memory cell. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0149069 [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0085055 Summary of the Invention

[0004] [The problem the invention aims to solve] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device, which can obtain a charge storage layer with a shape that can effectively improve the characteristics of memory cells. [Technical means to solve the problem]

[0005] A semiconductor memory device according to an embodiment includes: a stacked body formed by stacking a plurality of conductive layers separately from each other; and a pillar extending within the stacked body in the stacking direction; the pillar having: a semiconductor layer extending within the stacked body in the stacking direction; first and second insulating layers sequentially covering the sidewalls of the semiconductor layer from the semiconductor layer side; and a plurality of segment layers, which are respectively disposed between the third insulating layer and the upper conductive layer such that a third insulating layer containing a material different from the first and second insulating layers is scattered at the height position of the plurality of conductive layers. Between the first and second insulating layers; the first insulating layer has a first portion at a height position facing each of the plurality of segment layers, the outer shape of which at the first height position is a first distance along a first direction of the plurality of conductive layers, the first height position being located between the two ends of the plurality of conductive layers in the thickness direction; and a second portion, the outer shape of which at the second height position is a second distance greater than the first distance in the first direction, the second height position being located between the height positions of the two ends of the plurality of conductive layers and the first height position. Simple Explanation of the Diagram

[0006] Figures 1A and 1B are schematic diagrams illustrating a typical configuration example of the semiconductor memory device according to Embodiment 1. Figures 2A and 2B are cross-sectional views along the Y direction showing an example of the configuration of the semiconductor memory device according to Embodiment 1. Figures 3A to 3D are schematic diagrams illustrating the multilayer structure of the semiconductor memory device according to Embodiment 1. Figures 4A to 4D are diagrams illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figures 5A to 5C are diagrams illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figures 6A to 6D are diagrams illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figures 7A to 7C are diagrams illustrating a portion of the manufacturing method of the semiconductor memory device according to Embodiment 1. Figures 8A to 8H are enlarged cross-sectional views illustrating a portion of the sequence of methods for forming the memory layer in Implementation Method 1. Figures 9A to 9G are enlarged cross-sectional views illustrating a portion of the sequence of the memory layer formation method in Embodiment 1. Figure 10 is an enlarged cross-sectional view of the semiconductor memory device of Embodiment 1, at the height of the character line and the select gate line. Figure 11 is an enlarged cross-sectional view of the semiconductor memory device of Embodiment 1, at the height of the character line and the select gate line. Figure 12 is an enlarged cross-sectional view of the semiconductor memory device of Embodiment 1, at the height of the character line and the select gate line. Figures 13A to 13H are enlarged cross-sectional views showing examples of the configuration of pillars in a semiconductor memory device according to other variations of Embodiment 1. Figure 14 is an enlarged cross-sectional view of the column of the semiconductor memory device according to Embodiment 2 at the height of the word line and the select gate line. Figures 15A to 15G are enlarged cross-sectional views illustrating a portion of the sequence of methods for forming the memory layer in Embodiment 2. Figures 16A to 16H are enlarged cross-sectional views showing examples of the configuration of pillars in a semiconductor memory device according to other variations of Embodiment 2. Implementation

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited to the following embodiments. Also, the constituent elements in the following embodiments include elements that are readily conceived by the industry or substantially the same elements.

[0008] [Implementation Method 1] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0009] (Example of a semiconductor memory device) Figures 1A and 1B are schematic configuration examples of the semiconductor memory device 1 according to Embodiment 1. More specifically, Figure 1A is a cross-sectional view of the semiconductor memory device 1 along the X direction, and Figure 1B is a schematic top view showing the layout of the semiconductor memory device 1.

[0010] However, in Figure 1A, the shaded lines are omitted to make the diagram easier to read. Also, in Figure 1A, components that do not necessarily exist in the same cross-section are shown, and some upper-layer wiring is omitted.

[0011] Furthermore, in this specification, both the X and Y directions are directions along the plane of the character line WL, and the X and Y directions are orthogonal to each other. Also, sometimes the direction in which the electrical leads out of the character line WL are referred to as the first direction, which is along the X direction. Also, sometimes the direction intersecting the first direction is referred to as the second direction, which is along the Y direction. However, the semiconductor memory device 1 may contain manufacturing errors; therefore, the first and second directions are not necessarily orthogonal.

[0012] As shown in Figure 1A, the semiconductor memory device 1 includes, in sequence from the bottom of the paper, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which peripheral circuits CBA are provided.

[0013] A source line SL is disposed on the electrode film EL, separated by an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, through which the source line SL maintains electrical continuity with the electrode film EL. Although not shown, an electrode pad for supplying power and signals to the semiconductor memory device 1 from the outside is disposed on the same layer as the electrode film EL. A select gate line SGS, a plurality of character lines WL, and a select gate line SGD are sequentially stacked on the source line SL.

[0014] As shown in Figures 1A and 1B, a memory region MR is disposed at the center of a plurality of character lines WL in the X direction, and stepped regions SR are disposed at both ends of the plurality of character lines WL in the X direction. The memory region MR and the stepped regions SR are divided into a plurality of regions by a plurality of plate-shaped contacts LI, which penetrate the plurality of character lines WL and extend along the X direction.

[0015] Furthermore, the region located between adjacent plate-shaped contacts LI in the Y direction and containing the memory region MR and the stepped region SR is called the block region BLK. As described below, the memory region MR contains a plurality of memory cells that non-volatilely store data, and the aforementioned block region BLK is the unit for erasing such data.

[0016] Furthermore, a plurality of separation layers SHE are disposed between adjacent plate-shaped contacts LI in the Y direction. These separation layers SHE pass through the selected gate line SGD and extend in the X direction. The plurality of separation layers SHE cover the entire memory region MR and extend in the X direction, reaching a portion of the stepped regions SR at both ends in the X direction.

[0017] A plurality of pillars PL are disposed in the memory region MR, and these pillars PL pass through the word line WL and the select gate lines SGD and SGS in their stacking direction. The lower end of the pillar PL reaches the source line SL. A plurality of memory cells are formed at the intersection of the pillar PL and the word line WL. In this way, the semiconductor memory device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are disposed in three dimensions in the memory region MR.

[0018] In the stepped region SR, multiple word lines WL and select gate lines SGD and SGS are processed into a stepped shape and terminated. At this time, as the multiple word lines WL and select gate lines SGD and SGS constituting the stepped portion move away from the memory region MR along the X direction, they move from the upper layer side to the lower layer side. Therefore, the height position of the stepped portion decreases towards the source line SL side.

[0019] Furthermore, in this specification, the direction facing the planes of the plurality of character lines WL and the select gate lines SGD and SGS is defined as the upper side of the semiconductor memory device 1.

[0020] The aforementioned separation layer SHE extends from the memory region MR to the stepped region SR, and the select gate line SGD is processed into a stepped portion. In this way, within a block region BLK, the select gate line SGD is separated into multiple regions. In other words, the separation layer SHE penetrates a portion higher than the multiple character lines WL, and these upper portions are divided into a pattern of multiple select gate lines SGD.

[0021] Each layer of the surface, including multiple character lines WL and select gate lines SGD and SGS, is equipped with a contact CC that connects to each layer of character lines WL and select gate lines SGD and SGS. One contact CC is connected to each layer of character lines WL and select gate lines SGS. One contact CC is connected to each interval separated by the separation layer SHE in each layer of select gate lines SGD.

[0022] Here, within a single block region BLK, multiple contacts CC are configured on one side of the stepped regions SR on both sides of the X direction. Furthermore, when viewed from one side of the X direction, for example, multiple contacts CC are configured for every two block regions BLK.

[0023] That is, in the example of Figure 1B, in the uppermost block region BLK on the paper, a plurality of contacts CC are arranged in the stepped regions SR at both ends in the X direction, for example, the stepped region SR on the left side of the paper. Furthermore, in the block regions BLK one and two blocks below the aforementioned block region BLK, a plurality of contacts CC are arranged in the stepped regions SR at both ends in the X direction, specifically the stepped region SR on the right side of the paper. Moreover, in the lowermost block region BLK on the paper, a plurality of contacts CC are again arranged in the stepped region SR on the left side of the paper.

[0024] Therefore, the junctions CC of the stepped regions SR at both ends in the X direction shown in Figure 1A belong to different block regions BLK and are not actually in the same cross section.

[0025] Through these contacts CC, multi-layered word lines WL are brought out. More specifically, write voltage and read voltage are applied to the memory cells contained in the memory region MR at the center of the plurality of word lines WL via these contacts CC through the word lines WL at the same height position as the memory cells.

[0026] The plurality of character lines WL, the select gate lines SGD, SGS, PL, and the contact CC are covered by an insulating layer 50. The insulating layer 50 also extends around the components including the plurality of character lines WL.

[0027] The semiconductor substrate SB, such as a silicon substrate, covers the insulating layer 50 described above. Peripheral circuitry CBA, including transistors TR and wiring, is disposed on the surface of the semiconductor substrate SB. Various voltages applied from contacts CC to the memory cell are controlled by the peripheral circuitry CBA, which is electrically connected to the contacts CC. In this way, the peripheral circuitry CBA controls the electrical operation of the memory cell.

[0028] The peripheral circuit CBA is covered by an insulating layer 40. By joining the insulating layer 40 with an insulating layer 50 covering a plurality of word lines WL, a semiconductor memory device 1 is formed, which includes a plurality of word lines WL, select gate lines SGD, SGS, pillar PL, and contact CC, as well as the peripheral circuit CBA.

[0029] Next, a detailed configuration example of the semiconductor memory device 1 will be described using Figures 2A and 2B. Figures 2A and 2B are cross-sectional views along the Y direction showing an example of the configuration of the semiconductor memory device 1 according to Embodiment 1.

[0030] More specifically, Figure 2A is a cross-sectional view of the memory region MR of the semiconductor memory device 1. In Figure 2A, the structure below the insulating layer 60 and above the insulating layer 53 described below is omitted. Figure 2B is an enlarged cross-sectional view of the pillar PL at the height of the word line WL and the select gate lines SGD and SGS.

[0031] As shown in Figure 2A, the source line SL has a multilayer structure formed by sequentially depositing, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb, on the insulating layer 60. The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polycrystalline silicon layers. Among them, at least the intermediate source line BSL can be a polycrystalline silicon layer with diffused impurities and high conductivity.

[0032] Furthermore, the source line SL is connected to the peripheral circuit CBA via a through contact (not shown) and through the electrode film EL, which extends from the electrode film EL to the peripheral circuit CBA within the aforementioned insulating layer 50 outside the stacked body LM.

[0033] A stacked body LM is disposed on the source line SL. The stacked body LM has stacked bodies LMa and LMb formed by alternately stacking a plurality of character lines WL and a plurality of insulating layers OL.

[0034] The stacked layer LMa is positioned above the source line SL. Below the bottommost word line WL of the stacked layer LMa, a plurality of selector gate lines SGS0 and SGS1 are sequentially arranged from the layer above LMa, separated by an insulating layer OL. The stacked layer LMb is positioned on the stacked layer LMa. Above the topmost word line WL of the stacked layer LMb, a plurality of selector gate lines SGD0 and SGD1 are sequentially arranged from the layer above LMb, separated by an insulating layer OL.

[0035] However, the number of word lines WL and select gate lines SGD and SGS in the multilayer LM is arbitrary. The word lines WL and select gate lines SGD and SGS are, for example, tungsten or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0036] As shown in Figure 2B, the surfaces on both sides of the stacking direction of the stacked bodies LM of the plurality of character lines WL and the select gate lines SGD and SGS are sequentially covered by the barrier metal layer 25 and the metal-containing layer 55. Furthermore, the surfaces of the character lines WL and the select gate lines SGD and SGS facing the side of the pillar PL are also sequentially covered by the barrier metal layer 25 and the metal-containing layer 55.

[0037] The barrier metal layer 25 comprises, for example, at least one of a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, and a molybdenum nitride layer. Thereby, the barrier metal layer 25 inhibits the diffusion of metal atoms such as tungsten or molybdenum constituting the character lines WL to adjacent layers. The metal layer 55, for example, is an alumina (Al2O3) layer, which has a higher dielectric constant than the silicon oxide layer, and functions as a barrier insulating layer in the memory cell MC described below.

[0038] As shown in Figure 2A, the upper surface of the laminate LM is covered by insulating layer 52. Insulating layer 52 is covered by insulating layer 53. Insulating layers 52 and 53 each constitute a portion of insulating layer 50 in Figure 1A.

[0039] As described above, the laminated body LM is divided in the Y direction by a plurality of plate-like contacts LI. That is, each plate-like contact LI is arranged relative to the other in the Y direction and extends in the lamination direction of the laminated body LM and in the direction along the X direction.

[0040] Thus, the plate-shaped contact LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb, reaching the intermediate source line BSL.

[0041] Furthermore, the plate-shaped contact LI may have, for example, a tapered shape in which the width in the Y direction decreases from the upper end to the lower end. Alternatively, the plate-shaped contact LI may have, for example, a bowling pin shape in which the width in the Y direction is greatest at a predetermined position between the upper and lower ends.

[0042] Each plate-shaped contact LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polycrystalline silicon layer.

[0043] The insulating layer 54 covers the opposite sidewall of the plate-shaped contact LI in the Y direction. The conductive layer 24 fills the inner side of the insulating layer 54 and is electrically connected to the source line SL, which includes the intermediate source line BSL. However, instead of the plate-shaped contact LI, the plate-shaped member filled with the insulating layer can extend through the laminate LM and extend in the direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0044] Furthermore, a plurality of separation layers SHE are disposed between adjacent plate-shaped contacts LI in the Y direction. These separation layers SHE penetrate the upper portion of the stacked body LMb and extend in the X direction. These separation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selector gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selector gate line SGD1.

[0045] In other words, the separation layers SHE that penetrate the upper part of the stacked body LMb extend along the X direction between the plate-shaped contacts LI in one part of the memory region MR and the stepped region SR, thereby dividing the upper part of the stacked body LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0046] Within the memory region MR, a plurality of pillars PL are distributed, including a through-layer LM, an upper source line DSLb, an intermediate source line BSL, and a lower source line DSLa.

[0047] Multiple columns (PLs) are arranged in a staggered manner when viewed from the lamination direction of the lamination body (LM). Each column (PL) has a shape such as circular, elliptical, or oblong (oval) as its cross-sectional shape along the lamination direction of the lamination body (LM), that is, along the XY plane.

[0048] Furthermore, the portion of column PL that penetrates the laminate LMa and the portion that penetrates the laminate LMb respectively have a conical shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the portion of column PL that penetrates the laminate LMa and the portion that penetrates the laminate LMb respectively have a bowling pin shape in which the diameter and cross-sectional area become the largest at a predetermined position between the upper and lower layers.

[0049] Each of the multiple pillars PL has: a memory layer ME that extends in the stacking direction within the stacked body LM; a channel layer CN that penetrates the stacked body LM and is connected to the intermediate source line BSL; a capping layer CP that covers the upper surface of the channel layer CN; and a core layer CR that becomes the core material of the pillar PL.

[0050] More specifically, the channel layer CN is directly connected to the intermediate source line BSL at its depth position. That is, the memory layer ME is disposed on the side of the pillar PL, except at the depth position of the intermediate source line BSL. Furthermore, the memory layer ME is also disposed on the bottom surface of the pillar PL that reaches the depth of the lower source line DSLa.

[0051] As shown in Figure 2B, the memory layer ME has a stacked structure comprising a spacer layer SP, a barrier insulating layer BK, a tunnel insulating layer TN, and a charge storage layer CT.

[0052] More specifically, the spacer layer SP covers the surfaces of a plurality of insulating layers OL facing the pillars PL. The barrier insulating layer BK covers the spacer layer SP at the height of the plurality of insulating layers OL, covers the surfaces facing the pillars PL at the height of the plurality of character lines WL and select gate lines SGD and SGS, and extends in the stacking direction of the stack body LM.

[0053] Therefore, the internal shape of the barrier insulating layer BK is such that at the height positions of the plurality of character lines WL and the select gate lines SGD and SGS, it is recessed towards the outer periphery of the pillar PL compared to other parts. That is, when viewed from the center direction of the pillar PL, the recessed portion of the barrier insulating layer BK is concave. The charge storage layer CT includes a plurality of segment layers FG, which are distributed in the stacking direction of the stack body LM in such a way that they are embedded in the recessed portions of the barrier insulating layer BK.

[0054] Furthermore, the height positions of the plurality of character lines WL and select gate lines SGD and SGS refer to the height positions from one side of the stacking direction of the stacked body LM in each character line WL and select gate line SGD and SGS to the other side. That is, the height positions of these character lines WL and select gate lines SGD and SGS do not include the thickness of the barrier metal layer 25 in the stacking direction and the thickness of the metal layer 55 in the stacking direction.

[0055] Similarly, the height position of a plurality of insulating layers OL refers to the height position from one side of the stacking direction of the stacked body LM in each insulating layer OL to the other side.

[0056] The tunnel insulation layer TN covers the blocking insulation layer BK at the height of multiple insulation layers OL, covers the segment layer FG at the height of multiple character lines WL and select gate lines SGD and SGS, and extends in the stacking direction of the stack body LM.

[0057] By covering the surfaces along the opposing surfaces of the segment layer FG contained in the barrier insulation layer BK and the charge storage layer CT and the tunnel insulation layer TN, the tunnel insulation layer TN also has an internal shape that conforms to the internal shape of the barrier insulation layer BK, that is, at the height positions of the plurality of character lines WL and the selected gate lines SGD and SGS, it is recessed towards the outer periphery of the column PL compared to other parts.

[0058] However, by providing a segment layer FG with a charge storage layer CT between the barrier insulating layer BK and the tunnel insulating layer TN, the unevenness of the internal shape of the tunnel insulating layer TN is mitigated compared to the unevenness of the internal shape of the barrier insulating layer BK. Similarly, the channel layer CN, which covers the internal shape of the tunnel insulating layer TN and extends in the stacking direction, also has an internal shape that conforms to the internal shapes of the barrier insulating layer BK and the tunnel insulating layer TN.

[0059] The memory layer ME has a stacked structure as described above, while the charge storage layer CT adopts a segmented structure, that is, at the height position of each word line WL or select gate line SGD, SGS, each segment layer FG is dispersed between the barrier insulation layer BK and the tunnel insulation layer TN.

[0060] Furthermore, in each segment layer FG of the charge storage layer CT, the facing surface opposite to the tunnel insulating layer TN has a shape in which the central portion of the stacking direction of the stacked body LM protrudes inward toward the pillar PL compared to the two ends in the stacking direction. Therefore, the external shape of the tunnel insulating layer TN is larger at height position Pg than at height position Pb. Height position Pb is a predetermined height position located between the two ends in the thickness direction of each of the plurality of character lines WL and the select gate lines SGD and SGS, and is respectively facing the central portion in the stacking direction of each segment layer FG. Height position Pg is a predetermined height position located between the height position Pa of the two ends in the stacking direction of the character lines WL and the select gate lines SGD and SGS and the aforementioned height position Pb, and is respectively facing the portion that deviates from the central portion in the stacking direction of each segment layer FG.

[0061] In other words, for example, within the height range between the two ends of the stacking direction of the fragment layer FG, the height position of the most prominent part of the internal shape of the fragment layer FG in the direction of extension of the column PL can be defined as the height position Pb. Furthermore, within the range between the height positions of the two ends of the stacking direction of the fragment layer FG and the height position Pb, the height position of the part of the internal shape of the fragment layer FG that recedes last from the center in the direction of extension of the column PL can be defined as the height position Pg.

[0062] That is, when the shape of the column PL, as observed from the stacking direction of the stacked body LM, is, for example, circular, the tunnel insulation layer TN has an external shape in which the diameter at height position Pb is smaller than the diameter at height position Pg. Furthermore, the tunnel insulation layer TN has an external shape in which the distance ODb in the X direction at height position Pb is smaller than the distance ODg in the X direction at height position Pg.

[0063] As described above, the channel layer CN then penetrates the stack LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa, and making contact with the intermediate source line BSL on its side. In this way, the channel layer CN is electrically connected to the source line SL containing the intermediate source line BSL.

[0064] Furthermore, the top cover layer CP is disposed on the upper end of the pillar PL such that it at least covers the upper end of the channel layer CN, and is connected to the channel layer CN. Moreover, the top cover layer CP is connected to the bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in a direction along the Y direction, intersecting the lead-out direction of the word line WL.

[0065] Furthermore, in Figure 2A, only three of the six pillars PL are connected to plugs CH. These three pillars PL are respectively connected to three separate select gate lines SGD and electrically connected to the bit line BL shown in Figure 2A. The other pillars PL are connected to the other bit lines BL via plugs CH (not shown in Figure 2A). The other bit lines BL extend parallel to the bit line BL shown in Figure 2A in the Y direction at a position different from the cross-section shown in Figure 2A.

[0066] The memory layer ME consists of a spacer layer SP, a barrier insulating layer BK, a tunnel insulating layer TN, and a core layer CR, which may be a silicon oxide layer. The charge storage layer CT, comprising multiple segment layers FG, may be a silicon nitride layer. The channel layer CN and the capping layer CP are semiconductor layers, such as polycrystalline silicon or amorphous silicon layers.

[0067] However, besides silicon oxide layers, the barrier insulating layer BK can also be a metal oxide layer, or a layer composed of silicon oxide layers and metal oxide layers. Furthermore, besides silicon oxide layers, the tunnel insulating layer TN can also be a silicon oxynitride layer. Also, besides silicon nitride layers, the charge storage layer CT, which includes the fragment layer FG, can also be a silicon layer or a metal oxide layer.

[0068] As shown in Figure 2B, with the configuration described above, memory cells MC are formed on the side of the pillar PL, opposite to each character line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage to the character lines WL.

[0069] Furthermore, selective gate STDs are formed on the side of column PL, opposite to the selective gate lines SGD0 and SGD1 which are higher than the character line WL. Also, selective gate STSs are formed on the side of column PL, opposite to the selective gate lines SGS0 and SGS1 which are lower than the character line WL.

[0070] By applying predetermined voltages to the self-selection gate lines SGD and SGS respectively, the selection gates STD and STS are turned on or off, thereby enabling the memory cell MC of the column PL to which the selection gates STD and STS belong to to be set to a selected state or a non-selected state.

[0071] (Manufacturing method of semiconductor memory device) Next, the manufacturing method of the semiconductor memory device 1 according to Embodiment 1 will be described using Figures 3A to 9G. Figures 3A to 7C in Figures 3A to 9G are diagrams illustrating a portion of the manufacturing method of the semiconductor memory device 1 according to Embodiment 1 in sequence. Figures 3A to 7C show cross-sections along the Y direction of the region that will subsequently become the memory region MR.

[0072] As shown in Figure 3A, a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are sequentially formed on the support substrate SS.

[0073] As the support substrate SS, semiconductor substrates such as silicon substrates, insulating substrates such as ceramic substrates, or conductive substrates can be used. The aforementioned insulating layer 60 can also be formed on the upper surface side of the support substrate SS (see Figure 2A, etc.). The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and is a layer that will later be replaced by a polycrystalline silicon layer to become the intermediate source line BSL.

[0074] A laminate LMsa is formed on the upper source line DSLb by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that will later be replaced with a conductive material to become the word line WL or the select gate line SGS.

[0075] Subsequently, although not illustrated, insulating layers NL and OL are processed into a stepped shape in a portion of the stacked matrix LMsa. This processing can be performed by refining the masking pattern such as the photoresist layer and repeatedly etching the insulating layers NL and OL of the stacked matrix LMsa.

[0076] Specifically, a mask pattern is formed on the upper surface of the stacked layer LMsa, and the exposed portions of the insulating layers NL and OL are etched away layer by layer. Then, by using a process such as oxygen plasma, the ends of the mask pattern are retracted to expose a new portion of the upper surface of the stacked layer LMsa, and the insulating layers NL and OL are further etched away layer by layer. By repeating this process multiple times, a stacked layer LMsa with a stepped shape at both ends in the X direction is formed.

[0077] As shown in Figure 3B, a plurality of memory vias MHa are formed in the stacked matrix LMsa, extending along the stacking direction. These memory vias MHa penetrate the stacked matrix LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, reaching the lower source line DSLa. These memory vias MHa subsequently form part of the lower structure of the pillar PL.

[0078] As shown in Figure 3C, the memory holes MHa are filled with sacrificial layers 26, such as amorphous silicon layers or CVD-carbon layers. This forms a pillar PLc formed by filling a plurality of memory holes MHa with sacrificial layers 26.

[0079] As shown in Figure 3D, a stacked body LMsb is formed, which covers a stacked body LMsa and is composed of multiple insulating layers NL and multiple insulating layers OL, which are stacked alternately layer by layer. The insulating layer NL of the stacked body LMsb functions as a sacrificial layer that will later be replaced by a conductive layer to become a word line WL or a select gate line SGD.

[0080] Subsequently, although not illustrated, the insulating layers NL and OL are processed into a stepped shape in a portion of the stacked matrix LMsb. This processing is similar to the processing of the stacked matrix LMsa described above, and can be performed by refining the masking pattern such as the photoresist layer and repeatedly etching the insulating layers NL and OL of the stacked matrix LMsb.

[0081] At this point, the uppermost segment of the stepped portion already formed in the laminate LMsa and the lowermost segment of the stepped portion formed in the laminate LMsb are brought close together, forming a stepped shape in a manner that continuously connects from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. In this way, laminates LMsa and LMsb are formed such that stepped regions SR with a stepped shape extending from the laminate LMsa to the laminate LMsb are formed at both ends in the X direction.

[0082] As shown in Figure 4A, a plurality of memory vias MHb are formed, which penetrate the laminate LMsb and are respectively connected to a plurality of pillars PLc formed within the laminate LMsa. The memory vias MHb then become part of the upper structure of the pillars PL.

[0083] As shown in Figure 4B, the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory via MHb. This creates openings at the bottom of the multiple memory vias MHb, forming multiple memory vias MHa that penetrate the stacked layers LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, reaching the lower source line DSLa.

[0084] Furthermore, when the sacrificial layer 26 filled in the column PLC is a CVD-carbon layer or the like, when the masking pattern used to form the memory hole MHb in FIG4A is removed by ashing or the like using oxygen plasma, the sacrificial layer 26 can be removed from the column PLC together.

[0085] As shown in Figure 4C, a memory layer ME, a channel layer CN, and a core layer CR are sequentially formed within the memory via MH. This forms the memory layer ME and channel layer CN on the side surface of the memory via MH and the bottom surface exposing the lower source line DSLa, while the core layer CR fills the center of the memory via MH. The memory layer ME, channel layer CN, and core layer CR are also sequentially formed on the upper surface of the stack LMsb.

[0086] Furthermore, when forming the memory layer ME, after forming a charge storage layer CT that extends throughout the entire stacking direction of the stacked layers LMsa and LMsb within the memory aperture MH, the charge storage layer CT is segmented such that each segment FG (refer to Figure 2B) is positioned at the height of a plurality of insulating layers NL. Details regarding the segmentation method of the charge storage layer CT will be described below.

[0087] As shown in Figure 4D, a recess DN is formed at the upper end of the core layer CR and the channel layer CN.

[0088] As shown in Figure 5A, a capping layer CP is formed at the recess DN at the upper end of the memory via MH. The capping layer CP is also formed on the upper surface of the laminate LMsb.

[0089] As shown in Figure 5B, the memory layer ME on the upper surface of the stacked matrix LMsb is removed by CMP and other methods, and a top cap layer CP is formed at the upper end of the memory hole MH.

[0090] As shown in Figure 5C, the insulating layer OL of the topmost layer of the stacked matrix LMsb, which is thinned due to CMP, is deposited. This forms a capping layer CP embedded in the topmost insulating layer OL, forming a pillar PL. However, at this point in time, the memory layer ME covers the entire sidewall of the pillar PL, and it does not become a part of the sidewall of the channel layer CN exposed from the memory layer ME.

[0091] As shown in Figure 6A, a slit ST is formed that penetrates the stacked layers LMsb and LMsa and the upper source line DSLb, reaching the intermediate sacrificial layer SCN. Furthermore, an insulating layer 54s is formed on the opposite sidewall of the slit ST in the Y direction. The slit ST also extends within the stacked layers LMsa and LMsb in the X direction.

[0092] As shown in Figure 6B, a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, flows in through the slit ST protected by the insulating layer 54s on the sidewall, removing the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0093] This forms an interstitial layer GPs between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the interstitial layer GPs. At this time, the sidewalls of the slit ST are protected by the insulating layer 54s, thus preventing the removal of the insulating layer NL within the stacked layers LMsa and LMsb.

[0094] As shown in Figure 6C, the drug solution is appropriately allowed to flow into the interstitial layers GPs through the slit ST, and the barrier insulating layer BK, charge storage layer CT, and tunnel insulating layer TN of the memory layer ME exposed within the interstitial layers GPs are removed in sequence (see Figure 2B). In this way, the memory layer ME is removed from a portion of the sidewall of the pillar PL, exposing a portion of the inner channel layer CN within the interstitial layers GPs.

[0095] As shown in Figure 6D, a raw material gas such as amorphous silicon is injected through the slit ST, which is protected by the insulating layer 54s on the sidewall, and the interstitial layer GPs is filled with amorphous silicon. Furthermore, the support substrate SS is heated to polycrystalline the amorphous silicon filled in the interstitial layer GPs, thereby forming the intermediate source line BSL containing polycrystalline silicon.

[0096] In this way, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0097] As shown in Figure 7A, the insulating layer on the sidewall of the slit ST is temporarily removed for 54 seconds.

[0098] As shown in Figure 7B, a removal solution for insulating layer NL, such as hot phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb through the slit ST, thereby removing the insulating layer NL from the laminates LMsa and LMsb. This forms the laminates LMga and LMgb, which have multiple interstitial layers GP obtained by removing the insulating layer NL between insulating layers OL.

[0099] The laminates LMga and LMgb, containing multiple interstitial layers GP, are fragile structures. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulation layer OL remaining in the laminates LMga and LMgb from flexing, or the laminates LMga and LMgb from deforming or collapsing.

[0100] As shown in Figure 7C, a raw material gas containing a conductive material such as tungsten or molybdenum is injected into the interior of the laminates LMga and LMgb through a slit ST. The conductive material fills the interstitial layer GP of the laminates LMga and LMgb to form multiple character lines WL, etc. In this way, a laminate LM is formed, which consists of laminates LMa and LMb, formed by alternating layers of multiple character lines WL and multiple insulating layers OL.

[0101] The process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, as described above, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0102] Subsequently, an insulating layer 54 is formed on the sidewall of the slit ST, and a conductive layer 24 is filled into the insulating layer 54 to form a plate-shaped contact LI. However, it is also possible to fill the slit ST with an insulating layer 54 instead of a conductive layer 24 to form a plate-shaped member.

[0103] Subsequently, a trench is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 56 is filled into the trench, thereby forming a separation layer SHE that divides the conductive layers into a pattern of selective gate lines SGD.

[0104] Furthermore, a plurality of contacts CC are formed above the stepped region SR. These contacts CC respectively reach the character lines WL and the selector gate lines SGD and SGS of each level of the stepped structure constituting the stepped region SR.

[0105] Furthermore, an insulating layer 52 is formed on the upper surface of the laminate LM, and a plug CH connected to the post PL and a plug connected to the contact CC are formed through the insulating layer 52. Next, an insulating layer 53 is formed on the insulating layer 52, and a bit line BL connected to the plug CH and upper layer wiring connected to the contact CC via the plug are formed. Also, an electrode pad for electrical conduction with the surrounding circuit CBA is formed on the upper surface of the insulating layer 53.

[0106] Furthermore, plugs CH and bit lines BL can also be formed in one step by using methods such as bimetallic damascene.

[0107] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB that is different from the support substrate SS on which the multilayer LM is formed, and is covered by an insulating layer 40. In the insulating layer 40, contacts, vias, wiring, etc., are formed to lead the peripheral circuit CBA to the surface of the insulating layer 40, and are connected to electrode pads, etc., formed on the upper surface of the insulating layer 40.

[0108] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. Afterward, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected across the insulating layer 60 with the plug PG formed therein.

[0109] By following the above steps, the semiconductor memory device 1 of Embodiment 1 can be manufactured.

[0110] Next, the details of the method for segmenting the charge storage layer CT will be explained using Figures 8A to 9G. Figures 8A to 9G are enlarged cross-sectional views illustrating a portion of the sequence of the method for forming the memory layer ME according to Embodiment 1. Figures 8A to 9G show a cross-section of one side wall of the memory hole MH at the height of an arbitrary insulating layer NL that will later become the character line WL.

[0111] As shown in Figure 8A, a memory via MH is formed by the process described in Figure 4B above, which connects the stacked layers LMsa and LMsb.

[0112] As shown in Figure 8B, a spacer layer SP is formed by selectively growing a silicon oxide layer or similar material on the end face of the insulating layer OL exposed on the sidewall of the memory via MH. In this way, the spacer layer SP covers approximately the entire end face of the insulating layer OL. Furthermore, the ends of the stacked spacer layer SP can also partially cover the insulating layer NL.

[0113] As shown in Figure 8C, a barrier insulating layer BK is formed by covering the entire sidewall of the memory via MH with a silicon oxide layer or the like. Alternatively, a silicon nitride layer or the like can be formed to cover the entire sidewall of the memory via MH, and then oxidized to form a silicon oxide barrier insulating layer BK. However, as described above, in addition to a silicon oxide layer or the like, the barrier insulating layer BK can also be a metal oxide layer, or it can be a layer composed of a silicon oxide layer and a metal oxide layer.

[0114] This forms a barrier insulating layer BK, which covers the insulating layer NL exposed on the sidewall of the memory hole MH and the spacer layer SP formed at the height of the insulating layer OL. The barrier insulating layer BK thus formed has a recess DE at the height of the insulating layer NL that is recessed towards the outer periphery of the memory hole MH compared to other parts.

[0115] As shown in Figure 8D, a charge storage layer CT is formed on the surface of the barrier insulating layer BK by continuously covering the entire sidewall of the memory via MH with a silicon nitride layer or the like. However, as mentioned above, in addition to the silicon nitride layer, the charge storage layer CT can also be a silicon layer or a metal oxide layer, etc.

[0116] Through the above processing, the charge storage layer CT also has the following shape: at the recess DE of the blocking insulating layer BK formed at the height position of the insulating layer NL, it is recessed towards the outer periphery of the memory hole MH compared with other parts.

[0117] As shown in Figure 8E, a sacrificial layer 27, such as an amorphous silicon layer, is used to cover the charge storage layer CT on the sidewall of the memory hole MH. At this time, the thickness of the sacrificial layer 27 is adjusted according to the distance from the stacking direction of the recess DE of the blocking insulating layer BK, so that the receding height of the insulating layer NL at the outermost surface of the sacrificial layer 27, i.e., the surface facing the inner side of the memory hole MH, is mitigated. Furthermore, besides an amorphous silicon layer, the sacrificial layer 27 can also be an oxide metal layer such as a silicon oxide layer, a carbon layer, or a hafnium oxide layer.

[0118] As shown in Figure 8F, the thickness of the sacrificial layer 27 on the sidewall of the memory hole MH is selectively reduced. This preserves the sacrificial layer 27 at the height of the charge storage layer CT formed at the height of the insulating layer NL, while exposing the charge storage layer CT formed at the height of the insulating layer OL. Preferably, the thickness reduction conditions of the sacrificial layer 27 are adjusted to minimize the amount of thickness reduction of the sacrificial layer 27 remaining at the height of the charge storage layer CT. Preferably, the outermost surface of the remaining sacrificial layer 27, i.e., the surface facing the inner side of the memory hole MH, is located as close as possible to the inner side of the memory hole MH.

[0119] As shown in Figure 8G, the thickness of the charge storage layer CT on the sidewall of the memory hole MH is selectively reduced. This retains the recessed portion of the charge storage layer CT at the height of the insulating layer NL, while exposing the blocking insulating layer BK formed at the height of the insulating layer OL. A fragment layer FG, which is the remaining recessed portion of the charge storage layer CT, is formed by embedding it into the recess DE of the blocking insulating layer BK.

[0120] At this point, it is preferable to adjust the thickness reduction conditions of the charge storage layer CT so that the outermost surface of the fragment layer FG, i.e. the surface facing the inner side of the memory hole MH, is located closer to the outer periphery of the memory hole MH than the exposed surface of the blocking insulating layer BK formed at the height position of the insulating layer OL.

[0121] Furthermore, at this time, the central area of ​​the insulating layer NL in the thickness direction of the outermost surface of the fragment layer FG is protected by the sacrificial layer 27 remaining after the treatment described above in Figure 8F. In this way, the fragment layer FG becomes a shape in which the central area of ​​the insulating layer NL in the thickness direction protrudes towards the inside of the memory hole MH from both ends of the stacking direction of the laminates LMsa and LMsb.

[0122] As described above, when adjusting the thickness reduction processing conditions of the charge storage layer CT, the thickness reduction processing conditions of the charge storage layer CT can be adjusted in the following manner: on the surface of the internal shape of the fragment layer FG, i.e., on the central side in the extension direction toward the memory hole MH, the diameter at the height position Pa' of each end of the stacking direction of the plurality of fragment layers FG toward the center of the memory hole MH is larger than the diameter at the height position Pb of the central part in the stacking direction of each fragment layer FG.

[0123] Therefore, the fragment layer FG has an internal shape in which the distance ODa' in the X direction at height position Pa' is greater than the distance ODb in the X direction at height position Pb.

[0124] As shown in Figure 8H, the sacrificial layer 27 remaining on the outermost surface of the fragment layer FG is removed.

[0125] As shown in Figure 9A, a tunnel insulation layer TN is formed by covering the entire sidewall of the memory via MH with a silicon oxide layer or the like. However, as mentioned above, in addition to silicon oxide layers or the like, the tunnel insulation layer TN can also be a silicon oxynitride layer or the like.

[0126] Through the above processing, the tunnel insulation layer TN also has the following shape: at the recess DE of the barrier insulation layer BK formed at the height position of the insulation layer NL, it recedes towards the outer periphery of the memory hole MH compared with other parts. However, the degree of receding of the tunnel insulation layer TN is mitigated by the segment layer FG formed in the recess DE of the barrier insulation layer BK.

[0127] As shown in Figure 9B, a channel layer CN is formed by covering the entire sidewall of the memory hole MH with a semiconductor layer or the like. Herein, the channel layer CN also has the following shape: at the height position of the insulating layer NL, that is, at the position where the segment layer FG is formed in the recess DE that blocks the insulating layer BK, it is recessed towards the outer periphery of the memory hole MH compared with other parts.

[0128] As shown in Figure 9C, the core layer CR is formed by filling the memory hole MH, which is located inside the channel layer CN, with an oxide insulating layer.

[0129] Subsequently, the processing shown in Figures 4D to 5C is performed to form a pillar PL with a capping layer CP at the upper end. Then, the processing shown in Figures 6A to 6D is performed to form an intermediate source line BSL, and the channel layer CN is connected to the source line SL on the side.

[0130] Furthermore, the processing shown in Figures 7A to 7C is performed, replacing the insulating layer NL with the character line WL, etc. Details are shown below in Figures 9D to 9G.

[0131] As shown in Figure 9D, the insulating layer NL within the laminates LMsa and LMsb is removed by hot phosphoric acid or similar methods. This forms a gap layer GP between the plurality of insulating layers OL. Furthermore, within the gap layer GP, the upper and lower surfaces of the insulating layers OL and a portion of the sidewall of the pillar PL are exposed. More specifically, the exposed sidewall of the pillar PL within the gap layer GP is the outer surface of the blocking insulating layer BK that forms the recess DE.

[0132] As shown in Figure 9E, a metal-containing layer 55 is formed by covering the upper and lower surfaces of the exposed insulating layer OL inside the gap layer GP and the outer surface of the recess DE that blocks the insulating layer BK with a layer of dielectric constant such as aluminum oxide layer that is higher than silicon oxide layer.

[0133] As shown in Figure 9F, a barrier metal layer 25 is formed by covering the surface of the metal-containing layer 55 formed in the interstitial layer GP with a titanium layer, titanium nitride layer, tantalum layer, tantalum nitride layer or molybdenum nitride layer.

[0134] As shown in Figure 9G, a tungsten layer or a molybdenum layer is filled into the gap layer GP, which is further inside the barrier metal layer 25, to form the character line WL.

[0135] (Summary) In semiconductor memory devices such as three-dimensional non-volatile memory, the spacing between multiple word lines is being reduced. As the word line spacing decreases, interference may occur between memory cells. Furthermore, there is a situation where charge stored in the charge storage layer of a memory cell moves to adjacent memory cells, leading to a deterioration in the data retention characteristics of the memory cell. To suppress this inter-cell interference and data retention degradation, it is more effective, for example, to construct a segmented structure where the charge storage layer is segmented for each memory cell. After forming a charge storage layer covering the entire sidewall of the memory hole, the charge storage layer is segmented into individual segment layers at the height of the word line.

[0136] However, the individual fragment layers obtained by segmentation as described above sometimes form an arc shape, with both ends of the stacking direction protruding inwards towards the pillars and the central portion of the stacking direction concave. In this case, when data is written to the memory cell, a channel is formed between the two ends of the fragment layer in the stacking direction, and the charge concentrates in the central portion of the fragment layer in the stacking direction, thus causing localized writing. This results in a reduction in the effective length of the stacking direction in the fragment layer, making it prone to data saturation during writing.

[0137] According to the semiconductor memory device 1 of Embodiment 1, the tunnel insulating layer TN has an external shape at a height position Pb that is a predetermined distance ODb along the X direction, and an external shape at a height position Pg that is a distance ODg that is greater than the distance ODb at the height position Pb along the X direction. The height position Pb is the height position facing the plurality of segment layers FG respectively, and is located between the two ends of the plurality of word lines WL and select gate lines SGD and SGS in the thickness direction. The height position Pg is located between the height position Pa of the two ends of the word lines WL, etc. and the height position Pb.

[0138] This allows for the suppression of the fragment layer (FG) from becoming arc-shaped, resulting in a fragment layer FG with a flatter inner surface. Consequently, localized write concentration within the fragment layer FG can be suppressed, thereby improving the characteristics of the memory cell (MC).

[0139] Furthermore, by appropriately adjusting the method for forming the memory layer ME in Embodiment 1 above, it is possible to obtain various memory layer variations with different shapes. Several examples of memory layers with different shapes are shown in the following Variation Examples 1 to 3.

[0140] (Variation Example 1) Next, the semiconductor memory device of Variation 1 of Embodiment 1 will be described using FIG10. The semiconductor memory device of Variation 1 has a tunnel insulating layer TNab with a flatness of internal shape that is higher than that of the tunnel insulating layer TN in Embodiment 1 described above.

[0141] Furthermore, in Figure 10 below, sometimes the same symbols are used to mark the same components as in Embodiment 1 above, and their descriptions are omitted.

[0142] Figure 10 is an enlarged cross-sectional view of the column PLab of the semiconductor memory device in Variation 1 of Embodiment 1 at the height of the word line WL and the select gate lines SGD and SGS.

[0143] As shown in Figure 10, in Variation Example 1, the pillar PLab has a memory layer MEab comprising a barrier insulating layer BKab and a tunnel insulating layer TNab instead of the memory layer ME in Embodiment 1. The memory layer MEab has other spacer layers SP and a charge storage layer CT comprising a fragment layer FG with the same configuration as in Embodiment 1.

[0144] In Variation Example 1, the barrier insulating layer BKab has a thickness that varies depending on the height position of the laminate LM. More specifically, the barrier insulating layer BKab is thinner at the height positions of the plurality of insulating layers OL than at the height positions of the plurality of word lines WL and select gate lines SGD, SGS. Furthermore, at the positions between each insulating layer OL and each word line WL and select gate line SGD, SGS, the barrier insulating layer BKab almost disappears.

[0145] Therefore, at the height positions of each insulating layer OL, each character line WL, and the select gate lines SGD and SGS, the tunnel insulating layer TNab protrudes towards the blocking insulating layer BKab. Thus, the external shape of the tunnel insulating layer TNab has the following shape: at the height positions of the plurality of character lines WL and the select gate lines SGD and SGS, it protrudes towards the outer periphery of the post PL compared to other parts.

[0146] Therefore, in the tunnel insulation layer TNab, the layer thickness at the height positions of the multiple character lines WL and the selected gate lines SGD and SGS is greater than the layer thickness at the height positions of the multiple insulation layers OL. Thus, each segment layer FG is generally embedded in the protruding portion of the tunnel insulation layer TNab on the outer periphery of the facing pillar PL.

[0147] At this point, at the height positions of multiple character lines WL and select gate lines SGD and SGS, the total thickness of the blocking insulation layer BKab and the tunnel insulation layer TNab, excluding the segment layer FG, is greater than the total thickness at the height positions of multiple insulation layers OL.

[0148] By having the barrier insulating layer BKab and the tunnel insulating layer TNab with the shapes described above, the internal shape of the tunnel insulating layer TNab, overall, has increased flatness compared to the internal shape of the tunnel insulating layer TN in Embodiment 1. Similarly, the external and internal flatness of the channel layer CNab, overall, has increased compared to the channel layer CN in Embodiment 1.

[0149] At this time, when the shape of the column PLab observed in the stacking direction of the stacked body LM is, for example, circular, the difference between the diameter at height position Pb of the tunnel insulating layer TNab and the diameter at height position Pc of each of the plurality of insulating layers OL is less than the difference between the diameters at each height position Pb and Pc of the internal shape of the tunnel insulating layer TN in Embodiment 1. The height position Pb is the height position between the two ends of the thickness direction of each of the plurality of character lines WL and the selected gate lines SGD and SGS, and is respectively opposite to the central part of the stacking direction of each segment layer FGab.

[0150] Furthermore, the tunnel insulation layer TNab has the following internal shape: the difference between the diameter at the height position Pa' of each end of the plurality of segment layers FGab in the stacking direction opposite to the tunnel insulation layer TNab and the diameter at the height position Pc of each of the plurality of insulation layers OL is smaller than that of the tunnel insulation layer TN in Embodiment 1 described above.

[0151] Furthermore, the tunnel insulation layer TNab has an internal shape in which the distances in the X direction at each height position Pa', Pb, and Pc are approximately equal to each other. In this case, the tunnel insulation layer TNab may have an internal shape in which the distance in the X direction at height position Pb is less than or equal to the distance in the X direction at height position Pc.

[0152] According to the semiconductor memory device of Variation Example 1, the total thickness of the barrier insulating layer BKab and the tunnel insulating layer TNab at the height positions of the plurality of word lines WL and the select gate lines SGD and SGS, excluding the plurality of segment layers FG, is greater than the total thickness of the barrier insulating layer BKab and the tunnel insulating layer TNab at the height positions between the word lines WL, etc.

[0153] By adopting this configuration, the flatness of the tunnel insulation layer TNab is increased, thereby further reducing write concentration in the fragment layer FG.

[0154] According to the semiconductor memory device of Variation Example 1, the tunnel insulating layer TNab has an internal shape at a height position Pc between the plurality of word lines WL and the select gate lines SGD and SGS, which is a predetermined distance IDc in the direction along the X direction, and an internal shape at a height position Pb of the word lines WL, etc., which is a distance IDb below the distance IDc at the height position Pc in the direction along the X direction.

[0155] This indicates a further increase in the flatness of the tunnel insulation layer TNab. This, in turn, allows for a further reduction in write concentration within the fragment layer FG.

[0156] The semiconductor memory device according to Variation Example 1, except for the above, performs the same effects as the semiconductor memory device 1 of Embodiment 1.

[0157] (Variation Example 2) Next, the semiconductor memory device of Variation 2 of Embodiment 1 will be described using FIG11. The difference between the semiconductor memory device of Variation 2 and Embodiment 1 is that the length of the fragment layer FGac in the stacking direction of the stacked body LM is longer than the fragment layer FG of the charge storage layer CT in Embodiment 1.

[0158] Furthermore, in Figure 11 below, sometimes the same symbols are used to mark the same components as in Embodiment 1 above, and their descriptions are omitted.

[0159] Figure 11 is an enlarged cross-sectional view of the pillar PLAc of the semiconductor memory device in Variation 2 of Embodiment 1 at the height of the word line WL and the select gate lines SGD and SGS.

[0160] As shown in Figure 11, in Variation Example 2, the pillar PLAc is replaced by a memory layer MEac having a spacer layer SPac, a barrier insulating layer BKac, and a charge storage layer CTac containing a segment layer FGac. The other tunnel insulating layer TN has the same configuration as in Embodiment 1.

[0161] In Variation Example 2, the spacer layer SPac has a length in the stacking direction of the stack body LM that is shorter than the shape of the spacer layer SP in Embodiment 1. That is, it is set back in both directions of the stacking direction of the stack body LM relative to each character line WL and the select gate lines SGD and SGS, and is not located near the two ends of the stacking direction of each insulating layer OL.

[0162] Consequently, the width of the recessed portion of the barrier insulation layer BKac at the height position of each character line WL and the select gate lines SGD and SGS increases, and the length of the segment layer FGac formed in the stacking direction of the recessed portion of the barrier insulation layer BKac also increases. Preferably, the length of the segment layer FGac in the stacking direction is greater than or equal to the thickness of each character line WL and the select gate lines SGD and SGS.

[0163] That is, in variation example 2, it is preferable that the distance VDa' between the height positions Pa' of the two ends of each side opposite to the tunnel insulation layer TN in the stacking direction of the plurality of segment layers FGac is greater than the distance VDa between the height positions Pa of the two ends of the plurality of character lines WL and selected gate lines SGD and SGS in the stacking direction.

[0164] According to the semiconductor memory device of Variation Example 2, the length of each of the plurality of segment layers FGac in the stacking direction is greater than or equal to the thickness of the plurality of word lines WL and select gate lines SGD and SGS. This increases the effective length of the segment layers FGac in the stacking direction, thus mitigating localized write concentration. Furthermore, with this configuration, it is expected that write characteristics equivalent to those of a charge storage layer with a non-disconnected structure can be obtained.

[0165] The semiconductor memory device according to Variation Example 2, except for the above, performs the same effects as the semiconductor memory device 1 of Embodiment 1.

[0166] (Variation Example 3) Next, the semiconductor memory device of Variation 3 of Embodiment 1 will be described using FIG12. The semiconductor memory device of Variation 3 differs from that of Embodiment 1 in that it has a pseudo-disruption structure obtained by pseudo-disruption of the charge storage layer CT.

[0167] Furthermore, in Figure 12 below, sometimes the same symbols are used to mark the same components as in Embodiment 1 above, and their descriptions are omitted.

[0168] Figure 12 is an enlarged cross-sectional view of the column PLAd of the semiconductor memory device of Embodiment 1, at the height of the word line WL and the select gate lines SGD and SGS.

[0169] As shown in Figure 12, in addition to having a spacer layer SP, a barrier insulating layer BK, and a charge storage layer CT containing a fragment layer FG, the pillar PLAd of Variation Example 3 also has a memory layer MEad with a charge storage layer CTad.

[0170] The charge storage layer CTad is covered with a barrier insulating layer BK at the height of a plurality of insulating layers OL, and with a segment layer FG of the charge storage layer CT at the height of a plurality of word lines WL and select gate lines SGD and SGS, and extends continuously in the stacking direction of the stack body LM. The charge storage layer CTad is, for example, a silicon nitride layer, similar to the charge storage layer CT.

[0171] At this point, it is desirable that the charge storage layer CTad is thin enough to prevent the degradation of memory cell properties, such as those found in non-disjunct charge storage layers, from occurring. For example, the thickness of the charge storage layer CTad is at least less than the thickness of each segment layer FG.

[0172] With this configuration, the charge storage layer CTad connects the individual segment layers FG to each other, and these segment layers FG have a pseudo-discontinuity structure.

[0173] According to the semiconductor memory device of Variation 3, a charge storage layer CTad is further provided. The charge storage layer CTad contains the same material as the charge storage layer CT, is in contact with the faces of the plurality of segment layers FG and the tunnel insulating layer TN, and extends in the stacking direction of the stacked body LM at the position between the tunnel insulating layer TN and the plurality of segment layers FG and the barrier insulating layer BK.

[0174] In this way, the individual segments FG are connected to each other using a relatively thin charge storage layer CTad, thus making it less likely for data write saturation to occur. Furthermore, by making the charge storage layer CTad thin enough, for example, inter-cell interference and degradation of data retention characteristics can be suppressed.

[0175] The semiconductor memory device according to Variation Example 3, except for the above, performs the same effects as the semiconductor memory device 1 of Embodiment 1.

[0176] (Other examples of variations) Furthermore, the configurations shown in Embodiment 1 and Variations 1-3 above can be appropriately combined and applied to the memory layer of a semiconductor memory device. Next, the memory layer obtained by combining the above configurations will be illustrated using Figures 13A-13H.

[0177] Figures 13A to 13H are enlarged cross-sectional views showing examples of the pillar configuration of a semiconductor memory device according to other variations of Embodiment 1. Furthermore, in Figures 13A to 13H, sometimes the same symbols are used to label configurations that are the same as those in Embodiment 1 or variations 1 to 3 described above, and their descriptions are omitted.

[0178] Figure 13A shows an example of a column PL having the segment layer FG of Embodiment 1. The segment layer FG of Embodiment 1 has an inner surface shape that bulges towards the center of the column PL compared to the two ends of the stacked body LM in the stacking direction.

[0179] Figure 13B shows an example of a pillar PLab of the barrier insulating layer BKab and tunnel insulating layer TNab, in addition to the configuration of Embodiment 1. The thickness of the barrier insulating layer BKab and tunnel insulating layer TNab in Embodiment 1 varies depending on the height position of the pillar PLab. This increases the flatness of the tunnel insulating layer TNab in Embodiment 1.

[0180] Figure 13C shows an example of a columnar PLAc of the segment layer FGac, in addition to the configuration of Embodiment 1. In Embodiment 3, the length of the segment layer FGac in the lamination direction of the laminate LM is increased.

[0181] Figure 13D shows an example of a columnar PLAd with the charge storage layer CTad of Variation 3, in addition to the configuration of Embodiment 1. By having the charge storage layer CTad, the segment layer FG of Variation 3 has a pseudo-fracture structure.

[0182] Figure 13E shows an example of a column PLAe constructed by combining the configurations of Embodiment 1 and Variations 1 and 2. The column PLAe shown in Figure 13E has a tunnel insulation layer TNab with increased flatness and a segment layer FGac with increased length in the lamination direction of the laminate LM.

[0183] Figure 13F shows an example of a column PLAf with a configuration that combines the structures of Embodiment 1 and Variations 2 and 3. The column PLAf shown in Figure 13F has a segment layer FGac, the length of which is extended in the stacking direction of the stacked body LM, and it adopts a pseudo-discontinuity structure connected by a charge storage layer CTad.

[0184] Figure 13G is an example of a column PLAc with a configuration that combines the structures of Embodiment 1 and Variations 1 and 3. The column PLAc shown in Figure 13G has a tunnel insulation layer TNab with increased flatness and a segment layer FG with a pseudo-fraction structure connected by a charge storage layer CTad.

[0185] Figure 13H shows an example of a column PLAh constructed by combining all the components of Embodiment 1 and Variations 1 to 3. The column PLAh shown in Figure 13H includes: a segment layer FGac, which has an inner surface shape that bulges towards the center of the column PLAh compared to the two ends of the stacked body LM in the stacking direction, an increased length in the stacking direction of the stacked body LM, and a pseudo-discontinuity structure connected by a charge storage layer CTad; and a tunnel insulating layer TNab, whose flatness is increased.

[0186] [Implementation Method 2] Hereinafter, Embodiment 2 will be described in detail with reference to the drawings. In the semiconductor memory device of Embodiment 2, the shape of the segment layer included in the charge storage layer is different from that of Embodiment 1 described above.

[0187] In the following figures, sometimes the same symbols are used to mark the same components as in Embodiment 1 above, and their descriptions are omitted.

[0188] (Example of column composition) Figure 14 is an enlarged cross-sectional view of the column PLba of the semiconductor memory device of Embodiment 2 at the height of the word line WL and the select gate lines SGD and SGS.

[0189] As shown in Figure 14, in Embodiment 2, the pillar PLba has a memory layer MEba that includes a charge storage layer CTba containing a segment layer FGba and a tunnel insulating layer TNba, replacing the memory layer ME in Embodiment 1. The memory layer MEba has other spacer layers SP and barrier insulating layers BK with the same configuration as in Embodiment 1.

[0190] In embodiment 2, the face of each segment layer FGba contained in the charge storage layer CTba, which faces the tunnel insulating layer TNba, has the following shape: at the position between the central part and the two ends of the stacked body LM in the stacking direction, it protrudes towards the inside of the column PLba compared to the two ends in the stacking direction.

[0191] Therefore, the external shape of the tunnel insulation layer TNba is larger at height position Pg than at height position Pb. Height position Pb is a predetermined height position between the two ends of the plurality of character lines WL and the select gate lines SGD and SGS in the thickness direction, and is the height position of the most protruding part of the internal shape of each segment layer FGba in the extension direction of the column PLba. Height position Pg is a predetermined height position between the height position Pa of the two ends of the character lines WL and the select gate lines SGD and SGS in the stacking direction and the above-mentioned height position Pb, and is the height position of the last part of the internal shape of each segment layer FGba to recede from the center in the extension direction of the column PLba.

[0192] Furthermore, in Embodiment 2, within the height range between the two ends of the fragment layer FGba in the stacking direction, there are, for example, multiple height positions Pb corresponding to the most prominent part of the center of the internal shape of the fragment layer FGba in the extension direction toward the column PLba. Therefore, the height position Pg between the height position Pa and the height position Pb exists as follows: with a predetermined character line WL as a reference, the height position Pa above the surface of the character line WL in the stacking direction, i.e., the upper surface side, and the height position Pg between the height position Pa and the adjacent height position Pb in the stacking direction; and the height position Pg between the height position Pa below the surface of the character line WL in the stacking direction, i.e., the lower surface side, which is set as the reference character line WL, and the height position Pg between the height position Pa and the adjacent height position Pb in the stacking direction.

[0193] Furthermore, the opposing surface of each segment layer FGba to the tunnel insulation layer TNba has the following shape: at the central portion of the stacking direction of the stacked body LM, it recedes towards the outside of the pillar PL compared to the two ends of the stacking direction. Therefore, the opposing surface of each segment layer FGba to the tunnel insulation layer TNba has the following shape: at the height position Pe of the central portion of the stacking direction of the stacked body LM, it recedes towards the outside of the pillar PL compared to the opposing surface at the height position Pa of the two ends of the stacking direction of the plurality of character lines WL, etc.

[0194] At this time, the portion of fragment layer FGba at the height position Pe of the central part of the stacking direction of the stacked body LM can also have a greater amount of retreat than the portion of fragment layer FGba at the aforementioned height position Pg.

[0195] Therefore, the external shape of the tunnel insulation layer TNba at the height position Pe is larger than the external shape of the word lines WL and the selective gate lines SGD and SGS at the height positions Pa at both ends in the stacking direction. The height position Pe is a predetermined height position between the two ends in the thickness direction of the plurality of word lines WL and the selective gate lines SGD and SGS, and is respectively aligned with the central part of the stacking direction of each segment layer FG.

[0196] That is, when the shape of the column PLba, as observed from the stacking direction of the stacked body LM, is, for example, circular, the tunnel insulation layer TNba has an external shape in which the diameter at height position Pb is smaller than the diameter at height position Pa. Furthermore, the tunnel insulation layer TNba has an external shape in which the diameter at height position Pe is larger than the diameter at height position Pa.

[0197] Furthermore, the tunnel insulation layer TNba has an external shape in which the distances ODe and ODg in the X direction at height positions Pe and Pg are greater than the distance ODb in the X direction at height position Pb. Moreover, the tunnel insulation layer TNba may also have an external shape in which the distance ODe in the X direction at height position Pe is greater than the distance ODg in the X direction at height position Pg.

[0198] (Methods of forming memory layers) Next, the method for forming the memory layer MEba of the semiconductor memory device of Embodiment 2 will be described using Figures 15A to 15G. Figures 15A to 15G are enlarged cross-sectional views illustrating a portion of the method for forming the memory layer MEba of Embodiment 2 in sequence.

[0199] As shown in Figure 15A, a spacer layer SP, a barrier insulating layer BK, a charge storage layer CTba, and a sacrificial layer 27 are sequentially formed on the sidewall of the memory hole MH. However, at this point in time, the charge storage layer CTba is formed in the same manner as the charge storage layer CT in Embodiment 1 above, and has the same shape.

[0200] As shown in Figure 15B, the thickness of the sacrificial layer 27 is selectively reduced so that the sacrificial layer 27 formed in the retreat portion of the charge storage layer CT is retained, and the charge storage layer CT formed at the height position of the insulating layer OL is exposed.

[0201] As shown in Figure 15C, the thickness of the charge storage layer CTba is selectively reduced, so that the recessed portion of the charge storage layer CT is retained, and the blocking insulating layer BK formed at the height position of the insulating layer OL is exposed, thus forming the fragment layer FGba. Preferably, the thickness reduction conditions of the charge storage layer CTba are adjusted such that, when viewed from the stacking direction of the stacked volumes LMsa and LMsb, the position of the outermost surface of the fragment layer FGba is approximately consistent with the position of the outermost surface of the exposed blocking insulating layer BK at the height position of the insulating layer OL.

[0202] Therefore, when adjusting the thickness reduction processing conditions of the charge storage layer CT, for example, before the diameter at the height position Pa' at each end of the stacking direction of the plurality of fragment layers FGba towards the center of the memory hole MH on the central side of the internal shape of the fragment layer FGba is greater than the diameter at the height position between the two height positions Pb in the stacking direction of each fragment layer FGba, the diameter at the center of the stacking direction of each fragment layer FGba is greater than the diameter at the height position between the two height positions Pb. More preferably, the processing is stopped before the diameter at the height position Pa' at each end of the stacking direction of each fragment layer FGba increases by a predetermined distance relative to the diameter at the height position Pb of the most protruding part of each fragment layer FGba.

[0203] Furthermore, this allows for the acquisition of a shape where the central position, protected by the sacrificial layer 27, is the last to recede from the outermost surface of the fragment layer FGba. It also allows for a shape where the positions between the two ends in the lamination direction and the central position are receded from the outermost surface of the fragment layer FGba. In this case, the fragment layer FGba can have an internal shape where the distance ODa' in the X direction at height position Pa' is approximately equal to the distance ODb in the X direction at height position Pb. Furthermore, in this case, the amount of receding portion of the fragment layer FGba from the central position can also be greater than the amount of receding portion between the two ends in the lamination direction and the central position.

[0204] As shown in Figure 15D, the remaining sacrificial layer 27 is removed.

[0205] As described below, the subsequent processing is performed in the same manner as FIG. 9A of Embodiment 1 and the subsequent processing.

[0206] As shown in Figure 15E, a tunnel insulating layer TNba is formed, covering the barrier insulating layer BK and the segment layer FGba. A channel layer CN is then formed, covering the tunnel insulating layer TNba. Finally, a core layer CR is filled within the memory via MH.

[0207] Through the above steps, a spacer layer SP, a memory layer MEba, a channel layer CN, and a core layer CR are formed within the memory hole MH. Subsequent processing is performed in the same manner as in Embodiment 1 described above.

[0208] (Summary) According to the semiconductor memory device of Embodiment 2, the tunnel insulating layer TNba has an external shape at a height position Pb located between the two ends of the plurality of word lines WL and the select gate lines SGD and SGS in the thickness direction, which is a predetermined distance ODb in the X direction, and an external shape at a height position Pg located between the height positions Pa of the aforementioned two ends of the word lines WL, etc., which is a distance ODg in the X direction that is greater than the distance ODb at the aforementioned height position Pb.

[0209] This allows the inner surface of the fragment layer FGba to be suppressed from becoming arc-shaped. Therefore, localized write concentration within the fragment layer FGba can be suppressed, thereby improving the characteristics of the memory cell (MC).

[0210] According to the semiconductor memory device of Embodiment 2, the tunnel insulating layer TNba has a portion located at the center of each of the plurality of word lines WL and the select gate lines SGD and SGS in the thickness direction, and a distance ODe greater than the aforementioned distance ODg in the X direction. Furthermore, the fragment layer FGba at the height position Pb is disposed on both sides of the portion at the distance ODe in the stacking direction. This allows for the dispersion of areas where write concentration occurs by arranging a plurality of bumps and recesses on the inner surface of the fragment layer FGba.

[0211] (Other examples of variations) The configurations shown in variations 1 to 3 of Embodiment 1 above can also be appropriately combined and applied to the memory layer of the semiconductor memory device of Embodiment 2. Next, the memory layer obtained by combining the above configurations will be illustrated using Figures 16A to 16H.

[0212] Figures 16A to 16H are enlarged cross-sectional views showing examples of the column configuration of a semiconductor memory device according to other variations of Embodiment 2. Furthermore, in Figures 16A to 16H, sometimes the same symbols are used to label configurations that are the same as those in Embodiment 2 described above, and their descriptions are omitted.

[0213] Figure 16A shows an example of a column PLba having the segment layer FGba of Embodiment 2. The segment layer FGba of Embodiment 2 has a plurality of concave and convex inner surfaces in the lamination direction of the laminate LM.

[0214] Figure 16B shows an example of a pillar PLbb that, in addition to the configuration of Embodiment 2, also has a configuration equivalent to Variation 1 of Embodiment 1 described above. The thickness of the barrier insulation layer BKbb and the tunnel insulation layer TNbb in Figure 16B varies depending on the height position of the pillar PLbb. As a result, the flatness of the tunnel insulation layer TNbb in Figure 16(b) is increased.

[0215] Figure 16C has an example of a column PLbc that, in addition to the configuration of Embodiment 2, also has a configuration equivalent to Variation 2 of Embodiment 1 described above. In Figure 16C, the width of the recessed portion of the barrier insulating layer BKbc at the height of each character line WL and the select gate lines SGD and SGS increases, and the length of the segment layer FGbc in the stacking direction of the stack body LM is increased.

[0216] Figure 16D shows an example of a column PLbd that, in addition to the configuration of Embodiment 1, also has the charge storage layer CTad of Variation 3. By having the charge storage layer CTad, the segment layer FG of Variation 3 has a pseudo-fracture structure.

[0217] Figure 16E shows an example of a column PLbe constructed by combining the configurations of Embodiment 2 and variations 1 and 2 of Embodiment 1 described above. The column PLbc shown in Figure 16E has a tunnel insulation layer TNbb with increased flatness and a segment layer FGbc with increased length in the lamination direction of the laminate LM.

[0218] Figure 16F shows an example of a column PLbf constructed by combining the configurations of Embodiment 2 and variations 2 and 3 of Embodiment 1 described above. The column PLbf shown in Figure 16F has a segment layer FGbc, the length of which is extended in the stacking direction of the stacked body LM, and it adopts a pseudo-discontinuity structure connected by a charge storage layer CTbd.

[0219] Figure 16G is an example of a column PLbg with a configuration that combines the configurations of Embodiment 2 and variations 1 and 3 of Embodiment 1 described above. The column PLbc shown in Figure 16G has a tunnel insulation layer TNbb with increased flatness and a segment layer FG with a pseudo-fraction structure connected by a charge storage layer CTbd.

[0220] Figure 16H shows an example of a column PLbh constructed by combining all the components of Embodiment 2 and variations 1 to 3 of Embodiment 1 described above. The column PLbh shown in Figure 16H includes: a segment layer FGac, which has an inner surface shape that bulges towards the center of the column PL at the central portion of the laminated body LM in the laminated direction compared to the two ends in the laminated direction, an increased length in the laminated direction of the laminated body LM, and a pseudo-discontinuity structure connected by a charge storage layer CTbd; and a tunnel insulating layer TNab, whose flatness is increased. [Other Implementation Methods]

[0221] In the above-described embodiments 1, 2 and variations 1 to 3, the semiconductor memory device 1 includes a stacked body LM with a two-layer structure obtained by stacking two stacked bodies LMa and LMb one on top of the other. However, the structure of the stacked body is not limited to two layers; it may also be one layer or three or more layers.

[0222] Furthermore, in the above-described embodiments 1, 2, and variations 1 to 3, the pillar PL is equal to the side of the channel layer CN connected to the source line SL, but it is not limited to this. For example, the pillar can also be constructed by removing the memory layer at the bottom of the pillar and connecting it to the source line at the lower end of the channel layer.

[0223] Furthermore, in embodiments 1 and 2 and variations 1 to 3 described above, peripheral circuits CBA and CUA are disposed above or below the multilayer LM. However, the peripheral circuits may also be disposed on the same layer as the multilayer. In this case, the multilayer can be formed at a different location on the semiconductor substrate where the peripheral circuits are formed.

[0224] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0225] 1: Semiconductor memory devices 24: Conductive layer 25: Barrier metal layer 26,27: Sacrificial Layer 40, 50, 52, 53, 54, 54s, 56, 60: Insulation layer 55: Contains a metal layer BK, BKab, BKac, BKbb, BKbc: Barrier Insulation Layer BL: Bitline BLK: Block Region BSL: Intermediate Source Line CBA: Peripheral Circuits CC: Contact CH: plug CN: Channel Layer CP: Top Cover Layer CR: Core Layer CT, CTad, CTbd: Charge storage layer CTac, CTba: Charge storage layer DE: concave part DN: concave area DSLa: Lower source line DSLb: Upper source line EL: Electrode film FG, FGac, FGba, FGbc: Fragment layer GP,GPs interstitial layer IDa',IDb,IDc,ODa',ODb,Ode,ODg,VDa,VDa': distance LI: plate contact LM: Laminated body LMa, LMb: Lamination LMga, LMgb, LMsa, LMsb: laminated body MC: Memory Cell ME, MEab, MEac, MEad, MEba: Memory layer MH, MHa, MHb memory slots MR: Memory Region NL,OL: Insulation layer Pa,Pa',Pb,Pc,Pe,Pg: Height position PG: Plug PL,PLab,PLac,PLad,PLae,PLaf,PLag,PLah,PLba,PLbb,PLbc,PLbd,PLbe,PLbf,PLbg: column PLC: Column SB: Semiconductor substrate SCN: Intermediate Sacrificial Layer SHE: Separation layer SL: Source Line SP, SPac: Spacer layer SR: Stepped Area SGD, SGS: Selecting the gate wire SGD0, SGD1, SGS0, SGS1: Select gate wire SS: Support substrate ST: Slit STD, STS: Select gate TN, TNab, TNbb: Tunnel insulation layer TNba: Tunnel insulation layer TR: Transistor WL: Character Line

Claims

1. A semiconductor memory device comprising: a stacked body formed by stacking a plurality of conductive layers separately from each other; and a pillar extending within the stacked body in a stacking direction; the pillar comprising: a semiconductor layer extending within the stacked body in the stacking direction; first and second insulating layers sequentially covering the sidewalls of the semiconductor layer from the semiconductor layer side; and a plurality of segment layers respectively disposed between the first and second insulating layers such that a third insulating layer comprising a material different from the first and second insulating layers is dispersed at the height position of the plurality of conductive layers. The first insulating layer has a first portion at a height position facing each of the plurality of segment layers, the outer shape of which at the first height position is a first distance along a first direction of the plurality of conductive layers, the first height position being located between the two ends of the plurality of conductive layers in the thickness direction; and a second portion at a second height position, the outer shape of which at the second height position is a second distance greater than the first distance along the first direction, the second height position being located between the height positions of the two ends of the plurality of conductive layers and the first height position.

2. The semiconductor memory device of claim 1, wherein the second part is located at the height position at the center of the thickness direction of each of the plurality of conductive layers.

3. The semiconductor memory device of claim 1, wherein the first insulating layer has a third portion, the third portion being located at a height position at the center of the thickness direction of each of the plurality of conductive layers, and being a third distance in the first direction that is greater than the first distance.

4. The semiconductor memory device of claim 3, wherein the second part is disposed on both sides of the third part in the stacking direction.

5. The semiconductor memory device of claim 1, wherein the total thickness of the first and second insulating layers at the height positions of the plurality of conductive layers, excluding the plurality of segment layers, is greater than the total thickness of the first and second insulating layers at the height positions between the plurality of conductive layers.

6. The semiconductor memory device of claim 5, wherein the first insulating layer has: a fourth portion, the internal shape of which at a height position between the plurality of conductive layers is a fourth distance in the first direction; and a fifth portion, the internal shape of which at a height position between the plurality of conductive layers is a fifth distance below the fourth distance in the first direction.

7. The semiconductor memory device of claim 1, wherein the length of each of the plurality of segment layers in the stacking direction is greater than or equal to the thickness of each of the plurality of conductive layers.

8. The semiconductor memory device of claim 1, wherein the pillar further has a fourth insulating layer comprising the same material as the third insulating layer, is in contact with the respective faces of the plurality of segment layers and the first insulating layer, and extends in the stacking direction at a position between the first insulating layer and the plurality of segment layers and the second insulating layer.

9. The semiconductor memory device of claim 8, wherein the fourth insulating layer has substantially equal thickness at height positions between the plurality of conductive layers and at height positions above the uppermost conductive layer of the plurality of conductive layers.

10. A method for manufacturing a semiconductor memory device, comprising forming a stacked body composed of a plurality of sacrificial layers stacked separately from each other, forming a pillar extending in the stacked body in the stacking direction, and having: a semiconductor layer extending in the stacked body in the stacking direction; first and second insulating layers sequentially covering the sidewalls of the semiconductor layer from the semiconductor layer side; and a plurality of segment layers, respectively disposed between the first and second insulating layers such that a third insulating layer comprising a material different from the first and second insulating layers is dispersed at the height positions of the plurality of sacrificial layers; wherein, when forming the pillar, a hole extending in the stacked body in the stacking direction is formed, and the second insulating layer is formed such that, along a first direction of the plurality of sacrificial layers, the internal shape at the height position between each of the plurality of sacrificial layers is narrower than the internal shape at the height position of each of the plurality of sacrificial layers. A third insulating layer is formed, comprising a material different from the first and second insulating layers. The second insulating layer is continuously covered along its internal shape, with recesses at the height positions of each of the plurality of sacrificial layers. A protective layer is formed filling the recesses of the third insulating layer. The third insulating layer at the height positions between the plurality of sacrificial layers is removed to expose the second insulating layer. The inner surface of the third insulating layer at the height positions of the plurality of sacrificial layers is protected by the protective layer. The third insulating layer is then moved back to a position closer to the sidewall of the hole than the exposed inner surface of the second insulating layer at the height positions between the plurality of sacrificial layers. This forms the plurality of segment layers. After removing the protective layer, a first insulating layer is formed covering the plurality of segment layers and the exposed second insulating layer at the height positions between the plurality of sacrificial layers. A semiconductor layer covering the first insulating layer is formed.

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