Semiconductor memory devices and methods for manufacturing semiconductor memory devices

Abstract

A semiconductor memory device according to one embodiment of the present invention includes a first stacked layer, a second stacked layer, a source line, a first pillar portion, a second pillar portion, a first bit line, and a second bit line. The source line is disposed between the first stacked layer and the second stacked layer in a first direction. The first pillar portion extends within the first stacked layer in the first direction. The second pillar portion extends within the second stacked layer in the first direction. The first bit line is disposed on the opposite side of the source line relative to the first stacked layer. The second bit line is disposed on the opposite side of the source line relative to the second stacked layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Prior Technology

[0002] NAND flash memory with memory cells arranged in three dimensions is known (for example, see Japanese Patent Application Publication No. 2018-152419). Summary of the Invention

[0003] A semiconductor memory device according to one embodiment includes a first stacked layer, a second stacked layer, a source line, a first pillar portion, a second pillar portion, a first bit line, and a second bit line. The first stacked layer includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately layer by layer in a first direction. The second stacked layer is disposed on a first side in the first direction relative to the first stacked layer. The second stacked layer includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately layer by layer in the first direction. The source line is disposed between the first stacked layer and the second stacked layer in the first direction. The source line extends in a second direction intersecting the first direction. The first columnar portion extends within the first stacked layer in the first direction. The first columnar portion includes a first memory film having a charge storage portion and a first semiconductor film. The second columnar portion extends within the second stacked layer in the first direction. The second columnar portion includes a second memory film having a charge storage portion and a second semiconductor film. The first bit line is disposed on the opposite side of the source line relative to the first stacked layer. The first bit line is electrically connected to the first columnar portion. The second bit line is disposed on the opposite side of the source line relative to the second stacked layer. The second bit line is electrically connected to the second columnar portion. Simple Explanation of the Diagram

[0004] Figure 1 is a block diagram showing a portion of the semiconductor memory device according to the first embodiment. Figure 2 is a diagram showing the equivalent circuit of a portion of the memory cell array of the first embodiment. Figure 3 is a diagram used to illustrate the semiconductor memory device of the first embodiment. Figure 4 is a diagram illustrating the region division of the memory cell array in the first embodiment. Figure 5 is a cross-sectional view of the semiconductor memory device shown in Figure 4 along line F5-F5. Figure 6 is a cross-sectional view of the semiconductor memory device shown in Figure 4 along line F6-F6. Figure 7 is an enlarged representation of the area enclosed by line F7 in the structure shown in Figure 4. Figure 8 is an enlarged representation of the area enclosed by line F8 in the structure shown in Figure 7. Figure 9 is a cross-sectional view illustrating the memory column of the first embodiment. Figure 10 is a cross-sectional view of the structure shown in Figure 9 along line F10-F10. Figure 11 is a cross-sectional view showing the structure of the semiconductor memory device according to the first embodiment. Figure 12 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 13 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 15 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 16 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 17 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 18 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 19 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 20 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 21 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 22 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 23 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 24 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 25 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 26 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 27 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 28 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 29 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 30 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 31 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 32 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 33 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 34 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 35 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 36 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 37 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 38 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 39 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 40 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 41 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 42 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 43 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 44 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 45 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 46 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 47 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 48 is a cross-sectional view of a portion of the semiconductor memory device according to the second embodiment. Figure 49 is a cross-sectional view illustrating the memory column of the second embodiment. Figure 50 is a cross-sectional view of the structure shown in Figure 48 along line F50-F50. Figure 51 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 52 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 53 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 54 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 55 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 56 is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Implementation

[0005] Hereinafter, with reference to the drawings, the semiconductor memory device according to the embodiments and the manufacturing method of the semiconductor memory device will be described. In the following description, components having the same or similar functions are marked with the same symbols. Moreover, repeated descriptions of these components may be omitted at times. In the following description, reference symbols ending with numbers or letters for differentiation may also be omitted if there is no need to distinguish them. In the drawings described below, illustrations of components unrelated to the description may be omitted at times.

[0006] In this application, the terms are defined as follows. "Parallel," "orthogonal," or "identical" may include "substantially parallel," "substantially orthogonal," or "substantially identical," respectively. "Connection" is not limited to mechanical connections and may include electrical connections. That is, "connection" is not limited to the direct connection of multiple elements and may include the connection of multiple elements with other elements intervening in between. "Adjacent" is not limited to the contact of multiple elements and may include the adjacent arrangement of multiple elements with other elements intervening in between.

[0007] The definitions of the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are as described below. The +X direction is the extending direction of the following character line WL (refer to FIG. 5). The -X direction is the opposite direction of the +X direction. When there is no need to distinguish between the +X direction and the -X direction, it is simply referred to as the "X direction". The +Y direction is the direction intersecting with the X direction (for example, orthogonal). The +Y direction is the extending direction of the bit line BL (refer to FIG. 7). The -Y direction is the opposite direction of the +Y direction. When there is no need to distinguish between the +Y direction and the -Y direction, it is simply referred to as the "Y direction". The +Z direction is the direction intersecting with the X direction and the Y direction (for example, orthogonal). The +Z direction is the direction from the following first stacked body 40A to the second stacked body 40B (refer to FIG. 5). The -Z direction is the opposite direction of the +Z direction. When there is no need to distinguish between the +Z direction and the -Z direction, it is simply referred to as the "Z direction". In this application, sometimes the +Z direction side is referred to as "up", and the -Z direction side is referred to as "down". Also, in this application, sometimes the position in the Z direction is referred to as "height". However, these expressions are only for convenience of explanation and are not used to define the direction of gravity. The Z direction is an example of the "first direction". The +Z direction side is an example of the "first side". The -Z direction side is an example of the "second side". The X direction is an example of the "second direction".

[0008] (First Embodiment) <A1. Structure of Semiconductor Memory Device> FIG. 1 is a block diagram showing a part of the semiconductor memory device 1 of the first embodiment. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device. The semiconductor memory device 1 is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device. The semiconductor memory device 1 is used as a memory space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, an instruction register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a column decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k - 1) (k is an integer of 1 or more). The block BLK is a set of memory cell transistors. The block BLK is used as an erasure unit of data. A plurality of bit lines and a plurality of character lines are provided in the memory cell array 11. Each memory cell transistor is associated with one bit line and one character line.

[0010] The instruction register 12 stores the instruction CMD received by the semiconductor memory device 1 from the host device. The address register 13 stores the address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used for the selection of the block BLK, word lines, and bit lines. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, based on the instruction CMD stored in the instruction register 12, the control circuit 14 performs operations such as data writing, reading, or erasing.

[0011] The driver module 15 includes a voltage generation circuit that generates the voltages used in various operations of the semiconductor memory device 1. The column decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line and transfers the determination result as the read data DAT to the host device. The sense amplifier module 17 is an example of a "circuit".

[0012] <A2. Electrical Configuration of Memory Cell Array> <A2.1 Configuration Related to One Block BLK> FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. FIG. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, four strings STR0 to STR3).

[0013] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer of 1 or more), one or more drain-side selection transistors STD, and one or more source-side selection transistors STS.

[0014] In each NAND string NS, the memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage portion. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is stored in the charge storage portion according to the voltage applied to the control gate via the word line WL. Thereby, each memory cell transistor MT stores data non-volatily.

[0015] The drain of the drain-side selection transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor STD is connected to one end of the memory cell transistors MT0 to MTn connected in series. The control gate of the drain-side selection transistor STD is connected to any one of the drain-side selection gate lines SGD0 to SGD3. The drain-side selection transistor STD is electrically connected to the column decoder module 16 via the drain-side selection gate line SGD. When a predetermined voltage is applied to the corresponding drain-side selection gate line SGD, the drain-side selection transistor STD connects the NAND string NS to the bit line BL.

[0016] The drain of the source-side selection transistor STS is connected to the other end of the memory cell transistors MT0 to MTn connected in series. The source of the source-side selection transistor STS is connected to the source line SL. The control gate of the source-side selection transistor STS is connected to the source-side selection gate line SGS. When a predetermined voltage is applied to the source-side selection gate line SGS, the source-side selection transistor STS connects the NAND string NS to the source line SL.

[0017] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the respective corresponding word lines WL0 to WLn. In the same string STR, the control gates of the drain-side selection transistors STD are commonly connected to the corresponding drain-side selection gate lines SGD. The control gates of the source-side selection transistors STS are commonly connected to the source-side selection gate lines SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS assigned the same row address in a plurality of strings STR.

[0018] <Configuration related to a plurality of blocks BLK> FIG. 3 is a diagram for explaining the semiconductor memory device 1. FIG. 3 shows a plurality of blocks BLK included in the memory cell array 11. The memory cell array 11 includes a plurality of blocks BLK. The plurality of blocks BLK include a plurality of block BLKA (a plurality of block BLKA0 to BLKAj (j is an integer of 1 or more)) and a plurality of BLKB (a plurality of block BLKB0 to BLKBj (j is an integer of 1 or more)). The block BLKA is the block BLK included in the following first stacked body 40A (refer to FIG. 5). The block BLKB is the block BLK included in the following second stacked body 40B (refer to FIG. 5).

[0019] In this embodiment, the memory cell array 11 includes a plurality of bit lines BL. The plurality of bit lines BL includes a plurality of bit lines BLA (bit lines BLA0~BLAm (m is an integer greater than or equal to 1)) and a plurality of bit lines BLB (bit lines BLB0~BLBm (m is an integer greater than or equal to 1)).

[0020] A plurality of individual bit lines BLA are set corresponding to a plurality of blocks BLKA. For example, a plurality of individual bit lines BLA are set in common with respect to a plurality of blocks BLKA. Hereinafter, for ease of explanation, bit lines BLA are sometimes referred to as "lower bit lines BLA". The lower bit line BLA is an example of "first bit line".

[0021] A plurality of bit lines (BLBs) are set corresponding to a plurality of blocks (BLKBs). For example, a plurality of bit lines (BLBs) are set in common with respect to a plurality of blocks (BLKBs). Hereinafter, for ease of explanation, bit lines (BLBs) are sometimes referred to as "upper bit lines (BLBs)". The upper bit line (BLB) is an example of a "second bit line".

[0022] The sense amplifier module 17 has a plurality of sense amplifier units 17a. The plurality of sense amplifier units 17a are provided corresponding to a plurality of bit lines BL. Each sense amplifier unit 17a is, for example, a circuit controlled by a signal from the control circuit 14. For example, the sense amplifier unit 17a has a latching circuit electrically connected to the corresponding bit line BL. The sense amplifier unit 17a applies a voltage to the corresponding bit line BL based on the signal from the control circuit 14. Each sense amplifier unit 17a has a terminal 17t connected to the electrical connection line 18 described below. Terminal 17t is an example of a "first terminal".

[0023] In this embodiment, in addition to the above-described configuration, the memory cell array 11 further includes a plurality of electrical connection lines 18 and a switching circuit 19.

[0024] A plurality of electrical connection lines 18 are disposed between a plurality of sense amplifier units 17a and a plurality of bit lines BL. The plurality of electrical connection lines 18 are connection lines that electrically connect the plurality of sense amplifier units 17a and the plurality of bit lines BL. The plurality of electrical connection lines 18 are arranged in a one-to-one relationship with the plurality of sense amplifier units 17a. For example, the plurality of electrical connection lines 18 are electrically connected to the terminals 17t of the plurality of sense amplifier units 17a in a one-to-one relationship.

[0025] The switching circuit 19 is a circuit that can at least switch between a first state and a second state. The first state is a state in which the terminals 17t of the plurality of sense amplifier units 17a are electrically connected to the plurality of lower bit lines BLA one by one. The second state is a state in which the terminals 17t of the plurality of sense amplifier units 17a are electrically connected to the plurality of upper bit lines BLB one by one. The switching circuit 19 includes, for example, a switching circuit 19A and a switching circuit 19B.

[0026] The switching circuit 19A is provided between the plurality of electrical connection lines 18 and the plurality of lower bit lines BLA. The switching circuit 19A includes a plurality of switching elements 19Aa that electrically connect the plurality of electrical connection lines 18 and the plurality of lower bit lines BLA in a one-to-one relationship. The plurality of switching elements 19Aa are controlled, for example, by a common communication signal issued from the control circuit 14 to the plurality of switching elements 19Aa. The switching circuit 19A can switch between the first state and the second state. The first state is a state in which the plurality of electrical connection lines 18 are electrically connected to the plurality of lower bit lines BLA. The second state is a state in which the plurality of electrical connection lines 18 are electrically disconnected from the plurality of lower bit lines BLA.

[0027] The switching circuit 19B is provided between the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB. The switching circuit 19B includes a plurality of switching elements 19Ba that electrically connect the plurality of electrical connection lines 18 and the plurality of upper bit lines BLB in a one-to-one relationship. The plurality of switching elements 19Ba are controlled, for example, by a common communication signal issued from the control circuit 14 to the plurality of switching elements 19Ba. The switching circuit 19B can switch between the first state and the second state. The first state is a state in which the plurality of electrical connection lines 18 are electrically connected to the plurality of upper bit lines BLB. The second state is a state in which the plurality of electrical connection lines 18 are electrically disconnected from the plurality of upper bit lines BLB.

[0028] <A3. Structure of the semiconductor memory device> Next, the structure of the semiconductor memory device 1 will be described.

[0029] <A3.1 Regional division of the memory cell array> Here, the regional division of the memory cell array 11 will be described first. FIG. 4 is a diagram for explaining the regional division of the memory cell array 11. The memory cell array 11 includes, for example, a plurality of array regions AR, a plurality of wiring regions FR, and a plurality of bit line access regions BR.

[0030] In the array region AR, the following plurality of memory columns MH are provided. The array region AR is a region capable of storing data. The wiring region FR is a region where the following plurality of contact points CC are provided, and the following plurality of gate electrode layers 41 are electrically connected to the wiring portion 60. In the example shown in FIG. 4, the wiring region FR is provided on one side in the X direction of the array region AR. However, the wiring region FR may also be provided on both sides in the X direction of the array region AR.

[0031] In the bit line access region BR, the following plurality of contact points CS are provided. The bit line access region BR is a region where the switching circuit 19 (or the sense amplifier module 17) is electrically connected to the plurality of upper bit lines BLB. The bit line access region BR may also be referred to as the "bit line connection region". The bit line access region BR is arranged between two adjacent array regions AR in the Y direction. The bit line access region BR extends along the X direction.

[0032] <A3.2 Bonding Structure> Next, the bonding structure of the semiconductor memory device 1 will be described. FIG. 5 is a cross-sectional view of the semiconductor memory device 1 shown in FIG. 4 along the line F5-F5. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0033] (First Chip) The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of solder pads 24.

[0034] The semiconductor substrate 例如為作為第1晶片2之基底之基板。半導體基板21之至少一部分呈沿著X方向及Y方向之板狀。半導體基板21例如由諸如矽之半導體材料形成。

[0035] The peripheral circuit 22 is a circuit for enabling the above-mentioned memory cell array 11 to function. The peripheral circuit 22 includes a plurality of transistors 22a and a plurality of electrical connection lines 22b. The peripheral circuit 22 includes one or more of the above-mentioned instruction register 12, address register 13, control circuit 14, driver module 15, column decoder module 16, sense amplifier module 17, a plurality of electrical connection lines 18, and switching circuit 19. For example, the switching elements 19Aa and 19Ba of the switching circuit 19 are respectively formed by transistors 22a provided on the semiconductor substrate 21. The insulating portion 23 covers the peripheral circuit 22. A plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0036] (Second chip) The second chip 3 is an array chip including the memory cell array 11. The second chip 3, for example, has a memory cell array 11, an insulating portion 31, and a plurality of pads 32. Here, the insulating portion 31 and the plurality of pads 32 will be described. Regarding the memory cell array 11, it will be described below.

[0037] The insulating portion 31 covers the memory cell array 11 from the -Z direction side. A plurality of pads 32 are provided on the surface of the insulating portion 31. Each pad 32 is electrically connected to an electrical connection line (for example, electrical connection lines 61, 62, 63, 64) included in the wiring portion 60 of the following memory cell array 11. In the present embodiment, by relatively bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3, the first chip 2 and the second chip 3 are integrated.

[0038] <A4. Structure of array region and wiring region> Next, the structures of the array region AR and the wiring region FR will be described. As shown in FIG. 5, the memory cell array 11, for example, has a stacked body 40, an insulating portion 45, a plurality of memory columns MH, a plurality of lower bit lines BLA, a plurality of upper bit lines BLB, a plurality of contacts CH for the memory columns, a plurality of contacts VY for the memory columns, a contact CC for the gate electrode layer, a plurality of dividing portions 50 (refer to FIG. 6), and a wiring portion 60. The stacked body 40 includes a first stacked body 40A, a second stacked body 40B, and a source line SL. Furthermore, the memory columns MH will be described below.

[0039] <A4.1 First stacked body> The first stacked layer 40A is a stacked layer forming the aforementioned plurality of blocks BLKA. The first stacked layer 40A includes, for example, a plurality of gate electrode layers 41A, a plurality of insulating layers 42A, and an insulating layer 43. The plurality of gate electrode layers 41A and the plurality of insulating layers 42A are stacked alternately layer by layer in the Z direction.

[0040] Gate electrode layer 41A is a conductive layer along the X and Y directions. Each gate electrode layer 41A contains a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities). Gate electrode layer 41A is an example of a "first gate electrode layer".

[0041] Of the plurality of gate electrode layers 41A, one or more (e.g., a plurality of) upper gate electrode layers 41A function as source-side selected gate lines (SGS) for block BLKA. The source-side selected gate lines SGSA are commonly provided relative to the columnar portions 91 (hereinafter) below the plurality of memory pillars MH arranged in the X or Y direction. The intersection of the source-side selected gate lines SGSA with the channel layers 72 (hereinafter) of each memory pillar MH functions as the aforementioned source-side selected transistor STS.

[0042] Of the plurality of gate electrode layers 41A, one or more (e.g., a plurality of) lower gate electrode layers 41A function as drain-side selected gate lines SGD (drain-side selected gate lines SGDA) for the block BLKA. The drain-side selected gate lines SGDA are commonly provided relative to the columnar portions 91 (hereinafter) below the plurality of memory pillars MH arranged in the X or Y direction. The intersection of the drain-side selected gate lines SGDA with the channel layers 72 (hereinafter) of each memory pillar MH functions as the aforementioned drain-side selected transistor STD.

[0043] Of the plurality of gate electrode layers 41A, the remaining gate electrode layers 41A are those between the gate electrode layers 41A that function as source-side select gate line SGSA and drain-side select gate line SGDA. At least a portion of these remaining gate electrode layers 41A function as word lines WL (WLA) for block BLKA. The word lines WL are commonly provided relative to the columnar portions 91 (hereinafter) below the plurality of memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection of the word lines WL with the channel layers 72 (hereinafter) of each memory pillar MH functions as the aforementioned memory cell transistor MT.

[0044] The lengths of the plurality of gate electrode layers 41A in the X direction are different in the wiring region FR. For example, regarding the lengths of the plurality of gate electrode layers 41A laminated in the Z direction, the length of the gate electrode layer 41A on the +Z direction side in the X direction is larger than the length of the gate electrode layer 41A on the -Z direction side in the X direction. That is, the closer the gate electrode layer 41A is to the +Z direction side, the greater the length in the X direction. Thereby, the ends of the plurality of gate electrode layers 41A are arranged in a stepped manner in the wiring region FR.

[0045] The insulating layer 42A is provided between two adjacent gate electrode layers 41A in the Z direction. The insulating layer 42A is an interlayer insulating film that insulates the two gate electrode layers 41A. The insulating layer 42A extends along the X direction and the Y direction. The insulating layer 42A is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film). The insulating layer 42A is an example of the "first insulating layer".

[0046] [[ID=?]] The insulating layer 43 is an insulating layer provided above the gate electrode layer 41A arranged at the uppermost position. In other words, the insulating layer 43 can also be said to be an insulating layer provided above the uppermost gate electrode layer. The insulating layer 43 is arranged between the gate electrode layer 41A arranged at the uppermost position and the source line SL. The insulating layer 43 extends along the X direction and the Y direction. The insulating layer 43 is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is greater than the thickness of the insulating layer 42A in the Z direction.

[0047] <A4.2 Second Stacked Body> The second stacked body 40B is a stacked body that forms the plurality of blocks BLKB. The second stacked body 40B is arranged on the upper side (+Z direction side) with respect to the first stacked body 40A. The second stacked body 40B includes, for example, a plurality of gate electrode layers 41B, a plurality of insulating layers 42B, and an insulating layer 44. The plurality of gate electrode layers 41B and the plurality of insulating layers 42B are alternately laminated layer by layer in the Z direction.

[0048] The gate electrode layer 41B is a conductive layer extending along the X direction and the Y direction. Each gate electrode layer 41B contains a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities). The gate electrode layer 41B is an example of the "second gate electrode layer".

[0049] Of the plurality of gate electrode layers 41B, one or more (e.g., a plurality of) lower gate electrode layers 41B function as source-side selected gate lines (SGS) for the block BLKB. The source-side selected gate lines SGSB are commonly provided relative to the columnar portions 92 (hereinafter) on the plurality of memory pillars MH arranged in the X or Y direction. The intersection of the source-side selected gate lines SGSB with the channel layer 72 (hereinafter) of each memory pillar MH functions as the aforementioned source-side selected transistor STS.

[0050] Of the plurality of gate electrode layers 41B, one or more (e.g., a plurality of) gate electrode layers 41B located at the top function as drain-side selected gate lines SGD (drain-side selected gate lines SGDB) for the block BLKB. The drain-side selected gate lines SGDB are commonly provided with respect to the columnar portions 92 (hereinafter) on the plurality of memory pillars MH arranged in the X or Y direction. The intersection of the drain-side selected gate lines SGDB with the channel layers 72 (hereinafter) of each memory pillar MH functions as the aforementioned drain-side selected transistor STD.

[0051] Of the plurality of gate electrode layers 41B, the remaining gate electrode layers 41B are those between the gate electrode layers 41B that function as source-side select gate line SGSB and drain-side select gate line SGDB. At least a portion of these gate electrode layers 41B function as word lines WL (WLB) for the block BLKB. The word lines WL are commonly provided with respect to the columnar portions 92 (hereinafter) on the plurality of memory pillars MH arranged in the X and Y directions. In this embodiment, the intersection of the word lines WL with the channel layers 72 (hereinafter) of each memory pillar MH functions as the aforementioned memory cell transistor MT.

[0052] In the wiring region FR, the lengths of the plurality of gate electrode layers 41B in the X direction are not the same. For example, regarding the length of the plurality of gate electrode layers 41B stacked in the Z direction, the length of the gate electrode layer 41B located on the +Z direction side in the X direction is greater than the length of the gate electrode layer 41B located on the -Z direction side in the X direction. That is, the longer the gate electrode layer 41B is located on the +Z direction side, the greater its length in the X direction. Therefore, the ends of the plurality of gate electrode layers 41B are arranged in a stepped manner in the wiring region FR.

[0053] The insulating layer 42B is disposed between two gate electrode layers 41B adjacent in the Z direction. The insulating layer 42B is an interlayer insulating film that insulates the two gate electrode layers 41B. The insulating layer 42B extends in the X direction and the Y direction. The insulating layer 42B is formed of a film containing silicon and oxygen (for example, a silicon oxide film), for example. The insulating layer 42B is an example of the "second insulating layer".

[0054] The insulating layer 44 is an insulating layer disposed below the gate electrode layer 41B arranged at the lowermost position. In other words, the insulating layer 44 can also be said to be an insulating layer disposed below the lowermost gate electrode layer. The insulating layer 44 is disposed between the gate electrode layer 41B arranged at the lowermost position and the source line SL. The insulating layer 44 extends in the X direction and the Y direction. The insulating layer 44 is formed of a film containing silicon and oxygen (for example, a silicon oxide film), for example. For example, the thickness of the insulating layer 44 in the Z direction is larger than the thickness of the insulating layer 42B in the Z direction.

[0055] In an example of the semiconductor memory device 1, the number of the plurality of gate electrode layers 41A included in the first stacked body 40A is different from the number of the plurality of gate electrode layers 41B included in the second stacked body 40B. In this case, the size of the block BLKA included in the first stacked body 40A is different from the size of the block BLKB included in the second stacked body 40B. This point will be described in detail below. Further, the number of the plurality of gate electrode layers 41A included in the first stacked body 40A may be the same as the number of the plurality of gate electrode layers 41B included in the second stacked body 40B.

[0056] Further, hereinafter, when there is no need to distinguish between the first gate electrode layer 41A and the second gate electrode layer 41B, it will be simply referred to as "gate electrode layer 41". When there is no need to distinguish between the first insulating layer 42A and the second insulating layer 42B, it will be simply referred to as "insulating layer 42".

[0057] <A4.3 Source Line> The source line SL is disposed between the first stacked body 40A and the second stacked body 40B in the Z direction. The source line SL extends in the X direction and the Y direction. The source line SL is a conductive layer or a semiconductor layer along the X direction and the Y direction. The source line SL is formed of a semiconductor material containing silicon, for example. The source line SL is formed of polysilicon doped with impurities, for example. However, the material of the source line SL is not limited to the above examples. The source line SL may also be formed of a metal material such as tungsten or molybdenum. The thickness of the source line SL in the Z direction is larger than the sum of the thickness of the gate electrode layer 41 in the Z direction and the thickness of the insulating layer 42 in the Z direction, for example.

[0058] In this embodiment, the source line SL extends across the array region AR and the wiring region FR. The source line SL includes a first portion SLa disposed in the array region AR and a second portion SLb disposed in the wiring region FR. In this embodiment, the thicknesses in the Z direction of the first portion SLa and the second portion SLb are different. The thickness T1 in the Z direction of the first portion SLa is greater than the thickness T2 in the Z direction of the second portion SLb. For example, the thickness T1 in the Z direction of the first portion SLa is two times or more the thickness T2 in the Z direction of the second portion SLb. There is a step difference between the first portion SLa and the second portion SLb.

[0059] <Insulating portion of the wiring region A4.4> The insulating portion 45 is an insulating portion provided in the wiring region FR. The insulating portion 45 is formed using, for example, TEOS (tetraethoxysilane (Si(OC2H5)4)). A part of the insulating portion 45 covers the ends of the plurality of gate electrode layers 41A arranged in a stepped manner from the -Z direction side. A part of the insulating portion 45 covers the ends of the plurality of gate electrode layers 41B arranged in a stepped manner from the -Z direction side. A part of the insulating portion 45 is disposed between the second portion SLb of the source line SL and the first laminate 40A, and covers the second portion SLb of the source line SL from the -Z direction side.

[0060] [[ID=*]] <Lower bit line A4.5> The lower bit line BLA is an electrical connection line for selecting one of the following plurality of lower columnar portions 91. The plurality of lower bit lines BLA are arranged on the lower side (-Z direction side) with respect to the first laminate 40A. The plurality of lower bit lines BLA are arranged on the opposite side of the source line SL with respect to the first laminate 40A. The plurality of lower bit lines BLA are arranged at intervals in the X direction and extend in the X direction. The lower bit line BLA extends in the Y direction (see FIG. 6). The lower bit line BLA extends so as to pass below the corresponding plurality of lower columnar portions 91.

[0061] The lower bit line BLA is electrically connected to the channel layer 72 of the following lower columnar portion 91 via the contact VY and the contact CH. Thus, by the combination of the word line WLA and the lower bit line BLA, a memory cell transistor MT can be arbitrarily selected from the plurality of memory cell transistors MT three-dimensionally arranged in the first laminate 40A.

[0062] <Upper bit line A4.6> The upper bit line BLB is an electrical connection line for selecting one upper columnar portion 92 from the following plurality of upper columnar portions 92. The plurality of upper bit lines BLB are arranged on the upper side (+Z direction side) with respect to the second stacked body 40B. The plurality of upper bit lines BLB are arranged on the opposite side of the source line SL with respect to the second stacked body 40B. The plurality of upper bit lines BLB are arranged at intervals in the X direction and arranged in the X direction. The upper bit line BLB extends in the Y direction (see FIG. 6). The upper bit line BLB extends so as to pass above the corresponding plurality of upper columnar portions 92.

[0063] The upper bit line BLB is electrically connected to the channel layer 72 of the following upper columnar portion 92 via the contact VY and the contact CH. Thus, by the combination of the word line WLB and the upper bit line BLB, a memory cell transistor MT can be arbitrarily selected from the plurality of memory cell transistors MT arranged three-dimensionally in the second stacked body 40B. <A4.7 Contact for gate electrode layer>

[0064] The contact CC is an electrical connection portion that electrically connects the gate electrode layer 41 and an electrical connection line 63 (described below) included in the wiring portion 60. The plurality of contacts CC are provided, for example, in the wiring region FR of the memory cell array 11. The plurality of contacts CC extend in the Z direction within the stacked body 40. The lengths of the plurality of contacts CC in the Z direction are different from each other, and are respectively connected to different gate electrode layers 41. The contact CC has conductivity. The contact CC is formed of a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities). <0 A4.8 Disconnection portion>

[0065] In the present embodiment, the contact CC is connected to the plurality of gate electrode layers 41A included in the first stacked body 40A from the -Z direction side. Similarly, the contact CC is connected to the plurality of gate electrode layers 41B included in the second stacked body 40B from the -Z direction side.

[0066] Next, the disconnection portion 50 will be described. FIG. 6 is a cross-sectional view of the semiconductor memory device shown in FIG. 4 along the line F6-F6. The plurality of disconnection portions 50 are provided in the stacked body 40. The plurality of disconnection portions 50 are separately arranged in the Y direction. The plurality of disconnection portions 50 extend in the Z direction within the stacked body 40. The plurality of disconnection portions 50 disconnect one or more gate electrode layers 41 including the lowermost layer or the uppermost layer among the plurality of gate electrode layers 41 in the Y direction. The plurality of disconnection portions 50 include, for example, a plurality of disconnection portions ST (only one is shown in FIG. 6) and a plurality of disconnection portions SHE.

[0067] (Breaking part ST) The segment ST is a wall portion that divides the laminate 40 along the Y direction. Multiple segments ST are arranged separately in the Y direction. The segments ST extend in the Z direction. The segments ST penetrate the laminate 40. For example, the segments ST penetrate the first laminate 40A, the source line SL, and the second laminate 40B in the Z direction.

[0068] The segment ST extends in the X direction (see Figure 7). For example, the segment ST extends in the X direction, spanning the array region AR and the wiring region FR. The segment ST is a wall portion along both the X and Z directions. The segment ST segments all gate electrode layers 41 (all gate electrode layers 41A and all gate electrode layers 41B) included in the laminate 40 along the Y direction. In this embodiment, in the first laminate 40A, the region sandwiched between two adjacent segment STs in the Y direction corresponds to one block BLKA. Similarly, in the second laminate 40B, the region sandwiched between two adjacent segment STs in the Y direction corresponds to one block BLKB.

[0069] In this embodiment, the segment ST has an insulating film 51 and a conductive layer (conductive portion) 52. The insulating film 51 extends in the Z direction. The insulating film 51 penetrates the laminate 40. The insulating film 51 is provided across the entire length of the segment ST in the X direction. The insulating film 51 covers the conductive layer 52. The insulating film 51 has an insulating film 51s1 forming the surface of the segment ST in the +Y direction and an insulating film 51s2 forming the surface of the segment ST in the -Y direction. The insulating film 51 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film).

[0070] A conductive layer 52 is disposed inside the insulating film 51. For example, the conductive layer 52 is disposed between insulating films 51s1 and 51s2 in the Y direction. The conductive layer 52 extends in the Z direction. The conductive layer 52 penetrates the laminate 40. The conductive layer 52 is formed of a conductive material such as tungsten, molybdenum, or silicon doped with impurities. The upper end of the conductive layer 52 is electrically connected to an electrical connection line 64 within the memory cell array 11 via contacts 55 and 56.

[0071] In this embodiment, the break section ST has a first portion STa and a second portion STb. The insulating film 51 and the conductive layer 52 are disposed spanning the first portion STa and the second portion STb.

[0072] Part 1 STa extends through the first stacked body 40A in the Z direction. Part 1 STa divides the plurality of gate electrode layers 41A along the Y direction. Part 1 STa extends from the lower side to the upper side of the first stacked body 40A. The upper end of Part 1 STa is located inside the source line SL.

[0073] The second part STb is positioned on the upper side (+Z direction side) relative to the first part STa. The second part STb penetrates the second stacked body 40B in the Z direction. The second part STb divides the plurality of gate electrode layers 41B along the Y direction. The second part STb extends from the lower side to the upper side of the second stacked body 40B. The lower end of the second part STb is located inside the source line SL. The lower end of the second part STb, inside the source line SL, connects to the upper end of the first part STa. The boundary between the first part STa and the second part STb is located inside the source line SL.

[0074] The width W1 of the first part STa in the Y direction is greater than the width W2 of the second part STb in the Y direction. For example, the width W1 of the first part STa in the Y direction is more than twice the thickness of the insulating film 51s1 in the Y direction compared to the width W2 of the second part STb. At the boundary between the first part STa and the second part STb, a step difference Ts is formed, which is based on the difference between the width W1 of the first part STa and the width W2 of the second part STb in the Y direction. The step difference Ts is the step difference in the Y direction. The step difference Ts is located inside the source line SL.

[0075] In this embodiment, the insulating film 51 is not provided at the step difference Ts of the segment ST. The insulating film 51 is segmented along the Y direction at the boundary (step difference Ts) between the first part STa and the second part STb of the segment ST. For example, the insulating film 51 includes a first insulating film 51a located in the first part STa of the segment ST and a second insulating film 51b located in the second part STb of the segment ST. The first insulating film 51a extends in the Z direction in the first part STa. The first insulating film 51a is located between the conductive layer 52 and the plurality of gate electrode layers 41A. The second insulating film 51b extends in the Z direction in the second part STb. The second insulating film 51b is located between the conductive layer 52 and the plurality of gate electrode layers 41B. In this embodiment, the first insulating film 51a and the second insulating film 51b are separated in the Y direction at the step difference Ts.

[0076] On the other hand, conductive layer 52 is disposed in the first portion STa and the second portion STb. For example, conductive layer 52 is continuous across the first portion STa and the second portion STb. Therefore, in the region where the insulating film 51 is interrupted (at the step difference Ts), conductive layer 52 is exposed outside the interrupted portion 50 (outside the insulating film 51) and connected to the source line SL. In this way, conductive layer 52 is electrically connected to source line SL. Voltage is applied to source line SL via the electrical connection lines 64, contacts 55 and 56, and conductive layer 52 at the interrupted portion ST.

[0077] (Breaking part SHE) The segmentation section SHE is a segment whose length in the Z direction is shorter than that of the segmentation section ST. The segmentation section SHE is a wall portion that severs the lower or upper end of the laminate 40 along the Y direction. A plurality of segmentation sections SHE may include, for example, a plurality of segmentation sections SHEA and a plurality of segmentation sections SHEB.

[0078] The SHEA section is a wall portion that severs the lower end of the first laminate 40A along the Y direction. A plurality of SHEA sections are arranged separately in the Y direction. In this embodiment, a plurality of (e.g., 3) SHEA sections exist between two adjacent SHEA sections ST in the Y direction. The SHEA section extends in the Z direction to the middle of the first laminate 40A. The SHEA section extends in the X direction. The SHEA section is a wall portion along both the X and Z directions.

[0079] The SHEA segment penetrates a portion of the gate electrode layers 41A, including the lowest layer. The SHEA segments this portion of the gate electrode layers 41A along the Y direction. For example, the SHEA segments penetrate all gate electrode layers 41A that function as the drain-side select gate line (SGDA). On the other hand, the SHEA segments do not reach the gate electrode layers 41A that function as the word line (WLA). The SHEA segments only segment the gate electrode layers 41A that function as the drain-side select gate line (SGDA) along the Y direction. The SHEA segments are formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). In this embodiment, the region between two adjacent SHEA segments in the Y direction corresponds to one string STR.

[0080] The dividing portion SHEB is a wall portion that divides the upper end portion of the second stacked body 40B in the Y direction. A plurality of dividing portions SHEB are arranged separately in the Y direction. In the present embodiment, there are a plurality of (for example, three) dividing portions SHEB between two adjacent dividing portions ST in the Y direction. The dividing portion SHEB extends in the Z direction to the middle of the second stacked body 40B. The dividing portion SHEB extends in the X direction. The dividing portion SHEB is a wall portion along the X direction and the Z direction.

[0081] The dividing portion SHEB penetrates a part of the gate electrode layers 41B including the uppermost layer among the plurality of gate electrode layers 41B. The dividing portion SHEB divides the above-mentioned part of the gate electrode layers 41B in the Y direction. For example, the dividing portion SHEB penetrates all the gate electrode layers 41B that function as the drain-side selection gate lines SGDB respectively. On the other hand, the dividing portion SHEB does not reach the gate electrode layers 41B that function as the word lines WLB. The dividing portion SHEB only divides the gate electrode layers 41B that function as the drain-side selection gate lines SGDB in the Y direction. The dividing portion SHEB is formed of a film containing silicon and oxygen (for example, a silicon oxide film) for example. In the present embodiment, the area sandwiched between two adjacent dividing portions SHEB in the Y direction corresponds to one string STR.

[0082] <A4.9 Wiring portion> The wiring portion 60 is an electrical connection portion that electrically connects a plurality of solder pads 32 to each component included in the memory cell array 11. The wiring portion 60 includes, for example, a wiring portion 60A and a wiring portion 60B.

[0083] The wiring portion 60A is a wiring portion arranged between the first stacked body 40A and the semiconductor substrate 21. The wiring portion 60A includes, for example,a plurality of electrical connection lines 61, a plurality of electrical connection lines 62, and a plurality of electrical connection lines 63 (refer to FIG. 5).

[0084] A plurality of electrical connection lines 61 are arranged, for example, on the lower side (-Z direction side) with respect to a plurality of lower bit lines BLA. Each electrical connection line 61 extends in the X direction or the Y direction for example. A through hole VA that electrically connects the electrical connection line 61 and the lower bit line BLA is provided between the electrical connection line 61 and the lower bit line BLA.

[0085] The electrical connection line 61 electrically connects the peripheral circuit (for example, the sense amplifier unit 17a) to the lower bit line BLA. For example, the electrical connection line 61 electrically connects the switching circuit 19 (for example, the switching circuit 19A) to the lower bit line BLA. For example, the electrical connection line 61 electrically connects the switching element 19Aa of the switching circuit 19A to the lower bit line BLA. In the present embodiment, the electrical connection line 61 is electrically connected to the bonding pad 32 for bonding. The electrical connection line 61 is electrically connected to the switching circuit 19A via the bonding pads 24 and 32.

[0086] A plurality of electrical connection lines 62 are arranged on the lower side (-Z direction side) with respect to a plurality of contact points CS (only 1 is shown in FIG. 6) provided in the bit line access area BR. Each electrical connection line 62 extends in the X direction or the Y direction, for example. A contact point VB for electrically connecting the electrical connection line 62 and the contact point CS is provided between the electrical connection line 62 and the contact point CS.

[0087] The electrical connection line 62 electrically connects the peripheral circuit (for example, the sense amplifier unit 17a) to the contact point CS. For example, the electrical connection line 62 electrically connects the switching circuit 19 (for example, the switching circuit 19B) to the contact point CS. For example, the electrical connection line 62 electrically connects the switching element 19Ba of the switching circuit 19B to the contact point CS. In the present embodiment, the electrical connection line 62 is electrically connected to the bonding pad 32 for bonding. The electrical connection line 62 is electrically connected to the switching circuit 19B via the bonding pads 24 and 32. [[ID=,10]]

[0088] The electrical connection line 63 electrically connects the peripheral circuit to the contact point CC (refer to FIG. 5). In the present embodiment, the electrical connection line 63 is electrically connected to the bonding pad 32 for bonding. A voltage for selecting the gate electrode layer 41 (word line WL, drain side select gate line SGD or source side select gate line SGS) is applied to the electrical connection line 63.

[0089] <A5. Structure of the bit line access area> Next, the structure of the bit line access area BR will be described. As shown in FIG. 6, the bit line access area BR includes a third stacked body 40C, a fourth stacked body 40D, an insulating portion 47, and a plurality of contact points CS (only 1 is shown in FIG. 6).

[0090] <A5.1 The third stacked body> The third stacked body 40C is a stacked body around a part of the contact CS. The third stacked body 40C includes, for example, a plurality of insulating layers 46A and a plurality of insulating layers 42A. The plurality of insulating layers 46A and the plurality of insulating layers 42A are stacked alternately layer by layer in the Z direction.

[0091] The insulating layer 46A is located at the same height as the gate electrode layer 41A. The insulating layer 46A extends in the X direction and the Y direction. The insulating layer 46A is connected to the gate electrode layer 41A in the Y direction. The insulating layer 46A is formed, for example, by retaining a part of a sacrificial layer (the following sacrificial layer 111A) to be replaced with the gate electrode layer 41A during the manufacturing process without replacement. The insulating layer 46A is formed of a material different from the insulating layer 42A. The insulating layer 46A is formed, for example, of a film containing silicon and nitrogen (for example, a silicon nitride film).

[0092] The insulating layer 42A is provided between two adjacent insulating layers 46A in the Z direction. The insulating layer 42A extends in the X direction and the Y direction. The insulating layer 42A is formed, for example, of a film containing silicon and oxygen (for example, a silicon oxide film). The insulating layer 42A included in the bit line access region BR is located at the same height as the insulating layer 42A included in the array region AR. The insulating layer 42A included in the bit line access region BR is continuous with the insulating layer 42A included in the array region AR.

[0093] <A5.2 The fourth stacked body The fourth stacked body 40D is a stacked body around another part of the contact CS. The fourth stacked body 40D is arranged on the upper side (+Z direction side) with respect to the third stacked body 40C. The fourth stacked body 40D includes, for example, a plurality of insulating layers 46B and a plurality of insulating layers 42B. The plurality of insulating layers 46B and the plurality of insulating layers 42B are stacked alternately layer by layer in the Z direction.

[0094] The insulating layer 46B is located at the same height as the gate electrode layer 41B. The insulating layer 46B extends in the X direction and the Y direction. The insulating layer 46B is connected to the gate electrode layer 41B in the Y direction. The insulating layer 46B is formed, for example, by retaining a part of a sacrificial layer (the following sacrificial layer 111B) to be replaced with the gate electrode layer 41B during the manufacturing process without replacement. The insulating layer 46B is formed of a material different from the insulating layer 42B. The insulating layer 46B is formed, for example, of a film containing silicon and nitrogen (for example, a silicon nitride film).

[0095] The insulating layer 42B is disposed between two adjacent insulating layers 46B in the Z direction. The insulating layer 42B extends in the X and Y directions. The insulating layer 42B is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating layer 42B included in the bit line access region BR is at the same height as the insulating layer 42B included in the array region AR. The insulating layer 42B included in the bit line access region BR is continuous with the insulating layer 42B included in the array region AR.

[0096] <A5.3 Insulating Portion> The insulating portion 47 is disposed between the third stacked body 40C and the fourth stacked body 40D in the Z direction. The insulating portion 47 is embedded between the third stacked body 40C and the fourth stacked body 40D. The insulating portion 47 is adjacent to the source line SL in the Y direction.

[0097] <A5.4 Contact> The contact CS is an electrical connection portion that electrically connects a peripheral circuit (e.g., the sense amplifier unit 17a) and the upper bit line BLB. In the present embodiment, the contact CS electrically connects the switching circuit 19 and the upper bit line BLB. For example, the contact CS electrically connects the switching element 19Ba of the switching circuit 19B and the upper bit line BLB.

[0098] In the present embodiment, the contact CS is a columnar body extending in the Z direction. The contact CS penetrates the third stacked body 40C, the fourth stacked body 40D, and the insulating portion 47 in the Z direction. The contact CS extends across the lower side of the third stacked body 40C and the upper side of the fourth stacked body 40D.

[0099] The upper end of the contact VB is electrically connected to the upper bit line BLB via the contact VC, for example. The lower end of the contact CS is electrically connected to the switching circuit 19 via the contact VB, for example. Further, in another example of the semiconductor memory device 1, the switching circuit 19 may not exist. In a configuration without the switching circuit 19, the lower end of the contact CS is electrically connected to the sense amplifier unit 17a via the contact VB, for example.

[0100] FIG. 7 is a diagram showing an enlarged view of a region surrounded by the line F7 in the structure shown in FIG. 4. As shown in FIG. 7, the upper bit line BLB extends in the Y direction so as to overlap the contact CS and a plurality of blocks BLK when viewed from the Z direction.

[0101] FIG. 8 is a view showing an enlarged view of a region surrounded by a line F8 of the structure shown in FIG. 7. As shown in FIG. 7, in the bit line access region BR, a plurality of contacts CS are arranged separately from each other. For example, the plurality of contacts CS are arranged offset in the X direction and the Y direction. A plurality of upper bit lines BLB are electrically connected to corresponding contacts CS in a one-to-one relationship via the above-mentioned contacts VC in the bit line access region BR.

[0102] <A6. Memory pillar> <A6.1 Internal structure of the memory pillar> Next, the memory pillar MH will be described. A plurality of memory pillars MH are arranged in the X direction and the Y direction (refer to FIG. 7). Each memory pillar MH extends in the Z direction within the laminate 40. Each memory pillar MH penetrates the laminate 40. The memory pillar MH is an example of a "columnar body".

[0103] FIG. 9 is a cross-sectional view for explaining the memory pillar MH. The memory pillar MH has, for example, a memory film (multilayer film) 71, a channel layer 72, an insulating portion 73, and a cover portion 74.

[0104] The memory film 71 is disposed on the outer peripheral portion of the memory pillar MH. The memory film 71 extends in the Z direction. The memory film 71 is provided, for example, so as to span the entire Z-direction length of the memory pillar MH except for the upper end portion and the middle portion of the memory pillar MH. The memory film 71 is located between the plurality of gate electrode layers 41 and the channel layer 72.

[0105] FIG. 10 is a cross-sectional view taken along line F10-F10 of the structure shown in FIG. 9. The memory film 71 includes, for example, a block insulating film 81, a charge trapping film 82, and a tunnel insulating film 83.

[0106] The block insulating film 81 is disposed on the outermost peripheral portion of the memory pillar MH. The block insulating film 81 is provided between the plurality of gate electrode layers 41 and the charge trapping film 82. The block insulating film 81 is an insulating film that suppresses reverse tunneling. Reverse tunneling refers to a phenomenon in which charges return from the word line WL to the charge trapping film 82. The block insulating film 81 is formed in a ring shape. The block insulating film 81 extends in the Z direction. The block insulating film 81 is provided, for example, so as to span the entire Z-direction length of the memory pillar MH except for the upper end portion and the middle portion of the memory pillar MH. The block insulating film 81 is, for example, a laminated structure film formed by laminating a plurality of insulating films such as a film containing silicon and oxygen, or a film containing a metal and oxygen. An example of a film containing a metal and oxygen is an aluminum oxide film. The block insulating film 81 may also contain a high dielectric constant material (high-k material) such as silicon nitride or hafnium oxide.

[0107] A charge trapping film 82 is disposed on the inner periphery of the block insulating film 81 in both the X and Y directions. The charge trapping film 82 is located between the block insulating film 81 and the tunnel insulating film 83. The charge trapping film 82 is formed in a ring shape. The charge trapping film 82 extends in the Z direction. For example, the charge trapping film 82 is disposed in a manner that spans the entire length of the memory column MH in the Z direction, excluding the upper end and middle portion of the memory column MH. The charge trapping film 82 is a functional film having many crystal defects (trapping energy levels) and capable of trapping charge at the crystal defects. The charge trapping film 82 is formed, for example, from a film containing silicon and nitrogen. In the charge trapping film 82, the portion adjacent to each character line WL forms an example of a "charge storage section 82a" capable of storing information by storing charge.

[0108] A tunnel insulating film 83 is disposed on the inner periphery of the charge trapping film 82 in both the X and Y directions. The tunnel insulating film 83 is disposed between the charge trapping film 82 and the channel layer 72. The tunnel insulating film 83 is, for example, formed in a ring shape along the outer periphery of the channel layer 72. The tunnel insulating film 83 extends along the channel layer 72 in the Z direction. The tunnel insulating film 83 is, for example, disposed in a manner that spans the entire Z-direction length of the memory pillar MH, excluding the upper end and middle portion. The tunnel insulating film 83 acts as a potential barrier between the charge trapping film 82 and the channel layer 72. The tunnel insulating film 83 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0109] Channel layer 72 is disposed on the inner periphery of memory film 71 in the X and Y directions. Channel layer 72 is formed in a ring shape. Channel layer 72 extends in the Z direction. Channel layer 72 is disposed, for example, spanning the entire length of memory pillar MH in the Z direction. Channel layer 72 is formed of a semiconductor material such as polysilicon. Channel layer 72 may also be doped with impurities. When a voltage is applied to word line WL, channel layer 72 forms a channel to electrically connect bit line BL and source line SL. Channel layer 72 is an example of a "semiconductor film".

[0110] With the above configuration, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed at the same height as each word line WL. The memory cell transistor MT includes the edge of the word line WL adjacent to the memory pillar MH, a block insulating film 81, a charge trapping film 82, a tunnel insulating film 83, and a channel layer 72. Furthermore, regarding the charge storage section, the memory film 71 may also have a floating gate type charge storage section (floating gate electrode) instead of a charge trapping film 82. The floating gate type charge storage section is, for example, formed of polycrystalline silicon containing impurities.

[0111] Returning to FIG. 9, the remaining structure of the memory column MH will be described. The insulating portion 73 is provided on the inner peripheral side of the channel layer 72 in the X direction and the Y direction. The insulating portion 73 is embedded in at least a part of the inside of the channel layer 72. The insulating portion 73 is formed of a film containing silicon and oxygen (for example, a silicon oxide film). The insulating portion 73 extends in the Z direction. The insulating portion 73 is provided, for example, so as to span the entire length of the memory column MH in the Z direction except for the lower end portion of the memory column MH.

[0112] The cover portion 74 is provided below the insulating portion 73. The cover portion 74 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 74 may also contain impurities, for example. The cover portion 74 is disposed on the inner peripheral side of the lower end portion of the memory film 71. The cover portion 74 is integrated with the channel layer 72. The cover portion 74 and the lower end portion of the channel layer 72 together form the lower end portion of the memory column MH.

[0113] <A6.2 Multi-stage structure of the memory column> In the present embodiment, the memory column MH is formed of multi-stage (for example, three-stage) columnar bodies. For example, the memory column MH includes columnar bodies Ma, Mb, and Mc. The columnar bodies Ma, Mb, and Mc respectively have the above-described memory film (multi-layer film) 71, channel layer 72, and insulating portion 73.

[0114] The lower columnar body Ma is provided in the first stacked body 40A. The columnar body Ma extends inside the first stacked body 40A in the Z direction. The lower end of the columnar body Ma is electrically connected to the lower bit line BLA via the contact CH and the contact VY. The upper end of the columnar body Ma is located inside the first stacked body 40A. As the columnar body Ma advances from the upper side to the lower side, the perimeter (diameter) of the columnar body Ma in the cross section in the X direction and the Y direction gradually increases.

[0115] The middle columnar body Mb is provided on the upper side (+Z direction side) with respect to the columnar body Ma. The columnar body Mb is provided so as to straddle the first stacked body 40A and the second stacked body 40B. The columnar body Mb penetrates the source line SL in the Z direction. The columnar body Mb extends inside the first stacked body 40A and inside the second stacked body 40B in the Z direction. The lower end of the columnar body Mb is connected to the upper end of the columnar body Ma inside the first stacked body 40A. The upper end of the columnar body Mb is connected to the lower end of the columnar body Mc inside the second stacked body 40B. As the columnar body Mb advances from the upper side to the lower side, the perimeter (diameter) of the columnar body Mb in the cross section in the X direction and the Y direction gradually increases.

[0116] The upper columnar body Mc is disposed on the upper side (+Z direction side) with respect to the columnar body Mb. The columnar body Mc is disposed in the second stacked body 40B. The columnar body Mc extends inside the second stacked body 40B in the Z direction. The upper end of the columnar body Mc is electrically connected to the upper bit line BLB via the contact CH and the contact VY. As the columnar body Mc advances from the upper side to the lower side, the circumference (diameter) of the columnar body Mc in the cross section along the X direction and the Y direction gradually increases.

[0117] Furthermore, the configuration of the memory column MH is not limited to the above example. For example, the memory column MH may be formed of one or two columnar bodies, or may be formed of four or more columnar bodies, in addition to the structure formed of three columnar bodies.

[0118] <A6.3 Lower columnar portion and upper columnar portion> As shown in FIG. 9, the memory column MH includes a lower columnar portion 91, an upper columnar portion 92, and an intermediate portion 93.

[0119] (Lower columnar portion) The lower columnar portion 91 is a portion of the memory column MH corresponding to the first stacked body 40A. The lower columnar portion 91 extends inside the first stacked body 40A in the Z direction and penetrates the first stacked body 40A in the Z direction. In the present embodiment, the lower columnar portion 91 is formed of all of the columnar body Ma and the lower portion of the columnar body Mb. In the present embodiment, more than half of the portion of the lower columnar portion 91 in the Z direction is a portion where the circumference (diameter) of the lower columnar portion 91 in the cross section along the X direction and the Y direction gradually increases as it advances from the upper side to the lower side.

[0120] The lower columnar portion 91 includes a part of each of the memory film 71, the channel layer 72, the insulating portion 73, and the cover portion 74. Hereinafter, for the sake of convenience of explanation, the part of the memory film 71 included in the lower columnar portion 91 may be referred to as the "lower memory film 71A". The lower memory film 71A is an example of the "first memory film". Also, hereinafter, for the sake of convenience of explanation, the part of the channel layer 72 included in the lower columnar portion 91 may be referred to as the "lower semiconductor film 72A". The lower semiconductor film 72A is an example of the "first semiconductor film".

[0121] The contact CH is connected to the lower end of the lower columnar portion 91 from the -Z direction side. The lower end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the lower bit line BLA via the contact CH and the contact VY. The upper end of the channel layer 72 (lower semiconductor film 72A) of the lower columnar portion 91 is electrically connected to the source line SL via the intermediate portion 93 described below.

[0122] (Upper columnar part) The upper columnar portion 92 is disposed on the upper side (+Z direction side) relative to the lower columnar portion 91. The upper columnar portion 92 is the portion of the memory column MH that corresponds to the second laminate 40B. The upper columnar portion 92 extends within the second laminate 40B in the Z direction. The upper columnar portion 92 penetrates the second laminate 40B in the Z direction. In this embodiment, the upper columnar portion 92 is formed by the entirety of the columnar body Mc and the upper part of the columnar body Mb. In this embodiment, when viewed from the Z direction, the lower columnar portion 91 and the upper columnar portion 92 overlap. In this embodiment, the portion of the upper columnar portion 92 that occupies more than half in the Z direction is the portion whose circumference (diameter) gradually increases along the X and Y directions of the cross-section as it moves from the upper side to the lower side.

[0123] The upper columnar portion 92 includes a portion of each of the memory film 71, the channel layer 72, and the insulating portion 73. Hereinafter, for ease of explanation, the portion of the memory film 71 included in the upper columnar portion 92 will sometimes be referred to as the "upper memory film 71B". The upper memory film 71B is an example of a "second memory film". Furthermore, hereafter, for ease of explanation, the portion of the channel layer 72 included in the upper columnar portion 92 will sometimes be referred to as the "upper semiconductor film 72B". The upper semiconductor film 72B is an example of a "second semiconductor film".

[0124] The contact CH is connected to the upper end of the upper columnar portion 92 from the +Z direction side. The upper end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the upper bit line BLB via the contact CH and the contact VY. The lower end of the channel layer 72 (upper semiconductor film 72B) of the upper columnar portion 92 is electrically connected to the source line SL via the intermediate portion 93 described below.

[0125] (Middle section) An intermediate portion (intermediate columnar portion) 93 is disposed between the lower columnar portion 91 and the upper columnar portion 92 in the Z direction. The intermediate portion 93 passes through the source line SL in the Z direction. In this embodiment, the intermediate portion 93 is formed from a portion of the columnar body Mb. The intermediate portion 93 includes a portion of each of the memory film 71, the channel layer 72, and the insulating portion 73.

[0126] On the other hand, the memory film 71 does not exist in at least a part of the intermediate portion 93. In the present embodiment, the memory film 71 (lower memory film 71A) of the lower columnar portion 91 and the memory film 71 (upper memory film 71B) of the upper columnar portion 92 are separated in the Z direction. Therefore, in the region where the memory film 71 does not exist in the intermediate portion 93 (the region between the lower memory film 71A and the upper memory film 71B), the channel layer 72 is exposed to the outside of the memory column MH and connected to the source line SL. Thereby, the channel layer 72 is electrically connected to the source line SL.

[0127] <A7. Configuration example of the breaking portion and the bit line access region> <A7.1 Configuration example of the breaking portion> As shown in FIG. 6, the breaking portion ST is disposed between a plurality of memory columns MH (memory columns MHA and memory columns MHB) arranged in the Y direction.

[0128] The lower columnar portion 91 included in the memory column MHA is an example of the "first columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory column MHA is an example of the "first memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory column MHA is an example of the "first semiconductor film".

[0129] The upper columnar portion 92 included in the memory column MHA is an example of the "second columnar portion". The upper memory film 71B of the upper columnar portion 92 included in the memory column MHA is an example of the "second memory film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory column MHA is an example of the "second semiconductor film".

[0130] In one aspect, the lower columnar portion 91 included in the memory column MHB is an example of the "third columnar portion". The lower memory film 71A of the lower columnar portion 91 included in the memory column MHB is an example of the "third memory film". The lower semiconductor film 72A of the lower columnar portion 91 included in the memory column MHB is an example of the "third semiconductor film".

[0131] In one aspect, the upper columnar portion 92 included in the memory column MHB is an example of the "fourth columnar portion". The upper memory film 71B of the upper columnar portion 92 included in the memory column MHA is an example of the "fourth memory film". The upper semiconductor film 72B of the upper columnar portion 92 included in the memory column MHB is an example of the "fourth semiconductor film".

[0132] In the present embodiment, the conductive layer 52 of the disconnection part ST is provided in at least one of the following two regions. One region (the first region) among the two regions is the region between the lower columnar part 91 (the first columnar part) of the memory column MHA and the lower columnar part 91 (the third columnar part) of the memory column MHB. The other region (the second region) among the two regions is the region between the upper columnar part 92 (the second columnar part) of the memory column MHA and the upper columnar part 92 (the fourth columnar part) of the memory column MHB. Moreover, the conductive layer 52 of the disconnection part ST extends in the Z direction in the above-mentioned region and is connected to the source line SL.

[0133] <A7. Configuration example of bit line access area> As shown in FIG. 6, the bit line access area BR is arranged between a plurality of memory columns MH (memory column MHA and memory column MHC) arranged along the Y direction.

[0134] In one aspect, the lower columnar part 91 included in the memory column MHC is an example of the "fifth columnar part". The lower memory film 71A of the lower columnar part 91 included in the memory column MHC is an example of the "fifth memory film". The lower semiconductor film 72A of the lower columnar part 91 included in the memory column MHC is an example of the "fifth semiconductor film".

[0135] In one aspect, the upper columnar part 92 included in the memory column MHC is an example of the "sixth columnar part". The upper memory film 71B of the upper columnar part 92 included in the memory column MHC is an example of the "sixth memory film". The upper semiconductor film 72B of the upper columnar part 92 included in the memory column MHC is an example of the "sixth semiconductor film".

[0136] In the present embodiment, the peripheral circuit (for example, the sense amplifier module 17 or the switching circuit 19) is arranged on the opposite side (-Z direction side) of the second stacked body 40B with respect to the first stacked body 40A. Moreover, the contact point CS of the bit line access area BS is provided in the following two regions. One region (the first region) among the two regions is the region between the lower columnar part 91 (the first columnar part) of the memory column MHA and the lower columnar part 91 (the fifth columnar part) of the memory column MHC. The other region (the second region) among the two regions is the region between the upper columnar part 92 (the second columnar part) of the memory column MHA and the upper columnar part 92 (the sixth columnar part) of the memory column MHC. Moreover, the contact point CS of the bit line access area BS extends in the Z direction in the above-mentioned region. The contact point CS of the bit line access area BS electrically connects the above-mentioned peripheral circuit to the upper bit line BLB.

[0137] <A8. Manufacturing method> Next, the manufacturing method of semiconductor memory device 1 will be explained. Here, Figure 11 is a cross-sectional view schematically showing the structure of the semiconductor memory device 1. In Figure 11, for ease of explanation, the wiring area FR, the bit line access area BR, and the array area AR are arranged together. Figure 11 schematically integrates the structure related to the X direction and the structure related to the Y direction. Hereinafter, the manufacturing method will be described using the structure shown in Figure 11 as an example.

[0138] Figures 12 to 47 are cross-sectional views illustrating the manufacturing method of the semiconductor memory device 1. Furthermore, Figures 12 to 47 are shown in a reversed orientation relative to Figure 11 to illustrate the structure during the manufacturing process.

[0139] First, as shown in FIG12, an insulating layer 101 is formed on a semiconductor substrate 100. The insulating layer 101 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Second, as shown in FIG13, sacrificial layers 111B and insulating layers 42B are alternately deposited layer by layer in the Z direction. Thereby, a structure 40MA comprising the insulating layer 101, a plurality of sacrificial layers 111B, and a plurality of insulating layers 42B is formed. The sacrificial layer 111B is formed, for example, from a film containing silicon and nitrogen (e.g., a silicon nitride film).

[0140] Next, as shown in Figure 14, a cavity H1 corresponding to the columnar body Mc is formed in the structure 40MA. The cavity H1 is embedded with the sacrificial material 112. Then, as shown in Figure 15, sacrificial layers 111B and insulating layers 42B are alternately laminated in the Z direction. Furthermore, an insulating layer 44 is formed on the uppermost sacrificial layer 111B. In this way, a structure 40MB is formed in the structure 40MA by adding a plurality of sacrificial layers 111B, a plurality of insulating layers 42B, and an insulating layer 44. The structure 40MB is an example of a "first-stage laminated structure". The sacrificial layer 111B is an example of a "first layer". The insulating layer 42B is an example of a "second layer".

[0141] Next, as shown in Figure 16, a conductive layer 121, a sacrificial layer 122, a sacrificial layer 123, a sacrificial layer 124, a conductive layer 125, and a barrier layer 126 are sequentially deposited on the structure 40MB. The conductive layer 121, sacrificial layer 122, sacrificial layer 123, sacrificial layer 124, conductive layer 125, and barrier layer 126 extend in the X and Y directions, respectively. Conductive layers 121 and 125 are, for example, formed of polycrystalline silicon doped with impurities. Sacrificial layers 122 and 124 are, for example, formed of a film containing silicon and oxygen (e.g., a silicon oxide film). Sacrificial layer 123 and barrier layer 126 are, for example, formed of a film containing silicon and nitrogen (e.g., a silicon nitride film). Sacrificial layer 123 is an example of a "third layer". Secondly, as shown in Figure 17, the portions of the bit line access area BR and the wiring area FR contained in the sacrificial layers 122, 123, 124, the conductive layer 125 and the barrier layer 126 are removed.

[0142] Next, as shown in FIG18, the portion of the conductive layer 121 containing the bit line access region BR and the useless portion of the wiring region FR are removed. Then, as shown in FIG19, the barrier layer 126 is removed. Next, TEOS is supplied to the array region AR, the bit line access region BR, and the wiring region FR. Thereby, a portion of the insulating layer 43, the insulating layer 44, and the insulating portion 45 are formed. Thus, the structure 40MC is formed.

[0143] Next, as shown in Figure 20, sacrificial layer 111A and insulating layer 42A are alternately deposited one layer at a time along the Z direction on the structure 40MC. This forms a structure 40MD comprising a plurality of sacrificial layers 111A and a plurality of insulating layers 42A. Then, as shown in Figure 21, cavities H2 corresponding to the columnar body Mb are formed. The cavities H2 are embedded in the sacrificial material 112.

[0144] Next, as shown in Figure 22, sacrificial layer 111A and insulating layer 42A are alternately deposited layer by layer along the Z direction on the structure 40MD. This forms a structure 40ME in which a plurality of sacrificial layers 111A and a plurality of insulating layers 42A are added to the structure 40MD. Structure 40ME is an example of a "second-stage laminate". Sacrificial layer 111A is an example of a "fourth layer". Insulating layer 42A is an example of a "fifth layer". Next, holes H3 corresponding to columnar bodies Ma are formed. Then, by etching through holes H3, the sacrificial material 112 embedded in holes H1 and H2 is removed.

[0145] Next, as shown in Figure 23, a memory film 71, a channel layer 72, and an insulating portion 73 are sequentially deposited on the inner peripheral surfaces of the cavities H1, H2, and H3. Then, a cover portion 74 is formed. This forms the basic structure of the memory column MH. The columnar portion 92 on the upper part of the memory column MH is an example of the "columnar portion of the first stage". The columnar portion 91 below the memory column MH is an example of the "columnar portion of the second stage".

[0146] Next, an insulating layer 131 is formed on the structure 40ME. The insulating layer 131 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Thereby, the structure 40MF is formed.

[0147] Next, as shown in Figure 24, a trench G1 is formed at the position corresponding to the break ST on the structure 40MF. The trench G1 extends in both the Z and X directions. For example, the trench G1 is formed by using conductive layer 121 or conductive layer 125 as a barrier. Then, as shown in Figure 25, conductive layer 121 and conductive layer 125 are removed at the bottom of the trench G1 by etching. As a result, the sacrificial layer 124 is exposed at the bottom of the trench G1 in the array region AR.

[0148] Next, as shown in FIG26, a semiconductor film 132 is formed on the inner surface of the trench G1. The semiconductor film 132 is formed, for example, from amorphous silicon. Then, as shown in FIG27, the semiconductor film 132 is used as a protective film to protect the second sacrificial layer 112B and the second insulating layer 42B, while the bottom of the semiconductor film 132 and a portion of the sacrificial layer 124 are removed. This forms an opening K1 reaching the sacrificial layer 123.

[0149] Next, as shown in Figure 28, an etchant capable of removing the silicon nitride film (e.g., hot phosphoric acid) is supplied to the opening K1 to remove the sacrificial layer 123. Then, as shown in Figure 29, an etchant capable of removing the silicon oxide film is supplied to the opening K1 to remove the sacrificial layers 122 and 124, and to remove the memory film 71 exposed in the space S1 between the conductive layers 121 and 125. Hereby, the channel layer 72 is exposed in the space S1 between the conductive layers 121 and 125. At this point, the memory pillar MH is complete.

[0150] Next, as shown in Figure 30, the insulating layer 131 is removed. Then, a conductive layer 141 is formed in the space S1 between the conductive layers 121 and 125 through trench G1. The conductive layer 141 is formed of polycrystalline silicon doped with impurities. The conductive layer 141 is connected to the channel layer 72 of the memory pillar MH and is integrated with the conductive layers 121 and 125. Thus, the source line SL is formed by the conductive layers 121, 125, and 141.

[0151] Next, as shown in FIG31, an insulating film 146 is formed as a protective film on the inner surface of the trench G1. The insulating film 146 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). Then, as shown in FIG32, a mask 147 is formed on the inner surface of the insulating film 146. The mask 147 is formed, for example, from a metallic material such as titanium nitride or tungsten.

[0152] Next, as shown in Figure 33, a trench G2 is formed. This trench G2 penetrates the shield 147 and the insulating film 146 at the bottom of the trench G1, and also penetrates the structure 40MF in the Z direction. Here, since the shield 147 and the insulating film 146 are provided on the inner surface of the trench G1, the width of the trench G2 in the Y direction is smaller than the width of the trench G1 in the Y direction and corresponds to the thickness of the shield 147 and the insulating film 146. Then, as shown in Figure 34, the insulating film 146 and the shield 147 are removed. Thus, through the trenches G1 and G2, a trench G3 with a step difference Ts in the Z direction of the source line SL is formed.

[0153] Next, as shown in FIG35, an insulating film 151 is formed on the inner surface of trench G3 at the portion corresponding to the source line SL. The insulating film 151 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating film 151 is formed, for example, by oxidizing the surface of the source line SL. The insulating film 151 is a protective film that protects the source line SL in the replacement steps described below.

[0154] Next, as shown in Figure 36, an etchant (e.g., hot phosphoric acid) capable of removing the silicon nitride film is supplied to the trench G3. This removes a plurality of first sacrificial layers 111A and a plurality of second sacrificial layers 111B. At this time, the bit line access region BR is located far from the trench G3, making it difficult for the etchant to reach. Therefore, in the bit line access region BR, the plurality of first sacrificial layers 111A and the plurality of second sacrificial layers 111B remain as a plurality of insulating layers 46A and a plurality of insulating layers 46B.

[0155] Next, as shown in FIG37, conductive material is supplied through trench G3 to the space after the removal of the plurality of first sacrificial layers 111A and the plurality of second sacrificial layers 111B. This forms the plurality of first gate electrode layers 41A and the plurality of second gate electrode layers 41B. Then, an insulating film 152 is formed on the inner surface of trench G3. The insulating film 152 is formed, for example, of a film containing silicon and oxygen (e.g., a silicon oxide film).

[0156] Next, as shown in FIG. 38, by reactive ion etching (RIE), the insulating film 151 (the portions of the insulating film 151 along the X direction and the Y direction) existing at the step Ts in the groove G3 is removed. Thereby, the source line SL is exposed at the step Ts in the groove G3. In the present embodiment, the insulating film 51 of the dividing portion ST is formed by the insulating film 151 and the insulating film 152. Next, as shown in FIG. 39, a conductive material is supplied into the groove G3. Thereby, the conductive layer 52 is formed. Accordingly, the dividing portion ST is formed.

[0157] Next, as shown in FIG. 40, the dividing portion SHEA and the contact CH connected to the lower columnar portion 91 of the memory pillar MH are formed. Then, as shown in FIG. 41, the contact CS is formed in the bit line access region BR, and the contact CC is formed in the wiring region FR. Next, as shown in FIG. 42, the contact VY, the bit line BLA, and the wiring portion 60A are formed. Thereby, the basic structure of the second chip 3, that is, the structure 40MG is formed.

[0158] Next, as shown in FIG. 43, the structure 40MG is turned upside down, and the separately prepared first chip 2 is bonded to the structure 40MG. Then, the semiconductor substrate 100 is removed. Next, at the upper end portion of the memory pillar MH, the memory film 71 is removed to expose the channel layer 72. Furthermore, at this stage, a step of thickening the upper end portion of the channel layer 72 may be additionally performed.

[0159] Next, as shown in FIG. 44, the insulating portion 161 is formed on the structure 40MG. Then, the dividing portion SHEB is formed. Next, as shown in FIG. 45, the contact CH connected to the upper columnar portion 92 of the memory pillar MH and the contact 55 connected to the dividing portion ST are formed.

[0160] Next, as shown in FIG. 46, the upper bit line BLB is formed. Then, as shown in FIG. 47, the insulating portion 162 covering the upper bit line BLB is formed. Next, on the insulating portion 162, the electrical connection line 84 electrically connected to the source line SL via the dividing portion ST is formed. Then, the insulating portion covering the electrical connection line 84 is formed. Thus, the semiconductor memory device 1 is completed.

[0161] <A9. Advantages> In recent years, with the increase in the capacity of semiconductor memory devices, the number of stacked gate electrode layers has a tendency to increase. If the number of stacked gate electrode layers increases, the resistance of the string STR becomes large, and it is difficult to ensure the current flowing through the channel layer of the memory pillar.

[0162] In this embodiment, the semiconductor memory device 1 includes a first stacked layer 40A, a second stacked layer 40B, a source line SL, a lower columnar portion 91, an upper columnar portion 92, a lower bit line BLA, and an upper bit line BLB. The source line SL is disposed between the first stacked layer 40A and the second stacked layer 40B in the Z-direction. The lower columnar portion 91 extends within the first stacked layer 40A in the Z-direction. The lower columnar portion 91 includes a memory film 71A having a charge storage portion 82a and a lower semiconductor film 72A. The upper columnar portion 92 extends within the second stacked layer 40B in the Z-direction. The upper columnar portion 92 includes a memory film 71B having a charge storage portion 82a and an upper semiconductor film 72B. The lower bit line BLA is disposed opposite to the source line SL relative to the first stacked layer 40A. The lower first bit line BLA is electrically connected to the lower columnar portion 91. The upper-level line BLB is positioned opposite the source line SL, relative to the second stack 40B. The upper-level line BLB is electrically connected to the upper columnar portion 92.

[0163] Based on this configuration, for example, compared to the case where a source line SL exists on the +Z direction side relative to the first stacked layer 40A and the second stacked layer 40B, the resistance of the series STR is reduced, making it easier to ensure the current flowing through the channel layer 72. When the current flowing through the channel layer 72 is easily ensured, the reliability of the write operation of the semiconductor memory device 1 can be improved. Therefore, a semiconductor memory device 1 with improved electrical characteristics can be provided.

[0164] In this embodiment, when viewed from the Z direction, the lower columnar portion 91 and the upper columnar portion 92 overlap. With this configuration, the lower columnar portion 91 and the upper columnar portion 92 can be arranged at a higher density in the semiconductor memory device 1. This facilitates achieving a larger capacity in the semiconductor memory device 1.

[0165] In this embodiment, the semiconductor memory device 1 includes a memory column MH. The memory column MH includes a lower columnar portion 91 and an upper columnar portion 92. The memory column MH extends through the first stacked layer 40A, the second stacked layer 40B, and the source line SL in the Z direction. With this configuration, the lower columnar portion 91 and the upper columnar portion 92 can be formed by one memory column MH. Therefore, compared with the case where the lower columnar portion 91 and the upper columnar portion 92 are formed by different memory columns MH, the manufacturability of the semiconductor memory device 1 can be improved.

[0166] In this embodiment, the memory film 71 of the lower columnar portion 91 and the memory film 71 of the upper columnar portion 92 are separated in the Z direction. The memory column MH has the memory film 71 of the lower columnar portion 91, the memory film 71 of the upper columnar portion 92, and a channel layer 72. The channel layer 72 is connected to the source line SL in the region between the memory film 71 of the lower columnar portion 91 and the memory film 71 of the upper columnar portion 92. With this configuration, the electrical connection between the memory column MH and the source line SL can be ensured midway in the Z direction of the memory column MH.

[0167] In this embodiment, the number of gate electrode layers 41A included in the first stacked layer 40A is different from the number of gate electrode layers 41B included in the second stacked layer 40B. With this configuration, the capacity of the block BLKA included in the first stacked layer 40A can be different from the capacity of the block BLKB included in the second stacked layer 40B. Because the capacity of the block BLKA included in the first stacked layer 40A can be different from the capacity of the block BLKB included in the second stacked layer 40B, more suitable write operations can be performed. For example, by making the capacity of the block BLKA smaller than that of the block BLKB, the block BLKA can preferentially write data with smaller data sizes than the block BLKB, thereby achieving high-speed write operations.

[0168] In this embodiment, the semiconductor memory device 1 includes a sense amplifier module 17 having a terminal 17t and a switching circuit 19. The switching circuit 19 can switch between a first state and a second state. The first state is a state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the lower bit line BLA. The second state is a state in which the terminal 17t of the sense amplifier module 17 is electrically connected to the upper bit line BLB. According to this configuration, for example, compared with the case where the write target is switched between the first stack 40A and the second stack 40B using drain-side select gate lines SGDA and SGDB, the power consumption related to the switching of the write target can be reduced.

[0169] In this embodiment, the semiconductor memory device 1 has a contact CS. The contact CS is disposed between the memory cylinder MHA and the memory cylinder MHC. The contact CS extends in the Z direction and electrically connects the switching circuit 19 (or the sense amplifier module 17) to the upper-level line BLB. With this configuration, the electrical connection path between the switching circuit 19 (or the sense amplifier module 17) and the upper-level line BLB can be shortened. This can improve the processing speed of the semiconductor memory device 1 or reduce power consumption.

[0170] In the present embodiment, the semiconductor memory device 1 has a breaking portion ST. The breaking portion ST includes a first portion STa that breaks a plurality of gate electrode layers 41A along the Y direction, and a second portion STb that breaks a plurality of gate electrode layers 41B along the Y direction. The breaking portion ST has a conductive layer 52 and an insulating film 51 that covers the conductive layer 52. The conductive layer 52 and the insulating film 51 are provided across the first portion STa and the second portion STb. The width W1 in the Y direction of the first portion STa is greater than the width W2 in the Y direction of the second portion STb. The boundary between the first portion STa and the second portion STb is located inside the source line SL and has a step Ts in the Y direction. At the step Ts, the insulating film 51 is broken along the Y direction, and the conductive layer 52 is exposed outside the insulating film 51 and connected to the source line SL.

[0171] According to such a configuration, an electrical connection path connected to the source line SL can be provided inside the array region AR. According to this configuration, compared with the case where the above electrical connection path is provided in the wiring region FR, it is easier to improve the electrical characteristics of the semiconductor memory device 1. For example, according to the above configuration, at least one of the following effects can be obtained. · Compared with the case where the above electrical connection path is provided in the wiring region FR, the number of the above electrical connection paths can be increased. · The resistance of the electrical connection path to the source line SL can be reduced. · The path length between the above electrical connection path and each memory cell stack MH can be shortened.

[0172] <A9. Variation example> Hereinafter, several variation examples of the first embodiment will be described. Furthermore, these variation examples can also be applied to the following second embodiment.

[0173] In the semiconductor memory device 1 of the above first embodiment, a switching circuit 19 is provided, and the lower bit line BLA and the upper bit line BLB are switched by the switching circuit 19. In addition to such a configuration, in the variation example, the switching circuit 19 may not be provided. In this case, the switching between the lower bit line BLA and the upper bit line BLB can be performed, for example, using the drain side selection gate line SGDA of the first stacked body 40A and the drain side selection gate line SGDB of the second stacked body 40B.

[0174] In the semiconductor memory device 1 of the first embodiment described above, the electrical connection between the source line SL and the electrical connection line 64 is ensured by cutting the conductive layer 52 of the cutting portion ST. In addition to this, the conductive layer 52 of the cutting portion ST may also be omitted. In this case, in the wiring region FR, a contact CC for electrically connecting the source line SL and the electrical connection line 64 may also be provided.

[0175] (Second Embodiment) Next, the semiconductor memory device 1A of the second embodiment will be described. The difference between the second embodiment and the first embodiment is that the lower columnar portion 91 and the upper columnar portion 92 are formed by different memory columns. Furthermore, except for the configuration described below, the other configurations are the same as those of the first embodiment.

[0176] <B1. Memory Column> FIG. 48 is a cross-sectional view showing a part of the semiconductor memory device 1A of the second embodiment. In this embodiment, the semiconductor memory device 1A has a plurality of first memory columns MH1 and a plurality of second memory columns MH2, instead of having a plurality of memory columns MH of the first embodiment.

[0177] (First Memory Column) A plurality of first memory columns MH1 are arranged in the X direction and the Y direction. The first memory column MH1 extends in the Z direction within the first stacked body 40A. The first memory column MH1 penetrates the first stacked body 40A in the Z direction. In this embodiment, the entire length of the lower columnar portion 91 in the Z direction is formed by the entire length of the first memory column MH1 in the Z direction. The lower columnar portion 91 is an example of the "first columnar portion". Furthermore, the first memory column MH1 is not limited to a one-stage memory column in the Z direction, and may also be a two-stage or more memory column formed by stacking a plurality of columnar bodies in the Z direction.

[0178] (Second Memory Column) A plurality of second memory columns MH2 are arranged in the X direction and the Y direction. The second memory column MH2 extends in the Z direction within the second stacked body 40B. The second memory column MH2 penetrates the second stacked body 40B in the Z direction. In this embodiment, the entire length of the upper columnar portion 92 in the Z direction is formed by the entire length of the second memory column MH2 in the Z direction. The second memory column MH2 is an example of the "second columnar portion". Furthermore, the second memory column MH2 is not limited to a one-stage memory column in the Z direction, and may also be a two-stage or more memory column formed by stacking a plurality of columnar bodies in the Z direction.

[0179] Figure 49 is a cross-sectional view illustrating the memory pillars MH1 and MH2 of the second embodiment. The first memory pillar MH1 (lower pillar 91) includes a memory film 71 (lower memory film 71A), a channel layer 72 (lower semiconductor film 72A), an insulating portion 73, and a cover portion 74. The memory film 71 included in the first memory pillar MH1 is an example of a "first memory film". The channel layer 72 included in the first memory pillar MH1 is an example of a "first semiconductor film".

[0180] The first memory column MH1 does not penetrate the source line SL. The upper end of the first memory column MH1 is physically and electrically connected to the source line SL. The contact CH is connected to the lower end of the first memory column MH1 from the -Z direction side. The channel layer 72 of the first memory column MH1 is electrically connected to the lower bit line BLA via the contact CH and the contact VY. In this embodiment, as the first memory column MH1 (lower columnar portion 91) moves from the top to the bottom, the circumference (diameter) of the first memory column MH1 in the cross-section along the X and Y directions gradually increases.

[0181] The first memory column MH1 has a first end MHe1 (the +Z direction side end) connected to the source line SL, and a second end MHe2 (the -Z direction side end) located opposite to the first end MHe1. The second end MHe2 is connected to the contact CH. The second end MHe2 is electrically connected to the bit line BLA via the contact CH. In this embodiment, the circumference (diameter) of the first memory column MH1 with the second end MHe2 is greater than the circumference (diameter) of the first memory column MH1 with the first end MHe1.

[0182] The second memory column MH2 (upper columnar portion 92) includes a memory film 71 (upper memory film 71B), a channel layer 72 (upper semiconductor film 72B), an insulating portion 73, and a cover portion 74. The memory film 71 included in the second memory column MH2 is an example of a "second memory film". The channel layer 72 included in the second memory column MH2 is an example of a "second semiconductor film".

[0183] The second memory column MH2 does not penetrate the source line SL. The lower end of the second memory column MH2 is physically and electrically connected to the source line SL. The contact CH is connected to the upper end of the second memory column MH2 from the +Z direction side. The channel layer 72 of the second memory column MH2 is electrically connected to the upper bit line BLB via the contact CH and the contact VY. In this embodiment, as the second memory column MH2 (upper column 92) moves from the top to the bottom, the circumference (diameter) of the second memory column MHB in the cross-section along the X and Y directions gradually increases.

[0184] The second memory column MH2 has a third end MHe3 (the end on the -Z direction side) connected to the source line SL, and a fourth end MHe4 (the end on the +Z direction side) located on the opposite side of the third end MHe3. The fourth end MHe4 is connected to the contact CH. The fourth end MHe4 is electrically connected to the bit line BLB via the contact CH. In the present embodiment, the perimeter (diameter) of the second memory column MH2 at the fourth end MHe4 is smaller than the perimeter (diameter) of the second memory column MH2 at the third end MHe3.

[0185] In the present embodiment, the second memory column MH2 and the first memory column MH1 are separated in the Z direction. The first memory column MH1 and the second memory column MH2 are mutually disconnected. For example, the channel layer 72 (lower semiconductor film 72A) included in the first memory column MH1 and the channel layer 72 (upper semiconductor film 72B) included in the second memory column MH2 are separated in the Z direction. The channel layer 72 (lower semiconductor film 72A) included in the first memory column MH1 and the channel layer 72 (upper semiconductor film 72B) included in the second memory column MH2 are respectively electrically connected to the source line SL. The channel layer 72 included in the first memory column MH1 and the channel layer 72 included in the second memory column MH2 are electrically connected to each other via the source line SL.

[0186] <B2. Disconnection portion> FIG. 50 is a cross-sectional view of the semiconductor memory device 1A shown in FIG. 48 along the line F50 - F50. In the present embodiment, the semiconductor memory device 1A includes a first disconnection portion ST1 and a second disconnection portion ST2, instead of including the disconnection portion ST of the first embodiment.

[0187] (First disconnection portion) The first disconnection portion ST1 is a wall portion along the Z direction and the Y direction. The first disconnection portion ST1 extends in the first stacked body 40A in the Z direction. The first disconnection portion ST1 penetrates the first stacked body 40A in the Z direction. The first disconnection portion ST1 disconnects all the gate electrode layers 41 included in the first stacked body 40A along the Y direction. The first disconnection portion ST1 does not penetrate the source line SL. In the example shown in FIG. 50, the first disconnection portion ST1 does not have the conductive layer 52 and is formed only of the insulating film 51. Furthermore, in addition to the above example, the first disconnection portion ST1 may also have the insulating film 51 and the conductive layer 52.

[0188] (Second disconnection portion) The second dividing portion ST2 is a wall portion along the Z direction and the Y direction. The second dividing portion ST2 extends in the second stacked body 40B in the Z direction. The second dividing portion ST2 penetrates the second stacked body 40B in the Z direction. The second dividing portion ST2 divides all the gate electrode layers 41 included in the second stacked body 40B in the Y direction. In the present embodiment, the second dividing portion ST2 does not penetrate the source line SL. In the present embodiment, the second dividing portion ST2 is separated from the first dividing portion ST1 in the Z direction. In the example shown in FIG. 50, the second dividing portion ST2 has an insulating film 51 and a conductive layer 52. In addition, when the first dividing portion ST1 has a conductive layer 52, the second dividing portion ST2 may not have a conductive layer 52 and may be formed only of the insulating film 51.

[0189] <B3. Manufacturing Method> Hereinafter, a manufacturing method of the semiconductor memory device 1A will be described. FIGS. 51 to 56 are diagrams for explaining the manufacturing method of the semiconductor memory device 1A. First, as shown in FIG. 51, an insulating layer 101 is formed on the semiconductor substrate 100. Next, a sacrificial layer 111B and an insulating layer 42B are alternately stacked in the Z direction. Then, the ends of a plurality of sacrificial layers 111B are formed in a stepped shape. Also, a second memory column MH2 and a second dividing portion ST2 are formed. Next, through a replacement step, a plurality of sacrificial layers 111B are replaced with a plurality of gate electrode layers 41B. Thereby, a structure 40NA is formed.

[0190] Next, as shown in FIG. 52, a source line SL is provided on the structure 40NA. Thereby, a structure 40NB is formed. The source line SL is an example of the "third layer".

[0191] Next, as shown in FIG. 53, a sacrificial layer 111A and an insulating layer 42A are alternately stacked in the Z direction on the structure 40NA. Then, the ends of a plurality of sacrificial layers 111A are formed in a stepped shape. Also, a first memory column MH1 and a first dividing portion ST1 are provided. Next, through a replacement step, a plurality of sacrificial layers 111A are replaced with a plurality of gate electrode layers 41A. Thereby, a structure 4ONC is formed.

[0192] Next, as shown in FIG. 54, a dividing portion SHEA, a contact CH, a contact VY, a lower bit line BLA, a pad 32, and a wiring portion 60A are formed. Thereby, a structure 40ND is formed. The structure 40ND includes a basic portion of the second chip 3.

[0193] Next, as shown in FIG. 55, the structure 40ND is turned upside down, and the separately prepared first chip 2 is bonded to the structure 40ND. Then, the semiconductor substrate 100 is removed. Next, as shown in FIG. 56, an upper bit line BLB is formed. Then, a wiring portion 60B, an insulating portion, etc. are provided.至此,半導體記憶裝置1A完成。

[0194] <B4. Advantages> According to this configuration, similarly to the first embodiment, the electrical characteristics of the semiconductor memory device 1A can be improved.

[0195] <B5. Variation Example of Manufacturing Method> In the above second embodiment, the replacement step of replacing a plurality of sacrificial layers 111B with a plurality of gate electrode layers 41B is performed before forming the source line SL. In addition to this, the replacement step of replacing a plurality of sacrificial layers 111B with a plurality of gate electrode layers 41B may also be performed after forming the source line SL. For example, the replacement step of replacing a plurality of sacrificial layers 111B with a plurality of gate electrode layers 41B can also be performed simultaneously with the replacement step of replacing a plurality of sacrificial layers 111A with a plurality of gate electrode layers 41A.

[0196] As described above, several embodiments and variation examples have been described. However, the embodiments and variation examples are not limited to the above examples. For example, the above embodiments and variation examples can also be appropriately combined to be realized. Also, the source line SL can also be provided by being segmented by a string STR. Also, the lower bit line BLB and the upper bit line BLB can also be directly electrically connected to the sense amplifier module 17 respectively without passing through the switching circuit 19.

[0197] According to at least one embodiment described above, a semiconductor memory device includes a first stacked layer, a second stacked layer, a source line, a first pillar portion, a second pillar portion, a first bit line, and a second bit line. The first stacked layer includes a plurality of first gate electrode layers and a plurality of first insulating layers. The plurality of first gate electrode layers and the plurality of first insulating layers are stacked alternately layer by layer in a first direction. The second stacked layer is disposed on a first side in the first direction relative to the first stacked layer. The second stacked layer includes a plurality of second gate electrode layers and a plurality of second insulating layers. The plurality of second gate electrode layers and the plurality of second insulating layers are stacked alternately layer by layer in the first direction. The source line is disposed between the first stacked layer and the second stacked layer in the first direction. The source line extends in a second direction different from the first direction. The first columnar portion extends within the first laminate in the first direction. The first columnar portion includes a first memory film having a charge storage portion and a first semiconductor film. The second columnar portion extends within the second laminate in the first direction. The second columnar portion includes a second memory film having a charge storage portion and a second semiconductor film. The first bit line is disposed relative to the first laminate on a second side opposite to the first side in the first direction. The first bit line is electrically connected to the first columnar portion. The second bit line is disposed relative to the second laminate on the first side in the first direction. The second bit line is electrically connected to the second columnar portion. With this configuration, the electrical characteristics of the semiconductor memory device can be improved.

[0198] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents.

[0199] 1: Semiconductor memory devices 1A: Semiconductor memory device 2: First chip 3: Second chip 11: Memory Cell Array 12: Instruction Register 13: Address Register 14: Control circuit (sequencer) 15: Driver Module 16: Column Decoder Module 17: Sensing Amplifier Module (Circuit) 17a: Sensing Amplifier Unit 17t: Terminal (1st terminal) 18: Electrical connection wires 19: Switching circuit (circuit) 19A: Switching circuit 19Aa: Switching element 19B: Switching Circuit 19Ba: Switching element 21: Semiconductor substrate 22: Peripheral Circuits 22a: Transistor 22b: Electrical connection wire 23: Insulation section 24: Solder pad 31: Insulation section 32: Solder pad 40: Laminated body 40A: First layer 40B: Second layer 40C: Third layer 40D: Fourth layer 40MA: Construct 40MB: Construct 40MC: Construct 40MD: Construct 40ME: Construct 40MF: Construct 40MG: Construct 40NA: Construct 40NB: Construct 40NC: Construct 40ND: Construct 41A: Gate electrode layer (first gate electrode layer) 41B: Gate electrode layer (second gate electrode layer) 42A: Insulation layer (first insulation layer) 42B: Insulation layer (second insulation layer) 43: Insulation layer 44: Insulation layer 45: Insulation section 46A: Insulation layer 46B: Insulation layer 47: Insulation layer 50:Breaking part 51: Insulating film 51a: First insulating film 51b: Second insulating film 51s1: Insulating film 51s2: Insulating film 52: Conductive layer (conductive part) 55:Contact 56:Contact 60: Wiring Department 60A: Wiring Department 60B: Wiring Department 61: Electrical connection wire 62: Electrical connection wire 63: Electrical connection wires 64: Electrical connection wires 71: Memory membrane 71A: Memory membrane 71B: Memory membrane 72: Channel Layer 72A: Lower semiconductor film 72B: Top Semiconductor Film 73: Insulation section 74: Cover 81: Block insulating film 82: Charge trapping membrane 83: Tunnel insulation film 84: Electrical connection wires 91: Lower columnar portion (first columnar portion) 92: Upper columnar part (second columnar part) 93: Middle section 100: Semiconductor substrate 101: Insulation layer 111A: Sacrificial Layer 111B: Sacrificial Layer 112: Sacrificial Material 121: Conductive layer 122: Sacrifice Layer 123: Sacrifice Layer 124: Sacrifice Layer 125: Conductive layer 126: Barrier Layer 131: Insulation layer 132: Semiconductor film 141: Conductive layer 146: Insulating film 147: Mask 151: Insulating film 152: Insulating film 161: Insulation section 162: Insulation section ADD: Address Information AR: Array Area BL: Bitline BL0~BLm: Bit lines BLA: Lower byte line (first byte line) BLA0~BLAm: Lower bit lines (1st bit line) BLB: Upper Pixel Line (Second Pixel Line) BLB0~BLBm: Upper-level line (2nd-level line) BLK: block BLK0~BLK(k-1): Blocks BLKA: block BLKA0~BLKAj: block BLKB:block BLKB0~BLKBj: blocks BR: Bit line access area CC: Contact CH: contact CMD command CS: contact DAT: Read data FR: Wiring Area G1: Trench G2: Trench G3: Trench H1: Acupoint H2: Acupoint H3: Acupoint K1: Opening Ma: columnar body Mb: columnar body Mc: columnar body MH: Memory Column (Columnar Structure) MH1: Memory Pillar 1 MH2: Memory Pillar 2 MHA: Memory Column (Columnar Structure) MHB: Memory Column (Columnar Structure) MHC: Memory Column (Columnar Structure) MHe1: First end MHe2: Second end MHe3: Third end MHe4: Fourth end MT: Memory Cell Transistor MT0~MTn: Memory cell transistors NS: NAND string S1: Space SGD: Drain-side Selective Gate Line SGD0~SGD3: Drain-side gate selection line SGDA: Drain-side Selective Gate Line SGDB: Drain-side Selective Gate Line SGS: Source-side gate selection SGSA: Source-side gate selection line SGSB: Source-side gate selection line SHE: breaking part SHEA: breaking part SHEB: Breaking part SL: Source Line SLa: Part 1 SLb: Part 2 ST: Breaking part ST1: The first breaking part ST2: 2nd breaking part STa: Part 1 STb: Part 2 STD: Drain-side selective transistor STR: string STR0~STR3: strings STS: Source-Side Selective Transistor T1: Thickness T2: Thickness Ts: Step difference VA: Through hole VB: Contact VC: Node VY: Contact Point W1: Width W2: Width WL: Character Line WL0~WLn: Character lines WLA: Character Line WLB: Character Line

Claims

1. A semiconductor memory device comprising: a first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked in a first direction; a second stacked body disposed on a first side of the first direction relative to the first stacked body, and including a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked in the first direction; a source line disposed between the first stacked body and the second stacked body in the first direction, and extending in a second direction intersecting the first direction; and a first columnar portion extending in the first direction within the first stacked body, and including a first memory film having a charge storage portion and a first semiconductor film; The second columnar portion extends within the second stacked body in the first direction and includes a second memory film having a charge storage portion and a second semiconductor film; a first bit line is disposed on the opposite side of the source line relative to the first stacked body and is electrically connected to the first columnar portion; and a second bit line is disposed on the opposite side of the source line relative to the second stacked body and is electrically connected to the second columnar portion; and the portion of the first columnar portion occupying more than half in the first direction is the portion whose perimeter increases in the cross section intersecting the first direction as it advances from the first side to the second side opposite to the first side, and the portion of the second columnar portion occupying more than half in the first direction is the portion whose perimeter increases in the cross section intersecting the first direction as it advances from the first side to the second side.

2. The semiconductor memory device of claim 1, wherein when viewed from the first direction, the first columnar portion overlaps with the second columnar portion.

3. The semiconductor memory device according to claim 1 or 2, comprising: a columnar body including the first columnar portion and the second columnar portion, wherein the columnar body penetrates the first stacked layer, the second stacked layer and the source line in the first direction.

4. The semiconductor memory device of claim 3, wherein the first memory film and the second memory film are separated in the first direction, and the column has a semiconductor film comprising the first semiconductor film and the second semiconductor film, wherein the semiconductor film is connected to the source line in the region between the first memory film and the second memory film.

5. The semiconductor memory device of claim 1 or 2, wherein the first semiconductor film and the second semiconductor film are separated from each other in the first direction, and the first semiconductor film and the second semiconductor film are electrically connected to the source line respectively.

6. The semiconductor memory device of claim 1 or 2, wherein the first columnar portion has a first end connected to the source line and a second end located on the opposite side of the first end, the perimeter of the first columnar portion at the second end is greater than the perimeter of the first columnar portion at the first end, and the second columnar portion has a third end connected to the source line and a fourth end located on the opposite side of the third end, the perimeter of the second columnar portion at the fourth end is less than the perimeter of the second columnar portion at the third end.

7. The semiconductor memory device of claim 1 or 2 further comprises: a third columnar portion extending in the first direction within the first stacked layer and including a third memory film having a charge storage portion and a third semiconductor film; a fourth columnar portion extending in the first direction within the second stacked layer and including a fourth memory film having a charge storage portion and a fourth semiconductor film; and a conductive layer disposed between at least one of the first columnar portion and the third columnar portion, and between the second columnar portion and the fourth columnar portion, and extending in the first direction and connected to the source line.

8. The semiconductor memory device of claim 1 or 2, wherein the number of the plurality of first gate electrode layers contained in the first stacked body is the same as the number of the plurality of second gate electrode layers contained in the second stacked body.

9. A semiconductor memory device comprising: a first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked in a first direction; a second stacked body disposed on a first side of the first direction relative to the first stacked body, and including a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked in the first direction; a source line disposed between the first stacked body and the second stacked body in the first direction, and extending in a second direction intersecting the first direction; and a first columnar portion extending in the first direction within the first stacked body, and including a first memory film having a charge storage portion and a first semiconductor film; The second columnar portion extends in the first direction within the second stacked body and includes a second memory film having a charge storage portion and a second semiconductor film; a first bit line is disposed on the opposite side of the source line relative to the first stacked body and is electrically connected to the first columnar portion; and a second bit line is disposed on the opposite side of the source line relative to the second stacked body and is electrically connected to the second columnar portion; and the number of the plurality of first gate electrode layers included in the first stacked body is different from the number of the plurality of second gate electrode layers included in the second stacked body.

10. A semiconductor memory device comprising: a first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked in a first direction; a second stacked body disposed on a first side of the first direction relative to the first stacked body, and including a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked in the first direction; a source line disposed between the first stacked body and the second stacked body in the first direction, and extending in a second direction intersecting the first direction; and a first columnar portion extending in the first direction within the first stacked body, and including a first memory film having a charge storage portion and a first semiconductor film; The second columnar portion extends within the second stacked body in the first direction and includes a second memory film having a charge storage portion and a second semiconductor film; a first bit line is disposed on the opposite side of the source line relative to the first stacked body and is electrically connected to the first columnar portion; and a second bit line is disposed on the opposite side of the source line relative to the second stacked body and is electrically connected to the second columnar portion; and the semiconductor memory device further includes: a sense amplifier module having a first terminal; and a switching circuit capable of switching between a first state and a second state, wherein the first state is a state in which the first terminal is electrically connected to the first bit line, and the second state is a state in which the first terminal is electrically connected to the second bit line.

11. A semiconductor memory device comprising: a first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked in a first direction; a second stacked body disposed on a first side of the first direction relative to the first stacked body, and including a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked in the first direction; a source line disposed between the first stacked body and the second stacked body in the first direction, and extending in a second direction intersecting the first direction; and a first columnar portion extending in the first direction within the first stacked body, and including a first memory film having a charge storage portion and a first semiconductor film; The semiconductor memory device further comprises: a second columnar portion extending in the first direction within the second stacked body, and including a second memory film having a charge storage portion and a second semiconductor film; a first bit line disposed on the opposite side of the source line relative to the first stacked body, and electrically connected to the first columnar portion; and a second bit line disposed on the opposite side of the source line relative to the second stacked body, and electrically connected to the second columnar portion; and the semiconductor memory device further comprises: a fifth columnar portion extending in the first direction within the first stacked body, and including a fifth memory film having a charge storage portion and a fifth semiconductor film; and a sixth columnar portion extending in the first direction within the second stacked body, and including a sixth memory film having a charge storage portion and a sixth semiconductor film. The circuit is disposed on the opposite side of the second stack relative to the first stack; and the contact is disposed between the first columnar portion and the fifth columnar portion, and between the second columnar portion and the sixth columnar portion, and extends in the first direction to electrically connect the circuit to the second bit line.

12. A semiconductor memory device comprising: a first stacked body including a plurality of first gate electrode layers and a plurality of first insulating layers, wherein the plurality of first gate electrode layers and the plurality of first insulating layers are alternately stacked in a first direction; a second stacked body disposed on a first side of the first direction relative to the first stacked body, and including a plurality of second gate electrode layers and a plurality of second insulating layers, wherein the plurality of second gate electrode layers and the plurality of second insulating layers are alternately stacked in the first direction; a source line disposed between the first stacked body and the second stacked body in the first direction, and extending in a second direction intersecting the first direction; and a first columnar portion extending in the first direction within the first stacked body, and including a first memory film having a charge storage portion and a first semiconductor film; The second columnar portion extends within the second stacked body in the first direction and includes a second memory film having a charge storage portion and a second semiconductor film; a first bit line is disposed on the opposite side of the source line relative to the first stacked body and is electrically connected to the first columnar portion; and a second bit line is disposed on the opposite side of the source line relative to the second stacked body and is electrically connected to the second columnar portion; and the semiconductor memory device further includes: a segmentation portion comprising a first portion that segments the plurality of first gate electrode layers along the second direction, and a second portion that segments the plurality of second gate electrode layers along the second direction; and the segmentation portion has a conductive layer and an insulating film covering the conductive layer, the conductive layer and the insulating film being disposed across the first portion and the second portion, and the width of the first portion in the second direction being greater than the width of the second portion in the second direction. The junction of the first part and the second part is located inside the source line and has a step difference in the second direction. At the step difference, the insulating film is broken along the second direction, and the conductive layer is exposed outside the insulating film and connected to the source line.

13. A method for manufacturing a semiconductor memory device, comprising the following steps: forming a first-stage stack comprising a plurality of first layers and a plurality of second layers, wherein the plurality of first layers and the plurality of second layers are alternately stacked in a first direction; forming a third layer above the first-stage stack, the third layer extending in a direction intersecting the first direction; forming a second-stage stack comprising a plurality of fourth layers and a plurality of fifth layers above the third layer, wherein the plurality of fourth layers and the plurality of fifth layers are alternately stacked in the first direction and disposed on a first side of the first direction relative to the first-stage stack; A columnar portion is formed in the first stage, which extends in the first direction within the first stage of the laminate and includes a memory film having a charge storage portion and a semiconductor film; A columnar portion is formed in the second stage, which extends in the first direction within the second stage of the laminate and includes a memory film having a charge storage portion and a semiconductor film. A bit line is formed, which is located on the opposite side of the third layer relative to the columnar portion of the second stage, and is electrically connected to the columnar portion of the second stage; and a bit line is formed, which is located on the opposite side of the third layer relative to the columnar portion of the first stage, and is electrically connected to the columnar portion of the first stage; and the portion of the columnar portion of the second stage that occupies more than half of the first direction is the portion of the columnar portion of the second stage whose perimeter increases in the cross section intersecting the first direction as it advances from the first side to the second side opposite to the first side, and the portion of the columnar portion of the first stage that occupies more than half of the first direction is the portion of the columnar portion of the first stage whose perimeter increases in the cross section intersecting the first direction as it advances from the first side to the second side.

Images