Duty cycle correction device and duty cycle correction method thereof

Abstract

A duty cycle correction device and method thereof. A duty cycle adjustment circuit adjusts the duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal based on the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle by the amount of adjustment based on the logic level change of the integral signal.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a duty cycle correction device and a duty cycle correction method thereof. Prior Technology

[0002] Duty cycle correction devices are used to correct the duty cycle of a signal, maintaining it at a preset percentage, thereby improving system signal quality and ensuring normal system operation. Therefore, providing a duty cycle correction device that can quickly and accurately correct the signal's duty cycle is a very important issue. Summary of the Invention

[0003] This invention provides a duty cycle correction device and a duty cycle correction method, which can quickly and accurately correct the duty cycle of a signal.

[0004] The duty cycle correction device of the present invention includes a duty cycle adjustment circuit, an integrator circuit, and a correction control circuit. The duty cycle adjustment circuit adjusts the duty cycle of the input clock signal to output an output clock signal. The integrator circuit is coupled to the duty cycle adjustment circuit and generates an integral signal based on the output clock signal. The correction control circuit is coupled to both the integrator circuit and the duty cycle adjustment circuit, and periodically controls the duty cycle adjustment circuit to adjust the duty cycle by the amount of adjustment based on the logic level change of the integral signal.

[0005] In one embodiment of the present invention, when the logic level of the integral signal changes more than n times within a preset period, the correction control circuit controls the working cycle adjustment circuit to reduce the adjustment amount.

[0006] In one embodiment of the present invention, n is an integer greater than 1, which can be a fixed value or vary with the needs of different stages.

[0007] In one embodiment of the present invention, the aforementioned correction control circuit includes a multiplier circuit, an adder circuit, and a control circuit. The multiplier circuit is coupled to an integrator circuit and provides a product value based on the integral signal. The first input terminal of the adder circuit is coupled to the multiplier circuit, and the second input terminal and output terminal of the adder circuit are coupled to the adder circuit. The output terminal of the adder circuit is coupled to a duty cycle adjustment circuit, outputting a control code to the duty cycle adjustment circuit to control the adjustment amount of the duty cycle. The control circuit is coupled to both the multiplier circuit and the adder circuit, periodically controlling the multiplier circuit to adjust the product value based on the logic level change of the integral signal, and controlling the adder circuit to add or subtract the product value using the control code based on the logic level of the integral signal, thereby controlling the duty cycle adjustment circuit to adjust the duty cycle by the aforementioned adjustment amount.

[0008] In one embodiment of the present invention, the control circuit reacts to the product value being less than or equal to a preset product value and then stops adjusting the product value.

[0009] In one embodiment of the present invention, the integrator circuit includes a differential signal conversion circuit, a first comparator, a first resistor, a second resistor, a first capacitor, a second capacitor, and a second comparator. The differential signal conversion circuit is coupled to the output of the duty cycle adjustment circuit, converting the output clock signal into a differential signal. The first resistor is coupled between the differential signal conversion circuit and the positive input of the first comparator. The second resistor is coupled between the differential signal conversion circuit and the negative input of the first comparator. The first capacitor is coupled between the positive input of the first comparator and ground. The second capacitor is coupled between the negative input of the first comparator and ground. The positive and negative inputs of the second comparator are respectively coupled to the negative and positive outputs of the first comparator. The output of the second comparator is coupled to a correction control circuit and is used to output an integral signal.

[0010] In one embodiment of the present invention, the above-mentioned duty cycle correction device further includes a delay circuit, which is coupled between the duty cycle adjustment circuit and the integrator circuit.

[0011] This invention also provides a method for correcting the working cycle of a working cycle correction device. The working cycle correction device includes a working cycle adjustment circuit, which adjusts the working cycle of an input clock signal to output an output clock signal. The method for correcting the working cycle of the working cycle correction device includes the following steps: providing the output clock signal to an integrator circuit to generate an integrated signal; and periodically controlling the working cycle adjustment circuit to adjust the adjustment amount of the working cycle based on the logic level change of the integrated signal.

[0012] In one embodiment of the present invention, the working cycle correction method of the above-mentioned working cycle correction device includes the following steps: determining whether the number of changes in the logic level of the integral signal within a preset period is greater than n times. When the number of changes in the logic level of the integral signal within the preset period is greater than n times, controlling the working cycle adjustment circuit to reduce the adjustment amount.

[0013] In one embodiment of the present invention, n is an integer greater than 1.

[0014] In one embodiment of the present invention, the duty cycle correction method of the above-described duty cycle correction device includes the following steps: Periodically adjusting the provided product value according to the logic level change of the integral signal; adding or subtracting the product value to a control code according to the logic level of the integral signal; and outputting the control code to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the adjustment amount of the duty cycle.

[0015] In one embodiment of the present invention, the working cycle correction method of the above-mentioned working cycle correction device includes stopping the adjustment of the product value when the reaction product value is less than or equal to a preset product value.

[0016] Based on the above, the integrator circuit of this embodiment generates an integral signal based on the output clock signal of the duty cycle adjustment circuit. The correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle based on the logic level change of the integral signal. This allows for rapid and accurate correction of the duty cycle of the output clock signal, thereby improving the signal quality of the system using the duty cycle correction device and ensuring normal system operation.

[0017] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0018] Figure 1 is a schematic diagram of a working cycle correction device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a working cycle correction device according to another embodiment of the present invention. Figure 3 is an operation timing diagram of a working cycle correction device according to an embodiment of the present invention. Figure 4 is a flowchart of a working cycle correction method of a working cycle correction device according to an embodiment of the present invention. Figure 5 is a flowchart of a working cycle correction method of a working cycle correction device according to another embodiment of the present invention. Figure 6 is a flowchart of a working cycle correction method of a working cycle correction device according to another embodiment of the present invention. Implementation

[0019] Figure 1 is a schematic diagram of a duty cycle correction device according to an embodiment of the present invention. Please refer to Figure 1. The duty cycle correction device 100 includes a duty cycle adjustment circuit 102, an integrator circuit 104, and a correction control circuit 106. The integrator circuit 104 is coupled to the duty cycle adjustment circuit 102 and the correction control circuit 106, and the correction control circuit 106 is also coupled to the duty cycle adjustment circuit 102.

[0020] The duty cycle adjustment circuit 102 adjusts the duty cycle of the input clock signal CLK1 to output the output clock signal CLK2. The integrator circuit 104 generates an integral signal S1 based on the output clock signal CLK2. The correction control circuit 106 can periodically control the duty cycle adjustment circuit 102 to adjust the adjustment amount of the duty cycle of the input clock signal CLK1 based on the logic level changes of the integral signal S1. For example, when the logic level of the integral signal S1 changes more than n times within a preset period, the correction control circuit 106 can control the duty cycle adjustment circuit 102 to reduce the adjustment amount, where n is an integer greater than 1. The number of logic level changes can be, for example, counting the number of times the logic level changes from high logic level to low logic level and from low logic level to high logic level, or only counting the number of times the logic level changes from high logic level to low logic level, or only counting the number of times the logic level changes from low logic level to high logic level. In this way, the duty cycle of the output clock signal can be corrected quickly and accurately, improving the signal quality of the system using the duty cycle correction device and ensuring the normal operation of the system.

[0021] Furthermore, the implementation of the duty cycle correction device 100 can be shown in Figure 2. In the embodiment of Figure 2, the duty cycle correction device 100 may further include a delay circuit 202, which is coupled between the duty cycle adjustment circuit 102 and the integrator circuit 104. The delay circuit 202 can delay the output of the clock signal CLK2, and it can be implemented, for example, with multiple buffers. In addition, the delay circuit 202 can also output the clock signal CLK2 through the buffer BF1, but it is not limited thereto. In other embodiments, the delay circuit 202 may also directly output the clock signal CLK2.

[0022] The integrator circuit 104 may include a differential signal conversion circuit 204, comparators 206 and 208, resistors R1 and R2, and capacitors C1 and C2. The differential signal conversion circuit 204 is coupled to the delay circuit 202 and is coupled to the positive and negative input terminals of the comparator 206 through resistors R1 and R2. Further, the differential signal conversion circuit 204 may include multiple first inverters connected in series between the delay circuit 202 and resistor R1, and multiple second inverters connected in series between the delay circuit 202 and resistor R2. The number of first inverters may be even, for example, and the number of second inverters may be odd, but this is not a limitation. For example, in other embodiments, the number of first inverters may be odd, and the number of second inverters may be even. Capacitor C1 is coupled between the positive input terminal of the comparator 206 and ground, and capacitor C2 is coupled between the negative input terminal of the comparator 206 and ground. The positive and negative input terminals of comparator 208 are coupled to the negative and positive output terminals of comparator 206, respectively, and the output terminal of comparator 208 is coupled to the correction control circuit 106.

[0023] In this embodiment, the correction control circuit 106 may include a multiplier circuit 210, an adder circuit 212, and a control circuit 214. The multiplier circuit 210 is coupled to the integrator circuit 104, the adder circuit 210, and the control circuit 214. The adder circuit 212 is also coupled to the control circuit 214 and the duty cycle adjustment circuit 102. In addition, one input terminal and one output terminal of the adder circuit 212 are coupled.

[0024] The differential signal conversion circuit 204 converts the output clock signal CLK2 into a differential signal. In this embodiment, the differential signal includes two clock signals with opposite phases. The differential signal is converted into an integral signal S1 via resistors R1 and R2, capacitors C1 and C2, comparator 206, and comparator 208, and then output to the multiplier circuit 210. Furthermore, as shown in Figure 2, when the duty cycle ratio of the output clock signal CLK2 is larger, the output voltage "+" terminal of comparator 206 (as shown by output curve VO1) will be closer to the high voltage logic level VH, while when the duty cycle ratio of the output clock signal CLK2 is smaller, the output voltage "-" terminal of comparator 206 (as shown by voltage curve VO2) will be closer to the low voltage logic level VL. Comparator 208 generates an integral signal S1 based on the output voltage of comparator 206. When the output voltage of comparator 206 corresponds to output curve VO1, comparator 208 generates an integral signal S1 at a high voltage logic level (as shown in Figure 2). When the output voltage of comparator 206 corresponds to output curve VO2, comparator 208 generates an integral signal S1 at a low voltage logic level. Multiplier circuit 210 provides a product value based on the integral signal S1. For example, as shown in Figure 3, multiplier circuit 210 can provide different product values ​​M at different stages. The product value M can be, for example, 8, 4, 2, or 1, but is not limited to these. Adder circuit 212 outputs control code CD1 to duty cycle adjustment circuit 102 to control the duty cycle adjustment circuit 102 to adjust the duty cycle of the input clock signal CLK1. The control circuit 214 can periodically control the multiplier circuit 210 to adjust the product value M according to the logic level change of the integral signal S1, and control the adder circuit 212 to add or subtract the product value M to the control code CD1 according to the logic level of the integral signal S1, so as to control the working cycle adjustment circuit 102 to adjust the adjustment amount of the working cycle of the input clock signal CLK1.

[0025] For example, in the embodiment of Figure 3, the control circuit 214 can perform a counting operation (e.g., counting the rising edge of the base clock signal) to generate a count value, which is reset when it accumulates to a preset value (e.g., 3, but not limited thereto). The control circuit 214 can control the adder circuit 212 to add or subtract the product value M from the control code CD1 according to the logic level of the integral signal S1. For example, when the integral signal S1 is at a high logic level, the product value M is subtracted from the control code CD1, and when the integral signal S1 is at a low logic level, the product value M is added to the control code CD1. However, this is not a limitation; in other embodiments, it can also be set that when the integral signal S1 is at a high logic level, the product value M is added to the control code CD1, and when the integral signal S1 is at a low logic level, the product value M is subtracted from the control code CD1.

[0026] Furthermore, the control circuit 214 can periodically determine whether to control the multiplier circuit 210 to adjust the product value M based on the logical level changes of the integral signal S1. For example, in the embodiment of FIG3, the control circuit 214 can determine whether to control the multiplier circuit 210 to adjust the product value M based on the logical level changes of the integral signal S1 within each period defined by the count value (i.e., a preset period, which in FIG3 is the period from 0 to 3 accumulated). More specifically, the control circuit 214 can determine whether to control the multiplier circuit 210 to adjust the product value M by judging the number of logical level changes of the integral signal S1 within each period defined by the count value. For example, it can be set that when the number of logical level changes of the integral signal S1 within the period defined by the count value is greater than 1, the multiplier circuit 210 is controlled to adjust the product value M.

[0027] As shown in Figure 3, assuming the product value M equals 8 when entering stage A, during period T1, control circuit 214 continuously controls adder circuit 212 to subtract the product value M from control code CD1, reflecting that the integral signal S1 is at a high logic level. Since the number of logic level changes of the integral signal S1 during period T1 is less than 1, control circuit 214 does not control multiplier circuit 210 to adjust the product value M. During period T2, the integral signal S1 changes between high and low logic levels 4 times. Control circuit 214 reacts to the logic level changes of the integral signal S1 and controls adder circuit 212 to add or subtract the product value M from control code CD1. Since the number of logic level changes of the integral signal S1 during period T2 is greater than 1, control circuit 214 enters stage B and controls multiplier circuit 210 to reduce the product value M to 4. Similarly, during the period T3~T5, the logic level of the integral signal S1 changes more than once each time, so the control circuit 214 continuously controls the multiplier circuit 210 to reduce the product value M.

[0028] Furthermore, the control circuit 214 can determine whether the product value M is less than or equal to a preset product value. When the product value M is less than or equal to the preset value, it indicates that the working cycle is close to the target working cycle, and the control circuit 214 can end the adjustment of the product value M, that is, stop adjusting the adjustment amount of the working cycle. For example, in the embodiment of Figure 3, the preset product value can be set to 1. After the period T5 ends, the control circuit 214 enters stage E and stops the adjustment of the product value M.

[0029] Figure 4 is a flowchart of a duty cycle correction method according to an embodiment of the present invention. The duty cycle correction device includes a duty cycle adjustment circuit, which uses the adjusted duty cycle of the input clock signal to output an output clock signal. The duty cycle correction method of the duty cycle correction device may include at least the following steps: First, the output clock signal is provided to an integrator circuit to generate an integrated signal (step S402). Then, the duty cycle adjustment circuit is periodically controlled to adjust the adjustment amount of the duty cycle according to the logic level change of the integrated signal (step S404).

[0030] Furthermore, the method of periodically adjusting the adjustment amount of the working cycle based on the changes in the logic level of the integral signal can be illustrated in Figure 5. After step S402, it is determined whether the number of changes in the logic level of the integral signal within the preset period is greater than n (step S502), where n is an integer greater than 1. If the number of changes is greater than n, the working cycle adjustment circuit is controlled to reduce the adjustment amount (step S504). If the number of changes is less than n, the working cycle adjustment circuit is not controlled to reduce the adjustment amount (step S506).

[0031] In some embodiments, the adjustment amount of the duty cycle can be implemented, for example, by adjusting the product value generated based on the integral signal. For example, in the embodiment of FIG6, the provided product value can be periodically adjusted according to the change of the logic level of the integral signal (step S602). For example, when the number of changes in the logic level of the integral signal within a preset period is greater than n, the provided product value can be reduced. Then, the control code is added to or subtracted from the product value according to the logic level of the integral signal (step S604). For example, when the integral signal is at a high logic level, the control code is subtracted from the product value, and when the integral signal is at a low logic level, the control code is added to the product value. However, this is not a limitation. In other embodiments, it can also be set that when the integral signal is at a high logic level, the control code is added to the product value, and when the integral signal is at a low logic level, the control code is subtracted from the product value. Afterwards, the adjusted control code is output to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the adjustment amount of the duty cycle (step S606). Furthermore, when the product value is adjusted to be less than or equal to the preset product value, the adjustment of the product value can be stopped (step S608), that is, the adjustment of the adjustment amount of the working cycle is stopped.

[0032] In summary, the integrator circuit of this embodiment generates an integral signal based on the output clock signal of the duty cycle adjustment circuit, and the correction control circuit periodically controls the duty cycle adjustment circuit to adjust the duty cycle based on the logic level changes of the integral signal. This allows for rapid and accurate correction of the duty cycle of the output clock signal, thereby improving the signal quality of systems using the duty cycle correction device and ensuring normal system operation.

[0033] 100: Working cycle correction device 102: Operating Cycle Adjustment Circuit 104: Integrator Circuit 106: Correction control circuit 202: Delay Circuit 204: Differential signal conversion circuit 206, 208: Comparators 210: Multiplier Circuit 212: Adder Circuit 214: Control Circuit CLK1: Input clock signal CLK2: Output clock signal S1: Integral signal BF1: Buffer R1, R2: Resistors C1, C2: Capacitors CD1: Control Code M: Product value T1~T5: Periodic period S402, S404, S502~S506, S602~S608: Steps of the working cycle calibration method for the working cycle calibration device

Claims

1. A duty cycle correction device, comprising: A duty cycle adjustment circuit adjusts the duty cycle of an input clock signal to output an output clock signal. An integrator circuit, coupled to the duty cycle adjustment circuit, generates an integral signal based on the output clock signal; and a correction control circuit, coupled to the integrator circuit and the duty cycle adjustment circuit, periodically controls the duty cycle adjustment circuit to adjust the duty cycle by an adjustment amount based on the logic level change of the integral signal, wherein when the logic level of the integral signal changes more than n times within a preset period, the correction control circuit controls the duty cycle adjustment circuit to reduce the adjustment amount.

2. The duty cycle correction device as described in claim 1, wherein n is an integer greater than 1.

3. The duty cycle correction device as claimed in claim 1, wherein the correction control circuit comprises: A multiplier circuit, coupled to the integrator circuit, provides a product value based on the integration signal; An adder circuit has a first input terminal coupled to the multiplier circuit, a second input terminal coupled to the output terminal of the adder circuit, and an output terminal coupled to the duty cycle adjustment circuit, outputting a control code to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the adjustment amount of the duty cycle. A control circuit coupled to the multiplier circuit and the adder circuit periodically controls the multiplier circuit to adjust the product value according to the logic level change of the integral signal, and controls the adder circuit to add or subtract the product value to the control code according to the logic level of the integral signal, so as to control the working cycle adjustment circuit to adjust the adjustment amount of the working cycle.

4. The work cycle correction device as claimed in claim 3, wherein the control circuit stops adjusting the product value when the product value is less than or equal to a preset product value.

5. The duty cycle correction device as claimed in claim 1, wherein the integrator circuit comprises: A differential signal conversion circuit is coupled to the output terminal of the duty cycle adjustment circuit to convert the output clock signal into a differential signal; First comparator; A first resistor is coupled between the differential signal conversion circuit and the positive input terminal of the first comparator; a second resistor is coupled between the differential signal conversion circuit and the negative input terminal of the first comparator; a first capacitor is coupled between the positive input terminal of the first comparator and a ground; a second capacitor is coupled between the negative input terminal of the first comparator and the ground. A second comparator is provided, whose positive and negative inputs are respectively coupled to the negative and positive outputs of the first comparator. The output of the second comparator is coupled to the correction control circuit to output the integral signal.

6. The work cycle correction device as described in claim 1, further comprising: A delay circuit is coupled between the duty cycle adjustment circuit and the integrator circuit.

7. A method for correcting the working cycle of a working cycle correction device, the working cycle correction device comprising a working cycle adjustment circuit, the working cycle adjustment circuit adjusting a working cycle of an input clock signal to output an output clock signal, the method comprising: The output clock signal is provided to an integrator circuit to generate an integrated signal; The duty cycle adjustment circuit is periodically controlled to adjust the duty cycle by an adjustment amount based on the logical level change of the integral signal; it is determined whether the number of changes in the logical level of the integral signal within a preset period is greater than n; and when the number of changes in the logical level of the integral signal within the preset period is greater than n, the duty cycle adjustment circuit is controlled to reduce the adjustment amount.

8. The working cycle correction method of the working cycle correction device as described in claim 7, wherein n is an integer greater than 1.

9. A method for correcting the working cycle of the working cycle correction device as described in claim 7, comprising: The provided product value is periodically adjusted based on the logical level changes of the integral signal; The product value is added to or subtracted from a control code based on the logic level of the integral signal; and the control code is output to the duty cycle adjustment circuit to control the duty cycle adjustment circuit to adjust the adjustment amount of the duty cycle.

10. A method for correcting the working cycle of the working cycle correction device as described in claim 9, comprising: If the product value is less than or equal to a preset product value, the adjustment of the product value is stopped.

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