Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a carrier wafer structure and a plurality of transistor wafer structures. The plurality of transistor wafer structures are stacked on the carrier wafer structure. Each transistor wafer structure includes a transistor wafer, a first bonding layer, and a second bonding layer. The transistor wafer has a first side and a second side facing each other. The first bonding layer is located on the first side of the transistor wafer. The second bonding layer is located on the second side of the transistor wafer. The first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure including a transistor and a method for manufacturing the same. Prior Technology

[0002] In current semiconductor manufacturing processes, semiconductor structures have been developed that utilize epitaxial growth to stack transistors. However, minimizing the thickness of transistor wafers and reducing the process complexity of semiconductor structures remain ongoing goals. Summary of the Invention

[0003] This invention provides a semiconductor structure and its manufacturing method, which can minimize the thickness of the transistor wafer and reduce the process complexity of the semiconductor structure.

[0004] This invention proposes a semiconductor structure including a carrier wafer structure and multiple transistor wafer structures. The multiple transistor wafer structures are stacked on the carrier wafer structure. Each transistor wafer structure includes a transistor wafer, a first bonding layer, and a second bonding layer. The transistor wafer has a first side and a second side facing each other. The first bonding layer is located on the first side of the transistor wafer. The second bonding layer is located on the second side of the transistor wafer. The first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures.

[0005] According to one embodiment of the present invention, in the above-described semiconductor structure, the transistor wafer may include a transistor.

[0006] According to an embodiment of the present invention, in the above-described semiconductor structure, the transistor is, for example, a planar field-effect transistor (FET), a fin field-effect transistor (Fin FET), a gate-all-around field-effect transistor (GAA FET), or a complementary field-effect transistor (CFET).

[0007] According to an embodiment of the present invention, in the above-described semiconductor structure, the transistor is, for example, an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a combination thereof.

[0008] According to one embodiment of the present invention, in the above-described semiconductor structure, the carrier wafer structure may include a carrier wafer and a third bonding layer. The third bonding layer is located on the carrier wafer.

[0009] According to one embodiment of the present invention, in the above-described semiconductor structure, the first bonding layer closest to the supporting wafer structure may be bonded to the third bonding layer.

[0010] According to one embodiment of the present invention, the semiconductor structure described above may further include a first dielectric layer and a routing structure. The first dielectric layer is located on the transistor wafer structure furthest from the carrier wafer structure. The routing structure is located within the first dielectric layer.

[0011] According to one embodiment of the present invention, the above-described semiconductor structure may further include vias. The vias pass through multiple transistor wafer structures. The vias can be electrically connected to the wiring structure and the multiple transistor wafer structures.

[0012] According to one embodiment of the present invention, the semiconductor structure described above may further include multiple vias. The multiple vias are located in multiple transistor wafer structures and are interconnected. The multiple vias are electrically connected to the wiring structure and the multiple transistor wafer structures.

[0013] According to one embodiment of the present invention, the semiconductor structure described above may further include a first dielectric layer and a wiring structure. The first dielectric layer is located on the transistor wafer structure closest to the carrier wafer structure. The wiring structure is located within the first dielectric layer.

[0014] According to an embodiment of the present invention, in the above-described semiconductor structure, the first dielectric layer may be bonded to the third bonding layer.

[0015] According to one embodiment of the present invention, the semiconductor structure described above may further include a second dielectric layer and an interconnect structure. The second dielectric layer is located on the transistor wafer structure furthest from the supporting wafer structure. The interconnect structure is located within the second dielectric layer.

[0016] According to one embodiment of the present invention, the above-described semiconductor structure may further include vias. The vias pass through multiple transistor wafer structures. The vias can be electrically connected to the wiring structure, the multiple transistor wafer structures, and the interconnect structure.

[0017] According to one embodiment of the present invention, the above-described semiconductor structure may further include multiple vias. The multiple vias are located in multiple transistor wafer structures and are interconnected. The multiple vias can be electrically connected to the wiring structure, the multiple transistor wafer structures, and the interconnect structure.

[0018] According to one embodiment of the present invention, in the above semiconductor structure, the thickness of the transistor wafer can be less than 300 nanometers (nm).

[0019] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a carrier wafer structure. Forming a plurality of transistor wafer structures on the carrier wafer structure. Each transistor wafer structure includes a transistor wafer, a first bonding layer, and a second bonding layer. The transistor wafer has a first side and a second side facing each other. The first bonding layer is located on the first side of the transistor wafer. The second bonding layer is located on the second side of the transistor wafer. The first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures.

[0020] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the carrier wafer structure may include a first carrier wafer and a third bonding layer. The third bonding layer is located on the first carrier wafer. The first bonding layer, which is closest to the first carrier wafer, may be bonded to the third bonding layer.

[0021] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method for forming each transistor wafer structure may include the following steps: Providing a second carrier wafer; Forming a release layer on the second carrier wafer; Forming a second bonding layer on the release layer; Forming a transistor wafer on the second bonding layer; Forming a first bonding layer on the transistor wafer.

[0022] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method of forming a transistor wafer on the second bonding layer may include bonding the transistor wafer to the second bonding layer.

[0023] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: After bonding the first bonding layer closest to the carrier wafer structure to the third bonding layer, or bonding the first bonding layer of one of two adjacent transistor wafer structures to the second bonding layer of the other of two adjacent transistor wafer structures, the second carrier wafer is removed from the release layer. After removing the second carrier wafer, the release layer is removed.

[0024] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, the semiconductor structure includes a carrier wafer structure and multiple transistor wafer structures. Multiple transistor wafer structures are stacked on the carrier wafer structure. Each transistor wafer structure includes a transistor wafer, a first bonding layer, and a second bonding layer. The transistor wafer has a first side and a second side facing each other. The first bonding layer is located on the first side of the transistor wafer. The second bonding layer is located on the second side of the transistor wafer. The first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures. In this way, each transistor wafer can be fabricated independently, thus minimizing the thickness of the transistor wafer and reducing the process complexity of the semiconductor structure.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0026] Figures 1A to 1H are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Figure 2 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 3 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 4 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 5 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Implementation

[0027] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0028] Figures 1A to 1H are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention.

[0029] Referring to FIG1A, a carrier wafer structure 100 is provided. The carrier wafer structure 100 may include a carrier wafer 102 and a bonding layer 104. In some embodiments, the carrier wafer 102 may be a semiconductor wafer, such as a silicon wafer, but the present invention is not limited thereto. The bonding layer 104 is located on the carrier wafer 102. In some embodiments, the material of the bonding layer 104 is, for example, silicon oxide.

[0030] Referring to Figure 1B, a carrier wafer 106 may be provided. In some embodiments, the carrier wafer 106 may be a semiconductor wafer, such as a silicon wafer, but the present invention is not limited thereto. Next, a release layer 108 may be formed on the carrier wafer 106. In some embodiments, the material of the release layer 108 is, for example, a mixture of a metallic material and a dielectric material. Then, a bonding layer 110 may be formed on the release layer 108. In some embodiments, the material of the bonding layer 110 is, for example, silicon oxide.

[0031] Next, a transistor wafer 112 may be formed on the bonding layer 110. The transistor wafer 112 may have a first surface S1 and a second surface S2 facing each other. In some embodiments, the transistor wafer 112 may include a transistor 114. In some embodiments, the transistor 114 may be, for example, a planar field-effect transistor, a fin field-effect transistor (FFET), a gate-all-around field-effect transistor (GAAFET), or a complementary field-effect transistor (CFET). In some embodiments, the transistor 114 may be, for example, an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a combination thereof. In some embodiments, the thickness of the transistor wafer 112 may be less than 300 nanometers. In some embodiments, the material of the transistor wafer 112 may include silicon, silicon germanium (SiGe), a superlattice material, or a combination thereof. In some embodiments, the method of forming a transistor wafer 112 on the bonding layer 110 may include bonding the transistor wafer 112 to the bonding layer 110. Furthermore, although not shown in the figures, the transistor wafer 112 may further include necessary components such as a dielectric layer and / or interconnect structures.

[0032] A bonding layer 116 is formed on the transistor wafer 112. In some embodiments, the material of the bonding layer 116 is, for example, silicon oxide. By the above method, a transistor wafer structure 118 can be formed. The transistor wafer structure 118 may include the transistor wafer 112, the bonding layer 116, and the bonding layer 110. The bonding layer 116 is located on the first surface S1 of the transistor wafer 112. The bonding layer 110 is located on the second surface S2 of the transistor wafer 112.

[0033] Referring to FIG1C, bonding layer 116 may be bonded to bonding layer 104. In some embodiments, the method for bonding layer 116 to bonding layer 104 is, for example, a melt bonding method or a hybrid bonding method.

[0034] Referring to FIG1D, after bonding layer 116 is bonded to bonding layer 104, carrier wafer 106 can be removed from release layer 108. In some embodiments, the method for removing carrier wafer 106 from release layer 108 is, for example, laser removal.

[0035] Next, after removing the carrier wafer 106, the release layer 108 can be removed. In some embodiments, the method for removing the release layer 108 is, for example, dry etching or wet etching.

[0036] Referring to Figure 1E, the structure shown in Figure 1B can be provided. Furthermore, detailed descriptions of the structure in Figure 1B can be found in the description of Figure 1B, and will not be repeated here. Next, the bonding layer 116 of one of two adjacent transistor wafer structures 118 can be bonded to the bonding layer 110 of the other two adjacent transistor wafer structures 118. In some embodiments, the method for bonding the bonding layer 116 of one of two adjacent transistor wafer structures 118 to the bonding layer 110 of the other two adjacent transistor wafer structures 118 is, for example, fusion bonding or hybrid bonding.

[0037] Referring to Figure 1F, after bonding the bonding layer 116 of one of two adjacent transistor wafer structures 118 to the bonding layer 110 of the other two adjacent transistor wafer structures 118, the carrier wafer 106 can be removed from the release layer 108. In some embodiments, the method for removing the carrier wafer 106 from the release layer 108 is, for example, laser removal.

[0038] Next, after removing the carrier wafer 106, the release layer 108 can be removed. In some embodiments, the method for removing the release layer 108 is, for example, dry etching or wet etching.

[0039] Referring to Figure 1G, the steps of Figures 1E and 1F can be repeated to obtain the structure shown in Figure 1G. Using the above method, multiple transistor wafer structures 118 can be formed on the carrier wafer structure 100. Each transistor wafer structure 118 includes a transistor wafer 112, a bonding layer 116, and a bonding layer 110. Furthermore, the multiple transistor wafers 112 of the multiple transistor wafer structures 118 can have the same or different transistor layout designs. Additionally, the number of transistor wafer structures 118 is not limited to the number shown in the figures. Any number of transistor wafer structures 118 falls within the scope of this invention.

[0040] Referring to Figure 1H, a dielectric layer 120 and a wiring structure 122 can be formed on the transistor wafer structure 118 furthest from the carrier wafer structure 100. The dielectric layer 120 can be a single-layer structure or a multi-layer structure, and the number of dielectric layers 120 is not limited to the number shown in the figure. In some embodiments, the material of the dielectric layer 120 is, for example, silicon oxide. The wiring structure 122 is located in the dielectric layer 120. The wiring structure 122 can be a single-layer structure or a multi-layer structure, and the number of wiring structures 122 is not limited to the number shown in the figure. In some embodiments, the material of the wiring structure 122 can be copper, aluminum, tungsten, or a combination thereof.

[0041] The semiconductor structure 10 of the above embodiment will be described below with reference to FIG1H. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0042] Referring to FIG1H, the semiconductor structure 10 includes a carrier wafer structure 100 and a plurality of transistor wafer structures 118. In some embodiments, the semiconductor structure 10 may be fabricated using a wafer-on-wafer (WoW) process. The carrier wafer structure 100 may include a carrier wafer 102 and a bonding layer 104. The bonding layer 104 is located on the carrier wafer 102. A plurality of transistor wafer structures 118 are stacked on the carrier wafer structure 100. Each transistor wafer structure 118 includes a transistor wafer 112, a bonding layer 116, and a bonding layer 110. The transistor wafer 112 has a first side S1 and a second side S2 opposite to each other. In some embodiments, the first side S1 may be the front side of the transistor wafer 112, and the second side S2 may be the back side of the transistor wafer 112. The bonding layer 116 is located on the first side S1 of the transistor wafer 112. The bonding layer 110 is located on the second side S2 of the transistor wafer 112. A bonding layer 116 of one of two adjacent transistor wafer structures 118 is bonded to a bonding layer 110 of the other two adjacent transistor wafer structures 118. In some embodiments, the bonding layer 116 of one of the two adjacent transistor wafer structures 118 may be fused-bonded or mixed-bonded to the bonding layer 110 of the other two adjacent transistor wafer structures 118. The bonding layer 116 closest to the carrier wafer structure 100 may be bonded to a bonding layer 104. In some embodiments, the bonding layer 116 closest to the carrier wafer structure 100 may be fused-bonded or mixed-bonded to a bonding layer 104.

[0043] In some embodiments, the semiconductor structure 10 may further include a dielectric layer 120 and a wiring structure 122. The dielectric layer 120 is located on the transistor wafer structure 118 furthest from the carrier wafer structure 100. The wiring structure 122 is located within the dielectric layer 120. Furthermore, the wiring structure 122 and the plurality of transistor wafer structures 118 may be electrically connected to each other. In some embodiments, the wiring structure 122 and the plurality of transistor wafer structures 118 may be electrically connected to each other via conductive components (e.g., vias and / or interconnect structures, etc.) (not shown).

[0044] Based on the above embodiments, in the semiconductor structure 10 and its manufacturing method, the semiconductor structure 10 includes a carrier wafer structure 100 and a plurality of transistor wafer structures 118. The plurality of transistor wafer structures 118 are stacked on the carrier wafer structure 100. Each transistor wafer structure 118 includes a transistor wafer 112, a bonding layer 116, and a bonding layer 110. The transistor wafer 112 has a first surface S1 and a second surface S2 facing each other. The bonding layer 116 is located on the first surface S1 of the transistor wafer 112. The bonding layer 110 is located on the second surface S2 of the transistor wafer 112. The bonding layer 116 of one of two adjacent transistor wafer structures 118 is bonded to the bonding layer 110 of the other of the two adjacent transistor wafer structures 118. In this way, each transistor wafer 112 can be fabricated independently, thus minimizing the thickness of the transistor wafer 112 and reducing the process complexity of the semiconductor structure 10.

[0045] Figure 2 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0046] Referring to Figures 1H and 2, the manufacturing method of the semiconductor structure 20 in Figure 2 differs from the manufacturing method of the semiconductor structure 10 in Figure 1H as follows. The manufacturing method of the semiconductor structure 20 may further include the following steps: First, a carrier wafer structure 124 may be provided. The carrier wafer structure 124 may include a carrier wafer 126 and a bonding layer 128. In some embodiments, the carrier wafer 126 may be a semiconductor wafer, such as a silicon wafer, but the present invention is not limited thereto. The bonding layer 128 is located on the carrier wafer 126. In some embodiments, the material of the bonding layer 128 is, for example, silicon oxide. Next, a dielectric layer 120 may be bonded to the bonding layer 128.

[0047] Then, the carrier wafer 102 can be removed. Next, a dielectric layer 130 and an interconnect structure 132 can be formed on the transistor wafer structure 118 furthest from the carrier wafer structure 124. In some embodiments, the dielectric layer 130 may be located on the bonding layer 104. The dielectric layer 130 may be a single-layer structure or a multi-layer structure, and the number of dielectric layers 130 is not limited to the number shown in the figures. In some embodiments, the material of the dielectric layer 130 is, for example, silicon oxide. The interconnect structure 132 is located in the dielectric layer 130. The interconnect structure 132 may be a single-layer structure or a multi-layer structure, and the number of interconnect structures 132 is not limited to the number shown in the figures. In some embodiments, the material of the interconnect structure 132 is, for example, copper, aluminum, tungsten, or a combination thereof.

[0048] Furthermore, the semiconductor structure 20 of FIG2 differs from the semiconductor structure 10 of FIG1H as follows. In semiconductor structure 20, multiple transistor wafer structures 118 are stacked on a carrier wafer structure 124. In semiconductor structure 20, a dielectric layer 120 may be located on the transistor wafer structure 118 closest to the carrier wafer structure 124, and the dielectric layer 120 may be bonded to a bonding layer 128.

[0049] The semiconductor structure 20 may further include a dielectric layer 130 and an interconnect structure 132. The dielectric layer 130 is located on the transistor wafer structure 118 furthest from the carrier wafer structure 124. The interconnect structure 132 is located in the dielectric layer 130. In some embodiments, the wiring structure 122, the plurality of transistor wafer structures 118, and the interconnect structure 132 may be electrically connected to each other via conductive components (e.g., vias and / or interconnect structures, etc.) (not shown).

[0050] Furthermore, in the semiconductor structure 10 of FIG1H and the semiconductor structure 20 of FIG2, the same or similar components are represented by the same symbols and their descriptions are omitted.

[0051] Based on the above embodiments, in the semiconductor structure 20 and its manufacturing method, the semiconductor structure 20 includes a carrier wafer structure 124 and a plurality of transistor wafer structures 118. The plurality of transistor wafer structures 118 are stacked on the carrier wafer structure 124. Each transistor wafer structure 118 includes a transistor wafer 112, a bonding layer 116, and a bonding layer 110. The transistor wafer 112 has a first surface S1 and a second surface S2 that are opposite to each other. The bonding layer 116 is located on the first surface S1 of the transistor wafer 112. The bonding layer 110 is located on the second surface S2 of the transistor wafer 112. The bonding layer 116 of one of two adjacent transistor wafer structures 118 is bonded to the bonding layer 110 of the other of the two adjacent transistor wafer structures 118. In this way, each transistor wafer 112 can be fabricated independently, thus minimizing the thickness of the transistor wafer 112 and reducing the process complexity of the semiconductor structure 20.

[0052] Figure 3 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0053] Referring to Figures 1H and 3, the differences between the semiconductor structure 30 in Figure 3 and the semiconductor structure 10 in Figure 1H are as follows. In semiconductor structure 30, an example illustrates the electrical connection between wiring structure 122 and multiple transistor wafer structures 118. Semiconductor structure 30 may further include vias 300. The vias 300 pass through the multiple transistor wafer structures 118. The vias 300 can be connected to the transistor wafer 112 closest to the carrier wafer structure 100. The vias 300 can be electrically connected to wiring structure 122 and multiple transistor wafer structures 118. Therefore, wiring structure 122 and multiple transistor wafer structures 118 can be electrically connected to each other vias 300. In some embodiments, the material of the vias 300 is, for example, copper or tungsten.

[0054] In some embodiments, the semiconductor structure 30 may further include a via 302. The via 302 is located between the wiring structure 122 and the transistor wafer 112 closest to the wiring structure 122. The via 302 may be electrically connected to the wiring structure 122 and the transistor wafer 112 closest to the wiring structure 122. The via 302 may be located in the bonding layer 110. In some embodiments, the material of the via 302 is, for example, copper or tungsten.

[0055] Furthermore, in the semiconductor structure 10 of FIG1H and the semiconductor structure 30 of FIG3, the same or similar components are represented by the same symbols and their descriptions are omitted.

[0056] Figure 4 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0057] Referring to Figures 1H and 4, the differences between the semiconductor structure 40 in Figure 4 and the semiconductor structure 10 in Figure 1H are as follows. In semiconductor structure 40, an example illustrates the electrical connection between wiring structure 122 and multiple transistor wafer structures 118. Semiconductor structure 40 may further include multiple vias 400. The multiple vias 400 are located within the multiple transistor wafer structures 118 and are interconnected. The via 400 furthest from wiring structure 122 can be connected to the transistor wafer 112 closest to the carrier wafer structure 100. The multiple vias 400 can be electrically connected to wiring structure 122 and multiple transistor wafer structures 118. Therefore, wiring structure 122 and multiple transistor wafer structures 118 can be electrically connected to each other vias 400. The vias 400 can be a single-layer or multi-layer structure. In some embodiments, the material of the vias 400 is, for example, copper or tungsten.

[0058] In some embodiments, the semiconductor structure 400 may further include a via 402. The via 402 is located between the wiring structure 122 and the transistor wafer 112 closest to the wiring structure 122. The via 402 may be electrically connected to the wiring structure 122 and the transistor wafer 112 closest to the wiring structure 122. The via 402 may be located in the bonding layer 110. In some embodiments, the material of the via 402 is, for example, copper or tungsten.

[0059] Furthermore, in the semiconductor structure 10 of FIG1H and the semiconductor structure 40 of FIG4, the same or similar components are represented by the same symbols and their descriptions are omitted.

[0060] Figure 5 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0061] Please refer to Figures 2 and 5. The differences between the semiconductor structure 50 in Figure 5 and the semiconductor structure 20 in Figure 2 are as follows. In semiconductor structure 50, the electrical connection method of wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132 is illustrated by example. Semiconductor structure 50 may further include vias 500. Vias 500 pass through the multiple transistor wafer structures 118. Vias 500 may also pass through bonding layer 104. Vias 500 can be electrically connected to wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132. Therefore, wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132 can be electrically connected to each other via vias 500. In some embodiments, the material of via 500 is, for example, copper or tungsten.

[0062] In some embodiments, the semiconductor structure 500 may further include a via 502. The via 502 is located between the interconnect structure 132 and the transistor wafer 112 closest to the interconnect structure 132. The via 502 may be electrically connected to the interconnect structure 132 and the transistor wafer 112 closest to the interconnect structure 132. The via 502 may be located in the bonding layer 104 and the bonding layer 116. In some embodiments, the material of the via 502 is, for example, copper or tungsten.

[0063] Furthermore, in the semiconductor structure 20 of Figure 2 and the semiconductor structure 50 of Figure 5, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0064] Figure 6 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention.

[0065] Please refer to Figures 2 and 6. The differences between the semiconductor structure 60 in Figure 6 and the semiconductor structure 20 in Figure 2 are as follows. In semiconductor structure 60, the electrical connection method of wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132 is illustrated by example. Semiconductor structure 60 may further include multiple vias 600. The multiple vias 600 are located in the multiple transistor wafer structures 118 and are interconnected with each other. The multiple vias 600 can be electrically connected to wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132. Therefore, wiring structure 122, multiple transistor wafer structures 118, and interconnect structure 132 can be electrically connected to each other vias 600. The vias 600 can be a single-layer structure or a multi-layer structure. In some embodiments, the material of the vias 600 is, for example, copper or tungsten.

[0066] In some embodiments, the semiconductor structure 600 may further include a via 602. The via 602 is located between the interconnect structure 132 and the transistor wafer 112 closest to the interconnect structure 132. The via 602 may be electrically connected to the interconnect structure 132 and the transistor wafer 112 closest to the interconnect structure 132. The via 602 may be located in the bonding layer 104 and the bonding layer 116. In some embodiments, the material of the via 602 is, for example, copper or tungsten.

[0067] Furthermore, in the semiconductor structure 20 of Figure 2 and the semiconductor structure 60 of Figure 6, the same or similar components are represented by the same symbols, and their descriptions are omitted.

[0068] In summary, in the semiconductor structure and manufacturing method of the above embodiments, the semiconductor structure includes a carrier wafer structure and multiple transistor wafer structures. Multiple transistor wafer structures are stacked on the carrier wafer structure. Each transistor wafer structure includes a transistor wafer, a first bonding layer, and a second bonding layer. The transistor wafer has a first side and a second side facing each other. The first bonding layer is located on the first side of the transistor wafer. The second bonding layer is located on the second side of the transistor wafer. The first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures. In this way, each transistor wafer can be fabricated independently, thus minimizing the thickness of the transistor wafer and reducing the process complexity of the semiconductor structure.

[0069] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0070] 10, 20, 30, 40, 50, 60: Semiconductor structure 100, 124: Supporting wafer structure 102, 106, 126: Carrier wafers 104, 110, 116, 128: Bonding layers 108: Release Layer 112: Transistor Wafer 114: Transistor 118: Transistor wafer structure 120, 130: Dielectric layer 122: Wiring Structure 132: Internal Wiring Structure 300, 302, 400, 402, 500, 502, 600, 602: Through holes S1: First Page S2: Second side

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provides a carrier wafer structure; The method of forming a plurality of transistor wafer structures on the carrier wafer structure includes: a transistor wafer having a first face and a second face opposite to each other; a first bonding layer located on the first face of the transistor wafer; and a second bonding layer located on the second face of the transistor wafer, wherein the first bonding layer of one of two adjacent transistor wafer structures is bonded to the second bonding layer of the other of the two adjacent transistor wafer structures, the carrier wafer structure includes a first carrier wafer and a third bonding layer, the third bonding layer being located on the first carrier wafer, and the first bonding layer closest to the first carrier wafer being bonded to the third bonding layer, and the method of forming each transistor wafer structure includes: providing a second carrier wafer; forming a release layer on the second carrier wafer; forming the second bonding layer on the release layer; forming the transistor wafer on the second bonding layer; and forming the first bonding layer on the transistor wafer.

2. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the method of forming the transistor wafer on the second bonding layer includes bonding the transistor wafer to the second bonding layer.

3. The method for manufacturing the semiconductor structure as described in claim 1 further includes: After bonding the first bonding layer closest to the carrier wafer structure to the third bonding layer or bonding the first bonding layer of one of two adjacent transistor wafer structures to the second bonding layer of the other of two adjacent transistor wafer structures, the second carrier wafer is removed from the release layer; and after removing the second carrier wafer, the release layer is removed.

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