Semiconductor device

Abstract

This application discloses a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned on the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile; and a word line including a word line dielectric layer and a word line conductive layer, the word line dielectric layer uniformly and laterally surrounding the channel layer, the word line conductive layer laterally and partially surrounding the word line dielectric layer, extending along a second direction parallel to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 938,457 (i.e., priority date "November 6, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a vertical channel layer and a method of manufacturing a semiconductor device having a vertical channel layer. Prior Technology

[0003] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the ever-increasing demands for computing power. However, various problems arise during this shrinkage process, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a channel layer positioned above the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile; and a word line including a word line dielectric layer closely attached to and laterally surrounding the channel layer, and a word line conductive layer laterally and partially surrounding the word line dielectric layer, extending along a second direction parallel to a top surface of the substrate, and including an inverted trapezoidal cross-sectional profile.

[0006] Another embodiment of this disclosure provides a semiconductor device including a substrate; a channel layer positioned above the substrate and extending along a first direction perpendicular to a top surface of the substrate, wherein a width of a top surface of the channel layer is greater than a width of a bottom surface of the channel layer; and a word line including a word line dielectric layer that is close to and laterally surrounds the channel layer, and a word line conductive layer that is laterally and partially surrounds the word line dielectric layer and extends along a second direction parallel to a top surface of the substrate, wherein a width of a top surface of the word line conductive layer is greater than a width of a bottom surface of the word line conductive layer.

[0007] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a lower dielectric layer above the substrate; forming an intermediate dielectric layer on the lower dielectric layer; forming a word trench penetrating the intermediate dielectric layer, exposing the lower dielectric layer, and including an inverted trapezoidal cross-sectional profile; forming a word conductive layer filling the word trench; forming an upper dielectric layer on the intermediate dielectric layer; forming a channel opening penetrating the upper dielectric layer, the word conductive layer, and the lower dielectric layer to expose the substrate; forming a word dielectric layer in close contact with one sidewall of the channel opening; and forming a channel layer filling the channel opening. The word conductive layer and the word dielectric layer are configured together to form a word.

[0008] Due to the design of the semiconductor device disclosed herein, the process window for forming the channel layer can be increased by employing a word line conductive layer and a channel layer with an inverted trapezoidal cross-sectional profile. Therefore, defects in the manufactured semiconductor device can be reduced, and the yield of the manufactured semiconductor device can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When referring to the drawings in conjunction with the embodiments and the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 2 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 3 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 2. Figure 4 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 5 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 4. Figure 6 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figures 7 to 9 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 6, illustrating a portion of the process for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 10 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 11 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 10. Figure 12 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figures 13 to 16 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 12, illustrating a portion of the process for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 17 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figures 18 and 19 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 17, illustrating a portion of the process for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 20 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 21 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 20. Figures 22 to 24 are schematic cross-sectional views illustrating semiconductor devices according to some embodiments of this disclosure. Figure 25 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figures 26 to 30 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 25, illustrating a portion of the process for manufacturing a semiconductor device according to another embodiment of this disclosure. Figure 31 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 32 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 31. Figure 33 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 34 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 33. Figure 35 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 36 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 35. Figure 37 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of this disclosure. Figure 38 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 37. Implementation

[0011] The following description of this disclosure, accompanied by drawings incorporated into and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0012] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0013] To ensure a complete understanding of this disclosure, the following description provides detailed steps and structures. It is clear that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting the disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description but is defined by the claims.

[0014] Figure 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 3 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 2. Figure 4 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 5 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 4.

[0015] Referring to Figures 1 to 5, in step S11, a substrate 111 is provided, a plurality of bit lines 311 are formed in the substrate 111, and a plurality of bit line contact points 313 are formed on the plurality of bit lines 311.

[0016] Referring to Figures 2 and 3, substrate 111 includes a bulk semiconductor substrate. The bulk semiconductor substrate is formed of, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0017] In some embodiments, substrate 111 includes a semiconductor insulator structure comprising, from bottom to top, a handle substrate, an insulating layer, and a top semiconductor material layer. The handle substrate and the top semiconductor material layer are formed of the same material as the aforementioned bulk semiconductor substrate. The insulating layer is a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer is a dielectric oxide, such as silicon oxide. Another example is a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer comprises a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulating layer has a thickness between about 10 nm and about 200 nm. The insulating layer eliminates leakage current between adjacent elements in substrate 111 and reduces parasitic capacitance associated with the source / drain.

[0018] It should be noted that the term "about," used to modify the quantity of ingredients, components, or reactants used in this disclosure, refers to possible numerical variations, such as those resulting from typical measurements and liquid handling procedures used in the preparation of concentrates or solutions. Furthermore, variations may arise from unintentional errors in measurement procedures, manufacturing differences, variations in the source or purity of the ingredients used, and similar circumstances. In one embodiment, the term "about" means within 10% of the reported value. In another embodiment, the term "about" means within 5% of the reported value. In yet another embodiment, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0019] Referring to Figures 2 and 3, a plurality of bit lines 311 are formed in the substrate 111. In the cross-sectional perspective view, the top surface 311TS of the plurality of bit lines 311 and the top surface 111TS of the substrate 111 are substantially coplanar. In the top perspective view, the plurality of bit lines 311 are arranged along the Y direction. Each bit line 311 extends along the X direction.

[0020] In some embodiments, a plurality of bit line trenches (not shown) are formed in substrate 111. A conductive material (not shown) is deposited to completely fill the bit line trenches. A planarization process, such as chemical mechanical polishing, is performed until the top surface 111TS of substrate 111 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming a plurality of bit lines 311. In some embodiments, the conductive material is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0021] Referring to Figures 4 and 5, a dielectric layer 121 is formed on a substrate 111, covering a plurality of unit lines 311. In some embodiments, the dielectric layer 121 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, a low-dielectric-constant dielectric material, the like, or combinations thereof. In some embodiments, the dielectric layer 121 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the dielectric layer 121 is not shown in the top view. Low-dielectric-constant dielectric materials have a dielectric constant of less than 3.0 or even less than 2.5.

[0022] Referring to Figures 4 and 5, in the cross-sectional perspective view, a plurality of bit line contact points 313 are formed through the dielectric layer 121 and electrically connected to a plurality of bit lines 311. The top surface 313TS of the plurality of bit line contact points 313 and the top surface 121TS of the dielectric layer 121 are substantially coplanar. In the top perspective view, the plurality of bit line contact points 313 include, but are not limited to, a circular cross-section. The plurality of bit line contact points 313 are arranged along the X and Y directions.

[0023] In some embodiments, a plurality of bit-line contact point openings (not shown) are formed through dielectric layer 121 to expose a plurality of bit lines 311. A conductive material (not shown) is deposited to completely fill the plurality of bit-line contact point openings. A planarization process, such as chemical mechanical polishing, is performed until the top surface 121TS of dielectric layer 121 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the plurality of bit-line contacts 313. In some embodiments, the conductive material is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0024] Figure 6 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 7 to 9 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 6, illustrating a process portion of manufacturing semiconductor device 1A according to an embodiment of the present disclosure. Figure 10 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 11 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 10.

[0025] Referring to Figures 1 and 6 to 11, in step S13, an intermediate dielectric layer 141 is formed on the plurality of bit line contact points 313, a plurality of word line trenches TR1 including tapered sidewalls 141SW are formed through the intermediate dielectric layer 141, and a plurality of word line conductive layers 411 are formed that fill the plurality of word line trenches TR1 and include an inverted trapezoidal cross-sectional profile.

[0026] Referring to Figures 6 and 7, a dielectric layer 123 (also referred to as the lower dielectric layer 123) is formed on the dielectric layer 121 and covers a plurality of bit line contacts 313. In some embodiments, the dielectric layer 123 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, a low dielectric constant dielectric material, the like, or combinations thereof. In some embodiments, the dielectric layer 123 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the dielectric layer 123 is not shown in the top view.

[0027] Referring to Figures 6 and 7, an intermediate dielectric layer 141 is formed on the dielectric layer 123. In some embodiments, the intermediate dielectric layer 141 is formed of a material having etch selectivity for the dielectric layer 123. In some embodiments, the intermediate dielectric layer 141 is formed of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, silicon oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, boron silicon carbon nitride, or other suitable insulating materials. In some embodiments, the intermediate dielectric layer 141 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the intermediate dielectric layer 141 is not shown in the top view.

[0028] Referring to Figures 6 and 7, a first photomask layer 801 is formed on the intermediate dielectric layer 141. In some embodiments, the first photomask layer 801 is a photoresist layer and includes a first pattern P1. From a top view, the first pattern P1 includes a plurality of linear spaces extending along the Y direction. The intermediate dielectric layer 141 is partially exposed through the first pattern P1.

[0029] Referring to Figure 8, an etching process (also known as a word line etching process) is performed using a first photomask layer 801 as a mask to partially remove the intermediate dielectric layer 141 and form a plurality of word line trenches TR1. In some embodiments, the etching process is an anisotropic etching process, such as an anisotropic dry etching process. For the sake of brevity, clarity and ease of description, only one word line trench TR1 is described.

[0030] In some embodiments, the sidewalls 141SW of the word line trench TR1 are tapered. The width (or dimension) W1 of the word line trench TR1 gradually decreases from the top surface 141TS of the intermediate dielectric layer 141 towards the bottom surface 141BS of the intermediate dielectric layer 141 in the opposite direction of the Z direction. In other words, the width W1 of the word line trench TR1 near the top surface 141TS of the intermediate dielectric layer 141 is greater than the width W1 of the word line trench TR1 near the bottom surface 141BS of the intermediate dielectric layer 141.

[0031] After forming the word line groove TR1, the first photomask layer 801 is removed.

[0032] Referring to FIG9, a layer of first conductive material 811 is formed to completely fill the word line trench TR1. In some embodiments, the first conductive material 811 is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the layer of first conductive material 811 is formed by, for example, physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0033] Referring to Figures 10 and 11, a planarization process, such as chemical mechanical polishing, is performed until the top surface 141TS of the intermediate dielectric layer 141 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming a plurality of word line conductive layers 411. From a top view, the plurality of word line conductive layers 411 are arranged along the X direction and extend along the Y direction. For simplicity, clarity, and ease of description, only one word line conductive layer 411 is described.

[0034] Viewed in cross-section, the word line conductive layer 411 comprises an inverted trapezoidal cross-section. The sidewalls 411SW (or 141SW) of the word line conductive layer 411 are tapered. The width (or dimension) of the word line conductive layer 411 gradually decreases from the top surface 411TS of the word line conductive layer 411 towards the bottom surface 411BS of the word line conductive layer 411 in the opposite direction of the Z-direction. That is, the width W2 of the top surface 411TS of the word line conductive layer 411 is greater than the width W3 of the bottom surface 411BS of the word line conductive layer 411.

[0035] In some embodiments, the width W2 of the top surface 411TS of the word line conductive layer 411 and the width W4 of the bit line contact point 313 are substantially the same. In some embodiments, the width W2 of the top surface 411TS of the word line conductive layer 411 and the width W4 of the bit line contact point 313 are different.

[0036] In some embodiments, the width W3 of the bottom surface 411BS of the word line conductive layer 411 and the width W4 of the bit line contact point 313 are substantially the same. In some embodiments, the width W3 of the bottom surface 411BS of the word line conductive layer 411 and the width W4 of the bit line contact point 313 are different.

[0037] Figure 12 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 13 to 16 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 12, illustrating a process portion of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0038] Referring to Figures 1 and 12 to 16, in step S15, a plurality of channel openings OP1 are formed through a plurality of word line conductive layers 411 to expose a plurality of bit line contact points 313, and a plurality of word line dielectric layers 413 are conformally formed on the sidewalls 413SW of the plurality of channel openings OP1 to configure a plurality of word lines 410.

[0039] Referring to Figures 12 and 13, a dielectric layer 125 (also referred to as the upper dielectric layer 125) is formed on the intermediate dielectric layer 141 and covers a plurality of word line conductive layers 411. In some embodiments, the dielectric layer 125 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant dielectric materials, the like, or combinations thereof. In some embodiments, the dielectric layer 125 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the dielectric layer 125 is not shown in the top view.

[0040] Referring to Figures 12 and 13, a second photomask layer 803 is formed on the dielectric layer 125. In some embodiments, the second photomask layer 803 is a photoresist layer and includes a second pattern P2. Viewed from above, the second pattern P2 includes a plurality of circular spaces, which are respectively and correspondingly aligned in the Z direction with a plurality of bit line contact points 313. The second pattern P2 is located at the intersection of the word line conductive layer 411 and the plurality of bit lines 311. The dielectric layer 125 is partially exposed through the second pattern P2.

[0041] It should be noted that in the description of this disclosure, the term "element A (or feature A) aligned with element B (or feature B) in the Z direction" means that element A is directly below (or above) element B. From a top view, element A and element B may overlap.

[0042] Referring to Figure 14, an etching process (also known as a channel etching process) is performed using a second photomask layer 803 as a mask to remove the dielectric layer 125, the word line conductive layer 411, and to form a plurality of channel openings OP1. A plurality of bit line contacts 313 are exposed through the plurality of channel openings OP1. In some embodiments, the etching process is an anisotropic etching process, such as an anisotropic dry etching process. For simplicity, clarity, and ease of description, only one channel opening OP1 is described.

[0043] In some embodiments, the sidewall 413SW of the channel opening OP1 is tapered. The width (or dimension) W5 of the channel opening OP1 gradually decreases from the top surface 125TS of the dielectric layer 125 to the bottom surface 123BS of the dielectric layer 123 in the opposite direction of the Z direction. In other words, the width W5 of the channel opening OP1 near the top surface 125TS of the dielectric layer 125 is greater than the width W5 of the channel opening OP1 near the bottom surface 123BS of the dielectric layer 123.

[0044] After forming the channel opening OP1, the second photomask layer 803 is removed.

[0045] Referring to FIG. 15, a layer of first dielectric material 813 is conformally formed on the top surface 125TS of dielectric layer 125, the sidewall 413SW of channel opening OP1, and the bit line contact point 313 exposed through channel opening OP1. In some embodiments, the first dielectric material 813 is, for example, a high dielectric constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the layer of first dielectric material 813 may be formed through, for example, atomic layer deposition or other suitable deposition processes.

[0046] In some embodiments, the high dielectric constant dielectric material includes one or more hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0047] Referring to FIG16, a hole-etching process is performed to remove the first dielectric material 813 formed on the top surface 125TS of the dielectric layer 125 and the bit line contact 313. In some embodiments, the hole-etching process is an anisotropic etching process, such as an anisotropic dry etching process. After the hole-etching process, the bit line contact 313 is exposed through the channel opening OP1.

[0048] Figure 17 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 18 and 19 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 17, illustrating a process portion of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0049] Referring to Figures 1 and 17 to 19, in step S17, a plurality of channel layers 211 are formed to fill a plurality of channel openings OP1 and include an inverted trapezoidal profile.

[0050] Referring to Figures 17 and 18, a conductive material (not shown) is deposited to completely fill the channel opening OP1. A planarization process, such as chemical mechanical polishing, is performed until the top surface 125TS is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming a plurality of channel layers 211. In some embodiments, the conductive material is, for example, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. In some embodiments, the conductive material is formed through, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. For brevity, clarity, and ease of description, only one channel layer 211 is described. The channel layer 211 is disposed on and electrically connected to the bit line contact 313, and the bit line contact 313 contacts the channel layer 211 and the word line dielectric layer 413. The channel layer 211 and the word line conductive layer 411 are electrically isolated through the word line dielectric layer 413.

[0051] From a top view, the channel opening OP1 is located at the intersection of the word line conductive layer 411 and the bit line 311. From a cross-sectional view, the top surface 125TS of the dielectric layer 125, the top surface 413TS of the word line dielectric layer 413, and the top surface 211TS of the channel layer 211 are substantially coplanar. The channel layer 211 has an inverted trapezoidal cross-sectional profile. The sidewalls 211SW of the channel layer 211 are tapered. The width (or dimension) of the channel layer 211 gradually decreases from the top surface 211TS to the bottom surface 211BS of the channel layer 211 in the opposite direction of the Z-direction. That is, the width W6 of the top surface 211TS of the channel layer 211 is greater than the width W7 of the bottom surface 211BS of the channel layer 211.

[0052] In some embodiments, the width W6 of the top surface 211TS of the channel layer 211 is smaller than the width W2 of the top surface 411TS of the word line conductive layer 411. In some embodiments, the width W7 of the bottom surface 211BS of the channel layer 211 is smaller than the width W3 of the bottom surface 411BS of the word line conductive layer 411.

[0053] Referring to FIG19, a dielectric layer 127 is formed on dielectric layer 125 and covers channel layer 211 and word line dielectric layer 413. In some embodiments, dielectric layer 127 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant dielectric material, similar materials, or combinations thereof. In some embodiments, dielectric layer 127 may be formed through, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, dielectric layer 127 is not shown in the top view.

[0054] Figure 20 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 21 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 20.

[0055] Referring to Figures 1, 20 and 21, in step S19, a plurality of storage node structures 510 are formed on a plurality of channel layers 211.

[0056] For the sake of brevity, clarity and ease of description, only one storage node structure is described 510.

[0057] Referring to Figures 20 and 21, a storage node structure 510 is formed in the dielectric layer 127 and on the channel layer 211. The storage node structure 510 includes a first electrode layer 511, an intermediate insulating layer 513, and a second electrode layer 515. The first electrode layer 511 is disposed on the channel layer 211 and includes a U-shaped profile. In some embodiments, the first electrode layer 511 is formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0058] An intermediate insulating layer 513 is disposed on the first electrode layer 511 and includes a U-shaped profile. In some embodiments, the intermediate insulating layer 513 is formed of, for example, silicon oxide, silicon nitride, a high dielectric constant dielectric material or other suitable dielectric material.

[0059] A second electrode layer 515 is formed on the intermediate insulating layer 513. In some embodiments, the second electrode layer 515 is formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The first electrode layer 511 and the second electrode layer 515 are electrically isolated through the intermediate insulating layer 513.

[0060] From a top-down view, the storage node structure 510 is located at the intersection of word line 410 and bit line 311. The storage node structure 510 is aligned with the channel layer 211 in the Z direction. In other words, a plurality of storage node structures 510 are arranged along the X and Y directions.

[0061] By employing a word line conductive layer 411 and a channel layer 211 with an inverted trapezoidal cross-sectional profile, the process window for forming the channel layer 211 is increased. Therefore, defects in the manufacture of the semiconductor device 1A can be reduced, and the yield of the manufacture of the semiconductor device 1A can be improved.

[0062] Figures 22 to 24 are schematic cross-sectional views illustrating semiconductor devices 1B, 1C, and 1D according to some embodiments of this disclosure.

[0063] Referring to FIG22, semiconductor device 1B has a structure similar to that shown in FIG21. Elements in FIG22 that are the same as or similar to those in FIG21 are labeled with similar reference numerals, and repeated descriptions have been omitted.

[0064] Semiconductor device 1B includes a dielectric layer 129 disposed between a substrate 111 and a dielectric layer 123. In some embodiments, the dielectric layer 129 is formed of, for example, silica, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, a low dielectric constant dielectric material, the like, or combinations thereof. Bit lines 311 are disposed in the dielectric layer 129 and between bit line contacts 313 and the substrate 111.

[0065] Referring to FIG23, semiconductor device 1C has a structure similar to that shown in FIG21. Elements in FIG23 that are the same as or similar to those in FIG21 are labeled with similar reference numerals, and repeated descriptions have been omitted.

[0066] Semiconductor device 1C includes a plurality of bit line spacers 315. The plurality of bit line spacers 315 are disposed on the sidewalls 311SW of bit lines 311. In some embodiments, the plurality of bit line spacers 315 are porous materials having a low dielectric constant. In some embodiments, the plurality of bit line spacers 315 are air gaps. By employing air gaps or porous bit line spacers 315, parasitic capacitance between adjacent bit lines 311 can be reduced. Therefore, the performance of semiconductor device 1C can be improved.

[0067] Referring to Figure 24, semiconductor device 1D has a structure similar to that shown in Figure 21. Elements in Figure 24 that are the same as or similar to those in Figure 21 are labeled with similar reference numerals, and repeated descriptions have been omitted.

[0068] Semiconductor device 1D includes a plurality of bit line contact point spacers 317. The plurality of bit line contact point spacers 317 are disposed on the sidewalls 313SW of the bit line contacts 313. In some embodiments, the plurality of bit line contact point spacers 317 are porous materials having a low dielectric constant. In some embodiments, the plurality of bit line contact point spacers 317 may be air gaps. By employing air gaps or porous bit line contact point spacers 317, parasitic capacitance between adjacent bit line contacts 313 can be reduced. Therefore, the performance of semiconductor device 1D can be improved.

[0069] Figure 25 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 26 to 30 are schematic cross-sectional views taken along lines A-A' and B-B' in Figure 25, illustrating a process portion of manufacturing a semiconductor device 1E according to another embodiment of the present disclosure. Figure 31 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 32 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 31. Figure 33 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 34 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 33. Figure 35 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 36 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 35. Figure 37 is a schematic top view illustrating an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 38 is a schematic cross-sectional view taken along lines A-A' and B-B' in Figure 37.

[0070] Referring to Figures 25 and 26, a substrate 111 is provided, the fabrication process of which is similar to that shown in Figure 3 and will not be repeated here. A first hard mask layer 809 is formed on the substrate 111. In some embodiments, the first hard mask layer 809 is formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, or boron carbide. In some embodiments, the first hard mask layer 809 is formed by, for example, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes. It should be noted that, for clarity, the first hard mask layer 809 is not shown in the top view.

[0071] Referring to Figures 25 and 26, a plurality of storage node openings OP2 are formed, penetrating the first hard mask layer 809 and extending to the substrate 111. From a top view, the storage node openings OP2 are arranged along the X and Y directions. For simplicity, clarity, and ease of description, only one storage node opening OP2 is described.

[0072] Referring to Figure 27, a third photomask layer 805 is formed on the first hard mask layer 809. The third photomask layer 805 is a photoresist layer. Some portions of the first hard mask layer 809 are exposed through the pattern of the third photomask layer 805. For example, the third photomask layer 805 does not cover the portion of the first hard mask layer 809 adjacent to the memory node opening OP2. Subsequently, an etching process, such as a wet etching process, is performed to remove the exposed portions of the first hard mask layer 809. After removing the first hard mask layer 809, the top surface 111TS of the substrate 111 adjacent to the memory node opening OP2 is exposed. The third photomask layer 805 is removed after the etching process.

[0073] Referring to FIG28, an implantation process is performed to dope the exposed region of the substrate 111 (through the storage node opening OP2) and transform the region into the first electrode layer 511. In some embodiments, the dopant in the implantation process is, for example, phosphorus, arsenic, antimony, or boron. After the first electrode layer 511 is formed, the first hard mask layer 809 is removed.

[0074] Referring to FIG. 29, a layer of first insulating material 815 is conformally formed to cover substrate 111 and first electrode layer 511. In some embodiments, the layer of first insulating material 815 has a thickness between about 10 angstroms and about 1000 angstroms. In some embodiments, the layer of first insulating material 815 is formed by low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition or other suitable deposition processes.

[0075] In some embodiments, the layers of the first insulating material 815 are a stacked layer structure, such as an oxide-nitride-oxide structure. In some embodiments, the first insulating material 815 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like.

[0076] In some embodiments, the first insulating material 815 comprises, for example, a high dielectric constant dielectric material, such as metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal nitride, metal aluminate, zirconium silicate, zirconium aluminate, or combinations thereof. In some embodiments, the first insulating material 815 is formed of hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or combinations thereof. In some embodiments, the first insulating material 815 is a stacked layer structure comprising, for example, a layer of silicon oxide and another layer of a high dielectric constant dielectric material.

[0077] Referring to Figure 29, a layer of second conductive material 817 is formed to fill the storage node opening OP2 and cover a layer of first insulating material 815. A planarization process, such as chemical mechanical polishing, is performed to provide a substantially flat surface for subsequent process steps.

[0078] In some embodiments, the second conductive material 817 includes, for example, doped polycrystalline silicon, doped polycrystalline silicon-germanium, aluminum, copper, platinum, gold, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, or a gold-copper alloy.

[0079] In some embodiments, the second conductive material 817 comprises, for example, materials derived from metal borides, metal phosphides, and metal antimonides that include transition metals from Groups IV, V, and VI of the periodic table. The transition metals are titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, or tungsten. In some embodiments, the second conductive material 817 comprises titanium diboride, zirconium diboride, hafnium diboride, titanium phosphide, zirconium phosphide, hafnium phosphide, titanium antimonide, zirconium antimonide, or hafnium antimonide. The second conductive material 817 exhibits high thermal stability and excellent electrical conductivity.

[0080] Referring to Figure 29, a fourth photomask layer 807 is formed on the second conductive material 817. The fourth photomask layer 807 is a photoresist layer. The width W8 of the fourth photomask layer 807 is greater than the width W9 of the first electrode layer 511.

[0081] Referring to Figure 30, an etching process, such as an anisotropic dry etching process, is performed to remove portions of the second conductive material 817 and the first insulating material 815. After the etching process, the remaining second conductive material 817 is referred to as the second electrode layer 515. The remaining first insulating material 815 is referred to as the intermediate insulating layer 513. The first electrode layer 511 and the second electrode layer 515 are electrically isolated by the intermediate insulating layer 513. The first electrode layer 511, the intermediate insulating layer 513, and the second electrode layer 515 are configured together to form a storage node structure 510. After forming the storage node structure 510, the fourth photomask layer 807 is removed.

[0082] Referring to Figures 31 and 32, a dielectric layer 131 is formed on substrate 111. A planarization process, such as chemical mechanical polishing, is then performed until the top surface 515TS of the second electrode layer 515 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. The top surface 515TS of the second electrode layer 515 and the top surface 131TS of the dielectric layer 131 are substantially coplanar. In some embodiments, the dielectric layer 131 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, a low dielectric constant dielectric material, the like, or combinations thereof. In some embodiments, the dielectric layer 131 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the dielectric layer 131 is not shown in the top view.

[0083] In the top-view perspective, multiple storage node structures 510 are arranged along the X and Y directions.

[0084] Referring to Figures 33 and 34, a dielectric layer 123 is formed on the dielectric layer 131 and covers the storage node structure 510. The fabrication process is similar to that described in Figures 6 and 7, and the relevant description will not be repeated here. An intermediate dielectric layer 141 is formed on the dielectric layer 123, and the fabrication process is similar to that described in Figures 6 and 7, and the relevant description will not be repeated here.

[0085] Referring to Figures 33 and 34, a word line conductive layer 411 is formed in the intermediate dielectric layer 141, with a process similar to that described in Figures 8 to 11, and the relevant description will not be repeated here. A channel opening OP1 (not shown) is formed to expose the storage node structure 510, with a process similar to that described in Figures 12 to 14, and the relevant description will not be repeated here. A word line dielectric layer 413 and a channel layer 211 are formed in the channel opening OP1, with a process similar to that described in Figures 15 to 18, and the relevant description will not be repeated here. The word line conductive layer 411 and the word line dielectric layer 413 are together configured to accommodate word lines 410.

[0086] Referring to Figures 33 and 34, in the cross-sectional perspective view, the channel layer 211 is disposed on the storage node structure 510. In the top perspective view, the word line 410 is aligned with the storage node structure 510 in the Z direction. The channel layer 211 can be aligned with the storage node structure 510 in the Z direction.

[0087] Referring to Figures 35 and 36, a dielectric layer 121 is formed on dielectric layer 125, covering word line dielectric layer 413 and channel layer 211. The fabrication process is similar to that described in Figure 3, and will not be repeated here. Bit line contacts 313 are formed in dielectric layer 121, with a fabrication process similar to that described in Figures 4 and 5, and will not be repeated here. In the cross-sectional perspective view, bit line contacts 313 are positioned on channel layer 211. In the top perspective view, bit line contacts 313 are aligned with storage node structure 510 or channel layer 211 in the Z direction.

[0088] Referring to Figures 37 and 38, a dielectric layer 129 is formed on the dielectric layer 121 and covers the bit line contact point 313. In some embodiments, the dielectric layer 129 is formed of, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, a low dielectric constant dielectric material, similar materials, or combinations thereof. In some embodiments, the dielectric layer 129 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. It should be noted that, for clarity, the dielectric layer 129 is not shown in the top view.

[0089] Referring to Figures 37 and 38, bit lines 311 are formed in the dielectric layer 129 and at bit line contact points 313. In the top perspective view, a plurality of bit lines 311 are arranged along the Y direction. Each bit line 311 extends along the X direction. In some embodiments, a plurality of bit line trenches (not shown) are formed in the dielectric layer 129. A conductive material (not shown) is deposited to completely fill the bit line trenches. A planarization process, such as chemical mechanical polishing, may be performed until the top surface of the dielectric layer 129 is exposed to remove excess material, provide a substantially flat surface for subsequent process steps, and simultaneously form the plurality of bit lines 311. In some embodiments, the conductive material is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0090] One embodiment of this disclosure provides a semiconductor device including a substrate; a channel layer positioned above the substrate, extending along a first direction perpendicular to the top surface of the substrate, and including an inverted trapezoidal cross-sectional profile; and word lines including a word line dielectric layer that is close to and laterally surrounds the channel layer, and a word line conductive layer that is laterally and partially surrounds the word line dielectric layer, extends along a second direction parallel to the top surface of the substrate, and includes an inverted trapezoidal cross-sectional profile.

[0091] Another embodiment of this disclosure provides a semiconductor device including a substrate; a channel layer positioned above the substrate and extending along a first direction perpendicular to the top surface of the substrate, wherein the width of the top surface of the channel layer is greater than the width of the bottom surface of the channel layer; and word lines including a word line dielectric layer that is close to and laterally surrounds the channel layer, and a word line conductive layer that is laterally and partially surrounds the word line dielectric layer and extends along a second direction parallel to the top surface of the substrate, wherein the width of the top surface of the word line conductive layer is greater than the width of the bottom surface of the word line conductive layer.

[0092] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, including providing a substrate; forming a lower dielectric layer over the substrate; forming an intermediate dielectric layer on the lower dielectric layer; forming a word line trench penetrating the intermediate dielectric layer, exposing the lower dielectric layer, and including an inverted trapezoidal cross-sectional profile; forming a word line conductive layer filling the word line trench; forming an upper dielectric layer on the intermediate dielectric layer; forming a channel opening penetrating the upper dielectric layer, the word line conductive layer, and the lower dielectric layer to expose the substrate; and forming a word line dielectric layer in close contact with the sidewalls of the channel opening; and forming a channel layer filling the channel opening. The word line conductive layer and the word line dielectric layer are configured together to form word lines.

[0093] Due to the design of the semiconductor device disclosed herein, by employing a word line conductive layer 411 and a channel layer 211 with an inverted trapezoidal cross-sectional profile, the process window for forming the channel layer 211 can be increased. Therefore, defects in the manufacture of semiconductor device 1A can be reduced, and the yield of the manufacture of semiconductor device 1A can be improved.

[0094] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0095] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0096] 1A: Semiconductor Device 1B: Semiconductor Devices 1C: Semiconductor Device 1D: Semiconductor Device 1E: Semiconductor Devices 10: Method 111:Substrate 111TS: Top Surface 121: Dielectric layer 121TS: Top Surface 123: Dielectric layer 123BS: Bottom Surface 125: Dielectric layer 125TS: Top Surface 127: Dielectric layer 129: Dielectric layer 131: Dielectric layer 131TS: Top Surface 141: Intermediate Dielectric Layer 141BS: Bottom Surface 141SW: Sidewall 141TS: Top Surface 211: Channel Layer 211BS: Bottom Surface 211SW: Sidewall 211TS: Top Surface 311: Bitline 311TS: Top Surface 311SW: Sidewall 313: Bit line contact point 313TS: Top Surface 313SW: Sidewall 315: Bit line spacers 317: Bit line contact point spacer 410: Word Line 411: Word Line Conductive Layer 411BS: Bottom Surface 411SW: Sidewall 411TS: Top Surface 413: Word line dielectric layer 413TS: Top Surface 413SW: Sidewall 510: Storage Node Structure 511: First electrode layer 513: Intermediate Insulation Layer 515: Second electrode layer 515TS: Top Surface 801: First photomask layer 803: Second photomask layer 805: Third photomask layer 807: Fourth photomask layer 809: First hard mask layer 811: First conductive material 813: First Dielectric Material 815: First insulating material 817: Second conductive material A-A': line B-B': line OP1: Channel opening OP2: Storage node opening P1: Pattern P2: Pattern S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps TR1: Word line groove W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width W7: Width W8: Width W9: Width X: Direction Y: direction Z: Direction

Claims

1. A semiconductor device, comprising: One substrate; A channel layer, positioned above the substrate, extends along a first direction perpendicular to a top surface of the substrate, and includes an inverted trapezoidal cross-sectional profile. And a word line, comprising: a word line dielectric layer, which is close to and laterally surrounds the channel layer; a word line conductive layer, which is laterally and partially surrounds the word line dielectric layer, extends along a second direction parallel to a top surface of the substrate, and includes an inverted trapezoidal cross-sectional profile; and a bit line contact point, which contacts the channel layer and the word line dielectric layer.

2. The semiconductor device as claimed in claim 1 further includes a bit line positioned below the channel layer and electrically coupled to the channel layer.

3. The semiconductor device as claimed in claim 2, wherein the bit line contact is located between the channel layer and the bit line.

4. The semiconductor device as claimed in claim 3, wherein the bit line is positioned in the substrate and extends along a third direction perpendicular to the second direction.

5. The semiconductor device as claimed in claim 3, wherein the bit line is positioned on the substrate and extends along a third direction perpendicular to the second direction.

6. The semiconductor device as claimed in claim 3 further includes a storage node structure positioned on the channel layer and electrically connected to the channel layer.

7. The semiconductor device as claimed in claim 6, wherein the storage node structure includes: A first electrode layer is positioned on the channel layer and electrically connected to the channel layer; A second electrode layer is positioned on the first electrode layer; And an intermediate insulating layer is positioned between the first electrode layer and the second electrode layer to electrically isolate the first electrode layer and the second electrode layer.

8. The semiconductor device as claimed in claim 1 further includes a bit line positioned on the channel layer and electrically coupled to the channel layer.

9. The semiconductor device as claimed in claim 8, wherein the bit line contact is located between the bit line and the channel layer.

10. The semiconductor device as claimed in claim 9 further includes a storage node structure positioned below the channel layer and electrically connected to the channel layer.

11. The semiconductor device as claimed in claim 1, wherein the channel layer comprises doped polysilicon, doped polygermanium, or doped polysilicon-germanium.

12. The semiconductor device as claimed in claim 1, wherein the word line dielectric layer comprises a high dielectric constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

13. The semiconductor device as claimed in claim 1, wherein the word line conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminum compound, or a combination thereof.

14. A semiconductor device, comprising: One substrate; A channel layer, positioned above the substrate and extending along a first direction perpendicular to a top surface of the substrate, wherein a width of a top surface of the channel layer is greater than a width of a bottom surface of the channel layer; a word line, comprising: a word line dielectric layer, closely attached to and laterally surrounding the channel layer; and a word line conductive layer, laterally and partially surrounding the word line dielectric layer and extending along a second direction parallel to the top surface of the substrate, wherein a width of a top surface of the word line conductive layer is greater than a width of a bottom surface of the word line conductive layer; and a bit line contact point, contacting the channel layer and the word line dielectric layer.

15. The semiconductor device as claimed in claim 14 further includes a bit line positioned below the channel layer and electrically coupled to the channel layer.

16. The semiconductor device as claimed in claim 15, wherein the bit line contact is located between the channel layer and the bit line.

17. The semiconductor device as claimed in claim 16, wherein the bit line is positioned in the substrate and extends along a third direction perpendicular to the second direction.

18. The semiconductor device as claimed in claim 16, wherein the bit line is positioned on the substrate and extends along a third direction perpendicular to the second direction.

19. The semiconductor device as claimed in claim 16 further includes a storage node structure positioned on the channel layer and electrically connected to the channel layer.

20. The semiconductor device as claimed in claim 19, wherein the storage node structure includes: A first electrode layer is positioned on the channel layer and electrically connected to the channel layer; A second electrode layer is positioned on the first electrode layer; And an intermediate insulating layer is positioned between the first electrode layer and the second electrode layer to electrically insulate the first electrode layer and the second electrode layer.

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