Electronic device and operation method thereof

Abstract

An electronic device and its operating method are proposed. The electronic device includes a memory, a management and control circuit, and an input / output expander. The memory stores a power-on code and a power control code. The management and control circuit reads the power-on code and the power control code from the memory. The management and control circuit performs a power-on action based on the power-on code. The input / output expander receives the power control code from the management and control circuit. The input / output expander includes a power controller, which generates multiple power control signals based on the power control code.

Description

Technical Field

[0001] This invention relates to an electronic device and its operating method, and more particularly to an electronic device and its operating method that can reduce hardware costs. Prior Technology

[0002] In conventional electronic devices, the board management controller (BMC) communicates with the field-effect programmable gate array (FET) via a serial general-purpose input / output (SGPIO) interface. The FET can generate power control signals for the peripheral circuits of the electronic device. However, in current applications, the electronic device requires separate memory modules corresponding to the BMC and the FET. These two memory modules store the power-on code for the BMC and the power control code for the FET, respectively. In other words, in conventional electronic devices, a relatively large number of memory modules are required to effectively operate the BMC and the FET. Furthermore, the BMC and the FET also require separate memory control circuits, increasing hardware costs. Summary of the Invention

[0003] This invention provides an electronic device and its operating method, which can reduce the need for memory and reduce the cost of the electronic device.

[0004] The electronic device of the present invention includes a memory, a management control circuit, and an input / output expander. The memory stores a power-on code and a power control code. The management control circuit is coupled to the memory and reads the power-on code and power control code from the memory. The management control circuit performs a power-on operation based on the power-on code. The input / output expander is coupled to the management control circuit and receives the power control code from the management control circuit. The input / output expander includes a power controller that generates multiple power control signals based on the power control code.

[0005] The operation method of the electronic device of the present invention includes: storing a power-on code and a power control code in a memory; reading the power-on code and the power control code from the memory by a management control circuit; performing a power-on operation according to the power-on code by the management control circuit; and receiving the power control code from the power input / output expander by the management control circuit, and generating a plurality of power control signals from the power controller in the power input / output expander according to the power control code.

[0006] Based on the above, in the electronic device of the present invention, the power-on code of the management control circuit and the power control code required by the power controller in the input / output expander can be stored in the same memory. The power-on code and the power control code are obtained by the management control circuit reading the memory. The management control circuit can perform a power-on operation according to the obtained power-on code and transmit the obtained power control code to the input / output expander. Furthermore, the power controller in the input / output expander can generate power control signals for multiple peripheral circuits according to the power control code. Simple Explanation of the Diagram

[0007] Figure 1 illustrates a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 2 illustrates a schematic diagram of an electronic device according to another embodiment of the present invention. Figure 3 illustrates a flowchart of the operation mode of the electronic device according to an embodiment of the present invention. Figure 4 illustrates a schematic diagram of an electronic device according to another embodiment of the present invention. Figures 5A and 5B respectively illustrate the operation flowchart of the security check circuit of the embodiment of the present invention. Figure 6 illustrates the operation flowchart of the electronic device according to an embodiment of the present invention. Implementation

[0008] Please refer to Figure 1, which illustrates a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device 100 includes a memory 110, a management control circuit 120, and an input / output expander 130. The memory 110 stores a power-on code BTC and a power control code PMC. The management control circuit 120 is coupled to the memory 110. The management control circuit 120 reads the power-on code BTC and the power control code PMC from the memory 110. The management control circuit 120 can perform a power-on operation based on the power-on code BTC. Furthermore, the management control circuit 120 can transmit the power control code PMC to the input / output expander 130.

[0009] In this embodiment, the input / output expander 130 includes a power controller 131. The power controller 131 can receive the power control code PMC transmitted by the management control circuit 120, and generate multiple power control signals PC1~PCN according to the power control code PMC. Among them, the power control signals PC1~PCN can each correspond to multiple peripheral circuits, and are used to control the timing sequence of the power supply voltage provided by the electronic device 100 to the corresponding peripheral circuits.

[0010] In detail, during the power-on procedure of the electronic device 100, after the electronic device 100 performs a power-on operation, the management control circuit 120 can read the power-on code BTC and the power control code PMC from the memory 110. Then, the management control circuit 120 can start the power-on application and cause its central processing unit to perform the power-on operation based on the power-on code BTC. Furthermore, the management control circuit 120 can transmit the power control code PMC to the power controller 131 in the input / output expander 130. The power controller 131 can then determine the power-on sequence of each peripheral circuit based on the power control code PMC and generate power control signals PC1~PCN accordingly.

[0011] In this embodiment, the management control circuit 120 can be a Baseboard Management Controller (BMC) circuit. The memory 110 can be any type of memory, such as flash memory. The boot code BTC and power control code PMC can be pre-stored in a preset address of the memory 110. The management control circuit 120 can obtain the boot code BTC and power control code PMC by reading the preset address of the memory 110 during the boot process.

[0012] Notably, in this embodiment, the power-on code BTC and the power control code PMC are stored in the same memory 110. The electronic device 100 does not require an additional input / output expander 130 to store the power control code PMC in a separate memory. Besides reducing memory usage, this also eliminates the need for control circuitry related to memory access operations in the input / output expander 130. This simplifies the circuit design complexity of the input / output expander 130 and effectively reduces the cost of the electronic device 100, enhancing the product's competitiveness.

[0013] Please refer to Figure 2 below, which illustrates a schematic diagram of an electronic device according to another embodiment of the present invention. The electronic device 200 includes a memory 210, a management and control circuit 220, and an input / output expander 230. The memory 210 is coupled to the management and control circuit 220. In this embodiment, the management and control circuit 220 includes an interface circuit 221, a central processing unit (CPU) 222, a controller 223, and signal format conversion circuits 224 and 225. The signal format conversion circuits 224 and 225 are coupled to the interface circuit 221 and are respectively coupled to the CPU 222 and the controller 223 via buses BUS11 and BUS12. The signal format conversion circuits 224 and 225 are used for format conversion of transmitted and received data between the CPU 222, the controller 223, and the signal format conversion circuits 224 and 225. For example, in this embodiment, interface circuit 221 can be a Low Voltage Differential Signal (LVDS) Tunneling Protocol & Interface (LTPI) circuit and used to transmit data in the form of low voltage differential signals. Bus BUS11 can be used, for example, to transmit data in the format of Advanced High-performance Bus (AHB) signals, while bus BUS12 can be used, for example, to transmit data in the format of Meter Bus (M-BUS) signals.

[0014] In terms of implementation details, the signal format conversion circuit 224 can receive received data from the interface circuit 221, convert this received data from a low-voltage differential signal format to an advanced high-efficiency bus signal format, and transmit the received data in the advanced high-efficiency bus signal format to the central processing unit (CPU) 222 through bus BUS 11. Similarly, the signal format conversion circuit 225 can also receive received data from the interface circuit 221, convert this received data from a low-voltage differential signal format to an instrument bus signal format, and transmit the received data in the instrument bus signal format to the controller 223 through bus BUS 12.

[0015] Furthermore, signal format conversion circuits 224 and 225 can receive different transmission data via buses BUS11 and BUS12, respectively, through the central processing unit (CPU) and controller 223. Signal format conversion circuits 224 and 225 can convert the received transmission data into low-voltage differential signal format, and transmit the low-voltage differential signal format transmission data to interface circuit 221, which then transmits the low-voltage differential signal format transmission data out. Here, controller 223 can be a memory controller.

[0016] It is worth noting that in this embodiment, the number of signal format conversion circuits 224 and 225 in the management control circuit 220 can be one or more (more than two). Designers can adjust the number of signal format conversion circuits in the management control circuit according to actual needs, without any particular limitation. The illustration in Figure 2 is merely an example for illustrative purposes and is not intended to limit the scope of the invention.

[0017] On the other hand, the input / output expander 230 includes a power controller 231, an interface circuit 232, signal format conversion circuits 233 and 234, and multiple peripheral circuit controllers PD1 to PD6. Interface circuit 232, like interface circuit 221, is an LPTI format interface circuit used to transmit data as low-voltage differential signals. Signal format conversion circuits 233 and 234 are coupled to interface circuit 232. Signal format conversion circuit 233 is coupled to power controller 231 and peripheral circuit controllers PD1 to PD6 via bus 21; signal format conversion circuit 234 is coupled to peripheral circuit controllers PD4 and PD5 via bus 22.

[0018] The input / output expander 230 is coupled to the interface circuit 221 of the management and control circuit 220 through the interface circuit 232. In this way, the input / output expander 230 and the management and control circuit 220 can communicate with each other through the interface circuits 232 and 221.

[0019] Signal format conversion circuit 233 is used to convert the received data obtained by interface circuit 232 from interface circuit 221 from low-voltage differential signal format to advanced high-efficiency bus signal format, and then transmit the received data in advanced high-efficiency bus signal format to power controller 231 and at least one of the multiple peripheral circuit controllers PD1 to PD6 through bus BUS 21. Signal format conversion circuit 234 is also used to convert the received data obtained by interface circuit 232 from interface circuit 221 from low-voltage differential signal format to instrument bus signal format, and transmit the received data in instrument bus signal format to at least one of peripheral circuit controllers PD4 and PD5 through bus BUS 22.

[0020] Furthermore, the signal format conversion circuit 233 can receive and transmit data from at least one of the power controller 231 and peripheral circuit controllers PD1 to PD6, while the signal format conversion circuit 234 can receive and transmit data from at least one of the peripheral circuit controllers PD4 and PD5. The signal format conversion circuits 233 and 234 can respectively convert the received transmitted data into low-voltage differential signal format, and transmit the low-voltage differential signal format transmitted data to the interface circuit 232, which then transmits the low-voltage differential signal format transmitted data out.

[0021] Regarding the operational details of the electronic device 200, the management control circuit 220 can read the power-on code BTC and the power control code PMC from the memory 210. The central processing unit (CPU) 222 in the management control circuit 220 can perform a power-on operation based on the power-on code BTC. Further, the management control circuit 220 can convert the power control code PMC into a low-voltage differential signal format via one of the signal format conversion circuits 224 and 225, and transmit the power control code PMC through the interface circuit 221. On the other hand, the input / output expander 230 can receive the power control code PMC in low-voltage differential signal format via the interface circuit 232. Next, via the signal format conversion circuit 223, the power control code PMC in low-voltage differential signal format can be converted into an advanced high-efficiency bus signal format, and then transmitted to the power controller 231 via the bus BUS 21. In this way, the power controller 231 can generate multiple power control signals PC1~PCN according to the received power control code PMC.

[0022] Incidentally, in this embodiment, the peripheral circuit controllers PD1 to PD6 correspond to multiple peripheral circuits and are used to generate multiple control signals to perform control actions on the corresponding peripheral circuits. In one embodiment of the present invention, the multiple peripheral circuits corresponding to the peripheral circuit controllers PD1 to PD6 are, for example, analog-to-digital converter circuits, pulse modulation signal generation circuits, speed detection circuits, improved integrated bus circuits (I3C), integrated bus circuits (I2C), and Joint Test Action Group (JTAG) signal generation circuits, etc.

[0023] Of course, the types and quantities of peripheral circuits mentioned above are merely illustrative examples and should not be used to limit the scope of this invention. Those skilled in the art can configure the required peripheral circuits and adjust the number of peripheral circuit controllers accordingly based on actual needs, without any fixed limitations.

[0024] It is worth noting that in this embodiment, the signal format conversion circuits 224, 225, 233, and 234 can be digital circuits and can be implemented using hardware architectures of signal format converters well known to those skilled in the art, without any limitations. Furthermore, the power controller 231 can also be implemented using digital circuits; for example, the power controller 231 can be implemented using a field-programmable gate array (FPGA). Alternatively, in other embodiments of the present invention, the power controller 231 can also be implemented using a microcontroller (MCU), which is generally well known to those skilled in the art, without any limitations.

[0025] In this embodiment of the invention, the electronic device 200 does not require an additional corresponding input / output expander 230 to set up memory to provide power control codes (PMC), thus achieving a memory-less design concept. Furthermore, when the power controller 231 is implemented using a field-effect programmable gate array (FETA), the input / output expander 230 can achieve a memory-less and CPU-less design concept.

[0026] Please refer to Figures 2 and 3 simultaneously, where Figure 3 illustrates a flowchart of the operation of the electronic device according to an embodiment of the present invention. In step S310, the electronic device 200 performs a power-on operation. In step S320, the management control circuit 220 in the electronic device 200 reads the memory 210 to obtain a power-on code, thereby starting the power-on application and executing step S350. In step S330, the management control circuit 220 reads the memory 210 to obtain a power control code. In step S350, the management control circuit 220 performs a power-on operation based on the power-on code. In step S340, the management control circuit 220 transmits the obtained power control code to the power controller 231 in the input / output expander 230. In step S360, the power controller 231 executes the power control code PMC and thereby generates power control signals PC1~PCN.

[0027] In step S370, after the power-on operation of the management control circuit 220 and the generation of power control signals PC1~PCN by the power controller 231 are completed, the management control circuit 220 and the power controller 231 can continuously communicate through the interface circuits 221 and 232 between the management control circuit 220 and the input / output expander 230.

[0028] Please refer to Figure 4, which illustrates a schematic diagram of an electronic device according to another embodiment of the present invention. The electronic device 400 includes a memory 410, a management and control circuit 420, and an input / output expander 430. The input / output expander 430 includes a power controller 431 and a plurality of peripheral circuit controllers 432.

[0029] In this embodiment of the invention, the implementation details of the memory 410 and the input / output expander 430 are the same as those in the foregoing embodiments, and will not be repeated here. Unlike the foregoing embodiments, the management control circuit 420 includes a security check circuit 421. The security check circuit 421 is coupled to the path where the management control circuit 420 receives the power-on code BTC and the power control code PMC. The security check circuit 421 performs security verification actions on the power-on code BTC and the power control code PMC to prevent malicious individuals from executing malicious power-on code BTC and / or power control code PMC in the memory 410 to disrupt the normal operation of the electronic device 400.

[0030] For details on the operation of the security check circuit 421, please refer to Figures 4, 5A, and 5B, where Figures 5A and 5B respectively illustrate the operation flowchart of the security check circuit of this embodiment. Referring first to Figure 5A, in step S511, the security check circuit 421 can retrieve image information from an external storage device (e.g., memory 410). Then, in step S512, the security check circuit 421 can perform digital signature verification based on the retrieved image information. In step S513, the security check circuit 421 can determine whether the digital signature authentication is successful, and if the verification is successful, proceed to step S514; if the verification fails, proceed to step S515.

[0031] In step S514, when the digital signature verification is successful, the electronic device 400 enables the central processing unit (CPU) in the management control circuit 420 to power on based on the read power-on code BTC. Conversely, in step S515, when the digital signature verification fails, the management control circuit 420 returns to its original state.

[0032] Next, referring to Figure 5B, in step S521, the security check circuit 421 can receive the power control code PMC, and in step S522, it can perform a signature verification action on the power control code PMC, or perform a decryption algorithm on the power control code PMC, thereby performing a security verification action on the power control code PMC. In step S523, the security check circuit 421 can output the verification result generated in step S522.

[0033] In this embodiment of the invention, when the verification result indicates that the power control code PMC is safe, the power controller 431 can generate power control signals PC1~PCN according to the power control code PMC; conversely, when the verification result indicates that the power control code PMC is safe, the management control circuit 420 can mask the power control code PMC, thereby preventing the power controller 431 from executing an incorrect code and causing malfunction.

[0034] Please refer to Figure 6, which illustrates an operation flowchart of an electronic device according to an embodiment of the present invention. In step S610, the memory stores a power-on code and a power control code. In step S620, the management control circuit reads the power-on code and the power control code from the memory. In step S630, the management control circuit performs a power-on operation based on the power-on code. And, in step S640, the input / output expander receives the power control code from the management control circuit, and the power controller in the input / output expander generates multiple power control signals based on the power control code.

[0035] The implementation details of the above steps have been described in detail in the aforementioned embodiments, and will not be repeated here.

[0036] In summary, the electronic device of the present invention provides power control codes to the input / output expanders via a management control circuit, enabling the expanders to generate power control signals based on the power control codes. This eliminates the need for memory corresponding to the input / output expanders in the electronic device, effectively reducing memory usage and circuit complexity, thereby lowering design costs and enhancing product competitiveness.

[0037] 100, 200, 400: Electronic devices 110, 210, 410: Memory 120, 220, 420: Management and control circuits 130, 230, 430: Input / output expanders 131, 231, 431: Power controller 221: Interface Circuit 222: Central Processing Unit (CPU) 223: Controller 224, 225, 233, 234: Signal format conversion circuits 231: Power Controller 232: Interface Circuit BTC: Activation Code Buses 11-22: Buses PC1~PCN: Power control signals PD1~PD6, 432: Peripheral Circuit Controller PMC: Power Control Code S310~S370, S511~S523, S610~S640: Steps

Claims

1. An electronic device comprising: A memory module for storing a boot code and a power control code; A management control circuit is coupled to the memory, which reads the boot code and the power control code from the memory, and the management control circuit performs a boot action according to the boot code; An input / output expander is coupled to the management control circuit, which receives the power control code. The input / output expander includes a power controller that generates multiple power control signals based on the power control code. The management control circuit includes a security check circuit coupled to the path through which the management control circuit receives the power-on code and the power control code, for performing security verification actions on the power-on code and the power control code.

2. The electronic device as claimed in claim 1, wherein the management control circuit includes a first interface circuit, and the input / output extender further includes a second interface circuit, and the management control circuit performs data transmission operations between the first interface circuit and the second interface circuit of the input / output extender.

3. The electronic device as claimed in claim 2, wherein the first interface circuit and the second interface circuit are configured to transmit and receive data in low-voltage differential signal format.

4. The electronic device as claimed in claim 2, wherein the management control circuitry includes: At least one signal format conversion circuit is coupled to the first interface circuit for performing format conversion operations for sending and receiving data.

5. The electronic device of claim 4, wherein the at least one signal format conversion circuit is used to convert a transmitted data into a low-voltage differential signal format and to convert a received data into an advanced high-efficiency bus signal format or an instrument bus signal format.

6. The electronic device as claimed in claim 2, wherein the input / output expander comprises: At least one signal format conversion circuit is coupled to the second interface circuit for performing format conversion operations for sending and receiving data.

7. The electronic device of claim 6, wherein the power controller is coupled to the at least one signal format conversion circuit via a bus, receives the power control code via the bus and the at least one signal format conversion circuit, and generates the power control signals based on the power control code.

8. The electronic device as claimed in claim 6, wherein the input / output expander further comprises: Multiple peripheral circuit controllers are coupled to the at least one signal format conversion circuit, and perform data transmission operations with the management and control circuit through the at least one signal format conversion circuit, the second interface circuit, and the first interface circuit.

9. The electronic device of claim 1, wherein the security check circuit performs a signature verification operation on the memory to determine whether the management control circuit performs the power-on operation based on the power-on code.

10. The electronic device of claim 1, wherein the security check circuit performs a signature verification action or a decryption calculation on the power control code to confirm the validity of the power control code.

11. The electronic device of claim 1, wherein after a power-on operation, the management control circuit reads the power-on code from the memory and starts a power-on application to perform the power-on operation; the management control circuit reads the power control code from the memory and transmits the power control code to the power controller of the input / output expander.

12. The electronic device as claimed in claim 1, wherein the management control circuit is a substrate management control circuit.

13. A method of operating an electronic device, comprising: Store a boot code and a power control code in a memory; A management control circuit reads the power-on code and the power control code from the memory. The management control circuit performs a power-on action based on the power-on code; an input / output expander receives the power control code from the management control circuit, and a power controller in the input / output expander generates multiple power control signals based on the power control code; and a security check circuit is set up to perform security verification actions for the power-on code and the power control code.

14. The method of operating the electronic device as described in claim 13 further includes: The first interface circuit of the management control circuit is coupled to the second interface circuit of the input / output expander to perform data transmission.

15. A method of operating the electronic device as claimed in claim 14, wherein the first interface circuit and the second interface circuit are used to transmit and receive data in a low-voltage differential signal format.

16. The method of operating the electronic device as described in claim 13, further comprising: The security check circuit performs a signature verification action on the power-on code to determine whether the management control circuit should perform the power-on action based on the power-on code.

17. The method of operating the electronic device as described in claim 13, further comprising: The security check circuit performs a signature verification action or decryption calculation on the power control code to confirm its validity.

18. The method of operating the electronic device as described in claim 13, further comprising: After power-on, the management control circuit reads the boot code from the memory and starts a boot application to perform the boot action. And the power controller that enables the management control circuit to read the power control code from the memory and transmit the power control code to the input / output expander.

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