Electronic device

Abstract

An electronic device includes a first substrate, a plurality of data lines, a plurality of scan lines, a first pixel, and a second pixel. Each of the first and second pixels, which are adjacent in a first direction, includes a first sub-pixel and a second sub-pixel arranged in a second direction. The first sub-pixel of the first pixel is electrically connected to the i-th scan line and the j-th data line. The second sub-pixel of the first pixel is electrically connected to the i-th scan line and the (j+1)-th data line. The first sub-pixel of the second pixel is electrically connected to the (i+1)-th scan line and the (j+2)-th data line. The second sub-pixel of the second pixel is electrically connected to the (i+1)-th scan line and the (j+1)-th data line. The j-th data line has opposite polarities to the (j+1)-th data line, and the j-th data line has opposite polarities to the (j+2)-th data line.

Description

Technical Field

[0001] This invention relates to an electronic device. Prior Technology

[0002] In existing electronic devices, poor decoupling of data signals can lead to capacitive coupling to the common electrode layer (e.g., Vcom), causing crosstalk in the horizontal direction and affecting display quality. Summary of the Invention

[0003] The present invention provides an electronic device that helps to improve crosstalk in the horizontal direction.

[0004] In one embodiment of the present invention, the electronic device includes a first substrate, a plurality of data lines, a plurality of scan lines, a first pixel, and a second pixel. The plurality of data lines are disposed on the first substrate and arranged along a first direction. The plurality of data lines include a j-th data line, a (j+1)-th data line, and a (j+2)-th data line arranged adjacent to each other in the first direction, where j is a positive integer. The plurality of scan lines are disposed on the first substrate and arranged along a second direction. The plurality of scan lines include an i-th scan line, a (i+1)-th scan line, and a (i+2)-th scan line arranged adjacent to each other in the second direction, where i is a positive integer. The first pixel and the second pixel are adjacent in the first direction. Each of the first pixel and the second pixel includes a first sub-pixel and a second sub-pixel arranged in the second direction. The first sub-pixel of the first pixel is electrically connected to the i-th scan line and the j-th data line among the plurality of data lines. The second sub-pixel of the first pixel is electrically connected to the i-th scan line and the (j+1)-th data line among the plurality of data lines. The first sub-pixel of the second pixel is electrically connected to the (i+1)th scan line and the (j+2)th data line. The second sub-pixel of the second pixel is electrically connected to the (i+1)th scan line and the (j+1)th data line. The j-th data line has opposite polarities to the (j+1)-th data line, and the j-th data line has opposite polarities to the (j+2)-th data line.

[0005] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0006] Figures 1 and 2 are respectively a partial simplified circuit diagram and a partial top view of an electronic device according to some embodiments of the present disclosure. Figures 3A and 3B are schematic cross-sectional views corresponding to sections I-I' and II-II' in Figure 2, respectively. Figure 4 is a schematic diagram of a partial image displayed by an electronic device. Figure 5 is a timing diagram of the signals of multiple scan lines and multiple data lines when an electronic device displays the image shown in Figure 4. Figure 6 is a timing diagram showing the polarity of multiple data lines and a common electrode when an electronic device displays the image shown in Figure 4. Figures 7 and 8 are respectively a partial simplified circuit diagram and a partial top view of an electronic device according to some other embodiments of the present disclosure. Figures 9 and 10 are respectively a partial simplified circuit diagram and a partial top view of an electronic device according to some other embodiments of the present disclosure. Figure 11 is a schematic cross-sectional view corresponding to section line II-II' in Figure 10. Implementation

[0007] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0008] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names. In the following specification and claims, terms such as "containing" and "comprising" are open-ended and should therefore be interpreted as "containing but not limited to...".

[0009] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, the various figures illustrate general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of various films, regions, and / or structures may be reduced or enlarged.

[0010] In this disclosure, the description of one structure (or layer, element, substrate) being located on / above another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate spacer) between the two structures, with the lower surface of one structure adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single or multiple solid or non-solid structure, without limitation. In this disclosure, when a structure is placed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0011] The terms “approximately,” “substantially,” or “roughly” are generally interpreted as being within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Furthermore, the terms “range from the first value to the second value” or “range between the first value and the second value” indicate that the range includes the first value, the second value, and other values ​​in between.

[0012] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify elements do not inherently imply or represent any prior ordinal number for that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.

[0013] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components in two circuits, but not limited to these.

[0014] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), while the thickness or width can be measured from cross-sectional images obtained from an electron microscope, but these methods are not limited to this. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. Additionally, the terms "given range is from the first value to the second value," "given range falls within the range of the first value to the second value," or "given range is between the first value and the second value" indicate that the given range includes the first value, the second value, and other values ​​in between. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 degrees and 10 degrees.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0016] In this disclosure, the electronic device may include, but is not limited to, a light-emitting device, a display device, a backlight device, an antenna device, a packaging device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-emissive display device or a self-emissive display device. The display device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, quantum dot (QD), other suitable display media, or combinations thereof. The antenna device may include, for example, a reconfigurable intelligent surface (RIS), a frequency selective surface (FSS), a radio frequency filter, a polarizer, a resonator, or an antenna. The antenna may be a liquid crystal type antenna or a varactor diode antenna. The sensing device may be a sensing device for capacitance, light, heat, or ultrasound, but is not limited to these. In this disclosure, the electronic device may include electronic components, which may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes (LEDs), varactor diodes (VADs), or photodiodes. LEDs may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto. The packaging device may be suitable for wafer-level packaging (WLP) technology or panel-level packaging (PLP) technology, such as a chip-first or chip-last packaging device. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices (e.g., augmented reality or virtual reality), in-vehicle devices (e.g., car windshields), or splicing devices.

[0017] In the top view of this disclosure, some components and / or films are omitted to clearly show the relative arrangement of specific components and / or films. The omitted components and / or films can be referred to in the cross-sectional view and corresponding description. Furthermore, Figures 3A and 11 omit the films on the pixel electrodes; the films on the pixel electrodes can be referred to in Figure 3B and corresponding description. It should be understood that the features of several different embodiments described below can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0018] Figures 1 and 2 are a partial simplified circuit diagram and a partial top view of an electronic device according to some embodiments of the present disclosure, respectively. Figures 3A and 3B are cross-sectional views corresponding to sections I-I' and II-II' in Figure 2, respectively. Please refer to Figures 1, 2, and 3B first. The electronic device 1 may include a first substrate 10, multiple data lines DL, multiple scan lines SL, a first pixel PX1, and a second pixel PX2. The multiple data lines DL are disposed on the first substrate 10 and arranged along a first direction D1. As shown in Figure 1, the multiple data lines DL include the j-th data line DL(j), the (j+1)-th data line DL(j+1), and the (j+2)-th data line DL(j+2), which are adjacent and sequentially arranged in the first direction D1, where j is a positive integer. The multiple scan lines SL are disposed on the first substrate 10 and arranged along a second direction D2. Multiple scan lines SL include the i-th scan line SL(i), the (i+1)-th scan line SL(i+1), and the (i+2)-th scan line SL(i+2) arranged adjacently and sequentially in the second direction D2, where i is a positive integer. The first pixel PX1 and the second pixel PX2 are adjacent in the first direction D1. Each of the first pixel PX1 and the second pixel PX2 includes a first sub-pixel SP1 and a second sub-pixel SP2 arranged in the second direction D2. The first sub-pixel SP1 of the first pixel PX1 is electrically connected to the i-th scan line SL(i) and the j-th data line DL(j) of the multiple data lines DL. The second sub-pixel SP2 of the first pixel PX1 is electrically connected to the i-th scan line SL(i) and the (j+1)-th data line DL(j+1) of the multiple data lines DL. The first sub-pixel SP1 of the second pixel PX2 is electrically connected to the (i+1)th scan line SL(i+1) and the (j+2)th data line DL(j+2) of the multiple data lines DL. The second sub-pixel SP2 of the second pixel PX2 is electrically connected to the (i+1)th scan line SL(i+1) and the (j+1)th data line DL(j+1). The j-th data line DL(j) has opposite polarities to the (j+1)th data line DL(j+1), and the j-th data line DL(j) has opposite polarities to the (j+2)th data line DL(j+2).

[0019] In detail, the first substrate 10 can be a rigid substrate or a flexible substrate. The material of the first substrate 10 includes, but is not limited to, glass, quartz, ceramic, sapphire, or plastic. Plastics may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or combinations of the foregoing materials, but are not limited to these. Furthermore, the light transmittance of the first substrate 10 is not limited; that is, the first substrate 10 can be a transparent substrate, a semi-transparent substrate, or an opaque substrate.

[0020] Multiple data lines DL can belong to the same conductive layer, such as conductive layer 14 in Figure 3A. The material of the conductive layer to which the multiple data lines DL belong can be metal or metal stack, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto. The multiple data lines DL are spaced apart along the first direction D1. Figure 1 schematically illustrates seven data lines DL arranged adjacent to each other along the first direction D1 in sequence: the (j-1)th data line DL(j-1), the jth data line DL(j), the (j+1)th data line DL(j+1), the (j+2)th data line DL(j+2), the (j+3)th data line DL(j+3), the (j+4)th data line DL(j+4), and the (j+5)th data line DL(j+5), and other data lines are omitted from the drawing, but the number of data lines DL is not limited thereto.

[0021] In some embodiments, multiple data lines DL can be divided into multiple groups, each group comprising four consecutively arranged data lines DL, with the polarities of the four consecutive data lines DL sequentially being positive, negative, negative, and positive. In other words, the polarities of data lines DL 1, 4, 5, 8, 9, and 12 are positive, and the polarities of data lines DL 2, 3, 6, 7, 10, and 11 are negative. In Figure 1, (+) indicates that the polarity of a data line DL is positive, and (-) indicates that the polarity of a data line DL is negative. In Figure 1, j is, for example, 5. In other words, the seven data lines DL sequentially arranged along the first direction D1 in Figure 1 are, for example, the 4th to the 10th data lines, with polarities sequentially being positive, positive, negative, negative, positive, positive, and negative, but this disclosure is not limited to this. For ease of explanation, the following instructions use j=5 as an example, and illustrate the connection relationship between four data lines (DL(j), DL(j+1), DL(j+2), DL(j+3)) and related sub-pixels. These four data lines constitute one group. Electronic devices may include multiple overlapping groups of data lines, which will not be elaborated upon here.

[0022] Multiple scan lines SL can belong to the same conductive layer, such as conductive layer 11 in Figure 3A. Furthermore, the conductive layer to which the multiple scan lines SL belong can be different from the conductive layer to which the multiple data lines DL belong. Specifically, as shown in Figure 3A, the conductive layers to which the multiple scan lines SL belong and the conductive layers to which the multiple data lines DL belong can be stacked on a third-direction D3, and at least one insulating layer (insulating layer 12 as shown in Figure 3A) can be provided between the conductive layer 14 to which the multiple data lines DL belong and the conductive layer 11 to which the multiple scan lines SL belong, so that the multiple data lines DL and the multiple scan lines SL are electrically insulated from each other.

[0023] The material of the conductive layer to which the multiple scan lines SL belong may include metal or metal stacks, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto. The multiple scan lines SL are spaced apart along the second direction D2. Figure 1 schematically illustrates six scan lines SL arranged adjacent to each other along the second direction D2 in sequence: the i-th scan line SL(i), the (i+1)-th scan line SL(i+1), the (i+2)-th scan line SL(i+2), the (i+3)-th scan line SL(i+3), the (i+4)-th scan line SL(i+4), and the (i+5)-th scan line SL(i+5), with other scan lines omitted, but the number of scan lines SL is not limited thereto.

[0024] The arrangement direction of multiple data lines DL (first direction D1) intersects with the arrangement direction of multiple scan lines SL (second direction D2), so that the multiple data lines DL and multiple scan lines SL are staggered. In some embodiments, as shown in FIG1, the first direction D1 and the second direction D2 may be perpendicular to each other.

[0025] Multiple pixels PX can be arranged in an array along a first direction D1 and a second direction D2. Each of the multiple pixels PX can include sub-pixels of multiple colors to provide a color image. As shown in Figure 1, each of the multiple pixels PX can include a first sub-pixel SP1 and a second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 can be sub-pixels of different colors (described later). The color of the sub-pixels can be provided by the color of a color filter layer. Specifically, the color filter layer can include a first color unit, a second color unit, and a third color unit with different colors.

[0026] In some embodiments, as shown in FIG1, each of the plurality of pixels PX (including each of the first pixel PX1 and the second pixel PX2) may further include a third sub-pixel SP3, and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 may be arranged in the second direction D2, wherein the third sub-pixel SP3 of the first pixel PX1 is electrically connected to the (i+2)th scan line SL(i+2) and the jth data line DL(j) of the plurality of scan lines SL, and the third sub-pixel SP3 of the second pixel PX2 is electrically connected to the (i+3)th scan line SL(i+3) and the (j+2)th data line DL(j+2) of the plurality of scan lines SL. In the simplified circuit diagrams disclosed herein (e.g., Figures 1, 7, and 9), for ease of identification, solid dots are used to indicate electrical connections between pixel PX and adjacent conductors (e.g., scan lines SL or data lines DL). Conversely, conductor intersections not marked with solid dots indicate windings without actual electrical connections. In some embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be red, green, and blue sub-pixels, respectively, but are not limited thereto.

[0027] In some embodiments, as shown in FIG1, a third pixel PX3 among a plurality of pixels PX is adjacent to a second pixel PX2 in a first direction D1. The third pixel PX3 may include a first sub-pixel SP1 and a second sub-pixel SP2 arranged in a second direction D2. The first sub-pixel SP1 of the third pixel PX3 is electrically connected to the i-th scan line SL(i) and the (j+2)-th data line DL(j+2). The second sub-pixel SP2 of the third pixel PX3 is electrically connected to the i-th scan line SL(i) and the (j+3)-th data line DL(j+3) among the plurality of data lines DL. The j-th data line DL(j) and the (j+3)-th data line DL(j+3) may have the same polarity. For example, as mentioned above, the j-th data line DL(j) and the (j+3)-th data line DL(j+3) may be the 5th and 8th data lines DL, respectively, and have positive polarity.

[0028] In some embodiments, as shown in FIG1, the third pixel PX3 may also include a third sub-pixel SP3, and the third sub-pixel SP3 of the third pixel PX3 may be electrically connected to the (i+2)th scan line SL (i+2) and the (j+2)th data line DL (j+2). In detail, the connection relationship between the multiple sub-pixels, multiple data lines DL and multiple scan lines SL in the electronic device 1 can be referred to the connection relationship between the first sub-pixel SP1 of the first pixel PX1, the second sub-pixel SP2 of the first pixel PX1, the first sub-pixel SP1 of the second pixel, and the second sub-pixel SP2 of the second pixel and the adjacent data lines DL and adjacent scan lines SL, which will not be described again here.

[0029] In some embodiments, as shown in FIG1, in the second direction D2, the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel PX1 can be disposed between the i-th scan line SL(i) and the (i+1)-th scan line SL(i+1), and a portion of the i-th scan line SL(i) and a portion of the (i+1)-th scan line SL(i+1) can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1. Specifically, two adjacent horizontal rows of sub-pixels arranged in the second direction D2 can be located between two adjacent scan lines SL. Taking FIG1 as an example, the first horizontal row of sub-pixels H1 formed by multiple first sub-pixels SP1 arranged along the first direction D1 and the second horizontal row of sub-pixels H2 formed by multiple second sub-pixels SP2 arranged along the first direction D1 are located between the i-th scan line SL(i) and the (i+1)-th scan line SL(i+1).

[0030] In some embodiments, as shown in FIG2 and FIG3A, the electronic device 1 may further include a conductive layer 11, an insulating layer 12, a semiconductor layer 13, a conductive layer 14, an insulating layer 15, an insulating layer 16, a common electrode layer 17, an insulating layer 18, and a pixel electrode layer 19, but is not limited thereto. Depending on different requirements, the electronic device 1 may add or remove one or more components and / or film layers, such as the second substrate 21, color filter layer 22, display dielectric layer 23, and light-shielding layer 24 shown in FIG3B. The material of the semiconductor layer 13 may include amorphous silicon, polycrystalline silicon, or metal oxide, but is not limited thereto. For example, polycrystalline silicon may be low-temperature polycrystalline silicon (LTPS). The metal oxide may be indium gallium zinc oxide (IGZO).

[0031] Referring to Figures 2 and 3A, a conductive layer 11 is disposed on the first substrate 10. The material of the conductive layer 11 may include metal or metal stacks, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto. The conductive layer 11 may be a patterned conductive layer, and the conductive layer 11 may include multiple gates GE, multiple scan lines SL, and other lines (not shown), but is not limited thereto. The multiple gates GE are electrically connected to the multiple scan lines SL respectively. In Figure 2, the gates GE are directly connected to the scan lines SL and protrude toward the second direction D2.

[0032] An insulating layer 12 is disposed on the first substrate 10 and covers the conductive layer 11. The material of the insulating layer 12 may include inorganic materials, such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. The material of the insulating layer 12 may also include organic materials.

[0033] Semiconductor layer 13 is disposed on insulating layer 12. Semiconductor layer 13 is, for example, a patterned semiconductor layer and may include multiple semiconductor patterns CHP. The multiple semiconductor patterns CHP are respectively superimposed on multiple gates GE on third direction D3.

[0034] A conductive layer 14 is disposed on an insulating layer 12. The material of the conductive layer 14 can be referred to the material of the conductive layer 11, and will not be repeated here. The conductive layer 14 may be a patterned conductive layer, and the conductive layer 14 may include a plurality of sources SE, a plurality of drains DE, a plurality of data lines DL, and other lines (not shown), but is not limited thereto. The plurality of sources SE are electrically connected to the plurality of data lines DL. In some embodiments, as shown in FIG2, the source SE may be a part of the corresponding data line DL, but is not limited thereto. Each of the plurality of sources SE and a corresponding drain DE may be disposed on opposite sides of a corresponding semiconductor pattern CHP.

[0035] An insulating layer 15 is disposed on the insulating layer 12 and covers the semiconductor layer 13 and at least a portion of the conductive layer 14. The material of the insulating layer 15 can be referred to the material of the insulating layer 12, and will not be repeated here.

[0036] An insulating layer 16 is disposed on the insulating layer 15. The material of the insulating layer 16 includes, for example, organic insulating materials, inorganic insulating materials, or combinations thereof. Organic insulating materials include, for example, polymethyl methacrylate (PMMA), epoxy resin, acrylic-based resin, silicone, polyimide polymer, or combinations thereof, but are not limited thereto. Inorganic insulating materials include, for example, silicon oxide or silicon nitride, but are not limited thereto.

[0037] A common electrode layer 17 is disposed on the insulating layer 16 and has a plurality of openings A. Each of the plurality of openings A exposes a portion of its corresponding drain DE to be electrically connected to the pixel electrode PE. The material of the common electrode layer 17 may include a transparent conductive material, such as a metal oxide, graphene, other suitable transparent conductive materials, or a combination thereof. The metal oxide may include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other metal oxides. The common electrode layer 17 may be a single surface. For example, the common electrode layer 17 may overlap with a plurality of pixel electrodes PE. In some embodiments, as shown in FIG3A, the common electrode layer 17 may be disposed between the pixel electrode layer 19 and the first substrate 10. However, in other embodiments, although not shown, the pixel electrode layer 19 may be disposed between the common electrode layer 17 and the first substrate 10, and the common electrode layer 17 may not include openings A.

[0038] An insulating layer 18 is disposed on the insulating layer 16 and covers the common electrode layer 17. In some embodiments, as shown in FIG3A, the insulating layer 18 may further extend into the opening H penetrating the insulating layer 16 and the insulating layer 15, and the insulating layer 18 exposes the portion of the drain electrode DE to be electrically connected to the pixel electrode PE. The material of the insulating layer 18 can be referred to the material of the insulating layer 12, and will not be repeated here.

[0039] A pixel electrode layer 19 is disposed on the insulating layer 18. The material of the pixel electrode layer 19 can be referred to the material of the common electrode layer 17, and will not be repeated here. The pixel electrode layer 19 may be a patterned conductive layer, and may include multiple pixel electrodes PE and other circuits (not shown), but is not limited thereto. The multiple pixel electrodes PE can be electrically connected to multiple drains DE through multiple openings H.

[0040] Please refer to Figure 3B. The second substrate 21 is disposed opposite to the first substrate 10 on the third direction D3. Details of the second substrate 21 can be found in the relevant content of the first substrate 10, and will not be repeated here.

[0041] A color filter layer 22 is disposed on a second substrate 21, and the color filter layer 22 is disposed, for example, on the surface of the second substrate 21 facing the first substrate 10. The color filter layer 22 may include a first color unit 22a and a second color unit 22b. A sub-pixel may include a color unit and a corresponding pixel electrode. In a cross-sectional view, as shown in FIG3B, in the first pixel PX1, the first color unit 22a is disposed overlapping with the first pixel electrode PE1, and the second color unit 22b is disposed overlapping with the second pixel electrode PE2, and the first color unit 22a and the second color unit 22b are different colors. In some embodiments, as shown in FIG3B, the color filter layer 22 may further include a third color unit 22c disposed overlapping with the third pixel electrode PE3. The first color unit 22a, the second color unit 22b, and the third color unit 22c may be different colors, for example, red, green, and blue, but the present invention is not limited thereto. Specifically, referring to Figures 2 and 3B, the first sub-pixel SP1 may include a first color unit 22a and a corresponding first pixel electrode PE1, the second sub-pixel SP2 may include a second color unit 22b and a corresponding second pixel electrode PE2, and the third sub-pixel SP3 may include a third color unit 22c and a corresponding third pixel electrode PE3. Thus, the first pixel PX1 may include the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. The display medium layer 23 is disposed between the first substrate 10 and the color filter layer 22. The display medium layer 23 may include a liquid crystal layer, but is not limited thereto.

[0042] A light-shielding layer 24 is disposed on the second substrate 21, and for example, it is disposed on the surface of the second substrate 21 facing the first substrate 10. The light-shielding layer 24 may have multiple openings 24A, and at least a portion of the first color unit 22a, at least a portion of the second color unit 22b, and at least a portion of the third color unit 22c may be located in the multiple openings 24A respectively. As shown in FIG3B, the light-shielding layer 24 includes a first light-shielding portion 241 and a second light-shielding portion 242. There are no scanning lines at the corresponding positions of the first light-shielding portion 241, and two scanning lines (e.g., SL(i+1), SL(i+2)) at the corresponding positions of the second light-shielding portion 242. Therefore, in the second direction D2, the width of the first light-shielding portion 241 may be designed to be smaller than the width of the second light-shielding portion 242.

[0043] Please refer to Figures 4 to 6. Figure 4 is a schematic diagram of a partial image displayed by the electronic device. Figure 5 is a timing diagram of the signals of multiple scan lines and multiple data lines when the electronic device displays the image shown in Figure 4. Figure 6 is a timing diagram of the polarity of multiple data lines and a common electrode when the electronic device displays the image shown in Figure 4. In Figure 5, the horizontal axis represents time, and the vertical axis represents voltage. For ease of explanation, Figure 5 only shows four scan lines (including the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4) and four data lines (including the fifth data line DL5, the sixth data line DL6, the seventh data line DL7, and the eighth data line DL8), where the initial voltage (see the initial horizontal line) of each of the four scan lines and four data lines is 0.

[0044] When electronic device 1 displays an image with alternating bright and dark areas in a horizontal direction (e.g., the first direction D1) (e.g., bright, dark, bright, dark straight stripes as shown in FIG. 4; in FIG. 4, dark areas are represented by dotted grid backgrounds, and the remaining blank areas are bright areas), scanning signals (e.g., square waves as shown in FIG. 5) can be sequentially provided to multiple scanning lines (FIG. 5 only schematically illustrates the first scanning line SL1 to the fourth scanning line SL4). For example, a scanning signal is provided to the first scanning line SL1 from time t1 to time t2, a scanning signal is provided to the second scanning line SL2 from time t2 to time t3, a scanning signal is provided to the third scanning line SL3 from time t3 to time t4, a scanning signal is provided to the fourth scanning line SL4 from time t4 to time t5, and so on.

[0045] Simultaneously, a data signal of opposite polarity can be provided to each data line. For example, as shown in Figure 5, the polarities of the 5th data line DL5, the 6th data line DL6, the 7th data line DL7, and the 8th data line DL8 can be positive, negative, negative, and positive, respectively. When the voltage supplied to a data line is greater than the voltage supplied to the common electrode layer, the polarity of that data line is defined as positive. Conversely, when the voltage supplied to a data line is less than the voltage supplied to the common electrode layer, the polarity of that data line is defined as negative. Taking Figure 5 as an example, during the time intervals (e.g., time t1 to time t2, time t3 to time t4, etc.) when providing scan signals to odd-numbered scan lines (e.g., the first scan line SL1 and the third scan line SL3), positive voltages can be provided to the fifth data line DL5 and the eighth data line DL8, and negative voltages can be provided to the sixth data line DL6 and the seventh data line DL7. Conversely, during the time intervals (e.g., time t2 to time t3, time t4 to time t5, etc.) when providing scan signals to even-numbered scan lines (e.g., the second scan line SL2 and the fourth scan line SL4), neither positive nor negative voltages need to be provided to these data lines. Correspondingly, as shown in Figure 6, the data signals of every four data lines can be decoupled, thus improving the problem of capacitive coupling to the common electrode layer (e.g., Vcom), and therefore improving crosstalk in the horizontal direction.

[0046] Although Figures 4 to 6 illustrate the use of bright and dark straight stripes, the aforementioned pixel array design and polarity design can also improve other types of images with alternating bright and dark areas in the horizontal direction (e.g., the first direction D1), such as images with alternating bright and dark areas at the pixel or sub-pixel level and / or flicker patterns.

[0047] Figures 7 and 8 are a partial simplified circuit diagram and a partial top view of an electronic device according to some other embodiments of the present disclosure, respectively. Referring to Figures 7 and 8, the main difference between electronic device 1A and electronic device 1 of Figures 1 and 2 lies in the pixel array design. In the top view of electronic device 1A, as shown in Figure 7 or 8, each of the multiple scan lines SL presents a continuous square wave shape, such that the three sides of each sub-pixel (including the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3) are surrounded by a corresponding scan line SL, and at least a portion of each scan line SL extends between two adjacent sub-pixels arranged along the second direction D2. For example, as shown in Figure 7, the (i+1)th scan line SL(i+1) may include a first part P1 and a second part P2. In the second direction D2, the first part P1 of the (i+1)th scan line SL(i+1) is located between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1. In the second direction D2, the second part P2 of the (i+1)th scan line SL(i+1) is located between the first sub-pixel SP1 and the second sub-pixel SP2 of the second pixel PX2.

[0048] As previously described, in the embodiments of Figures 1, 2, and 3B, two scan lines (e.g., SL(i+1) and SL(i+2)) are disposed between two adjacent sub-pixels (e.g., the second sub-pixel SP2 and the third sub-pixel SP3). Therefore, a wider second light-shielding portion 242 is provided between the two adjacent sub-pixels (e.g., the second sub-pixel SP2 and the third sub-pixel SP3) to shield the two scan lines (e.g., SL(i+1) and SL(i+2)). As shown in Figure 7, only one scan line is disposed between two adjacent sub-pixels in the second direction D2. For example, the first part P1 of the (i+1)th scan line SL(i+1) is disposed between the second sub-pixel SP2 and the third sub-pixel SP3 of the first pixel PX1. Therefore, the light-shielding portion overlapping the scan line (or the light-shielding portion used to shield the scan line) can be configured to have approximately the same width in the second direction D2, without the need for a widened light-shielding portion as shown in FIG. 3B (e.g., the second light-shielding portion 242). In this way, with the pixel array design of FIG. 7 described above, the area of ​​the light-shielding layer (e.g., black matrix; not shown) used to shield the scan line SL can be reduced, which helps to improve the aperture ratio.

[0049] Further, referring to FIG8, a portion of the pixel electrode PE in the second sub-pixel SP2 of the first pixel PX1 can cross the i-th scan line SL(i) in the second direction D2, and a portion of the pixel electrode PE in the first sub-pixel SP1 of the second pixel PX2 can cross the (i+1)-th scan line SL(i+1) in the second direction D2. In some embodiments, as shown in FIG8, the (i+1)-th scan line SL(i+1) may include a plurality of recesses CC and a plurality of protrusions CV, the plurality of recesses CC may be recessed toward the direction of the (i+2)-th scan line SL(i+2) (refer to FIG7), and the plurality of protrusions CV may be protruded toward the direction of the i-th scan line SL(i). In some embodiments, in the top view, as shown in FIG8, the plurality of recesses of the (i+1)-th scan line SL(i+1) constitute a plurality of first accommodating regions AC1, and at least a portion of the second sub-pixel SP2 of the first pixel PX1 is disposed within one of the plurality of first accommodating regions AC1. In some embodiments, in a top view, as shown in FIG8, a plurality of protrusions CV of the (i+1)th scan line SL(i+1) constitute a plurality of second accommodating regions AC2, and at least a portion of the second sub-pixel SP2 of the second pixel PX2 is disposed within one of the plurality of second accommodating regions AC2.

[0050] The details and polarity design of the electronic device 1A can be found in the relevant descriptions of Figures 3A to 6, and will not be repeated here.

[0051] Figures 9 and 10 are a partial simplified circuit diagram and a partial top view of an electronic device according to further embodiments of the present disclosure, respectively. Referring to Figures 9 to 11, the main difference between electronic device 1B and electronic device 1 of Figures 1 and 2 lies in the pixel array design. In electronic device 1B, as shown in Figure 9, the i-th scan line SL(i) is located between the first sub-pixel SP1 of the first pixel PX1 and the second sub-pixel SP2 of the first pixel PX1, and between the first sub-pixel SP1 of the second pixel PX2 and the second sub-pixel SP2 of the second pixel PX2, and the second sub-pixel SP2 of the first pixel PX1 and the second sub-pixel SP2 of the second pixel PX2 are located between the i-th scan line SL(i) and the (i+1)-th scan line SL(i+1).

[0052] Furthermore, as shown in Figure 10, at least one pixel electrode PE extends through a corresponding scan line SL to be electrically connected to a corresponding drain DE, such that the at least one pixel electrode PE can partially overlap the corresponding scan line SL, for example, the at least one pixel electrode PE can cross the corresponding scan line SL. As shown in Figure 10, a portion of the pixel electrode PE in the first sub-pixel SP1 of the second pixel PX2 crosses the i-th scan line SL(i) in the second direction D2.

[0053] In addition, the semiconductor pattern CHP of each of the multiple pixels PX includes a first branch BH1, a second branch BH2 and a connecting portion CT that connects the first branch BH1 and the second branch BH2, and each of the first branch BH1 and the second branch BH2 is crossed by a corresponding scan line SL of the multiple scan lines SL.

[0054] The pixel array design described above reduces the area of ​​the light-shielding layer (e.g., a black matrix; not shown) used to shield the scan lines SL, thus contributing to an increase in aperture ratio. It should be understood that Figure 10 is merely an example and is not intended to limit this disclosure. In other embodiments not shown, the semiconductor pattern CHP may employ different patterns and / or layouts as required.

[0055] Figure 11 is a cross-sectional view corresponding to section line II-II' in Figure 10. In some embodiments, as shown in Figure 11, the electronic device 1B may further include a light-shielding layer 20, an insulating layer 21, an insulating layer 22, and an insulating layer 23, but is not limited thereto. Depending on different requirements, the electronic device 1B may add or remove one or more components and / or film layers.

[0056] A light-shielding layer 20 is disposed on the first substrate 10. The material of the light-shielding layer 20 may include metal or metal stack, but is not limited thereto. The light-shielding layer 20 may be a patterned light-shielding layer, and the light-shielding layer 20 may include a plurality of light-shielding patterns 20P, wherein the plurality of light-shielding patterns 20P are respectively superimposed on a plurality of gates GE on a third direction D3.

[0057] An insulating layer 21 is disposed on the first substrate 10 and covers the light-shielding layer 20. The material of the insulating layer 21 can be referred to the material of the insulating layer 12, and will not be repeated here.

[0058] An insulating layer 12 is disposed on an insulating layer 21, and a semiconductor layer 13 is disposed on an insulating layer 12. Each of the plurality of semiconductor patterns CHP may include a source region 13S, a drain region 13D, and a channel region 13CH disposed between the source region 13S and the drain region 13D.

[0059] An insulating layer 15 is disposed on the insulating layer 12 and covers the semiconductor layer 13. A conductive layer 11 is disposed on the insulating layer 15. Insulating layers 22 and 23 are sequentially disposed on the insulating layer 15 and cover the conductive layer 11. The materials of the insulating layers 22 and 23 can be referred to the material of the insulating layer 12, and will not be repeated here.

[0060] A conductive layer 14 is disposed on an insulating layer 23. Each of the plurality of source electrodes SE can penetrate insulating layers 15, 22, and 23 and is electrically connected to a corresponding source region 13S. Each of the plurality of drain electrodes DE can penetrate insulating layers 15, 22, and 23 and is electrically connected to a corresponding drain region 13D.

[0061] An insulating layer 16 is disposed on the insulating layer 23 and covers at least a portion of the conductive layer 14. The insulating layer 16 may have a plurality of through holes TH, and each of the plurality of through holes TH may expose a portion of a corresponding drain DE.

[0062] The common electrode layer 17, the insulating layer 18 and the pixel electrode layer 19 are sequentially disposed on the insulating layer 16. The details are as described above and will not be repeated here.

[0063] In summary, in the embodiments disclosed herein, by designing the pixel array and polarity, data signals can be decoupled to improve the problem of capacitive coupling to the shared electrode layer, thereby improving crosstalk in the horizontal direction.

[0064] The above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

[0065] While the embodiments and advantages of this disclosure have been presented above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure, and features of the various embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand from the content of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

[0066] 1, 1A, 1B: Electronic devices 10: First substrate 11, 14: Conductive layer 12, 15, 16, 18, 21, 22, 23: Insulation layer 13: Semiconductor layer 13CH: Passage Area 13D: Drain Zone 13S: Source Region 17: Shared electrode layer 19: Pixel Electrode Layer 20, 24: Light-blocking layer 20P: Blackout Pattern 21: Second substrate 22: Color Filter Layer 22a: First color unit 22b: Second color unit 22c: Third color unit 23: Display media layer 24A, A: Opening 241: First shading section 242: Second shading section AC1: First Capacity Zone AC2: Second Storage Area BH1: First Branch BH2: Second Branch CC: Concave CHP: Semiconductor Pattern CV: convex part CT: Connecting part D1: First Direction D2: Second Direction D3: Third direction DE: drain DL, DL5, DL6, DL7, DL8, DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5): data line GE: Gate H: Opening H1: The first horizontal sub-pixel H2: The second horizontal row of sub-pixels P1: Part 1 P2: Part Two PE: pixel electrode PE1: First pixel electrode PE2: Second pixel electrode PE3: Third pixel electrode PX: pixel PX1: first pixel PX2: second pixel PX3: third pixel SE: Source SL, SL1, SL2, SL3, SL4, SL(i), SL(i+1), SL(i+2), SL(i+3), SL(i+4), SL(i+5): scan line SP1: first sub-pixel SP2: Second sub-pixel SP3: The third sub-pixel t1, t2, t3, t4, t5: Time TH: Through-hole I-I', II-II': section line

Claims

1. An electronic device comprising: First substrate; Multiple data lines are disposed on the first substrate and arranged along a first direction, wherein the multiple data lines include a j-th data line, a (j+1)-th data line, and a (j+2)-th data line arranged adjacent to each other in the first direction, where j is a positive integer; multiple scan lines are disposed on the first substrate and arranged along a second direction, wherein the multiple scan lines include an i-th scan line, a (i+1)-th scan line, and a (i+2)-th scan line arranged adjacent to each other in the second direction, where i is a positive integer; and a first pixel and a second pixel are adjacent in the first direction, each of the first pixel and the second pixel includes a first sub-pixel and a second sub-pixel arranged in the second direction, the first sub-pixel of the first pixel is electrically connected to the i-th scan line and the j-th data line, and the second sub-pixel of the first pixel is electrically connected to the i-th scan line and the (j+1)-th data line. The first sub-pixel of the second pixel is electrically connected to the (i+1)th scan line and the (j+2)th data line. The second sub-pixel of the second pixel is electrically connected to the (i+1)th scan line and the (j+1)th data line. The jth data line has opposite polarity to the (j+1)th data line, and the jth data line has opposite polarity to the (j+2)th data line.

2. The electronic device of claim 1, wherein each of the first pixel and the second pixel further comprises a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in the second direction, wherein: The plurality of scan lines also includes a (i+3)th scan line, and in the second direction, the (i+2)th scan line is disposed adjacent to the (i+1)th scan line and the (i+3)th scan line. The third sub-pixel of the first pixel is electrically connected to the (i+2)th scan line and the jth data line, and the third sub-pixel of the second pixel is electrically connected to the (i+3)th scan line and the (j+2)th data line.

3. The electronic device as claimed in claim 1, further comprising a third pixel, wherein: In the first direction, the second pixel is disposed adjacent to the first pixel and the third pixel. The third pixel includes a first sub-pixel and a second sub-pixel arranged in the second direction. The plurality of data lines also includes a (j+3)th data line. In the first direction, the (j+2)th data line is disposed adjacent to the (j+1)th data line and the (j+3)th data line. The first sub-pixel of the third pixel is electrically connected to the i-th scan line and the (j+2)th data line. The second sub-pixel of the third pixel is electrically connected to the i-th scan line and the (j+3)th data line. The j-th data line and the (j+3)th data line have the same polarity.

4. The electronic device as claimed in claim 2, wherein in the second direction, the first sub-pixel and the second sub-pixel of the first pixel are disposed between the i-th scan line and the (i+1)-th scan line, and a portion of the (i+1)-th scan line and a portion of the (i+2)-th scan line are disposed between the second sub-pixel and the third sub-pixel of the first pixel.

5. The electronic device as claimed in claim 2, wherein: The (i+1)th scan line includes a first part and a second part. In the second direction, the first part of the (i+1)th scan line is disposed between the second sub-pixel and the third sub-pixel of the first pixel, and in the second direction, the second part of the (i+1)th scan line is disposed between the first sub-pixel and the second sub-pixel of the second pixel.

6. The electronic device as claimed in claim 5, wherein: A portion of the pixel electrode in the second sub-pixel of the first pixel crosses the i-th scan line in the second direction, and a portion of the pixel electrode in the first sub-pixel of the second pixel crosses the (i+1)-th scan line in the second direction.

7. The electronic device of claim 1, wherein, in a top view, the (i+1)th scan line includes a plurality of recesses and a plurality of protrusions, the plurality of recesses being recessed toward the (i+2)th scan line and the plurality of protrusions being protruded toward the i-th scan line.

8. The electronic device of claim 7, wherein, in the top view, the plurality of recesses of the (i+1)th scan line constitute a plurality of first receiving regions, and at least a portion of a second sub-pixel of the first pixel is disposed within one of the plurality of first receiving regions.

9. The electronic device of claim 7, wherein, in the top view, the plurality of protrusions of the (i+1)th scan line constitute a plurality of second accommodating regions, and at least a portion of a second sub-pixel of the second pixel is disposed within one of the plurality of second accommodating regions.

10. The electronic device as claimed in claim 1, wherein: The i-th scan line is disposed between the first sub-pixel of the first pixel and the second sub-pixel of the first pixel, and between the first sub-pixel of the second pixel and the second sub-pixel of the second pixel.

11. The electronic device as claimed in claim 10, wherein: A portion of the pixel electrode in the first sub-pixel of the second pixel crosses the i-th scan line in the second direction.

12. The electronic device as claimed in claim 1, wherein: The first sub-pixel and the second sub-pixel have different colors.

13. The electronic device as claimed in claim 12, further comprising: The first pixel electrode and the second pixel electrode are disposed on the first substrate; Second substrate; A color filter layer is disposed on the second substrate; And a display medium layer is disposed between the first substrate and the color filter layer, wherein the color filter layer includes a first color unit and a second color unit, the first sub-pixel includes the first color unit and a first pixel electrode, the second sub-pixel includes the second color unit and a second pixel electrode, and the first color unit and the second color unit are different colors.

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