Planar inductive component

Abstract

A planar inductive element includes a first circuit board, a second circuit board, and a core. The first circuit board includes a first through-hole and a first mating surface, and a plurality of first traces are formed around the first through-hole. The second circuit board includes a second through-hole and a second mating surface for mating with the first mating surface, and a plurality of second traces are formed around the second through-hole. When current flows through the planar inductive element, the potential of a first low-voltage terminal of a layer of first traces located on the first mating surface is substantially the same as the potential of a second low-voltage terminal of a layer of second traces located on the second mating surface, and the potential of a first high-voltage terminal of the first trace located on the first mating surface is substantially the same as the potential of a second high-voltage terminal of the second trace not located on the second mating surface.

Description

Technical Field

[0001] This invention relates to a planar inductive element, and more particularly to a planar inductive element composed of multiple stacked circuit boards. Prior Technology

[0002] With the rapid development of the information industry, power supplies and power conversion circuits have played an indispensable role. Power supplies and power conversion circuits typically contain inductive components such as inductors and transformers, whose main function is to control the coupling and flow of energy through switching. Generally, traditional wound inductors or transformers consist of an iron core, enameled wire coils, insulating tape, and / or a bobbin. The manufacturing process requires using a winding machine to wind the enameled wire onto the bobbin or iron core, followed by insulation with tape, assembly, impregnation, and adhesive application. Therefore, traditional inductors or transformers are characterized by their large size, complex manufacturing process, and high cost.

[0003] Therefore, in the field of power electronics, planar inductors and planar transformers (hereinafter referred to as planar inductive components) that use circuit board traces as coils have gradually been developed. Specifically, planar inductive components utilize the copper foil traces of the circuit board as coils, replacing the winding frame and enameled wire process, and have advantages such as being lightweight, thin, small in size, easy to manufacture, and highly stable. However, since the copper foil traces need to be wrapped around the iron core, the copper foil traces are often not wide enough due to design parameters such as the size of the iron core and the number of turns, resulting in a higher impedance value. Furthermore, most circuit boards are multi-layered board designs, which makes it difficult for the inner layers of the circuit board to conduct heat, leading to excessively high temperatures in the copper foil coils.

[0004] Specifically, since the planar inductive element is formed on a single circuit board, the equivalent impedance of the copper foil trace T on that circuit board is shown in Figure 1. In Figure 1, it is assumed that the equivalent impedance R of the coil W is 1 ohm, and the current I flowing through the planar inductive element 100 is 3A. Therefore, the power loss (Ploss = I²R) of the current I flowing through the coil W can be calculated as (3*3)*1 = 9W. Thus, the magnitude of the impedance of the coil W directly affects the amount of power loss. Furthermore, all of this power loss will cause the coil W to heat up. Therefore, if this heat accumulates in the poorly heated inner layers of the circuit board, it will lead to an excessively high temperature of the copper foil coil.

[0005] Therefore, how to design a planar inductive element to reduce the total impedance of the trace and thus reduce the loss of the planar inductive element and reduce heat loss is a major research topic that the creators of this project intend to conduct. Summary of the Invention

[0006] To address the aforementioned problems, this disclosure provides a planar inductive element to overcome the limitations of the prior art. Therefore, the planar transformer of this disclosure includes a first circuit board, a second circuit board, and a core. The first circuit board includes a first coil, a first through-hole, and a first mating surface. The first coil includes a plurality of layers of first traces, each of which surrounds the first through-hole. The second circuit board includes a second coil, a second through-hole, and a second mating surface for mating with the first mating surface. The second coil includes a plurality of layers of second traces, each of which surrounds the second through-hole. The core includes a first core post. The first coil is electrically connected to the second coil to form a parallel structure, and the first core post passes through the first and second through-holes to form a planar inductive element. Among them, one of the multiple layers of first traces located on the first bonding surface has a first high voltage terminal and a first low voltage terminal, and one of the multiple layers of second traces located on the second bonding surface has a second high voltage terminal and a second low voltage terminal; when current flows through the planar inductive element, the potentials of the first low voltage terminal and the second low voltage terminal are approximately the same, and the potentials of the first high voltage terminal and the second high voltage terminal are approximately the same.

[0007] In one embodiment, the first trace on the first bonding surface and the second trace on the second bonding surface are mirror images of each other, such that the potential at any specific point on the first trace on the first bonding surface is the same as the potential at the same location on the second trace on the second bonding surface.

[0008] In one embodiment, on the plane defined by the X-axis and Y-axis, the first trace of the layer located on the first bonding surface and the second trace of the layer located on the second bonding surface are mirror images of each other, such that the first trace of the layer located on the first bonding surface and the second trace of the layer located on the second bonding surface have the same potential at the same X-axis coordinate value and Y-axis coordinate value position along the Z-axis direction, wherein the X-axis, Y-axis and Z-axis systems are perpendicular to each other.

[0009] In one embodiment, current flows in from the end of the first trace in the layer located at the first bonding surface and the end of the second trace in the layer not located at the second bonding surface, so that the first bonding surface and the second bonding surface are both high voltage layers.

[0010] In one embodiment, current flows out from the end of the first trace in the layer located on the first bonding surface and the end of the second trace in the layer located on the second bonding surface, so that the first bonding surface and the second bonding surface are both low-voltage layers.

[0011] In one embodiment, the impedance of the first traces in the plurality of layers is approximately equal to the impedance of the second traces in the plurality of layers in the corresponding layers.

[0012] In one embodiment, the impedance of the outer layer of the second circuit board is greater than the impedance of each layer within the outer layer of the second circuit board.

[0013] In one embodiment, the end of the first trace in the first layer located at the first mating surface forms a first end of the first coil, and the end of another first trace in the plurality of first traces, located away from the first trace in the first layer, forms a second end of the first coil. The end of another second trace in the plurality of second traces, located away from the second trace in the first layer, forms a third end of the second coil, and the end of the second trace in the second mating surface forms a fourth end of the second coil. The first end is electrically connected to the fourth end, and the second end is electrically connected to the third end to form a parallel structure.

[0014] In one embodiment, the planar inductive element is a planar inductor, and the first coil and the second coil form an inductor coil with a parallel structure.

[0015] In one embodiment, the planar inductive element is a planar transformer, and the first coil and the second coil form either the primary coil or the secondary coil in a parallel structure.

[0016] In one embodiment, the primary side coil or the secondary side coil is disposed on the first circuit board or the second circuit board to form a planar transformer by passing the first iron core post through the first through hole and the second through hole.

[0017] In one embodiment, the core further includes a second core post, and the other of the primary side coil or the secondary side coil is disposed on a third circuit board; the first core post passes through the first through hole and the second through hole, and the second core post passes through the third through hole of the third circuit board to form a planar transformer.

[0018] The main purpose and effect of this disclosure is that by electrically parallelizing the first and second traces of a planar inductive element and placing them within the same iron core, the current flowing through the planar inductive element can be shunted (or considered as reducing the total impedance of the traces). This achieves the effect of reducing power loss and heat loss.

[0019] To gain a deeper understanding of the techniques, means, and effects employed by this invention to achieve its intended purpose, please refer to the following detailed description and accompanying drawings. It is believed that the purpose, features, and characteristics of this invention can be understood in a thorough and specific manner from these drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit the scope of this invention. Simple Explanation of the Diagram

[0020] Figure 1 is a schematic diagram of the equivalent circuit of a conventional planar inductive element;

[0021] Figure 2 is a schematic diagram of the equivalent circuit of the planar inductive element disclosed in this paper;

[0022] Figure 3A is a circuit diagram of the first circuit board disclosed herein;

[0023] Figure 3B is a circuit diagram of the second circuit board disclosed herein;

[0024] Figure 4A is a top view schematic diagram of the top layer routing configuration of the first circuit board;

[0025] Figure 4B is a top perspective view of the bottom layer routing configuration of the second circuit board.

[0026] Figure 4C is a bottom view schematic diagram of the bottom layer routing configuration of the second circuit board;

[0027] Figure 5A is a cross-sectional view along the first axis after the first and second circuit boards of this disclosure are stacked;

[0028] Figure 5B is an exploded view of the structure of the flat-plate inductive element disclosed in this paper;

[0029] Figure 6A is an equivalent circuit diagram of the trace section of the circuit board disclosed herein;

[0030] Figure 6B is a schematic diagram of the equivalent circuit of the traces in Figure 6A when the flat-plate inductive element is in operation;

[0031] Figure 7A is an equivalent circuit diagram of the first embodiment after the traces of the first circuit board and the second circuit board are stacked.

[0032] Figure 7B is an equivalent circuit diagram of the second embodiment after the traces of the first and second circuit boards are stacked.

[0033] Figure 7C is an equivalent circuit diagram of the third embodiment after the traces of the first and second circuit boards of this disclosure are stacked; and

[0034] Figure 8 is a cross-sectional view of one embodiment of the planar transformer disclosed herein. Implementation

[0035] The technical content and detailed description of this invention are explained below with reference to the accompanying drawings:

[0036] Please refer to Figure 2 for the equivalent circuit diagram of the planar inductive element disclosed herein, and also refer to Figure 1. One of the objectives and effects of this disclosure is that, through the parallel connection of the two coils in the two circuit boards, the first coil W1, which serves as the main coil, and the second coil W2, which serves as the auxiliary coil, can reduce the copper loss caused by the DC resistance (DCR) of the planar inductive element 100, thereby reducing the operating temperature of the planar inductive element 100 (i.e., the heat caused by the losses). Specifically, under the same conditions as in Figure 1 (i.e., the equivalent impedance R of coil W is 1 ohm, and the current I flowing through the planar inductive element is 3A), the equivalent impedance R of the first coil W1 is 1 ohm, and the equivalent impedance R of the second coil W2 is the same as that of the first coil W1, so that the two are connected in parallel, the current I can be evenly split (i.e., 1.5A of current flows through the first coil W1 and the second coil W2 respectively). Therefore, the power loss of each individual coil is (1.5*1.5)*1=2.25, and the sum of the power losses of the two coils is 4.5W. Thus, it can be clearly seen that the planar inductive element 100 disclosed herein, through the parallel connection of two coils W1 and W2, can halve the power loss of the current I flowing through coils W1 and W2 (i.e., from 9W in Figure 1 to 4.5W in Figure 2), thereby reducing the heat generated by the loss.

[0037] Please refer to Figure 3A, which is a circuit structure diagram of the first circuit board disclosed herein, and Figure 3B, which is a circuit structure diagram of the second circuit board disclosed herein, in conjunction with Figure 1. Figure 3A mainly shows the physical structure of the first coil W1 in Figure 2. The first circuit board 1 includes a first coil W1 that can be used to form a flat-type inductive element 100, a first through hole H1, a trace portion 12, a connecting portion 14, and a first mating surface 18. The first coil W1 includes a plurality of layers of first traces T1_1 to T1_N from top to bottom. The plurality of layers of first traces T1_1 to T1_N are respectively wrapped around the first through hole H1. The plurality of layers of first traces T1_1 to T1_N are connected in series with each other in sequence, and the two ends of the entire series of traces are electrically connected to the connecting portion 14 (they can be directly connected or connected by traces from other layers after descending to other layers through vias such as, but not limited to, through holes, blind vias, buried vias, etc.).

[0038] Referring to Figure 4A, the uppermost first trace T1_1 among the multiple layers of first traces T1_1~T1_N of the first coil W1 is located on the first mating surface 18. The uppermost first trace T1_1 has a first high voltage terminal T1_1_H and a first low voltage terminal T1_1_L.

[0039] Figure 3B mainly shows the physical structure of the second coil W2 in Figure 2. The second circuit board 2 includes the second coil W2, which can be used to form a flat inductive element 100, a second through hole H2, a trace portion 22, a connecting portion 24, and a second mating surface 28. The second coil W2 includes a plurality of layers of second traces T2_1 to T2_N from top to bottom, and the plurality of layers of second traces T2_1 to T2_N are respectively wrapped around the second through hole H2. The plurality of layers of second traces T2_1 to T2_N are connected in series, and the two ends of the entire series of traces are electrically connected to the connecting portion 24 (either directly connected or connected by traces from other layers after descending to other layers through vias such as, but not limited to, through holes, blind vias, buried vias, etc.).

[0040] Referring to Figures 4B and 4C, the top perspective view and bottom view view of the lowest layer of the trace configuration on the second circuit board show that the lowest layer of the second traces T2_1 to T2_N of the second coil W2 is located on the second mating surface 28, and the lowest layer of the second trace T2_N has a second high voltage terminal T2_N_H and a second low voltage terminal T2_N_L.

[0041] It is worth mentioning that, in one embodiment, the number of turns of the first trace T1 around the first through hole H1 can be adjusted according to actual needs (such as, but not limited to, parameters such as inductance and turns ratio), and due to the characteristics of the flat inductive element 100 being formed on the circuit board, the number of turns can be a non-integer number, so as to facilitate fine-tuning of parameters.

[0042] The first circuit board 1 can be the main circuit board, and it may also include a circuit section 16 for configuring circuit elements. The second circuit board 2 can be an auxiliary circuit board, mainly for providing another set of coils W2, and therefore may selectively include a circuit section depending on the actual circuit requirements (Figure 3B shows a circuit section not included). In addition, in Figure 4A, the trace section 12 may also form additional specific traces Ts. The specific traces Ts are mainly for sensing voltage and current by coupling the first trace T1 or the second trace T2. Therefore, the specific traces Ts can be used for detection (e.g., but not limited to, as a coil for sensing current magnitude, such as a current transformer), or for obtaining coupled energy to power components such as, but not limited to, a controller. On the other hand, although not specifically shown in Figure 4B, the trace section 22 may also form additional traces (e.g., but not limited to, specific traces Ts) as in the embodiment of Figure 4A, which will not be described in detail here.

[0043] Referring to Figure 5A, which is a cross-sectional view along the first axis after the first and second circuit boards are stacked, and further referring to Figures 2-4B, the circuit structure in Figure 5A is mainly a cross-sectional view of the flat-plate inductive element 100 after assembly, using the first axis A1 as shown in Figure 4B. In Figure 5A, the flat-plate inductive element 100 also includes a core C, and the core C includes a first core component C-1, a second core component C-2, and a first core post C1. This disclosure mainly involves stacking the second circuit board 2 on one side of the first circuit board 1, and after the first core component C-1 and the second core component C-2 of the core C are combined, the first core post C1 passes through the first through hole H1 and the second through hole H2 to form a flat-plate inductive element. Among them, the core C can be of type UT as shown in Figure 5A, but can also be, for example, but not limited to, EE type, EI type, U type, etc., and is not limited here. When the second circuit board 2 is stacked on one side of the first circuit board 1, the connecting part 24 is also stacked on one side of the connecting part 14. Therefore, the connecting parts 14 and 24 can be electrically connected by techniques such as, but not limited to, soldering and tinning, so as to electrically connect the first coil W1 to the second coil W2 and form a parallel structure of two coils.

[0044] On the other hand, since the two circuit boards 1 and 2 are stacked to allow the first iron core post C1 to pass through, the iron core C can be fitted with the two coils W1 and W2 to form a flat inductive element 100. Therefore, this disclosure electrically connects the first coil W1 and the second coil W2 of the flat inductive element 100 in the same iron core C, thereby shunting the current (or reducing the total impedance of the traces), thus reducing power loss and heat loss. In addition, in order to facilitate the fitting of the iron core C, the trace portions 12 and 22 are preferably of the same shape, and the first through hole H1 and the second through hole H2 can also be through holes of the same shape, but are not limited thereto.

[0045] Please refer to Figure 5B, which is an exploded view of the structure of the flat-panel inductive element disclosed herein, and in conjunction with Figures 2-5A. Figure 5B is mainly an exploded three-dimensional structural view of the stacked structure in Figure 5A, therefore, the X-axis, Y-axis, and Z-axis are defined to be perpendicular to each other. Furthermore, on the plane defined by the X-axis and Y-axis, the mating surfaces of the first circuit board 1 and the second circuit board 2 are the first mating surface 18 and the second mating surface 28. Moreover, as can be seen from the three-dimensional structure, the first core component C-1 is a structure in which the first core post passes through the first through hole H1 and the second through hole H2, and the second core component C-2 can precisely engage with the sides of the wiring portions 12 and 22. In this way, after the first core component C-1 and the second core component C-2 are combined, the first circuit board 1 and the second circuit board 2 are fixed, preventing them from becoming unstable and shaking.

[0046] Furthermore, referring to Figures 4A and 4B, on the planes defined by the X and Y axes, the first trace T1_1 on the uppermost layer of the first coil W1 and the second trace T2_4 on the lowermost layer of the second coil W2 are mirror images of each other. Therefore, when the potentials of the first low-voltage terminal T1_1_L and the second low-voltage terminal T2_N_L are approximately the same, and the potentials of the first high-voltage terminal T1_1_H and the second high-voltage terminal T2_N_H are approximately the same, then the first trace T1_1 on the first mating surface 18 and the second trace T2_N on the second mating surface 28 have the same potential at the same X-axis and Y-axis coordinate positions along the Z-axis direction.

[0047] Please refer to Figure 6A, which is an equivalent circuit diagram of the first coil W1 of the circuit board disclosed herein, and Figure 6B, which is an equivalent circuit diagram of the first coil W1 of Figure 6A when a total voltage of 400V is applied across its terminals. Also refer to Figures 2-5. Figure 6A is a schematic example of the first circuit board 1 having four layers of material, but it is not a limitation. Therefore, the first circuit board 1 and the second circuit board 2 of this disclosure can actually have two or more layers of material, and the number of layers in the first circuit board 1 and the second circuit board 2 can also be different.

[0048] Referring to Figures 3A, 4A, 6A, and 7A, the first circuit board 1 has, from top to bottom, a first board layer L1 (top layer), a second board layer L2, a third board layer L3, and a fourth board layer L4 (bottom layer). On these four board layers, first traces T1_1 to T1_4 are formed, each surrounding a first through-hole H1. These four first traces T1_1 to T1_4 can be connected in series vias to form a first coil W1. The end of the first trace T1_1 on the first board layer L1 forms the first end W1-1 of the first coil W1, and the end of the first trace T1_4 on the fourth board layer L4 forms the second end W1-2 of the first coil W1.

[0049] The second circuit board 2 is similar, and from top to bottom, it has a first board layer L1 (top layer), a second board layer L2, a third board layer L3, and a fourth board layer L4 (bottom layer). On these four board layers, second traces T2_1 to T2_4 are formed, each surrounding a second through-hole H2. These four second traces T2_1 to T2_4 can be connected in series vias to form a second coil W2, with the two ends of the second coil W2 being the third end W2-1 and the fourth end W2-2.

[0050] In Figure 6B, assuming the planar inductive element 100 is operating, the total voltage across the first terminal W1-1 to the second terminal W1-2 is 400V, and the impedances of the first traces T1_1 to T1_4 in each layer are the same. Therefore, the partial voltages V1 to V4 borne by the first traces T1_1, T1_2, T1_3, and T1_4 in each layer are 100V (i.e., one-quarter of the total voltage across 400V). Under this condition, there is a voltage difference of at least 200V between the first board layer L1 (top layer) and the fourth board layer L4 (bottom layer) (i.e., the voltage difference between the second board layer L2 and the third board layer L3), and the maximum voltage difference of the first coil W1 is 400V (i.e., the total voltage across).

[0051] Referring to Figure 7A, which is an equivalent circuit diagram of the first embodiment disclosed herein, after the first circuit board and the second circuit board are stacked, the first coil W1 and the second coil W2 are connected in parallel. When the first circuit board 1 and the second circuit board 2 are stacked, the first circuit board 1 has a first mating surface 18 (i.e., the bottom surface of the first circuit board 1) close to the second circuit board 2, and the second circuit board 2 also has a second mating surface 28 (i.e., the top surface of the second circuit board 2) close to the first circuit board 1. Therefore, the uppermost first trace T1_1 of the first coil W1 on the mating surface 18 and the lowermost second trace T2_4 of the second coil W2 on the mating surface 28 are close to each other and are insulated from each other only by a thin layer of insulating varnish coated on the surfaces of the circuit boards 1 and 2.

[0052] However, if the voltage difference between the two coils is too large (for example, but not limited to, the total cross voltage of V400V in Figures 6A-6B), directly bonding the two circuit boards 1 and 2 will cause the high-voltage layer (i.e., the first layer L1) of the first circuit board 1 to adhere to the low-voltage layer (i.e., the fourth layer L4) of the second circuit board 2, resulting in a cross voltage of up to 400V between these two layers. This could lead to sparking and damage between the contact surfaces of the two circuit boards 1 and 2. However, if the bonding surfaces are not specially thickened for insulation, relying solely on the surface coating for insulation will inevitably result in insufficient insulation. Furthermore, adding tape or other insulation mechanisms would increase costs and time.

[0053] Therefore, referring to Figure 7B, which is an equivalent circuit diagram of the second embodiment after the wiring portions of the first and second circuit boards of this disclosure are stacked, this disclosure electrically connects the second end W1-2 of the bottom layer of the first coil W1 to the third end W2-1 of the top layer of the second coil W2, and the first end W1-1 of the top layer of the first coil W1, located on the bonding surface 18, is electrically connected to the fourth end W2-2 of the bottom layer of the second coil W2, located on the bonding surface 28, so that the first coil W1 and the second coil W2 form a parallel structure through the above-mentioned electrical connection. Thus, as shown in Figure 7A, when the first end W1-1 is the ground end, the fourth end W2-2 is also the ground end. Conversely, as shown in Figure 7B, when the first end W1-1 receives a 400V voltage, the fourth end W2-2 also receives a 400V voltage.

[0054] Therefore, taking the architecture of Figure 7A as an example, when current I flows from the first terminal W1-1 and the fourth terminal W2-2 to the ground terminal, the first bonding surface 18 is a low-voltage layer, and the voltage across the two ends of the first trace T1_1 (i.e., the trace located on the top layer of the first board L1 of the first circuit board 1) is E1 (i.e., the voltage across the two ends of the first trace T1_1 changes from 0V to 100V). Similarly, the second bonding surface 28 is also a low-voltage layer, and the voltage across the two ends of the second trace T2_4 (i.e., the trace located on the bottom layer of the fourth board L4 of the second circuit board 2) is E2 (i.e., the voltage across the two ends of the second trace T2_4 changes from 0V to 100V). Therefore, the voltage range E1 across the two ends of the first trace T1_1 and the voltage range E2 across the two ends of the second trace T2_4 can be made approximately the same (i.e., the upper and lower limits of the voltage range at both ends of the traces are 100V and 0V, respectively). The phrase "generally" means that it can accept, for example, but not more than, a pressure difference of ±5%. The same applies to the same statements that appear later in the text, and will not be repeated here.

[0055] Similarly, taking the architecture of Figure 7B as an example, when current I flows from the first terminal W1-1 and the fourth terminal W2-2 into traces T1 and T2, the first bonding surface 18 is a high-voltage layer, and the voltage across the two ends of the first trace T1_1 is E1 (i.e., the voltage across the two ends of the first trace T1_1 changes from 300V to 400V). The second bonding surface 28 is also a high-voltage layer, and the voltage across the two ends of the second trace T2_4 is E2 (i.e., the voltage across the two ends of the second trace T2_4 also changes from 300V to 400V). Therefore, the voltage ranges of E1 across the two ends of the first trace T1_1 and E2 across the two ends of the second trace T2_4 can also be made approximately the same (i.e., the upper and lower limits of the voltage range at both ends of the traces are 400V and 300V, respectively). Therefore, if the circuit configuration shown in Figures 7A and 7B is used, the voltage difference between the two traces T1 and T2 will not be too large. Thus, even if the flat-plate inductive element 100 is only insulated by the basic surface insulating varnish of the circuit boards 1 and 2, there is no concern about arcing or damage. There is no need to thicken the surface varnish of the mating surfaces for insulation, or to add tape or other insulation mechanisms, which can avoid increasing costs and time.

[0056] In addition, the potentials of corresponding points on any layer are approximately the same for the first traces T1_1 to T1_4 and the corresponding second traces T2_4 to T2_1 (for example, but not limited to, the first trace T1_2 of the second layer L2 corresponds to the second trace T2_3 of the third layer L3, and so on). For example, but not limited to, the potential of the via point of the first trace T1_2 of the second layer L2 in Figure 7A is approximately the same as the potential of the via point of the second trace T2_3 of the third layer L3, and so on. This will not be elaborated further here.

[0057] In detail, in Figures 7A-7B, the first trace T1_1 located on the first mating surface 18 has a first high-voltage terminal and a first low-voltage terminal (in Figure 7A, the ground terminal is the first low-voltage terminal, and the other end of the ground terminal at 100V is the first high-voltage terminal), so that the voltage E1 across the first trace T1_1 on the first mating surface 18 varies from 0 to 100V from the first low-voltage terminal to the first high-voltage terminal. The second trace T2_4 located on the second mating surface 28 also has a second high-voltage terminal and a second low-voltage terminal (in Figure 7A, the ground terminal is the second low-voltage terminal, and the other end of the ground terminal at 100V is the second high-voltage terminal), so that the voltage E2 across the second trace T2_4 on the second mating surface 28 also varies from 0 to 100V from the second low-voltage terminal to the second high-voltage terminal. The term "transition voltage E1 and transition voltage E2 are approximately the same" means that the potentials of the first low-voltage terminal and the second low-voltage terminal are both grounded and therefore approximately the same, and the potentials of the first high-voltage terminal and the second high-voltage terminal are both 100V and therefore approximately the same. Furthermore, the transition voltages at corresponding points between the high-voltage terminal and the low-voltage terminal are also approximately the same.

[0058] Furthermore, in Figure 7C, a third circuit board 3 is added to the architecture of Figure 7A, and the third circuit board 3 is similar to the first circuit board 1 or the second circuit board 2. Specifically, the third circuit board 3 includes a third coil W3, and the two ends of the third coil W3 form a fifth end W3-1 and a sixth end W3-2, respectively. The third coil W3 is formed by third traces T3_1 to T3_4, and the first circuit board 1 and the third circuit board 3 are also stacked to form a third mating surface 38 and a fourth mating surface 48. The circuit structures and characteristics of the first circuit board 1 and the second circuit board 2 are the same as in Figure 7A, and will not be described again here. On the other hand, the circuit structures and characteristics of the first circuit board 1 and the third circuit board 3 are the same as in Figure 7B.

[0059] That is, when current I flows from the second terminal W1-2 and the fifth terminal W3-1 to traces T1_4 and T3_1, the third bonding surface 38 is a high-voltage layer, and the voltage across the two ends of the first trace T1_4 of the fourth layer board L4 is E3 (i.e., the voltage across the two ends of the first trace T1_4 changes from 300V to 400V). The fourth bonding surface 48 is also a high-voltage layer, and the voltage across the two ends of the third trace T3_1 of the third coil W3 is E4 (i.e., the voltage across the two ends of the third trace T3_1 also changes from 300V to 400V). Therefore, the range of variation of the third voltage E3 and the fourth voltage E4 can be made approximately the same (i.e., the upper and lower limits of the voltage range at both ends of the trace are 400V and 300V, respectively).

[0060] Furthermore, referring to Figures 4A and 4B, if the first trace T1_1 on the first mating surface 18 and the second trace T2_4 on the second mating surface 28 of the disclosed planar inductive element 100 can be mirror-configured, a better effect can be achieved. Specifically, assuming that Figures 4A and 4B are the mating surfaces 18 and 28 of the first trace T1_1 and the second trace T2_4, respectively, and the shapes of the first trace T1_1 and the second trace T2_4 are exactly the same as the number of turns around the through holes H1 and H2, the first trace T1_1 and the second trace T2_4 are mirror-configured. Therefore, when the two mating surfaces 18 and 28 are mated, the first trace T1_1 and the second trace T2_4 can completely overlap and stack. Because the two are mirror images of each other, when current I flows through the first trace T1_1 and the second trace T2_4 on the two mating surfaces 18 and 28, there is almost no voltage difference at any specific point on the first trace T1_1 and the second trace T2_4 at the same point, so the potentials at the same points are the same (for example, if the potential of the first trace T1_1 at a certain point on the mating surface 18 is 50V, then the potential of the second trace T2_4 at the same point on the mating surface 28 should also be 50V). Therefore, the requirement for the surface paint thickness will be lower.

[0061] Furthermore, referring to the X, Y, and Z axes in Figure 5B, the first trace T1_1 and the second trace T2_4 are mirror images of each other on the planes defined by the X and Y axes. Therefore, the first trace T1_1 on the first mating surface 18 and the second trace T2_4 on the second mating surface 28 have the same potential at the same X-axis and Y-axis coordinate values ​​along the Z-axis direction. Similarly, if the first traces T1_2~T1_4 on other layers and the corresponding second traces T2_3~T2_1 on the corresponding layers are also mirror images, then the first traces T1_2~T1_4 and the second traces T2_3~T2_1 will also have the same potential at the same X-axis and Y-axis coordinate values ​​along the Z-axis direction.

[0062] It is worth mentioning that in Figures 7A and 7B, only the case where the impedances of the first traces T1_1~T1_4 and the second traces T2_1~T2_4 are the same across all layers is shown, so that the voltage received by each layer is exactly 1 / 4. However, the impedances of the first traces T1_1~T1_4 and the second traces T2_1~T2_4 can be different, resulting in different voltage divisions across each layer. For example, but not limited to, if the impedance distribution of the first traces T1_1~T1_4 across the four layers of the board is 0.5, 0.5, 2, and 1, then the voltages V1~V4 received by each layer should be 50V, 50V, 200V, and 100V. Therefore, as long as the impedance formed by the first traces T1_1 to T1_4 on each layer of the first circuit board 1 is approximately equal to the impedance formed by the second traces T2_4 to T2_1 on the corresponding layers of the second circuit board 2 (i.e., the first traces T1_1 to T1_4 correspond to the second traces T2_4 to T2_1 respectively), the effect disclosed in Figures 7A to 7B can be achieved.

[0063] On the other hand, in one embodiment, the impedance of traces T1_1~T1_4 and T2_1~T2_4 is related to the number of turns of each layer's traces T1_1~T1_4 and T2_1~T2_4 around the vias H1 and H2, as well as the thickness of the traces T1_1~T1_4 and T2_1~T2_4. However, except for the traces T1_1 and T2_4 on mating surfaces 18 and 28, which can achieve special effects by being mirrored, the other layers are mainly considered in terms of impedance magnitude. Therefore, there is no requirement for a corresponding relationship between the number of turns and the thickness of each layer's traces T1_2~T1_4 and T2_1~T2_3. Conversely, if the number of turns and the thickness of the traces T1_2~T1_4 and T2_1~T2_3 on the corresponding layers are the same, it can be reasonably inferred that the impedances of the two corresponding layers should be the same.

[0064] Furthermore, due to the characteristics of circuit boards, the heat dissipation effect is generally better on the surface layer or the outermost layer. Conversely, the heat dissipation effect is generally poor on the innermost layer, as it is stacked with one or more other layers above and below it. Therefore, the first traces T1_1~T1_4 and T2_1~T2_4 of each layer of the first circuit board 1 disclosed herein can utilize this characteristic to increase the heat dissipation effect. That is, the number of turns and trace thickness of the first traces T1_1 and T1_4 (especially the first trace T1_4 of the fourth layer L4) of the first circuit board 1 can be designed to have higher impedance (for example, but not limited to configuring a first trace T1_4 with more turns), thereby reducing the impedance of the second layer L2 and the third layer L3, thus improving the heat dissipation efficiency. The design of the second circuit board 2 is similar, and will not be elaborated here.

[0065] On the other hand, referring to Figures 7A-7C, the circuit boards 1 and 2 disclosed herein are four-layer boards, but their number can be increased or decreased according to actual needs. For example, but not limited to, the second layer L2 and the third layer L3 of circuit boards 1 and 2 can be removed. Alternatively, the second circuit board 2 can have two additional layers LA and LB (shown as dashed frames in Figures 7A-7C) added to form a six-layer board. Furthermore, additional traces can be configured on the extra layers LA and LB. The same applies to the first circuit board 1 and the third circuit board 3, and will not be elaborated further here.

[0066] Referring to Figures 3A-7C, the planar inductive element 100 disclosed herein can be a planar inductor or a planar transformer. Specifically, when the planar inductive element 100 is a planar inductor, a parallel inductor coil (i.e., coil assembly) can be formed by connecting the first coil W1 and the second coil W2 in parallel, and the planar inductor is further formed by the installation of the iron core C. When the planar inductive element 100 is a planar transformer, one of the primary-side coils or the secondary-side coils (i.e., primary-side coil or secondary-side coil assembly) can be formed by connecting the first coil W1 and the second coil W2 in parallel. Furthermore, the other of the primary-side coils or the secondary-side coils can have various configurations.

[0067] Specifically, referring to Figures 7A-7C, the primary coil or the other of the secondary coil can be configured on an additional layer board LA, LB, or as shown in Figure 7C, on an additional circuit board (i.e., the third circuit board 3), so as to form a planar transformer by passing the first core post C1 through the first through hole H1 and the second through hole H2. Alternatively, referring to Figure 4A, the other of the primary coil or the secondary coil can be configured on the same layer as the first trace T1_1~T1_4 (or the second trace T2_1~T2_4) for a specific trace Ts, and can also form a planar transformer by passing the first core post C1 through the first through hole H1 and the second through hole H2.

[0068] On the other hand, Figure 8 is a cross-sectional view of one embodiment of the planar transformer disclosed herein. The circuit structure in Figure 8 is a cross-sectional view of the planar inductive element 100 after assembly, using the second axis A2 as shown in Figure 4B. In Figure 8, the circuit structure of the third circuit board 3 is similar to that of circuit boards 1 and 2, and includes a third through hole H3. The third circuit board 3 is mainly used for routing the other of the primary side coil WP or the secondary side coil WS (taking the secondary side coil WS as an example here), and the iron core C further includes a second iron core post C2. When the first iron core component C-1 and the second iron core component C-2 of the iron core C are sleeved on circuit boards 1, 2, and 3, the first iron core post C1 passes through the first through hole H1 and the second through hole H2, and the second iron core post C2 passes through the third through hole H3. In this way, a planar transformer can also be formed. It is worth mentioning that, in one embodiment, the iron core C in Figure 8 can be U-shaped, or it can be, for example, but not limited to, UU-shaped iron cores, etc., without limitation.

[0069] However, the above description is only a detailed description and illustration of preferred embodiments of the present invention. The features of the present invention are not limited thereto and are not intended to limit the present invention. The scope of the present invention should be determined by the following claims. All embodiments that conform to the spirit of the claims and similar variations of the present invention should be included in the scope of the present invention. Any variations or modifications that can be easily conceived by those skilled in the art within the field of the present invention can be covered by the following claims.

[0070] 100: Flat-plate inductive element W: Coil 1: First circuit board 12: Wiring Department H1: First perforation 14: Connecting part T1, T1_1~T1_4: First routing line T1_1_H: First high voltage terminal T1_1_L: First low voltage terminal W1: First coil W1-1: First End W1-2: Second end 16: Circuit Section Ts: Specific routing 2: Second circuit board 22: Wiring Department H2: Second perforation 24: Connecting part T2, T2_1~T2_4: Second routing line T2_N_H: Second high voltage terminal T2_N_L: Second low voltage terminal W2: Second coil W2-1: Third end W2-2: Fourth End via: through hole L1~L4, LA, LB: Layers 18: First mating surface 28: Second mating surface 3: Third circuit board H3: Third perforation T3_1~T3_4: Third routing line W3: Third coil W3-1: Fifth End W3-2: Sixth End 38: Third bonding surface 48: Fourth bonding surface WP: Primary side coil WS: Secondary coil C: Iron core C-1: First core component C-2: Second core component C1: First core post C2: Second core post I: Current R: Equivalent impedance V1~V4: Voltage E1: First transverse pressure E2: Second transverse pressure E3: Third transverse pressure E4: Fourth Transpressor A1: First axis A2: Second axis

Claims

1. A planar inductive element, comprising: A first circuit board includes a first coil, a first through-hole, and a first mating surface. The first coil includes a plurality of first traces, and the plurality of first traces are respectively wrapped around the first through-hole. A second circuit board includes a second coil, a second through-hole, and a second mating surface for mating with the first mating surface. The second coil includes a plurality of second traces, and the plurality of second traces are respectively wrapped around the second through-hole. A core includes a first core post. The first coil is electrically connected to the second coil to form a parallel structure, and the first core post passes through the first through-hole and the second through-hole to form the planar inductive element. Among them, one of the multiple layers of first traces located on the first bonding surface has a first high voltage terminal and a first low voltage terminal, and one of the multiple layers of second traces located on the second bonding surface has a second high voltage terminal and a second low voltage terminal; when a current flows through the planar inductive element, the potentials of the first low voltage terminal and the second low voltage terminal are approximately the same, and the potentials of the first high voltage terminal and the second high voltage terminal are approximately the same.

2. The planar inductive element as described in claim 1, wherein the first trace and the second trace of the layer are mirror images of each other, such that the potential at any specific point on the first trace is the same as the potential at the same location on the second trace of the layer.

3. The planar inductive element as described in claim 1, wherein on a plane defining an X-axis and a Y-axis, the first trace and the second trace of the layer are mirror images of each other, such that the first trace and the second trace of the layer have the same potential at positions corresponding to the same X-axis coordinate value and the same Y-axis coordinate value along a Z-axis direction, wherein the X-axis, Y-axis and Z-axis are perpendicular to each other.

4. The planar inductive element as described in claim 1, wherein the current flows in from the end of the first trace of the layer and the end of the second trace of the layer, such that the first bonding surface and the second bonding surface are both high voltage layers.

5. The planar inductive element as described in claim 1, wherein the current flows out from the end of the first trace of the layer and the end of the second trace of the layer, such that the first bonding surface and the second bonding surface are both low-voltage layers.

6. The planar inductive element as described in claim 1, wherein the impedance of the plurality of first traces in each layer is approximately equal to the impedance of the plurality of second traces in the corresponding layer.

7. The planar inductive element as described in claim 1, wherein the impedance of the outer layer of the first circuit board is greater than the impedance of each layer within the outer layer of the first circuit board.

8. The planar inductive element as described in claim 1, wherein the impedance of the outer layer of the second circuit board is greater than the impedance of each layer within the outer layer of the second circuit board.

9. A planar inductive element as described in claim 1, wherein the end of the first trace of the first layer forms a first end of the first coil, and the end of another first trace of the plurality of first traces, which is away from the first trace of the first layer, forms a second end of the first coil; the end of another second trace of the plurality of second traces, which is away from the second trace of the first layer, forms a third end of the second coil, and the end of the second trace of the second layer forms a fourth end of the second coil; the first end is electrically connected to the fourth end, and the second end is electrically connected to the third end, to form a parallel structure.

10. The planar inductive element as described in claim 9, wherein the planar inductive element is a planar inductor, and the first coil and the second coil form an inductor coil in parallel.

11. The planar inductive element as described in claim 9, wherein the planar inductive element is a planar transformer, and the first coil and the second coil form a primary-side coil or a secondary-side coil in parallel.

12. A planar inductive element as described in claim 11, wherein the primary coil or the other of the secondary coil is disposed on the first circuit board or the second circuit board to form the planar transformer by means of the first core post passing through the first through hole and the second through hole.

13. The planar inductive element as described in claim 11, wherein the core further includes a second core post, and the primary coil or the secondary coil is disposed on a third circuit board; the first core post passes through the first through hole and the second through hole, and the second core post passes through a third through hole of the third circuit board to form the planar transformer.

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