Method for controlling logical units of flash memory and related memory controller and data storage device

Abstract

A method for controlling a plurality of logical units in a flash memory includes: transmitting on-chip terminal enable control information on a control bus corresponding to the plurality of logical units via a data transfer start command to enable on-chip terminal operation of one or more non-target logical units; and transmitting on-chip terminal disable control information on the control bus via a data transfer stop command or a data transfer pause command to disable on-chip terminal operation of the one or more non-target logical units.

Description

Technical Field

[0001] This invention relates to flash memory, and more particularly to a method for enhancing on-chip terminal control of the logic units of flash memory, as well as related memory controllers and data storage devices. Prior Technology

[0002] In modern NAND flash memory devices, efficient communication between the memory controller and the flash memory is crucial. While traditional parallel interfaces can function, they require a large number of pins and may face signal integrity challenges at high speeds. As NAND flash memory devices continue to evolve, achieving higher densities and faster operating speeds, the demand for more efficient command and data transfer protocols is increasing.

[0003] The Separate Command Address Architecture (SCA) protocol was developed to address these challenges. This protocol defines the communication interface between the memory controller and flash memory, providing a streamlined and efficient method for command and data transmission. However, existing SCA implementations face issues related to command efficiency and latency. With the increasing demands of NAND flash memory applications, particularly in enterprise-level storage systems and high-performance computing environments, the need for enhanced protocol functionality that better supports various operations is also growing. Summary of the Invention

[0004] In view of this, one of the objectives of the present invention is to provide an on-die termination control mechanism. Specifically, the present invention enables on-die termination of non-target logic units by embedding on-die termination enable control information into a data burst start command. Simultaneously, the present invention also disables on-die termination of non-target logic units by embedding on-die termination disable control information into a data burst terminate command or a data burst pause command. In embodiments of the present invention, the data burst start command embedding on-die termination enable control information can be a select chip enable (SCE) packet defined in the SCA protocol, wherein the present invention uses reserved bits in the SCE packet to record on-die termination enable control information. Furthermore, the data burst terminate command or data burst pause command embedding on-die termination disable control information can be a select chip terminate (SCT) packet or a select chip pause (SCP) packet defined in the SCA protocol. The present invention uses reserved bits in the SCT or SCP packet to record on-die termination disable control information. By embedding on-chip terminal control information into existing data burst start and data burst stop / pause commands, the efficiency of on-chip terminal control can be improved.

[0005] An embodiment of the present invention provides a method for controlling a plurality of logical units in a flash memory. The method includes: transmitting on-chip terminal enable control information on a control bus corresponding to the plurality of logical units via a data transmission start command to enable on-chip terminal operation of one or more non-target logical units; and transmitting on-chip terminal disable control information on the control bus via a data transmission stop command or a data transmission pause command to disable on-chip terminal operation of the one or more non-target logical units.

[0006] Embodiments of the present invention provide a memory controller for controlling a plurality of logical units in a flash memory. The memory controller includes a storage unit and a processing unit. The storage unit stores program code. The processing unit executes the program code to perform operations on the flash memory, including: transmitting on-die termination (ODT) enable control information on a control bus corresponding to the plurality of logical units via a data transfer start command to enable ODT operation of one or more non-target logical units; and transmitting on-die termination disable control information on the control bus via a data transfer stop command or a data transfer pause command to disable ODT operation of the one or more non-target logical units. Simple Explanation of the Diagram

[0007] Figure 1 illustrates the architecture of an electronic device and a data storage device according to an embodiment of the present invention. Figure 2 illustrates how the memory controller manages and controls the logic units of non-volatile memory through chip enable control. Figure 3 illustrates the structure of the SCE packet. Figure 4 illustrates the structure of an SCT or SCP packet. Figure 5A illustrates a timing diagram of non-target ODT control according to an embodiment of the present invention. Figure 5B illustrates a timing diagram of non-targeted ODT control according to another embodiment of the present invention. Figure 6 illustrates a flowchart of a method for controlling the logic unit of flash memory according to an embodiment of the present invention. Implementation

[0008] Embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the inventive concept can be embodied in various different forms and should not be construed as limited to the embodiments shown. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the inventive concept to those skilled in the art. Therefore, known processes, elements, and techniques relating to some embodiments of the inventive concept will not be described. Unless otherwise stated, the same reference numerals in the drawings and written description denote the same elements and are therefore not repeated. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0009] The terms "an embodiment" or "an example" used in this specification mean that a particular feature, structure, or characteristic shown in that embodiment or example will be included in at least one embodiment of the invention. Therefore, the terms "in an embodiment" or "in an example" appearing throughout this specification do not all refer to the same embodiment. Furthermore, specific features, structures, or characteristics of the invention can be combined in any suitable combination and / or sub-combination to be implemented in one or more embodiments.

[0010] Figure 1 illustrates a schematic diagram of the architecture of an electronic device and a data storage device according to an embodiment of the present invention. As shown, the electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include: at least one processor 52 for controlling the operation of the host device 50, and a random-access memory (RAM) 54 for storing data and information required by the processor 52. Examples of the host device 50 may include (but are not limited to): smartphones, tablets, wearable devices, personal computers (such as desktop computers or laptops), image capturing devices (such as digital cameras or camcorders), game consoles, in-vehicle navigation systems, printers, scanners, or server systems. Examples of the data storage device 100 may include, but are not limited to: portable memory devices (such as memory cards conforming to SD / MMC, CF, MS, XD, or UFS specifications), solid-state drives (SSDs), and various embedded storage devices (such as embedded storage devices conforming to UFS or eMMC specifications).

[0011] In different embodiments of the present invention, the data storage device 100 may include a memory controller 110 and further include non-volatile (NV) memory 120. NV memory 120 may include one or more NV memory elements, such as a plurality of NV memory elements (MUs) 122-1-122_N. In some embodiments, NV memory 120 may be NAND flash memory, and NV memory elements 122_1-122_N may be a plurality of NAND flash memory chips or a plurality of NAND flash memory dies, but the present invention is not limited thereto.

[0012] In some embodiments, the NV memory 120 may include multiple memory blocks (BLKs), which may be grouped into multiple superblocks (SBLKs). A memory block (BLK) may be a physical block containing multiple memory cells. A superblock (SBLK) may be a unit of logical memory regions used by the memory controller 110 to manage the NV memory 120. Furthermore, the composition of the superblocks (SBLKs) may span NV memory chips 122_1 to 122_N. A memory block (BLK) may be a memory cell array, where multiple memory cells form a two-dimensional or three-dimensional array structure. A memory cell may be a single-level storage cell programmed with one bit of information, or a multi-level storage cell programmed with two or more bits of information (e.g., a two-level, three-level, or four-level storage cell). Additionally, a memory block (BLK) may contain multiple pages, where a page may consist of memory cells connected to the same word line. Additionally, a memory block (BLK) may be the unit of an erase operation, while a page may be the unit of a program and a read operation.

[0013] In some embodiments, each NV memory die 122_1 to 122_N is equipped with control circuitry for executing memory operation commands issued by the memory controller 110. Each NV memory die 122_1 to 122_N may contain multiple planes, each plane having multiple blocks composed of memory storage cells, and associated row and column control circuitry. Through multi-plane operation commands, various memory operations can be performed in parallel on different planes to perform multi-plane read, write, or erase operations.

[0014] Furthermore, the NV memory 120 may contain one or more targets. A target is controlled by a chip select enable (e.g., CE_n). A target is organized into one or more logical units (LUNs). A logical unit is the smallest unit that can independently execute commands and report its status. Specifically, different logical units can operate in parallel with arbitrary command sequences. For example, a page programming operation can be initiated on the first logical unit, and a read command can be initiated on the second logical unit before that operation completes. A logical unit contains at least one page register and a flash array. The number of page registers depends on the number of multi-plane operations supported by the logical unit. The flash array contains blocks, and a block contains pages, and a page consists of bytes or words. Furthermore, each logical unit should have at least one page register. The page register is used for temporary storage before data is moved to a page in the flash array or after data is moved out of a page in the flash array. The position of a byte or word in a page register is called a column. This architecture has two mechanisms for parallel processing: issuing multiple commands to different logic units simultaneously, and using multi-plane operations to execute additional dependent operations in parallel, thereby achieving greater parallelism within a logic unit.

[0015] The memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, internal memory 113, a transmission interface circuit 118, and error checking and correction (ECC) processing circuitry 130. At least a portion of these circuits and components may be coupled to each other via a bus. The internal memory 113 may be implemented by one or more RAM devices. For example, the internal memory 113 may include static RAM (SRAM) and / or dynamic RAM (DRAM). The internal memory 113 may be used to provide internal storage space for the memory controller 110, such as temporarily storing information like data, addresses, commands, mapping information, variables, and / or parameters. In some embodiments, the memory controller 110 may not include DRAM. Instead, the memory controller 110 may rely on host memory buffer (HMB) technology. Using HMB technology, the memory controller 110 can utilize the RAM 54 (e.g., DRAM) of the host device 50 as all, part or an extension of the internal memory 113, thereby improving the read and write performance of the data storage device 100.

[0016] Furthermore, in this embodiment, ROM 112M is used to store program code 112C, and processing unit 112 is used to execute program code 112C, thereby controlling access to NV memory 120. Program code 112C may contain one or more program modules, such as boot loader code. When data storage device 100 obtains power from host device 50, processing unit 112 can initiate the initialization process of data storage device 100 by executing program code 112C. During the initialization process, microprocessor 112 can load a set of in-system programming (ISP) code from NV memory 120. Microprocessor 112 can execute ISP code, enabling data storage device 100 to perform various functions. According to one embodiment of the present invention, ISP code may include, but is not limited to, one or more program modules related to memory access (e.g., reading, programming, and erasing), such as a read operation module, a lookup table module, a wear-leveling module, a read refresh module, a read reclaim module, a garbage collection module, and a sudden power-off recovery (SPOR) module. These modules are used to perform corresponding read, lookup table, wear-leveling, read refresh, read reclaim, garbage collection, SPOR, and other operations.

[0017] The memory controller 110 can control the reading, writing, and erasing of the NV memory 120 through the control logic circuit 114. In addition, the memory controller 110 can simultaneously process host commands from the host device 50 to write data, and read and rewrite valid data from the NV memory 120 through garbage collection and / or wear leveling operations. The transmission interface circuit 118 may conform to specific communication specifications, such as Universal Serial Bus (USB), Secure Digital (SD) interface or its subsequent upgrades, Ultra High Speed-I (UHS-I) interface, Ultra High Speed-II (UHS-II) and its subsequent upgrades, CompactFlash (CF) interface and its subsequent upgrades, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) specification, Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Peripheral Component Interconnect Express (PCI-E), and Universal Flash Storage (UFS) specification, and may communicate with the host device 50 according to the specific communication specifications.

[0018] Typically, host device 50 may indirectly access memory device 100 by transmitting host commands and corresponding logical addresses to memory controller 110. Memory controller 110 receives host commands and logical addresses, converts host commands into memory operation commands, and further uses memory operation commands to control NV memory 120 to perform read, program, or erase operations on memory storage units or data pages with physical addresses within NV memory 120.

[0019] In some embodiments, a logical-to-physical (L2P) address mapping table with multiple logical-to-physical (L2P) address mapping entries can be divided into multiple mapping groups. Each mapping group contains a portion of the entire L2P address mapping table for performing logical-to-physical address translation. These L2P mapping groups are permanently stored in blocks of NV memory 120 and loaded into internal memory 113 when needed. Similarly, a physical-to-logical (P2L) address mapping table with multiple physical-to-logical (P2L) address mapping entries can be divided into multiple mapping groups. Each mapping group contains a portion of the P2L address mapping table for performing physical-to-logical address translation. These P2L mapping groups are permanently stored in blocks of NV memory 120.

[0020] Typically, the memory controller 110 uses chip enable signals to control the enabling of NV memory cells 122_1 to 122_N. When the memory controller 110 needs to communicate with a target NV memory cell to perform an access operation, the chip enable signal corresponding to the target NV memory cell will be in an active state, allowing the target memory cell to perform active operations, including data input and / or output. Meanwhile, the chip enable signals corresponding to other (i.e., non-target) NV memory cells will be in an inactive state, preventing their active operations and putting these NV memory cells into a low-power standby mode, with their outputs in a floating state.

[0021] Figure 2 illustrates how the memory controller 110 manages and controls the logical units (LUNs) of the NV memory 120 via chip enable control based on the Separate-Command-Address (SCA) protocol. In this example, the memory controller 110 controls LUNs L0 to L3 via command / address (CA) bus 301, data input / output (DQ) bus 302, a first CA bus enable signal (e.g., signal CA_CE0#) 303, and a second CA bus enable signal (e.g., signal CA_CE1#) 304. Note that the number of LUNs and bus enable signals mentioned above is for illustrative purposes only.

[0022] Specifically, the first CA bus enable signal 303 is used to enable CA bus 301 for LUN L0 and LUN L1, while the second CA bus enable signal 304 is used to enable CA bus 301 for LUN L2 and LUN L3. When the first CA bus enable signal 303 is active (active low), LUN L0 and LUN L1 are allowed to respond to control signals / commands and addresses on CA bus 301. Similarly, when the second CA bus enable signal 304 is active, LUN L2 and LUN L3 are allowed to respond to control signals / commands and addresses on CA bus 301.

[0023] Furthermore, NV memory 120 implements on-die termination (ODT), a technology designed to improve signal integrity on the DQ bus 302 by independently turning on / off the termination resistors of any or all LUNs in NV memory 120 via memory controller 110. This is because data exchange between memory controller 110 and LUNs L0-L3 relies on the shared DQ bus 302. To prevent data signals from being interfered with by reflections from non-target LUNs, ODT for non-target LUNs can be selectively enabled on the DQ bus 302, thereby adjusting the ODT behavior of specific non-target LUNs according to system requirements.

[0024] More specifically, the memory controller 110 sends ODT enable control information and ODT disabling control information to the LUN, thereby enabling or disabling ODT operation for non-target LUNs. In some embodiments, the ODT enable control information and ODT disabling control information can be implemented by issuing non-target ODT (NTO) packets on the CA bus 301. Please refer to Figure 2 and Figure 5A for further understanding, where Figure 5A illustrates a timing diagram of the non-target ODT control mechanism of an embodiment of the present invention. In the embodiment shown in Figure 5A, it is assumed that the access target is LUN L0 in the example of Figure 2. To enable non-target ODT operation on the DA bus 302, the memory controller 110 first issues a first type of NTO packet PA1 on the CA bus 301 to instruct those LUNs controlled by one or more bus enable signals that do not correspond to the target LUN to enable their ODT. In this embodiment, since the access target (i.e., the target LUN) is LUN L0, this means that the first type of NTO packet PA1 will be used to indicate LUN L2 and LUN L3 controlled by the bus enable signal CA_CE1#, which does not correspond to the target LUN L0. As shown in Figure 5A, when the second bus enable signal CA_CE1# is active (active low), LUN L2 and LUN L3 will receive and respond to the first type of NTO packet PA1, thereby enabling the ODT operation of LUN L2 and LUN L3 to provide ODT (i.e., state STA3) on the DQ bus 302.

[0025] Then, the memory controller 110 issues a second type NTO packet PA2 on the CA bus 301 to instruct the LUNs controlled by the same bus enable signal as the target LUN to enable ODT operation on the DA bus 302. The second type NTO packet also contains address information about the LUN that needs to enable ODT operation. Since the access target (i.e., the target LUN) is LUN L0, this means that the second type NTO packet PA2 will be used to instruct LUN L1 to enable ODT. As shown, when the first bus enable signal CA_CE0# is active (active low), LUN L0 and LUN L1 will receive the second type NTO packet PA2. Since LUN L1 is addressed by the second type NTO packet PA2, the ODT operation of LUN L1 will be enabled to provide ODT (i.e., status STA2) on the DQ bus 302 in response to the second type NTO packet PA2.

[0026] After the first and second types of NTO packets PA1 and PA2 successfully indicate that the non-target LUN has enabled ODT, the memory controller 110 will issue a select chip enable (SCE) packet PA3 on the CA bus 301 to instruct the target LUN L0 to start or resume a data burst operation, thereby inputting or outputting data on the DQ bus 302 (i.e., state STA1). After the data burst operation is completed, or when a pause is required, the memory controller 110 will issue a select chip terminate (SCT) or select chip pause (SCP) packet PA4 on the CA bus 301 to instruct the target LUN L0 to stop or pause the data burst operation on the DQ bus 302 (i.e., end of state STA1).

[0027] Furthermore, the memory controller 110 will issue a third type NTO packet PA5 on the CA bus 301 to instruct LUNs controlled by the same bus enable signal as the target LUN, wherein the third type NTO packet contains address information about the LUNs whose ODT operations need to be disabled. In this example, the third type NTO packet PA5 is used to instruct LUN L1 to disable ODT operations. In response to the third type NTO packet PA5, LUN L1 will disable ODT operations on the DQ bus 302 (i.e., the end of state STA2). Then, the memory controller 110 will issue a fourth type NTO packet PA6 on the CA bus 301 to instruct LUNs controlled by one or more bus enable signals that do not correspond to the target LUN to disable their ODT operations. That is, the fourth type NTO packet PA6 is used to instruct LUN L2 and LUN L3 to disable ODT operations on the DQ bus 302 (i.e., the end of state STA3).

[0028] In this embodiment, the number of second-type NTO packets PA2 (for enabling ODT operations of non-target LUNs controlled by the same bus enable signal as the target LUN) and third-type NTO packets PA5 (for disabling ODT operations of non-target LUNs controlled by the same bus enable signal as the target LUN) issued by the memory controller 110 will significantly increase with the number of non-target LUNs controlled by the same bus enable signal as the target LUN. In the above embodiment, since the number of non-target LUNs controlled by the same bus enable signal CA_CE0# as the target LUN L0 is "1" (i.e., LUN L1), the memory controller 110 only needs to issue one NTO packet PA2 and one NTO packet PA5. However, if the bus enable signal CA_CE0# is designed to control a larger number of LUNs, such as four LUNs, then the memory controller 110 needs to issue three NTO packets PA2 and three NTO packets PA5 to control the ODT operations of these non-target LUNs. As the number of LUNs with enabled signals on the shared bus increases, this method becomes less and less efficient.

[0029] To improve the efficiency of non-target ODT control, this invention provides another method for transmitting ODT enable control information and ODT disable control information. In one embodiment, the memory controller 110 uses SCE packets to transmit ODT enable control information to non-target LUNs controlled by the same bus enable signal as the target LUN, thereby instructing them to enable ODT operation. In another embodiment, the memory controller 110 uses SCT or SCP packets to transmit ODT disable control information to non-target LUNs controlled by the same bus enable signal as the target LUN, thereby instructing them to disable ODT operation.

[0030] Figure 3 illustrates a typical structure of an SCE packet. As shown, an SCE packet includes: header bits h[0]~h[3] indicating the current packet type (indicating that the packet is starting or resuming a data burst operation on the DQ bus); address bits a[0]~a[3] indicating the LUN address of the target LUN; burst direction bits DIR indicating the direction of the data burst operation; and reserved bits r[1]~r[3]. In one embodiment, the memory controller 110 is used to set the value of at least one of the reserved bits r[1]~r[3] to indicate the enabled state of the ODT operation (e.g., as the enable bit NTEN). Furthermore, the memory controller 110 is further configured to set the value of at least one second bit in the reserved bits r[1] to r[3] of the SCE packet, thereby indicating the direction of the data burst operation (e.g., as the burst direction bit NTDIR), thereby indicating that ODT for the data input burst or ODT for the data output burst is enabled on the DQ bus 302. By embedding the ODT enable control information into the SCE packet (i.e., setting bits in the reserved bits r[1] to r[3] to indicate the enable status and burst direction), ODT operation of a non-target LUN controlled by the same bus enable signal as the target LUN can be effectively enabled.

[0031] Specifically, when a non-target LUN controlled by the same bus enable signal as the target LUN receives an SCE packet containing ODT enable control information, the non-target LUN will parse address bits a[0]~a[3] to determine the LUN address of the target LUN. Once the non-target LUN detects that it is not addressed by the LUN address of the target LUN, the non-target LUN will further parse reserved bits r[1]~r[3] to determine whether to enable ODT operation based on the ODT enable control information embedded therein.

[0032] Figure 4 illustrates a typical structure of an SCT or SCP packet. As shown, an SCT or SCP packet includes: header bits h[0]~h[3] indicating the current packet type (indicating that the packet is for terminating or pausing a data burst operation currently in progress on DQ bus 302); address bits a[0]~a[3] indicating the LUN address of the target LUN; and reserved bits r[0]~r[3]. In one embodiment, memory controller 110 is used to set the value of at least one of the reserved bits r[0]~r[3] in the SCT or SCP to indicate the disabled state of ODT operation (e.g., as the enable bit NTEN). Optionally, the memory controller 110 is further configured to set the value of at least one second bit in the reserved bits r[0]~r[3] of the SCT or SCP packet to indicate the direction of the ongoing data burst operation (e.g., as the burst direction bit NTDIR), thereby indicating that ODT for data input bursts or ODT for data output bursts is disabled on the DQ bus 302. By embedding ODT disable control information in the SCT or SCP packet (i.e., setting bits in the reserved bits r[0]~r[3] to indicate the disable status and the optional burst direction), ODT operation of a non-target LUN controlled by the same bus enable signal as the target LUN can be effectively disabled.

[0033] In particular, when a non-target LUN controlled by the same bus enable signal as the target LUN receives an SCT or SCP packet containing ODT disable control information, the non-target LUN will parse address bits a[0]~a[3] to determine the LUN address of the target LUN. Once the non-target LUN detects that it is not specified by the LUN address of the target LUN, the non-target LUN will further parse reserved bits r[0]~r[3] to determine whether to disable ODT operation based on the ODT disable control information embedded therein.

[0034] Please refer to Figure 5B, along with Figure 2, for further understanding. Figure 5B illustrates the timing diagram of the non-targeted ODT control mechanism of an embodiment of the present invention. First, the second bus enable signal CA_CE1# will be set to an active state (this signal is active low), which will enable the CA bus 301 for LUN L2 and LUN L3. Accordingly, LUN L2 and LUN L3 will receive and respond to the NTO packet PB1 issued by the memory controller 110, thereby enabling the ODT operation of LUN L2 and LUN L3 to provide ODT (i.e., state STB3) on the DQ bus 302.

[0035] Subsequently, the second bus enable signal CA_CE1# will be set to inactive, while the first bus enable signal CA_CE0# will be set to active (active low), enabling bus 301 for LUN L0 and LUN L1. At this time, LUN L0 and LUN L1 will receive and respond to the SCE packet PB2 containing ODT enable control information issued by the memory controller 110. For the target LUN L0, it will start or resume data burst operation on the DQ bus 302 (i.e., state STB1). For the non-target LUN L1, it will detect that it is not specified by the LUN address contained in the SCE packet. Therefore, the non-target LUN L1 will parse the reserved bits in the SCE packet and respond with the ODT enable control information (e.g., enable status and burst direction) indicated by the specific reserved bits in the SCE packet, thereby enabling ODT operation to provide ODT on the DQ bus 302 (i.e., state STB2).

[0036] On the other hand, once the ongoing data burst operation is complete or needs to be paused, the memory controller 110 will issue an SCT or SCP packet embedded with ODT disable control information on the CA bus 302. Since the first bus enable signal CA_CE0# remains active, LUN L0 and LUN L1 will receive and respond to the SCT or SCP packet PB3 embedded with ODT disable control information issued by the memory controller 110. For the target LUN L0, it will terminate or pause the ongoing data burst operation on the DQ bus 302 (i.e., the end of state STB1). For the non-target LUN L1, it will detect that it is not specified by the LUN address contained in the SCT or SCP packet. Therefore, the non-target LUN L1 will parse the reserved bits in the SCT or STP packet and respond with the ODT disable control information (e.g., disable status and / or burst direction) indicated by the reserved bits in the SCT or SCP packet, thereby disabling ODT operation on the DQ bus 302 (i.e., the end of state STB2).

[0037] Finally, the second bus enable signal CA_CE1# will be set to active, and the first bus enable signal CA_CE0# will be set to inactive, which will enable the CA bus 301 for LUN L2 and LUN L3. Accordingly, LUN L2 and LUN L3 will receive and respond to the NTO packet PB4 issued by the memory controller 110, thereby disabling ODT operation on the DQ bus 302 (i.e., the end of state STB3).

[0038] Figure 6 illustrates a flowchart of a method for controlling multiple logic units of flash memory with an enhanced on-chip terminal control mechanism in an embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0039] Step S101: Transmit on-chip terminal enable control information on a control bus corresponding to multiple logic units via a data transmission start command to enable on-chip terminal operation of one or more non-target logic units; and

[0040] Step S102: Transmit on-chip terminal disable control information on the control bus via a data transmission termination command or a data transmission pause command to disable the on-chip terminal operation of the one or more non-target logic units.

[0041] Since the principles and specific details of the above steps have been clearly described in the above embodiments, they will not be repeated here. It should be noted that the above process can be improved by adding other additional steps or making appropriate modifications and / or adjustments to achieve better performance of flash memory.

[0042] Please note that while the above embodiments describe embedding ODT enable control information in SCE packets of the SCA protocol and embedding ODT disable control information in SCT or SCP packets of the SCA protocol, the present invention is not limited to these specific implementations. ODT control information can be embedded in any appropriate command packet used to manage data transfer between the memory controller and the memory device. For example, ODT enable control information can be embedded in, but is not limited to: data transfer start commands, data transfer initialization commands, read / write preparation commands, or any commands in various communication protocols that indicate the start of data transfer. Similarly, ODT disable control information can be embedded in, but is not limited to: data transfer termination commands, data transfer pause commands, data transfer completion commands, or any commands in various communication protocols that indicate the end of data transfer operations or a temporary pause.

[0043] Embodiments of the present invention can be implemented as an apparatus, method, or computer program product. Accordingly, embodiments of the present invention may take the form of a completely hardware implementation, a completely software implementation, or a combination of software and hardware aspects, all of which are collectively referred to as "modules" or "systems" in this specification. Furthermore, embodiments of the present invention may take the form of a computer program product embodied in any tangible medium containing computer-usable code. In terms of hardware, the present invention can be implemented by applying any of the following techniques or related combinations: individual operation logic having logic gates capable of performing logical functions according to data signals, and application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), or field-programmable gate arrays (FPGAs) having appropriate combinatorial logic.

[0044] The flowcharts and block diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that each block in the block diagram and / or flowchart description, and combinations of blocks in the block diagram and / or flowchart description, may be implemented by a dedicated hardware system that performs the specified function or action, or a combination of dedicated hardware and computer instructions. These computer program instructions may be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture containing means of instruction to implement the functions / actions specified in the blocks of the flowchart and / or block diagram. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0045] 10: Electronic devices

[0046] 50: Main unit

[0047] 52: Processor

[0048] 54: RAM

[0049] 100: Data storage device

[0050] 110: Memory controller

[0051] 112: Processing Unit

[0052] 112M:ROM

[0053] 112C: Code

[0054] 113: Internal Memory

[0055] 114: Control Logic Circuit

[0056] 118: Transmission Interface Circuit

[0057] 130: ECC processing circuit

[0058] 120: NV Memory

[0059] 122_1~122_2: NV memory units

[0060] BLK: Block

[0061] SBLK: Super Block

[0062] LUN L0~L3: Logic Unit

[0063] 301: Command / Address Bus

[0064] 302: Data Input / Output Bus

[0065] CA_CE#, CA_CE0#, CA_CE1#: Bus enable signal

[0066] CA[0], CA[1], CA_CLK: CA bus signal

[0067] h[0]~h[3]: Header bits

[0068] a[0]~a[3]: Address bits

[0069] DIR: Direction bit

[0070] r[0]~r[3]: Reserved bits

[0071] PA1~PA6, PB1~PB4: Packets

[0072] STA1~STA3, STB1~STB3: Status

[0073] S101~S102: Steps

Claims

1. A method for controlling a plurality of logical units in a flash memory, comprising: transmitting on-die termination (ODT) enable control information on a control bus corresponding to the plurality of logical units via a data transfer start command to enable on-die termination operation of one or more non-target logical units; and transmitting on-die termination disable control information on the control bus via a data transfer stop command or a data transfer pause command to disable on-die termination operation of the one or more non-target logical units; wherein, The on-chip termination operation corresponds to enabling and disabling the termination resistor of one or more non-target logic units.

2. The method as described in claim 1, wherein the data transmission start command is a select chip enable (SCE) packet as defined in the Separate-Command-Address (SCA) protocol, the data transmission stop command is a select chip terminate (SCT) packet as defined in the Separate-Command-Address (SCA) protocol, and the data transmission pause command is a select chip pause (SCP) packet as defined in the Separate-Command-Address (SCA) protocol.

3. The method as described in claim 2, wherein the step of transmitting the on-chip terminal enable control information comprises: setting the value of at least one first bit in the reserved bits of the select chip enable packet to indicate the enable state of the on-chip terminal operation; and setting the value of at least one second bit in the reserved bits of the select chip enable packet to indicate the direction of a data burst operation for which the on-chip terminal operation is enabled.

4. The method as described in claim 3, further comprising: setting address bits in the selected chip enable packet to indicate a logic cell address of a target logic cell.

5. The method as described in claim 2, wherein the step of transmitting the on-chip terminal disable control information comprises: setting the value of at least one first bit in the reserved bits of the select chip termination packet or the select chip pause packet to indicate the disabled state of on-chip terminal operation.

6. The method of claim 5 further comprises: setting address bits in the select chip termination packet or the select chip pause packet to indicate a logic cell address of a target logic cell.

7. The method as described in claim 1, further comprising: enabling on-chip terminal operation of the one or more non-target logic units in response to on-chip terminal enable control information, wherein the one or more non-target logic units are controlled by a bus enable signal identical to that of a target logic unit.

8. The method as described in claim 1, further comprising: disabling on-chip terminal operation of the one or more non-target logic units in response to on-chip terminal disable control information, wherein the one or more non-target logic units are controlled by a bus enable signal identical to that of a target logic unit.

9. A memory controller for controlling a plurality of logical units in a flash memory, comprising: a storage unit for storing program code; and a processing unit for executing the program code to perform operations on the flash memory, comprising: transmitting on-die termination (ODT) enable control information on a control bus corresponding to the plurality of logical units via a data transfer start command to enable on-die termination operation of one or more non-target logical units; and transmitting on-die termination disable control information on the control bus via a data transfer stop command or a data transfer pause command to disable on-die termination operation of the one or more non-target logical units; wherein, The on-chip termination operation corresponds to enabling and disabling the termination resistor of one or more non-target logic units.

10. The memory controller as claimed in claim 9, wherein the data transfer start command is a select chip enable (SCE) packet as defined in the Separate-Command-Address (SCA) protocol, the data transfer stop command is a select chip terminate (SCT) packet as defined in the Separate-Command-Address (SCA) protocol, and the data transfer pause command is a select chip pause (SCP) packet as defined in the Separate-Command-Address (SCA) protocol.

11. The memory controller of claim 10, wherein when the code is executed, the memory controller is configured to: set the value of at least one first bit in the reserved bits of the select chip enable packet to indicate the enable state of on-chip terminal operation; and set the value of at least one second bit in the reserved bits of the select chip enable packet to indicate the direction of a data burst operation for which on-chip terminal operation is enabled.

12. The memory controller as claimed in claim 11, wherein when the code is executed, the memory controller is configured to: set address bits in the select chip enable packet to indicate a logic cell address of a target logic cell.

13. The memory controller of claim 10, wherein when the code is executed, the memory controller is configured to: set the value of at least one first bit in the reserved bits of the select chip termination packet or the select chip pause packet to indicate a disabled state of on-chip terminal operation.

14. The memory controller of claim 13, wherein when the code is executed, the memory controller is configured to: set address bits in the select chip termination packet or the select chip pause packet to indicate a logic cell address of a target logic cell.

15. The memory controller as claimed in claim 9, wherein when the code is executed, the memory controller is configured to: enable on-chip terminal operation of the one or more non-target logic units in response to on-chip terminal enable control information, wherein the one or more non-target logic units are controlled by a bus enable signal identical to that of a target logic unit.

16. The memory controller as claimed in claim 9, wherein when the code is executed, the memory controller is configured to: disable on-chip terminal operation of the one or more non-target logic units in response to on-chip terminal disable control information, wherein the one or more non-target logic units are controlled by a bus enable signal identical to that of a target logic unit.

17. A data storage device includes a flash memory and a memory controller as described in claim 9.

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