Isolation switching converter and control circuit and control method thereof

Abstract

An isolated switching converter and its control circuit and method are disclosed. The switching converter includes a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein the secondary coil is coupled to provide an output voltage. The control method includes: monitoring the voltage across the auxiliary coil to generate a wake-up detection signal; generating an error amplification signal based on the difference between a reference voltage signal and a feedback voltage signal representing the output voltage; determining whether to pull up the error amplification signal based on the magnitude relationship between a first reference value and the error amplification signal when the wake-up detection signal is valid; and generating a primary switching control signal based on the error amplification signal and the wake-up detection signal to control the primary switching transistor. This switching converter exhibits good transient response performance.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuits, and more particularly to isolated switching converters and their control circuits and control methods. Prior Technology

[0002] Figure 1 illustrates a conventional isolated switching converter 50 employing primary-side control. The switching converter 50 obtains information about the output voltage Vout by detecting the voltage on the auxiliary coil, thereby controlling the on / off state of the primary switch MP to transfer energy to the output. However, in the isolated switching converter 50 shown in Figure 1, the voltage on the auxiliary coil only reflects the output voltage Vout when the rectifier diode Da is on. Under light load or no-load conditions, the switching converter 50 typically operates at a lower switching frequency, and the primary switch MP does not switch for extended periods, resulting in the rectifier diode Da not conducting for a long time. This prevents the switching converter 50 from obtaining real-time information about the output voltage Vout. If a load increase occurs during the period when the rectifier diode Da is not conducting, the switching converter 50 will not be able to respond in time, leading to a large undershoot in the output voltage Vout. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes an isolated switching converter and its control circuit and control method, which has good transient response performance under light load or no-load conditions.

[0004] According to an embodiment of the present invention, a control circuit for an isolated switching converter is disclosed. The switching converter includes a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein the secondary coil is coupled to provide an output voltage. The control circuit includes: a first pin coupled to the auxiliary coil to receive an auxiliary sampling signal representing the voltage across the auxiliary coil; a wake-up detection circuit coupled to the first pin to receive the auxiliary sampling signal and generate a wake-up detection signal based on the auxiliary sampling signal; and an error amplifier circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a reference voltage signal, and the second input terminal receives a representative voltage signal. The system includes: a feedback voltage signal for the output voltage; an error amplifier circuit that generates an error amplification signal at the output based on the reference voltage signal and the feedback voltage signal; a pull-up circuit having a first terminal, a second terminal, and a control terminal, wherein the first terminal receives a first reference value, the second terminal is coupled to the output of the error amplifier circuit, and the control terminal receives a wake-up detection signal; the pull-up circuit is configured to pull up the value of the error amplification signal to the first reference value if the error amplification signal is less than the first reference value when the wake-up detection signal is valid; and a primary switch control circuit that receives the wake-up detection signal and the error amplification signal, and generates a primary switch control signal based on the wake-up detection signal and the error amplification signal to control the primary switch transistor.

[0005] According to another embodiment of the present invention, a control circuit for an isolated switching converter is disclosed. The switching converter includes a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil. A first end of the secondary coil is coupled to provide an output voltage to a load. The control circuit includes: a secondary control circuit, including: a first pin coupled to a second end of the secondary coil; a second pin coupled to receive the output voltage; a load rise detection circuit coupled to the second pin to receive the output voltage and detect whether a load rise has occurred based on the output voltage; a wake-up processing circuit coupled to the first pin and the load rise detection circuit, which pulls down the voltage at the first pin when a load rise occurs; and a primary control circuit, including: a third pin coupled to the auxiliary coil to receive an auxiliary sampling signal representing the voltage across the auxiliary coil; a wake-up detection circuit coupled to the third pin to receive the auxiliary sampling signal and generate a wake-up detection signal based on the auxiliary sampling signal; and a primary switching control circuit that generates a primary switching control signal based on the wake-up detection signal to control the primary switching transistor.

[0006] According to another embodiment of the present invention, an isolated switching converter is disclosed, comprising: a transformer having a primary coil, a secondary coil and an auxiliary coil, wherein a first end of the secondary coil is coupled to provide an output voltage to a load; a primary switching transistor coupled to the primary coil; and a control circuit as described above.

[0007] According to another embodiment of the present invention, a control method for an isolated switching converter is disclosed. The switching converter includes a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein the secondary coil is coupled to provide an output voltage. The control method includes: monitoring the voltage across the auxiliary coil and generating a wake-up detection signal; generating an error amplification signal based on the difference between a reference voltage signal and a feedback voltage signal representing the output voltage; determining whether to pull up the error amplification signal based on the magnitude relationship between a first reference value and the error amplification signal when the wake-up detection signal is valid; and generating a primary switching control signal based on the error amplification signal and the wake-up detection signal to control the primary switching transistor.

[0008] According to an embodiment of the present invention, when the secondary side of the isolated switching converter detects a load increase, it pulls down the voltage at one end of the secondary coil. The primary side can detect the occurrence of the load increase in a timely manner by monitoring the voltage on the auxiliary coil, and thus respond quickly, thereby improving the transient response efficiency of the switching converter and reducing the undershoot of the output voltage. Simple Explanation of the Diagram

[0009] To better understand the present invention, it will be described in detail with reference to the following drawings:

[0010] [Figure 1] shows an existing isolated switching converter 50 employing primary-side control;

[0011] [Figure 2] shows a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0012] [Figure 3] shows a comparison between the operating waveforms of an isolated switching converter 100 according to an embodiment of the present invention and those of a conventional switching converter;

[0013] [Figure 4] shows a circuit schematic of a secondary control circuit 10A for an isolated switching converter 100 according to an embodiment of the present invention;

[0014] [Figure 5] shows a circuit schematic of a secondary control circuit 10B for an isolated switching converter 100 according to another embodiment of the present invention;

[0015] [Figure 6] shows a circuit schematic of a primary control circuit 11A for an isolated switching converter 100 according to an embodiment of the present invention;

[0016] [Figure 7] shows the operating waveform of the wake-up detection circuit 111 in Figure 6 according to an embodiment of the present invention;

[0017] [Figure 8] shows a circuit schematic of a primary control circuit 11B for an isolated switching converter 100 according to another embodiment of the present invention;

[0018] [Figure 9] shows the relationship between the peak current threshold IPKL and the switching frequency Freq of the switching converter 100 and the error amplification signal Vea in Figure 8 according to an embodiment of the present invention;

[0019] [Figure 10] shows the operating waveform diagram of the primary control circuit 11B shown in Figure 8 according to an embodiment of the present invention;

[0020] [Figure 11] shows a flowchart of a control method 1100 for an isolated switching converter according to an embodiment of the present invention. Implementation

[0021] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0022] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. The same reference numerals indicate the same elements. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0023] Throughout this specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply an order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the claim language. The order of text in any claim does not imply that the processing steps must be performed in such an order or logical order, unless specifically specified in the claim language. These processing steps may be interchanged in any order without departing from the scope of the invention, provided that such interchange does not contradict the claim language and does not result in logical absurdity.

[0024] This invention can be applied to any isolated switching converter. In the following detailed description, for the sake of brevity, only a flyback converter will be used as an example to explain the specific working principle of this invention.

[0025] Figure 2 shows a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention. As shown in Figure 2, the isolated switching converter 100 includes an input capacitor Cin, a transformer T1, a primary switch MP, a secondary switch MS, an output capacitor Cout, a secondary control circuit 10, and a primary control circuit 11. The transformer T1 has a primary coil Pri, a secondary coil Sec, and an auxiliary coil Aux, wherein both the primary coil Pri and the secondary coil Sec have a first terminal and a second terminal. The first terminal of the primary coil Pri is coupled to the input capacitor Cin to receive the input voltage Vin, and the first terminal of the secondary coil Sec is coupled to the output capacitor Cout to provide an output voltage Vout across the output capacitor Cout. The primary switch MP is coupled between the second terminal of the primary coil Pri and the primary reference ground. The secondary switch MS is coupled between the second terminal of the secondary coil Sec and the secondary reference ground. In the embodiment shown in Figure 1, the primary switch MP is schematically shown inside the primary control circuit 11. Those skilled in the art will understand that in other embodiments, the primary switch MP may also be located outside the primary control circuit 11.

[0026] The primary control circuit 11 generates a primary switching control signal CTRLP to control the primary switching transistor MP, and the secondary control circuit 10 generates a secondary switching control signal CTRLS to control the secondary switching transistor MS. The switching converter 100 converts the input voltage Vin into the output voltage Vout to supply the load by turning the primary switching transistor MP and the secondary switching transistor MS on and off.

[0027] The secondary control circuit 10 has multiple pins, including an output detection pin VO coupled to the output voltage Vout, a wake-up pin WAKE coupled to the second terminal of the secondary coil Sec, a drive pin GATE that provides the secondary switch control signal CTRLS to the secondary switch MS, and a secondary reference ground pin SGND coupled to the secondary reference ground.

[0028] The primary control circuit 11 has multiple pins, including a feedback pin FB coupled to the auxiliary coil Aux to receive an auxiliary sampling signal Vfb representing the voltage across the auxiliary coil Aux, a switching pin SW coupled to the second terminal of the primary coil Pri, and a primary reference ground pin PGND coupled to the primary reference ground. In the embodiment shown in FIG2, the switching converter 100 further includes a voltage divider circuit 12 coupled to the auxiliary coil Aux for generating the auxiliary sampling signal Vfb. In one embodiment, the voltage divider circuit 12 includes resistors R1 and R2.

[0029] The secondary control circuit 10 receives the output voltage Vout through the output detection pin VO. Based on the output voltage Vout, it detects whether a load increase has occurred. When a load increase is detected, it pulls down the voltage Vwake at the wake-up pin WAKE. Correspondingly, the voltage across the auxiliary coil Aux will fluctuate, and the auxiliary sampling signal Vfb will also fluctuate. The primary control circuit 11 determines whether a load increase has occurred on the secondary side based on the fluctuation amplitude of the auxiliary sampling signal Vfb. When the primary control circuit 11 determines that a load increase has occurred on the secondary side, the primary side is woken up, and the primary switch MP is turned on.

[0030] In one embodiment, when the amplitude of the auxiliary sampling signal Vfb jitter exceeds a wake-up voltage threshold Vthw, it indicates that a load increase has occurred on the secondary side. In one embodiment, a load increase refers to a rapid increase in the current drawn by the load.

[0031] Figure 3 shows a comparison between the operating waveforms of an isolated switching converter 100 according to an embodiment of the present invention and those of a conventional switching converter. From top to bottom, Figure 3 shows the load current ILOAD, the output voltage Vout of the switching converter 100, the voltage Vwake at the wake-up pin WAKE, the auxiliary sampling signal Vfb, the primary switching control signal CTRLP, the secondary switching control signal CTRLS, and the output voltage Vout1, primary switching control signal CTRLP1, and secondary switching control signal CTRLS1 of a conventional switching converter using primary-side control.

[0032] As shown in Figure 3, before time t1, the load is light and the switching converter 100 operates at a lower switching frequency.

[0033] At time t1, the load increases, the load current ILOAD increases rapidly, and the output voltage Vout begins to decrease.

[0034] At time t2, the secondary control circuit 10 detects a load increase based on the output voltage Vout and pulls down the voltage Vwake at the wake-up pin WAKE (as shown by 301 in Figure 3). Due to the low voltage Vwake, the auxiliary sampling signal Vfb exhibits significant jitter (as shown by 302 in Figure 3). Upon detecting this significant jitter, the primary control circuit 11 turns on the primary switch MP. Subsequently, the switching converter 100 operates at a higher switching frequency, causing the output voltage Vout to recover to the desired value within a short time.

[0035] In existing switching converters, after the load increases, the switching converter continues to operate at the original lower switching frequency until time t3, when the secondary switch turns on, and the switching converter can detect the load increase and respond accordingly. At this time, the output voltage Vout has already experienced a large undershoot.

[0036] According to an embodiment of the present invention, when a load increase occurs, the secondary side pulls down the voltage Vwake at the wake-up pin WAKE. The primary side can detect the occurrence of the load increase in a timely manner by monitoring the auxiliary sampling signal Vfb, thereby responding quickly, improving the transient response efficiency of the switching converter 100, and reducing the undershoot of the output voltage Vout.

[0037] Figure 4 shows a circuit schematic of a secondary control circuit 10A for an isolated switching converter 100 according to an embodiment of the present invention. As shown in Figure 4, the secondary control circuit 10A includes an enable circuit 101, a load rise detection circuit 102, a wake-up processing circuit 103, and a secondary switch control circuit 104.

[0038] The enable circuit 101 is coupled to the wake-up pin WAKE and generates an enable signal EN based on the voltage Vwake at the wake-up pin WAKE. In one embodiment, the enable signal EN is active (e.g., high potential) when the voltage Vwake is less than the enable voltage threshold Vthe for a duration that reaches the enable duration threshold Tthe, and this active state is maintained for a set duration TH.

[0039] The load rise detection circuit 102 is coupled to the output detection pin VO to receive the output voltage Vout and detect whether a load rise has occurred based on the output voltage Vout.

[0040] In the embodiment shown in Figure 4, the load rise detection circuit 102 includes an output feedback circuit 1021, an output sample-and-hold circuit 1022, and a load comparison circuit 1023. The output feedback circuit 1021 is coupled to the output detection pin VO to receive the output voltage Vout and generates a first feedback voltage signal Vfb1 representing the output voltage Vout. The output sample-and-hold circuit 1022 samples and holds the first feedback voltage signal Vfb1 to generate an output sample-and-hold signal Vosh. In one embodiment, the output sample-and-hold circuit 1022 is coupled to an enable circuit 101 to receive an enable signal EN. When the enable signal EN is valid, the output sample-and-hold circuit 1022 is enabled and samples and holds the first feedback voltage signal Vfb1 to generate the output sample-and-hold signal Vosh. The load comparison circuit 1023 compares the first feedback voltage signal Vfb1 with a proportional voltage signal Vp representing the output sample-and-hold signal Vosh to generate a load comparison signal LCA. When the first feedback voltage signal Vfb1 is less than the proportional voltage signal Vp, the load comparison signal LCA is valid, indicating a load increase. In one embodiment, the proportional voltage signal Vp is the product of the output sample-and-hold signal Vosh and the scaling factor K. In a further embodiment, the scaling factor K is 97%.

[0041] The wake-up processing circuit 103 is coupled to the wake-up pin WAKE and also to the load comparison circuit 1023 to receive the load comparison signal LCA. Since the load comparison signal LCA is valid, indicating that the load has increased, the wake-up processing circuit 103 pulls down the voltage Vwake at the wake-up pin WAKE.

[0042] The secondary switch control circuit 104 is coupled to the wake-up pin WAKE and generates a secondary switch control signal CTRLS based on the voltage Vwake at the wake-up pin WAKE to control the secondary switch MS. In one embodiment, the secondary switch control circuit 104 controls the turn-on of the secondary switch MS based on the falling slope of the voltage Vwake, and controls the turn-off of the secondary switch MS based on the comparison result of the voltage Vwake and a turn-off threshold Voff.

[0043] Figure 5 shows a circuit schematic of a secondary control circuit 10B for an isolated switching converter 100 according to another embodiment of the present invention. As shown in Figure 5, the secondary control circuit 10B includes an enable circuit 101B, a load rise detection circuit 102B, a wake-up processing circuit 103B, and a secondary switch control circuit 104B.

[0044] The enable circuit 101B includes an enable comparator circuit 1011, a first timer 1012, and a first pulse generator 1013. The enable comparator circuit 1011 compares the voltage Vwake at the wake-up pin (WAKE) with an enable voltage threshold Vthe, generating an enable comparator signal ECA. When the voltage Vwake is less than the enable voltage threshold Vthe, the enable comparator signal ECA is active (e.g., high level). In one embodiment, the enable comparator circuit 1011 includes a comparator CMP1.

[0045] The first timer 1012 counts the duration for which the enable comparison signal ECA is valid, generating an enable timing signal ET. The enable timing signal ET becomes valid when the countdown reaches the enable duration threshold Tthe. In response to the valid enable timing signal ET, the first pulse generator 1013 generates an enable signal EN with a set duration TH.

[0046] The load rise detection circuit 102B includes an output feedback circuit 1021B, an output sample-and-hold circuit 1022B, a proportional voltage generation circuit 1024B, and a load comparator circuit 1023B. The output feedback circuit 1021B includes a voltage divider circuit composed of resistors R3 and R4, which divides the output voltage Vout to generate a first feedback voltage signal Vfb1. In other embodiments, the output feedback circuit 1021B may include multiple voltage divider circuits to obtain feedback voltage signals with different division ratios.

[0047] The output sample-and-hold circuit 1022B includes a switch S1 and a capacitor C1 coupled between the output terminal of the output feedback circuit 1021B and the secondary reference ground. The output sample-and-hold circuit 1022B receives an enable signal EN. In response to the enable signal EN being valid, the switch S1 is turned on, and the output sample-and-hold circuit 1022B samples and holds the first feedback voltage signal Vfb1, generating an output sample-and-hold signal Vosh across the capacitor C1.

[0048] The proportional voltage generation circuit 1024B includes a voltage divider circuit composed of resistors R5 and R6, which divides the output sample-and-hold signal Vosh to generate a proportional voltage signal Vp. The voltage division ratio of the proportional voltage generation circuit 1024B is the proportionality coefficient K.

[0049] The load comparison circuit 1023B compares the first feedback voltage signal Vfb1 with the proportional voltage signal Vp to generate a load comparison signal LCA. The load comparison signal LCA is active (e.g., high potential) when the first feedback voltage signal Vfb1 is less than the proportional voltage signal Vp. In one embodiment, the load comparison circuit 1023B includes a comparator CMP2.

[0050] The wake-up processing circuit 103B includes an RS flip-flop 1031, a second pulse generator 1032, and a pull-down switch S2. The RS flip-flop 1031 has a setting terminal S, a reset terminal R, and an output terminal Q, wherein the setting terminal S receives a load comparison signal LCA, the reset terminal R receives an enable signal EN, and the output terminal Q provides a trigger signal Tr. The second pulse generator 1032 generates a pulse of a duration in response to the trigger signal Tr to turn on the pull-down switch S2 for that duration. In one embodiment, the duration is 1 μs. In one embodiment, in response to the trigger signal Tr, the second pulse generator 1032 generates a pulse of a duration at intervals until the primary side of the switching converter 100 is woken up. In a further embodiment, the interval duration is 30 μs. In the embodiment shown in FIG. 5, the wake-up processing circuit 103B further includes a current limiting circuit 1033 to limit the current flowing through the pull-down switch S2 when it is turned on, preventing damage to the pull-down switch S2.

[0051] The secondary switch control circuit 104B includes a slope detection circuit 1041, a turn-off comparator circuit 1042, and a first logic circuit 1043. The slope detection circuit 1041 detects the falling slope of the voltage Vwake at the wake-up pin WAKE and generates a turn-on control signal Gon to control the turn-on of the secondary switch MS. In one embodiment, the turn-on control signal Gon is active (e.g., high potential) when the falling slope of the voltage Vwake is greater than a slope threshold.

[0052] The shutdown comparator circuit 1042 compares the voltage Vwake at the wake-up pin (WAKE) with the shutdown threshold Voff, generating a shutdown control signal Goff to control the shutdown of the secondary switch MS. The shutdown control signal Goff is active (e.g., high potential) when the voltage Vwake is greater than the shutdown threshold Voff. In one embodiment, the shutdown threshold Voff is -3mV. In one embodiment, the shutdown comparator circuit 1042 includes a comparator CMP3.

[0053] The first logic circuit 1043 generates a secondary switch control signal CTRLS based on the turn-on control signal Gon and the turn-off control signal Goff to control the secondary switch MS.

[0054] Figure 6 shows a circuit schematic of a primary control circuit 11A for an isolated switching converter 100 according to an embodiment of the present invention. The primary control circuit 11A includes a wake-up detection circuit 111, a feedback sample-and-hold circuit 112, an error amplifier circuit 113, a pull-up circuit 114, and a primary switch control circuit 115.

[0055] The wake-up detection circuit 111 is coupled to the feedback pin FB to receive the auxiliary sampling signal Vfb and generate a wake-up detection signal Swake based on the auxiliary sampling signal Vfb. Specifically, if the auxiliary sampling signal Vfb remains below the wake-up voltage threshold Vthw for a duration equal to a wake-up duration threshold Twake, and if the auxiliary sampling signal Vfb is detected to be greater than the wake-up voltage threshold Vthw, the wake-up detection signal Swake is valid, indicating a load increase on the secondary side.

[0056] Figure 7 shows the operating waveforms of the wake-up detection circuit 111 in Figure 6 according to an embodiment of the present invention. Under light load or no-load conditions, the switching converter 100 operates at a lower switching frequency. After both the primary switch MP and the secondary switch MS are turned off, the auxiliary sampling signal Vfb begins to oscillate. At time tw1, the oscillation amplitude of the auxiliary sampling signal Vfb begins to be less than the wake-up voltage threshold Vthw. At time tw2, the duration for which the auxiliary sampling signal Vfb remains less than the wake-up voltage threshold Vthw reaches the wake-up duration threshold Twake. Subsequently, due to a load increase on the secondary side, the secondary control circuit 10 (as shown in Figure 2) pulls down the voltage Vwake at the wake-up pin WAKE, and correspondingly, the auxiliary sampling signal Vfb exhibits significant jitter. At time tw3, the wake-up detection circuit 111 detects this significant jitter, i.e., detects that the auxiliary sampling signal Vfb is greater than the wake-up voltage threshold Vthw, and switches the wake-up detection signal Swake from invalid (e.g., low potential) to valid (e.g., high potential). By setting the wake-up duration threshold Twake, the wake-up detection circuit 111 can distinguish the oscillation waveform of the auxiliary sampling signal Vfb after both the primary switch MP and the secondary switch MS are turned off from the large jitter of the auxiliary sampling signal Vfb caused by the pull-down voltage Vwake when the secondary load rises, and generate a wake-up detection signal Swake that accurately indicates the secondary load rises.

[0057] Continuing with the description in Figure 6, the feedback sample-and-hold circuit 112 is coupled to the feedback pin FB to receive the auxiliary sampling signal Vfb and generates a second feedback voltage signal Vfb2 representing the output voltage Vout based on the auxiliary sampling signal Vfb. In one embodiment, the feedback sample-and-hold circuit 112 samples and holds the auxiliary sampling signal Vfb to generate the second feedback voltage signal Vfb2 after the primary switch MP is turned off and the secondary switch MS is turned on.

[0058] The error amplifier circuit 113 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a reference voltage signal Vref, and the second input terminal receives a second feedback voltage signal Vfb2. Based on the difference between the reference voltage signal Vref and the second feedback voltage signal Vfb2, the error amplifier circuit 113 generates an error amplification signal Vea at the output terminal.

[0059] The pull-up circuit 114 has a first terminal, a second terminal, and a control terminal. The first terminal receives a first reference value, Vea_ref, the second terminal is coupled to the output of the error amplifier circuit 113, and the control terminal receives a wake-up detection signal, Swake. When the wake-up detection signal Swake is valid, the pull-up circuit 114 determines whether to perform a pull-up operation on the error amplifier signal Vea based on the relationship between the error amplifier signal Vea and the first reference value, Vea_ref. In one embodiment, if the error amplifier signal Vea is less than the first reference value, Vea_ref, the pull-up circuit 114 pulls the value of the error amplifier signal Vea up to the first reference value, Vea_ref; if the error amplifier signal Vea is greater than the first reference value, Vea_ref, the pull-up circuit 114 does not change the value of the error amplifier signal Vea.

[0060] The primary switch control circuit 115 receives a wake-up detection signal Swake and an error amplification signal Vea, and generates a primary switch control signal CTRLP based on the wake-up detection signal Swake and the error amplification signal Vea to control the primary switch MP. In one embodiment, the primary switch MP is turned on when the wake-up detection signal Swake is valid.

[0061] In the embodiment shown in Figure 6, the primary switch control circuit 115 also receives a current sampling signal ISEN representing the current flowing through the primary switch MP, and generates a primary switch control signal CTRLP based on the wake-up detection signal Swake, the error amplification signal Vea, and the current sampling signal ISEN. In one embodiment, when the current sampling signal ISEN increases to a peak current threshold IPKL, the primary switch MP is turned off.

[0062] In the embodiment shown in Figure 6, the primary switch MP is schematically represented as a series structure consisting of a normally-on switch J1 and a normally-off switch M1. The normally-on switch J1 has a first terminal and a second terminal, with the first terminal coupled to the switch pin SW. The normally-off switch M1 has a first terminal, a second terminal, and a control terminal, with the first terminal coupled to the second terminal of the normally-on switch J1, the second terminal coupled to the primary reference ground pin PGND, and the control terminal receiving the primary switch control signal CTRLP. In other embodiments, the primary switch MP can also be other controllable semiconductor devices, such as BJTs, JFETs, MOSFETs, IGBTs, etc.

[0063] Figure 8 shows a circuit schematic of a primary control circuit 11B for an isolated switching converter 100 according to another embodiment of the present invention. The primary control circuit 11B includes a wake-up detection circuit 111B, a feedback sample-and-hold circuit 112B, an error amplifier circuit 113B, a pull-up circuit 114B, and a primary switch control circuit 115B.

[0064] The wake-up detection circuit 111B includes a wake-up comparator circuit 1111B, a second timer 1112B, and a gate circuit AND1. The wake-up comparator circuit 1111B compares an auxiliary sampling signal Vfb with a wake-up voltage threshold Vthw to generate a wake-up comparison signal WCA. The wake-up comparison signal WCA is valid (e.g., high potential) when the auxiliary sampling signal Vfb is greater than the wake-up voltage threshold Vthw. In one embodiment, the wake-up comparator circuit 1111B includes a comparator CMP4.

[0065] The second timer 1112B generates a wake-up timing signal WT based on the primary switch control signal CTRLP and the wake-up comparison signal WCA. After the primary switch MP is turned off, the second timer 1112B starts timing based on the wake-up comparison signal WCA, generating the wake-up timing signal WT. During the timing process, if the wake-up comparison signal WCA is valid, i.e., the auxiliary sampling signal Vfb is greater than the wake-up voltage threshold Vthw, the timing duration of the second timer 1112B is reset to zero. When the timing duration reaches the wake-up duration threshold Twake, the wake-up timing signal WT becomes valid (e.g., high potential).

[0066] The gate circuit AND1 performs a logical AND operation on the wake-up comparison signal WCA and the wake-up timing signal WT to generate the wake-up detection signal Swake.

[0067] The feedback sample-and-hold circuit 112B is coupled to the feedback pin FB to receive the auxiliary sampling signal Vfb and generate a second feedback voltage signal Vfb2 based on the auxiliary sampling signal Vfb.

[0068] Error amplifier circuit 113B includes error amplifier EA. Error amplifier EA has a non-inverting input, an inverting input, and an output. The non-inverting input receives a reference voltage signal Vref, and the inverting input receives a second feedback voltage signal Vfb2. Error amplifier EA provides an error amplification signal Vea at the output based on the difference between the reference voltage signal Vref and the second feedback voltage signal Vfb2.

[0069] The pull-up circuit 114B includes an absorption circuit BUF, a one-way conduction circuit D1, and a switch S3. The absorption circuit BUF has an input terminal and an output terminal, where the input terminal receives a first reference value Vea_ref. The one-way conduction circuit D1 has an input terminal and an output terminal, where the input terminal is coupled to the output terminal of the absorption circuit BUF to receive the first reference value Vea_ref. The switch S3 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the output terminal of the one-way conduction circuit D1, and the second terminal is coupled to the output terminal of the error amplifier circuit 113B. When the wake-up detection signal Swake is valid, the switch S3 is turned on. At this time, if the first reference value Vea_ref is greater than the error amplifier signal Vea, the one-way conduction circuit D1 is turned on, and the value of the error amplifier signal Vea is pulled up to the first reference value Vea_ref; if the first reference value Vea_ref is less than the error amplifier signal Vea, the one-way conduction circuit D1 is turned off, and the value of the error amplifier signal Vea remains unchanged, unaffected by the first reference value Vea_ref. In one embodiment, the unidirectional conduction circuit D1 includes a diode.

[0070] In one embodiment, the pull-up circuit 114B further includes a third pulse generator 1141. In response to the activation of the wake-up detection signal (Swake), the third pulse generator 1141 generates a pulse of a duration to turn on the switch S3 for that duration. In one embodiment, the duration is 10 μs.

[0071] The primary switch control circuit 115B includes a clock generator 1151, a current threshold generation circuit 1152, a current comparison circuit 1153, a second logic circuit 1154, and a drive circuit 1155.

[0072] Clock generator 1151 receives the error amplification signal Vea and generates a clock signal CLK based on the error amplification signal Vea to control the switching frequency of the primary switch MP, that is, the switching frequency Freq of the switching converter 100. In one embodiment, the frequency of the clock signal CLK is related to the error amplification signal Vea, that is, the switching frequency Freq of the switching converter 100 is related to the error amplification signal Vea.

[0073] The current threshold generation circuit 1152 receives the error amplification signal Vea and generates a peak current threshold IPKL based on the error amplification signal Vea to control the peak value of the current flowing through the primary switch MP. In the embodiment shown in FIG8, the peak current threshold IPKL has an upper limit value IPKM. The current threshold generation circuit 1152 also receives a wake-up detection signal Swake. In response to the wake-up detection signal Swake being valid, the current threshold generation circuit 1152 sets the peak current threshold IPKL to the upper limit value IPKM, thereby increasing the peak value of the current flowing through the primary switch MP, increasing the energy transferred to the output of the switching converter 100, and rapidly reducing the undershoot of the output voltage Vout.

[0074] The current comparator circuit 1153 compares the current sampling signal ISEN, representing the current flowing through the primary switch MP, with a peak current threshold IPKL to generate a turn-off control signal Coff to control the turn-off of the primary switch MP. In one embodiment, when the current sampling signal ISEN increases to the peak current threshold IPKL, the turn-off control signal Coff is active, turning off the primary switch MP. In a further embodiment, the current comparator circuit 1153 compares the superposition signal ISUM of the current sampling signal ISEN and a compensation signal Scomp with the peak current threshold IPKL to generate the turn-off control signal Coff. In one embodiment, the compensation signal Scomp is a triangular wave signal.

[0075] The second logic circuit 1154 generates a primary switch control signal CTRLP based on the clock signal CLK, the wake-up detection signal Swake, and the shutdown control signal Coff to control the primary switch MP. In one embodiment, when the wake-up detection signal Swake is valid, the primary switch control signal CTRLP is valid, and the primary switch MP is turned on; when the shutdown control signal Coff is valid, the primary switch control signal CTRLP is invalid, and the primary switch MP is turned off; the second logic circuit 1154 controls the switching frequency of the primary switch MP based on the clock signal CLK.

[0076] The drive circuit 1155 generates a drive signal DRV based on the primary switch control signal CTRLP to drive the primary switch MP.

[0077] Figure 9 illustrates the relationship between the peak current threshold IPKL and the switching frequency Freq of the switching converter 100 in Figure 8, and the error amplification signal Vea, according to an embodiment of the present invention. As shown in Figure 9, when the error amplification signal Vea is less than the first error amplification threshold Vea1, the peak current threshold IPKL remains unchanged at the first current threshold IPK1; when the error amplification signal Vea is between the first error amplification threshold Vea1 and the second error amplification threshold Vea2, as the error amplification signal Vea increases, the peak current threshold IPKL increases from the first current threshold IPK1 to the second current threshold IPK2, wherein the first error amplification threshold Vea1 is less than the second error amplification threshold Vea2; when the error amplification signal Vea is greater than the second error amplification threshold Vea2, the peak current threshold IPKL remains unchanged at the second current threshold IPK2. In the embodiment shown in Figure 9, the second current threshold IPK2 is the same as the upper limit value IPKM of the peak current threshold IPKL.

[0078] When the error amplification signal Vea is between the third error amplification threshold Vea3 and the first error amplification threshold Vea1, the switching frequency Freq increases from the first frequency Freq1 to the second frequency Freq2 as the error amplification signal Vea increases, where the third error amplification threshold Vea3 is less than the first error amplification threshold Vea1; when the error amplification signal Vea is between the first error amplification threshold Vea1 and the second error amplification threshold Vea2, the switching frequency Freq remains unchanged at the second frequency Freq2; when the error amplification signal Vea is greater than the second error amplification threshold Vea2, the switching frequency Freq increases as the error amplification signal Vea increases. Furthermore, in the embodiment shown in Figure 9, when the error amplification signal Vea is less than the fourth error amplification threshold Vea4, the switching frequency Freq remains unchanged at the third frequency Freq3; when the error amplification signal Vea is between the fourth error amplification threshold Vea4 and the third error amplification threshold Vea3, as the error amplification signal Vea increases, the switching frequency Freq increases from the third frequency Freq3 to the first frequency Freq1, wherein the fourth error amplification threshold Vea4 is less than the third error amplification threshold Vea3.

[0079] According to one embodiment of the present invention, when a load increase occurs, the wake-up detection circuit 111B generates a valid wake-up detection signal Swake based on the auxiliary sampling signal Vfb. In response to the valid wake-up detection signal Swake, the pull-up circuit 114B pulls up the error amplification signal Vea. As the error amplification signal Vea is pulled high, the frequency of the clock signal CLK and / or the peak current threshold IPKL increases, the switching frequency Freq of the switching converter 100 and / or the peak value of the current flowing through the primary switching transistor MP also increase, thereby increasing the energy transferred to the output of the switching converter 100 and rapidly reducing the undershoot of the output voltage Vout.

[0080] Those skilled in the art will understand that in other embodiments, the relationship between the peak current threshold IPKL and the switching frequency Freq and the error amplification signal Vea may also be different from that shown in Figure 9, as long as raising the error amplification signal Vea can increase the peak current threshold IPKL and / or the switching frequency Freq, thereby increasing the energy transmitted to the output of the switching converter 100.

[0081] Figure 10 shows the operating waveforms of the primary control circuit 11B shown in Figure 8 according to an embodiment of the present invention. From top to bottom, Figure 10 shows the auxiliary sampling signal Vfb, the wake-up detection signal Swake, the error amplification signal Vea, the superposition signal ISUM, and the primary switch control signal CTRLP.

[0082] At time tc1, the wake-up detection circuit 111B detects a large fluctuation in the auxiliary sampling signal Vfb and switches the wake-up detection signal Swake from invalid (e.g., low potential) to valid (e.g., high potential). In response to the valid wake-up detection signal Swake, the pull-up circuit 114B pulls the error amplification signal Vea high, the primary switch control circuit 115B turns on the primary switch MP, and the current threshold generation circuit 1152 sets the peak current threshold IPKL to the upper limit value IPKM.

[0083] After the primary switch MP is turned on, the current flowing through the primary switch MP increases, and the superimposed signal ISUM also increases accordingly.

[0084] At time tc2, the superimposed signal ISUM increases to the peak current threshold IPKL (at this time, the peak current threshold IPKL is the upper limit IPKM), and the primary switch control circuit 115B turns off the primary switch MP. After the wake-up detection signal Swake is valid, the peak current threshold IPKL corresponding to the first switching cycle of the primary switch MP is set to the upper limit IPKM, which can increase the energy transferred to the output of the switching converter 100 and quickly and effectively reduce the undershoot of the output voltage Vout.

[0085] After time tc2, the peak current threshold IPKL and the switching frequency Freq are determined by the error amplification signal Vea.

[0086] At time tc3, the primary switch control signal CTRLP is valid, and the primary switch MP is turned on.

[0087] At time tc4, the superimposed signal ISUM increases again to the peak current threshold IPKL, and the primary switch MP is turned off.

[0088] After several switching cycles, the switching converter 100 enters steady-state operation. In one embodiment, steady-state operation refers to the operating state of the switching converter when the load level is stable.

[0089] Figure 11 shows a flowchart of a control method 1100 for an isolated switching converter according to an embodiment of the present invention. The isolated switching converter includes a transformer having a primary coil, a secondary coil, and an auxiliary coil, a primary switching transistor, and a secondary switching transistor, wherein a first terminal of the secondary coil is coupled to provide an output voltage to a load, the primary switching transistor is coupled to the primary coil, and the secondary switching transistor is coupled to a second terminal of the secondary coil. The control method 1100 includes steps S101 to S106.

[0090] In step S101, the load increase is detected based on the output voltage.

[0091] In step S102, when a load increase is detected, the voltage at the second terminal of the secondary coil is pulled down.

[0092] In step S103, the voltage across the auxiliary coil is monitored to generate a wake-up detection signal. In one embodiment, if the auxiliary sampling signal representing the voltage across the auxiliary coil remains below the wake-up voltage threshold for a duration exceeding the wake-up duration threshold, and the auxiliary sampling signal is detected to be above the wake-up voltage threshold, the wake-up detection signal is valid.

[0093] In step S104, an error amplification signal is generated based on the difference between the reference voltage signal and the feedback voltage signal representing the output voltage. In one embodiment, the feedback voltage signal is generated by sampling and holding the voltage across the auxiliary coil.

[0094] In step S105, when the wake-up detection signal is valid, a decision is made on whether to pull up the error amplification signal based on the magnitude relationship between the first reference value and the error amplification signal. In one embodiment, if the error amplification signal is less than the first reference value, the value of the error amplification signal is pulled up to the first reference value; if the error amplification signal is greater than the first reference value, the value of the error amplification signal is not changed.

[0095] In step S106, a primary switch control signal is generated based on the error amplification signal and the wake-up detection signal to control the primary switch transistor. In one embodiment, the primary switch transistor is turned on when the wake-up detection signal is valid.

[0096] In one embodiment, the control method 1100 further includes: generating a peak current threshold based on an error amplification signal and a wake-up detection signal; and comparing a current sampling signal representing the current flowing through the primary switch with the peak current threshold to generate a turn-off control signal to control the turn-off of the primary switch, wherein the peak current threshold is set to an upper limit value in response to the wake-up detection signal being valid.

[0097] Note that in the flowchart described above, the functions marked in the boxes may occur in a different order than that shown in Figure 11. For example, two consecutively indicated boxes may actually be executed in essentially parallel order, or they may sometimes be executed in reverse order, depending on the specific functions involved.

[0098] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

[0099] 50: Switching converter Vin: Input voltage Vout: Output voltage MP: Primary switching transistor Vfb: Auxiliary sampling signal Da: Rectifier tube 100: Switching Converter Cin: Input capacitor T1: Transformer Pri: Primary coil Aux: Auxiliary coil SW: Switch pin CTRLP: Primary switch control signal FB: Feedback and support PGND: Primary Reference Ground Pin R1: Resistor R2: Resistor 12: Voltage divider circuit Sec: Secondary coil Vwake: Voltage WAKE: Wake-up connector 10: Secondary control circuit VO: Output Detection Pin GATE: Driver pin SGND: Secondary reference ground pin CTRLS: Secondary switch control signal MS: Secondary switching transistor Cout: Output capacitor ILOAD: Load current Vout1: Output voltage CTRLP1: Primary switch control signal CTRLS1: Secondary switch control signal t1: Time t2: Time t3: Time 10A: Secondary control circuit Vfb1: First feedback voltage signal LCA: Load Comparison Signal EN: Enable signal Vp: Proportional voltage signal K: Proportionality coefficient Vosh: Output sample-and-hold signal 101: Enable Circuit 102: Load Rise Detection Circuit 103: Wake-up processing circuit 104: Secondary switch control circuit 1021: Output Feedback Circuit 1022: Output Sample and Hold Circuit 1023: Load Comparator Circuit 10B: Secondary control circuit 1031: RS flip-flop 1032: Second Pulse Generator 1033: Current limiting circuit 103B: Wake-up Processing Circuit S2: Pull-down switch Tr: Trigger signal S: Setting end R: Reset terminal 1021B: Output Feedback Circuit 1022B: Output Sample and Hold Circuit 1023B: Load Comparator Circuit CMP2: Comparator R3: Resistor R4: Resistor R5: Resistor R6: Resistor 102B: Load Rise Detection Circuit S1: Switch C1: Capacitor 1011: Enable Comparator Circuit 1012: First Timer 1013: First Pulse Generator CMP1: Comparator ECA: Enable Comparison Signal ET: Enable Timing Signal 101B: Enable Circuit 1041: Slope Detection Circuit 1042: Turn off the comparator circuit [] 1043: First Logic Circuit Voff: Shutdown threshold CMP3: Comparator Gon: On / off control signal Goff: Disables control signal 104B: Secondary switch control circuit Vthe: Enable voltage threshold TH: Set duration 1024B: Proportional Voltage Generation Circuit Q: Output terminal 11,11A: Primary control circuit 111: Wake-up detection circuit 112: Feedback Sample and Hold Circuit 113: Error Amplifier Circuit 114: Pull-up circuit 115: Primary switch control circuit Vref: Reference voltage signal Vfb2: Second feedback voltage signal Vea: Error Amplification Signal Vea_ref: First reference value Swake: Wake-up detection signal ISEN: Current sampling signal J1: Normally Open Switching Device M1: Normally closed switch device Vthw: Wake-up voltage threshold Twake: Wake-up duration threshold tw1: Moment [] tw2: Moment tw3: Moment 112B: Feedback Sample and Hold Circuit 113B: Error Amplifier Circuit 114B: Pull-up circuit BUF: Absorption circuit D1: Unidirectional conduction circuit S3: Switch 1141: Third Pulse Generator CMP4: Comparator 1111B: Wake-up Comparator Circuit WCA: Wake-up Comparison Signal 1112B: Second timer WT: Wake-up timer signal AND1: Gate circuit 111B: Wake-up Detection Circuit 11B: Primary control circuit 115B: Primary switch control circuit 1151: Clock Generator CLK: Clock signal 1154: Second Logic Circuit 1155: Drive Circuit DRV: Drive Signal Coff: Turn off control signal CMP5: Comparator 1153: Current Comparison Circuit 1152: Current threshold generation circuit IPKL: Peak Current Threshold ISUM: Superimposed signal Scomp: Compensation signal IPKM: Upper Limit IPK1: First current threshold IPK2: Second Current Threshold Freq: Switching frequency Freq1: First frequency Freq2: Second frequency Freq3: Third frequency Vea1: First error amplification threshold Vea2: Second error amplification threshold Vea3: Third Error Amplification Threshold Vea4: Fourth Error Amplification Threshold tc1: Time tc2: time tc3: time tc4: time 1100: Control Method S101: Steps S102: Steps S103: Steps S104: Steps S105: Steps S106: Steps

Claims

1. A control circuit for an isolated switching converter, the switching converter including a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein the secondary coil is coupled to provide an output voltage, the control circuit comprising: The first pin is coupled to the auxiliary coil to receive an auxiliary sampling signal representing the voltage across the auxiliary coil. A wake-up detection circuit is coupled to the first pin to receive the auxiliary sampling signal and generate a wake-up detection signal based on the auxiliary sampling signal; An error amplifier circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a reference voltage signal, and the second input terminal receives a feedback voltage signal representing the output voltage. The error amplifier circuit generates an error amplification signal at the output terminal based on the reference voltage signal and the feedback voltage signal. A pull-up circuit has a first terminal, a second terminal, and a control terminal. The first terminal receives a first reference value, the second terminal is coupled to the output terminal of the error amplifier circuit, and the control terminal receives a wake-up detection signal. The pull-up circuit is configured to pull up the value of the error amplification signal to the first reference value if the error amplification signal is less than the first reference value when the wake-up detection signal is valid. The primary switch control circuit receives the wake-up detection signal and the error amplification signal, and generates a primary switch control signal based on the wake-up detection signal and the error amplification signal to control the primary switch transistor.

2. The control circuit as claimed in claim 1, wherein the pull-up circuit comprises: A unidirectional conduction circuit has an input terminal and an output terminal, wherein the input terminal is coupled to receive the first reference value; The switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the output terminal of the unidirectional conduction circuit, the second terminal is coupled to the second terminal of the pull-up circuit, and the control terminal receives the wake-up detection signal, wherein the switch is turned on in response to the wake-up detection signal being valid.

3. The control circuit as claimed in claim 2, wherein the pull-up circuit further comprises: An absorption circuit has an input terminal and an output terminal, wherein the input terminal is coupled to receive the first reference value, and the output terminal is coupled to the input terminal of the unidirectional conduction circuit.

4. The control circuit as claimed in claim 1, wherein the primary switch control circuit comprises: A current threshold generation circuit generates a peak current threshold based on the error amplification signal and the wake-up detection signal; The circuit also includes a current comparison circuit that compares a current sampling signal representing the current flowing through the primary switch with the peak current threshold to generate a turn-off control signal to control the turn-off of the primary switch.

5. The control circuit as described in claim 4, wherein: The current comparison circuit further compares the superimposed signal of the current sampling signal and a compensation signal with the peak current threshold to generate the turn-off control signal.

6. The control circuit as described in claim 4, wherein: In response to the activation of the wake-up detection signal, the peak current threshold is set to an upper limit value.

7. The control circuit as described in claim 4, wherein: When the error amplification signal is less than the first error amplification threshold, the peak current threshold remains unchanged at the first current threshold; when the error amplification signal is between the first error amplification threshold and the second error amplification threshold, the peak current threshold increases as the error amplification signal increases, wherein the first error amplification threshold is less than the second error amplification threshold; and when the error amplification signal is greater than the second error amplification threshold, the peak current threshold remains unchanged at the second current threshold.

8. The control circuit as claimed in claim 1, wherein the primary switch control circuit further comprises: A clock generator generates a clock signal based on the error amplification signal to control the switching frequency of the primary switching transistor; When the error amplification signal is between a first error amplification threshold and a second error amplification threshold, the switching frequency increases from a first frequency to a second frequency as the error amplification signal increases, wherein the first error amplification threshold is less than the second error amplification threshold; when the error amplification signal is between the second error amplification threshold and a third error amplification threshold, the switching frequency remains unchanged at the second frequency; and when the error amplification signal is greater than the third error amplification threshold, the switching frequency increases as the error amplification signal increases.

9. The control circuit as claimed in claim 1, wherein after the duration during which the auxiliary sampling signal remains below the wake-up voltage threshold reaches a wake-up duration threshold, if the wake-up detection circuit detects that the auxiliary sampling signal is greater than the wake-up voltage threshold, then the wake-up detection signal is valid.

10. The control circuit of claim 9, wherein the wake-up detection circuit comprises: A wake-up comparison circuit compares the auxiliary sampling signal with the wake-up voltage threshold to generate a wake-up comparison signal, wherein the wake-up comparison signal is valid when the auxiliary sampling signal is greater than the wake-up voltage threshold; a timer generates a wake-up timing signal based on the primary switch control signal and the wake-up comparison signal, wherein the wake-up timing signal is valid when the duration for which the auxiliary sampling signal is less than the wake-up voltage threshold reaches the wake-up duration threshold after the primary switch is turned off; and a gate circuit performs a logical AND operation on the wake-up comparison signal and the wake-up timing signal to generate the wake-up detection signal.

11. A control circuit for an isolated switching converter, the switching converter including a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein a first terminal of the secondary coil is coupled to provide an output voltage to a load, the control circuit comprising: The secondary control circuit includes: a first pin coupled to a second end of the secondary coil; a second pin coupled to receive the output voltage; a load rise detection circuit coupled to the second pin to receive the output voltage and detect whether a load rise has occurred based on the output voltage; and a wake-up processing circuit coupled to the first pin and the load rise detection circuit, which pulls down the voltage at the first pin when a load rise occurs; and a primary control circuit including: a third pin coupled to the auxiliary coil to receive an auxiliary sampling signal representing the voltage across the auxiliary coil; a wake-up detection circuit coupled to the third pin to receive the auxiliary sampling signal and generate a wake-up detection signal based on the auxiliary sampling signal; and a primary switch control circuit that generates a primary switch control signal based on the wake-up detection signal to control the primary switch transistor.

12. The control circuit as claimed in claim 11, wherein the load rise detection circuit comprises: An output sample-and-hold circuit receives a first feedback voltage signal representing the output voltage, samples and holds the first feedback voltage signal to generate an output sample-and-hold signal; and a load comparison circuit compares the first feedback voltage signal with a proportional voltage signal representing the output sample-and-hold signal to generate a load comparison signal, wherein the load comparison signal is valid when the first feedback voltage signal is less than the proportional voltage signal to indicate that a load increase has occurred.

13. The control circuit as claimed in claim 11, wherein the wake-up processing circuit comprises: A pull-down switch, coupled between the first pin and the secondary reference ground, is turned on when the load increases.

14. The control circuit as claimed in claim 11, wherein: In response to the validity of the wake-up detection signal, the primary switch is turned on.

15. The control circuit as claimed in claim 11, wherein the primary control circuit further comprises: An error amplifier circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a reference voltage signal, and the second input terminal is coupled to a third pin to receive a second feedback voltage signal representing the output voltage. The error amplifier circuit generates an error amplification signal at the output terminal based on the reference voltage signal and the second feedback voltage signal. A pull-up circuit has a first terminal, a second terminal, and a control terminal. The first terminal receives a first reference value, the second terminal is coupled to the output terminal of the error amplifier circuit, and the control terminal receives a wake-up detection signal. The pull-up circuit is configured to, when the wake-up detection signal is valid, determine whether to perform a pull-up operation on the error amplification signal based on the magnitude relationship between the first reference value at the first terminal and the error amplification signal at the second terminal. The primary switch control circuit also receives the error amplification signal and generates the primary switch control signal based on the error amplification signal and the wake-up detection signal.

16. The control circuit of claim 15, wherein the pull-up circuit determines whether to pull up the error amplification signal signal, comprising: If the error amplification signal is less than the first reference value, the pull-up circuit will pull the value of the error amplification signal up to the first reference value; Furthermore, if the error amplification signal is greater than the first reference value, the pull-up circuit does not change the value of the error amplification signal.

17. An isolated switching converter, comprising: A transformer has a primary coil, a secondary coil, and an auxiliary coil, wherein a first end of the secondary coil is coupled to provide an output voltage to a load; The primary switching transistor is coupled to the primary coil; And the control circuit as described in any one of claims 1 to 16.

18. A control method for an isolated switching converter, the switching converter including a transformer having a primary coil, a secondary coil, and an auxiliary coil, and a primary switching transistor coupled to the primary coil, wherein the secondary coil is coupled to provide an output voltage, the control method comprising: Monitor the voltage across the auxiliary coil to generate a wake-up detection signal; An error amplification signal is generated based on the difference between a reference voltage signal and a feedback voltage signal representing the output voltage; when the wake-up detection signal is valid, a pull-up operation is performed on the error amplification signal based on the magnitude relationship between a first reference value and the error amplification signal; and a primary switch control signal is generated based on the error amplification signal and the wake-up detection signal to control the primary switch transistor.

19. The control method of claim 18, wherein the step of determining whether to perform a pull-up operation on the error amplification signal based on the magnitude relationship between the first reference value and the error amplification signal includes: If the error amplification signal is less than the first reference value, the value of the error amplification signal is pulled up to the first reference value; And if the error amplification signal is greater than the first reference value, the value of the error amplification signal is not changed.

20. The control method as described in claim 18 further includes: A peak current threshold is generated based on the error amplification signal and the wake-up detection signal; And compare the current sampling signal representing the current flowing through the primary switch with the peak current threshold to generate a turn-off control signal to control the turn-off of the primary switch. In response to the validity of the wake-up detection signal, the peak current threshold is set to an upper limit value.

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