Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device includes a semiconductor substrate having a plurality of photodiodes formed therein, a trench isolation grid having a plurality of trench isolation units extending vertically from the back side of the substrate into a first layer adjacent to or the same as the front side of the substrate, and a metal grid having a plurality of metal units. The trench isolation units laterally surround the photodiodes. Each metal unit includes a first portion extending vertically from its upper surface into the trench isolation units to the first layer and laterally surrounded by the trench isolation units, and a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation units into a first dielectric layer to a second layer below the upper surface of the first dielectric layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Prior Technology

[0002] Digital cameras and other optical imaging devices employ image sensors. Image sensors convert optical images into digital data that can be represented as digital images. An image sensor comprises an array of pixel sensors and supporting logic. The pixel sensors in the array are unit devices used to measure incident light, while the supporting logic facilitates the readout of the measurements. One type of image sensor commonly used in optical imaging devices is the back-side illumination (BSI) image sensor. Back-side illumination image sensors can be manufactured using conventional semiconductor processes to achieve low cost, small size, and high integration. Furthermore, back-side illumination image sensors feature low operating voltage, low power consumption, high quantum efficiency, low readout noise, and allow random access. [ ] Summary of the Invention

[0003] In some embodiments, this disclosure relates to a semiconductor device comprising: a substrate in which a plurality of photodiodes are formed, wherein a first dielectric layer is disposed on a back surface of the substrate; a trench isolation grid of an isolation material, comprising a plurality of trench isolation units extending vertically from the back surface of the substrate to a first layer adjacent to or the same as its front surface, wherein one of the trench isolation units laterally surrounds one of the plurality of photodiodes; and a metal grid of a metal material, comprising a plurality of metal units, wherein one of the metal units comprises: a first portion extending vertically from the upper surface of the trench isolation unit to the first layer in the trench isolation unit and laterally surrounded by the trench isolation unit, and a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into the first dielectric layer to a second layer below the upper surface of the first dielectric layer.

[0004] In other embodiments, this disclosure relates to a method comprising: forming a plurality of trenches extending perpendicularly from a back surface of a substrate into the substrate to a first layer adjacent to or coplanar with a front surface thereon, wherein the substrate has a plurality of photodiodes formed therein; depositing an insulating material on the inner surfaces of the plurality of trenches to form a plurality of trench insulating units, and depositing an insulating material on the remaining back surface of the substrate; depositing a metallic material to fill the plurality of trenches to form a first portion of a plurality of metallic units and covering the insulating material deposited on the remaining back surface of the substrate; and forming a second portion of the plurality of metallic units covering the first portion of the plurality of metallic units.

[0005] In yet another embodiment, this disclosure relates to a method comprising: providing a substrate having a plurality of photodiodes formed therein; forming a trench isolation grid comprising an isolation material, wherein forming the trench isolation grid comprises forming a plurality of trench isolation units extending vertically from a back surface into the substrate to a first layer at the same or adjacent to a front surface of the substrate, wherein one of the trench isolation units laterally surrounds one of the plurality of photodiodes; and forming a metal grid comprising a metallic material and a plurality of metal units, wherein forming one of the plurality of metal units comprises: forming a first portion extending vertically from the upper surface of the trench isolation unit into the trench isolation unit to the first layer and being laterally surrounded by the trench isolation unit; and forming a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into a first dielectric layer to a second layer below the upper surface of the first dielectric layer. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure are best understood when read in conjunction with the accompanying drawings. These drawings are drawn to clearly illustrate relevant aspects of the embodiments. These drawings may illustrate the relationships between various structures and / or elements in the embodiments. It should be noted that these drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a cross-sectional view of a semiconductor structure for a back-illuminated pixel sensor according to some embodiments. Figure 2 is a top view of a portion of the semiconductor structure for a back-illuminated pixel sensor, taken along the tangent A-A' in Figure 1 according to some embodiments. Figure 3 illustrates an implementation of a partial semiconductor structure and some dimensions according to one embodiment. Figure 4 shows another embodiment of a partial semiconductor structure according to another embodiment and some dimensions. Figure 5 shows yet another embodiment of a partial semiconductor structure and some dimensions according to yet another embodiment. Figure 6 is a cross-sectional view of a semiconductor structure for a back-illuminated image sensor package according to some embodiments. Figures 7-17 are cross-sectional views of intermediate semiconductor structures showing some example steps in manufacturing a semiconductor structure for a back-illuminated pixel sensor, according to some embodiments. Figure 18 is a flowchart illustrating, according to some embodiments, a process implemented in a method for manufacturing a semiconductor structure for a back-illuminated pixel sensor as shown in Figure 1. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on or over a second feature in the following description may include embodiments in which the first and second features form direct contact, or embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as “below,” “lower,” “above,” “higher,” and similar terms, may be used herein to conveniently describe the relationship between one element or feature and another element or feature as shown in the figures. Spatially relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figures. The device may be rotated (90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. In some embodiments, the terms “approximately” and / or “about” may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms “approximately” and / or “about” may be interpreted as meaning within the normal manufacturing tolerances of a given wafer fabrication process.

[0009] Back-illuminated (BSI) image sensors include an array of pixel sensors. The semiconductor structure for a BSI image sensor includes an integrated circuit having a semiconductor substrate and photodiodes corresponding to the pixel sensors disposed within the substrate. Back-end-of-line (BEOL) metallization stacks of the integrated circuit are located below the semiconductor substrate along the front side of the semiconductor substrate. Color filters (CF) and microlenses (ML) of the semiconductor structure correspond to the pixel sensors and are sequentially stacked on the back side of the semiconductor substrate above the photodiodes corresponding to the pixel sensors.

[0010] When a back-illuminated image sensor includes a trench isolation grid and a metal mesh covering the trench isolation grid within a semiconductor substrate, optical isolation between adjacent pixel sensors can be improved. The trench isolation grid can be implemented by filling a dielectric material in deep trench isolation (DTI) regions arranged around and between photodiodes within the semiconductor substrate. The metal mesh can be implemented in a layer covering the semiconductor substrate. However, the dielectric material filling the DTI regions of the trench isolation grid may cause light leakage between adjacent photodiodes due to the relatively high light transmittance of the dielectric material, thus unintentionally leading to crosstalk between adjacent photodiodes. Furthermore, alignment misalignment issues may occur between the trench isolation grid and the metal mesh due to the fabrication process used to form the metal mesh covering the trench isolation grid, unintentionally reducing the light reflection of the mesh and affecting the optical path of the back-illuminated image sensor.

[0011] In view of the foregoing, in some embodiments, this disclosure relates to a semiconductor structure for a back-illuminated image sensor and a method of manufacturing said semiconductor structure, wherein a metal mesh is self-aligned with a trench isolation mesh, extending fully from the upper surface of the trench isolation mesh into a first layer adjacent to, flush with, or even below the front surface of the semiconductor substrate, and protruding from the upper surface of the trench isolation mesh into a second layer. Thus, the metal mesh and the trench isolation mesh together create a composite metal mesh, thereby advantageously mitigating alignment misalignment problems between the metal mesh and the trench isolation mesh, as well as crosstalk problems between adjacent photodiodes.

[0012] Figure 1 is a cross-sectional view of a semiconductor structure 100 for a back-illuminated pixel sensor 102 according to some embodiments. In some embodiments, the semiconductor structure 100 includes a plurality of back-illuminated pixel sensors 102, which are typically arranged within a pixel sensor array (not shown). In some embodiments, the semiconductor structure 100 includes a semiconductor substrate 104 in which photodiodes 106 corresponding to the pixel sensors 102 are arranged. The photodiodes 106 are arranged in rows and / or columns within the semiconductor substrate 104 and are configured to accumulate charge (e.g., electrons) from photons incident on the back side of the semiconductor substrate 104. The semiconductor substrate 104 may be, for example, a bulk semiconductor substrate, such as a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 104 has a front surface 104F and a back surface 104B.

[0013] In some embodiments, as shown in FIG1, the semiconductor structure 100 for the back-illuminated pixel sensor 102 further includes a first dielectric layer 125 disposed on the back surface 104B of the substrate 104, a trench isolation grid 110G having a plurality of trench isolation units 110 (e.g., 110' in FIG10) of isolation material, the trench isolation units 110 extending vertically from the back surface 104B of the semiconductor substrate 104 into the semiconductor substrate 104 to a first layer "L1", the first layer being adjacent to or the same as the front surface 104F of the semiconductor substrate 104, and a metal grid 120G having a plurality of metal units 120 (120' in FIG11).

[0014] In some embodiments, one of the plurality of metal units 120 includes a first portion 120A and a second portion 120B. In some embodiments, the first portion 120A of the metal unit 120 extends vertically from the upper surface 110F of the trench isolation unit 110 into the trench isolation unit 110 to a first layer "L1", and is laterally surrounded by the trench isolation unit 110. In some embodiments, the second portion 120B of the metal unit 120 vertically covers the first portion 120A of the metal unit 120, and protrudes from the upper surface 110F of the trench isolation unit 110 into the first dielectric layer 125 to a second layer "L2", the second layer being lower than the upper surface 125F of the first dielectric layer 125.

[0015] In some embodiments, the trench isolation unit 110 includes a deep trench isolation (DTI) unit, and the isolation material of the trench isolation unit 110 (e.g., 110' in FIG. 10) includes an oxide material, such as silicon dioxide (SiO₂). In some embodiments, the trench isolation unit 110 is lined with a barrier film 109 of a high dielectric constant material (e.g., 109' in FIG. 10). The barrier film 109 of the trench isolation unit 110 separates the isolation material of the trench isolation unit 110 (e.g., 110' in FIG. 10) from the semiconductor material of the semiconductor substrate 104 (e.g., 104' in FIG. 7). In some embodiments, the semiconductor material (e.g., 104' in FIG. 7) may be silicon (Si). In some embodiments, the high dielectric constant material (e.g., 109' in FIG. 10) is selected from aluminum oxide (AlO), hafnium oxide (HfO), titanium oxide (TiO), tantalum oxide (TaO), or zirconium oxide (ZrO).

[0016] In some embodiments, the metal material of the metal mesh 120G (e.g., 120' in FIG. 11) is selected from aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), or titanium (Ti). In some embodiments, as shown in FIG. 1 and FIG. 3, a first portion 120A of the metal unit 120 rests on a shallow trench isolation (STI) structure 115 disposed above and adjacent to the front surface 104F of the semiconductor substrate 104. In other embodiments, as shown in FIG. 4, the first portion 120A of the metal unit 120 rests on the front surface 104F of the semiconductor substrate 104. In yet another embodiment, as shown in FIG. 5, the first portion 120A of the metal unit 120 extends vertically through the semiconductor substrate 104 to a third height below the front surface 104F of the semiconductor substrate 104 and contacts (not shown) an interconnect metal layer (e.g., 162 in FIG. 6) disposed below the front surface 104F of the semiconductor substrate 104.

[0017] In some embodiments, the semiconductor structure 100 for the back-illuminated pixel sensor 102 further includes an anti-reflection coating (ARC) layer 130 deposited on the upper surface 125F of the first dielectric layer 125 to reduce light reflection. In some embodiments, the anti-reflection coating layer 130 includes silicon dioxide (SiO₂), magnesium fluoride (MgF₂), titanium dioxide (TiO₂), or zinc sulfide (ZnS). By minimizing reflection, the anti-reflection coating layer 130 advantageously enhances light transmission through the upper surface 125F of the first dielectric layer 125, thereby improving the performance and efficiency of the semiconductor structure 100.

[0018] In some embodiments, the semiconductor structure 100 for the back-illuminated pixel sensor 102 further includes a plurality of color filters (CL) 140 disposed on the upper surface of the antireflective coating layer 130 and vertically aligned with a plurality of photodiodes 106 disposed below the antireflective coating layer 130. The plurality of color filters 140 are laterally separated from each other. In some embodiments, the semiconductor structure 100 further includes a plurality of microlenses (ML) 150 disposed on and vertically aligned with the plurality of color filters 140. The plurality of microlenses 150 are laterally separated from each other.

[0019] In some embodiments, the semiconductor structure 100 for the back-illuminated pixel sensor 102 further includes a high-absorption structure 112 formed on the back surface 104B of the semiconductor substrate 104. When the photodiode 106 is irradiated by light incident on the back surface 104B of the semiconductor substrate 104, the high-absorption structure 112 advantageously reduces the light reflectivity of the back surface 104B of the semiconductor substrate 104. With the high-absorption structure 112, more light is absorbed by the photodiode 106 in the pixel sensor 102. In some embodiments, the high-absorption structure 112 has a serrated profile or other periodic pattern along the back surface 104B of the semiconductor substrate 104. In some embodiments, the semiconductor substrate 104 has nanoporous silicon and / or some other high-absorption semiconductor material at the high-absorption structure 112.

[0020] In some embodiments, the semiconductor structure 100 for the back-illuminated pixel sensor 102 further includes a barrier film 116 disposed on the top surface of the high-absorption structure, and an isolation film 118 disposed on the top surface of the barrier film 116. In some embodiments, the barrier film 116 is made of a high-dielectric-constant dielectric material (e.g., 109' in FIG. 10), including aluminum oxide (AlO), hafnium oxide (HfO), titanium oxide (TiO), tantalum oxide (TaO), or zirconium oxide (ZrO). In some embodiments, the isolation film 118 is made of an isolation material (e.g., 110' in FIG. 10), including oxide materials such as silicon dioxide (SiO₂). In some embodiments, the top and bottom surfaces of the barrier film 116 conform to the serrated profile of the high-absorption structure 112. In some embodiments, the top and bottom surfaces of the isolation film 118 conform to the serrated profile of the high-absorption structure 112. In some embodiments, a first dielectric layer 125 covers the top surface of the isolation film 118.

[0021] Figure 2 is a top view of a portion of the semiconductor structure 100 for a back-illuminated pixel sensor 102, taken along tangent A-A' in Figure 1 according to some embodiments. In some embodiments, referring to Figures 1 and 2, a first portion 120A and a second portion 120B of a plurality of metal units 120 define a plurality of regions that laterally surround a plurality of photodiodes 106, respectively.

[0022] Figure 3 is a cross-sectional view 300 illustrating an embodiment of a partial semiconductor structure for a back-illuminated pixel sensor 102 and some dimensions, according to one embodiment. In some embodiments, a first portion 120A of the metal unit 120 extends completely into the trench isolation unit 110 and falls on a first layer "L1" of a shallow trench isolation (STI) structure 115 disposed above and adjacent to the front surface 104F of the semiconductor substrate 104. Therefore, compared to an arrangement where the metal unit 120 does not extend completely into the trench isolation unit 110, the optical performance, such as the modulation transfer function (MTF), of the semiconductor structure for the back-illuminated pixel sensor 102 can be improved by approximately 15%. In some embodiments, the thickness "T" of the semiconductor substrate 104 from the back surface 104B to the front surface 104F is in the range of 2.4 micrometers to 7.2 micrometers. In some embodiments, the depth "D1" of the trench isolation unit 110 is in the range of 1.6 micrometers to 7.2 micrometers. In some embodiments, the first portion 120A and the second portion 120B of the metal unit 120 both have the same width W1, ranging from 100 nanometers to 170 nanometers. In some embodiments, the first portion 120A has a first height "H1" ranging from 1.6 micrometers to 7.2 micrometers, while the second portion 120B has a second height "H2" ranging from 0.34 micrometers to 0.95 micrometers. In some embodiments, the back-illuminated pixel sensor 102 has a pixel pitch "P" ranging from 0.28 micrometers to 5.0 micrometers between two adjacent metal units 120.

[0023] Figure 4 is a cross-sectional view 400 showing another embodiment of a partial semiconductor structure for a back-illuminated pixel sensor 102, and some dimensions, according to another embodiment. The embodiment shown in Figure 4 is similar to the embodiment shown in Figure 3, except for some differences. As shown in Figure 4, the first portion 120A of the metal unit 120 completely extends through the trench isolation unit 110 and the shallow trench isolation (STI) structure 115, and rests on the front surface 104F of the semiconductor substrate 104. Therefore, compared with an arrangement in which the metal unit 120 does not fully extend into the trench isolation unit 110, the optical performance, such as the modulation transfer function (MTF), of the semiconductor structure for the back-illuminated pixel sensor 102 can be improved by about 15%. Furthermore, unlike the embodiment shown in Figure 3, the first portion 120A and the second portion 120B of the metal unit 120 have different widths. In some embodiments, the first width "W1" of the first portion 120A is in the range of 100 nanometers to 170 nanometers, while the second width "W2" of the second portion 120B is in the range of 170 nanometers to 240 nanometers.

[0024] Figure 5 is a cross-sectional view 500 illustrating another embodiment of a partial semiconductor structure for a back-illuminated pixel sensor 102, and some dimensions, according to another embodiment. The embodiment shown in Figure 5 is similar to the embodiments shown in Figures 3 and 4, except for some differences. As shown in Figure 5, a first portion 120A of the metal unit 120 extends completely through the trench isolation unit 110 and the semiconductor substrate 104 to reach a third layer "L3", which is located below the front surface 104F of the semiconductor substrate 104. In some embodiments, a second depth "D2" from the front surface 104F to the third layer "L3" is in the range of 0.3 micrometers to 0.8 micrometers. In some embodiments not shown, the first portion 120A of the metal unit 120 rests on or contacts one of the metallization layers 162 within a BEOL metallization stack 160 located below the semiconductor substrate 104 (in Figure 6). Therefore, compared to the arrangement where the metal unit 120 does not fully extend into the trench isolation unit 110, the optical performance, such as the modulation transfer function (MTF), of the semiconductor structure used for the back-illuminated pixel sensor 102 can be improved by about 20%.

[0025] Figure 6 is a cross-sectional view of the semiconductor structure of a back-illuminated image sensor package 600 according to some embodiments. In Figure 6, the back-illuminated image sensor package 600 includes an array (not shown) of pixel sensors 102 arranged in rows and columns on the back side of integrated circuit 170. In some embodiments, the pixel sensor array includes pixel sensors 102. In some embodiments, the pixel sensor array may include millions of pixel sensors arranged in hundreds or thousands of rows and hundreds or thousands of columns.

[0026] The integrated circuit 170 includes a semiconductor substrate 104, a back-end process (BEOL) metallization stack 160, and a device region 105 located between the semiconductor substrate 104 and the BEOL metallization stack 160. The device region 105 is arranged along the front surface 104F of the semiconductor substrate 104 and extends into the semiconductor substrate 104. The device region 105 includes a photodiode 106 corresponding to the pixel sensor 102 and logic devices (not shown), such as a transistor for reading out the photodiode 106. The photodiode 106 is arranged in rows and columns within the semiconductor substrate 104 and configured to accumulate charge generated by photons incident on the photodiode 106. The photodiodes 106 are optically isolated from each other by a composite grid having a trench isolation grid 110G and a metal grid 120G, as described above with reference to FIG1, thereby advantageously mitigating alignment misalignment problems between the metal grid and the trench isolation grid, as well as crosstalk problems between adjacent photodiodes.

[0027] The BEOL metallization stack 160 of the integrated circuit 170 is located beneath the semiconductor substrate 104 and includes multiple metallization layers 162 stacked in an interlayer dielectric (ILD) layer 166. One or more vias 163 of the BEOL metallization stack 160 extend between the metallization layers (e.g., 162) to interconnect the metallization layers. Additionally, one or more contacts 168 of the BEOL metallization stack 160 extend from the metallization layers 162 to the device region 105. The metallization layers 162, contacts 168, and vias 163 may be made of a metallic material, such as copper or aluminum. The ILD layer 166 may be made of a low-dielectric-constant dielectric material (i.e., a dielectric material with a dielectric constant less than about 3.9), such as an oxide.

[0028] The BEOL metallized stack 160 of the integrated circuit 170 can be bonded to at least one carrier substrate 180. Various suitable bonding techniques (e.g., wire bonding, through-silicon via (TSV), or metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding) or combinations thereof can be used to bond the BEOL metallized stack 160 of the integrated circuit 170 to at least one carrier substrate 180. In some embodiments, the BEOL metallized stack 160 of the integrated circuit 170 is bonded to at least one carrier substrate 180 using a hybrid bonding technique involving direct bonding at the wafer or grain level surface, combining metal-to-metal and dielectric-to-dielectric connections.

[0029] In some embodiments, as shown in FIG6, the BEOL metallization stack 160 of the integrated circuit 170 includes one or more metal interconnects 165 and dielectric interfaces 160S, and the carrier substrate 180 includes one or more corresponding metal interconnects 185 and corresponding dielectric interfaces 180S. Therefore, the BEOL metallization stack 160 of the integrated circuit 170 can be bonded to the carrier substrate 180 via hybrid bonding at the wafer level. In this way, the integrated circuit 170 including the BEOL metallization stack 160 can be bonded to a number (e.g., two to four) carrier wafers (e.g., 180 in FIG6), thereby advantageously allowing high-density integration.

[0030] Figures 7-17 are cross-sectional views of intermediate semiconductor structures showing some example steps of a method for manufacturing a semiconductor structure for a back-illuminated pixel sensor 102, according to some embodiments. Although Figures 7-17 are described with respect to one method, it should be understood that the structures disclosed in Figures 7-17 are not limited to this method, but can exist independently of the method.

[0031] Referring to a cross-sectional view 700 of FIG7, a semiconductor substrate 104 with an embedded photodiode 106 is provided for a semiconductor device. A plurality of shallow trench isolation (STI) structures 115 extend from a front surface 104F into the semiconductor substrate 104, are substantially surrounded by the semiconductor substrate 104, and laterally define the boundaries of the desired back-illuminated pixel sensor 102 (e.g., in FIG1 and FIG6). In some embodiments, the semiconductor substrate 104 is made of a semiconductor material 104' (e.g., silicon), has a front surface 104F and a back surface 104B, and includes a high-absorption structure 112 formed on its back surface 104B, the high-absorption structure 112 having a serrated profile along its back surface 104B. In some embodiments, the semiconductor device further includes a back-end process (BEOL) metallization stack 160 located beneath the substrate 104, which includes a plurality of metallization layers 162 stacked in an interlayer dielectric (ILD) layer 166, and a plurality of vias 163 extending between the plurality of metallization layers 162 to interconnect them.

[0032] Next, referring to the cross-sectional view 800 of FIG8, a plurality of trenches 801 are formed. The trenches 801 extend vertically from the back surface 104B of the semiconductor substrate 104 into the semiconductor substrate 104 and extend to the first layer "L1". The first layer is located above and adjacent to the front surface 104F of the semiconductor substrate 104. In some embodiments, lithography and etching processes may be used to form the plurality of trenches 801. Viewed from the top direction, the plurality of trenches 801 laterally surround the plurality of photodiodes 106.

[0033] Next, referring to the cross-sectional view 900 of FIG9, a plurality of barrier films 109 composed of a high dielectric constant dielectric material 109' are formed on the inner surfaces of the plurality of trenches 801 and the remaining back surface 104B of the semiconductor substrate 104. In some embodiments, a deposition process, such as atomic layer deposition (ALD), is used to form the plurality of barrier films 109. The high dielectric constant dielectric material 109' may be aluminum oxide (AlO), hafnium oxide (HfO), titanium oxide (TiO), tantalum oxide (TaO), or zirconium oxide (ZrO).

[0034] Next, referring to the cross-sectional view 1000 of FIG10, a plurality of trench isolation cells 110 made of isolation material 110' are deposited on a plurality of barrier films 109 made of high dielectric constant dielectric material 109'. Furthermore, the isolation material 110' is also deposited on the remaining back surface 104B of the semiconductor substrate 104. In some embodiments, a deposition process such as Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) is used to form the plurality of barrier films 109. The isolation material 110' may be an oxide material, such as silicon dioxide (SiO₂).

[0035] Next, referring to the cross-sectional view 1100 of FIG11, a deposited metal material 120' fills the plurality of trenches 801 (e.g., in FIG10) and covers the isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104. The first portion 120A of the plurality of metal units 120 (e.g., in FIGS. 1 and 6) is formed by the metal material 120' filling the plurality of trenches 801. In some embodiments, an atomic layer deposition (ALD) process is first performed in the plurality of trenches 801 to form a barrier film of a barrier material (e.g., TiN and TaN), followed by a chemical vapor deposition (CVD) process to deposit the metal material 120'. The metal material 120' can be aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), or titanium (Ti), or a combination thereof.

[0036] Next, referring to the cross-sectional view 1200 of FIG12, a mask layer having a pattern 1201 is formed on a metal material 120' that covers the isolation material 110' filling the plurality of trenches 801 and covers the isolation material 110' deposited on the remaining back surface 104B of the substrate 104. In some embodiments, photolithography and etching processes may be used to form the pattern 1201 of the mask layer.

[0037] Next, referring to the cross-sectional view 1300 of FIG13, a second portion 120B of the plurality of metal units 120 covering the first portion 120A of the plurality of metal units 120 is formed. In some embodiments, the second portion 120B of the plurality of metal units 120 is formed by removing an excess portion of the metal material 120' covering the insulating material 110' deposited on the remaining back surface 104B of the substrate 104 to expose the insulating material 110' deposited on the remaining back surface 104B of the substrate 104, while retaining the remaining portion of the metal material 120' covering the first portion 120A of the plurality of metal units 120. In some embodiments, the excess portion of the metal material 120' is removed by etching the mask layer covering the metal material 120' deposited on the insulating material 110' deposited on the remaining back surface 104B of the substrate 104 according to the pattern 1201 in the mask layer (in FIG12), stopping at the upper surface of the insulating material 110' deposited on the remaining back surface 104B of the substrate 104.

[0038] In some embodiments, referring to Figures 4 and 13, the first width "W1" of the first portion 120A is in the range of 100 nm to 170 nm, while the second width "W2" of the second portion 120B is in the range of 170 nm to 240 nm. In other embodiments, referring to Figure 3, the first portion 120A and the second portion 120B have the same width, which is in the range of 100 nm to 170 nm.

[0039] Next, referring to the cross-sectional view 1400 of FIG14, a first dielectric layer 125 is deposited on the second portion 120B of the plurality of metal cells 120 and on the exposed upper surface of the isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104. The first dielectric layer 125 may be made of a dielectric material, such as silicon dioxide (SiO₂). The plurality of trench isolation cells 110 collectively create a trench isolation grid 110G, the plurality of metal cells 120 extend completely into the plurality of trench isolation cells 110 and collectively create a metal grid 120G, and the trench isolation grid 110G and the metal grid 120G are combined to create a composite metal grid, thereby advantageously mitigating the alignment misalignment problem between the metal grid 120G and the trench isolation grid 110G, as well as the crosstalk problem between adjacent photodiodes 106.

[0040] Next, referring to the cross-sectional view 1500 of FIG15, an anti-reflective coating (ARC) layer 130 is formed on the upper surface of the first dielectric layer 125 by a deposition process (e.g., CVD process), thereby reducing light reflection from the back-illuminated pixel sensor 102 of the semiconductor device and improving the performance and efficiency of the semiconductor device. In some embodiments, the anti-reflective coating layer 130 is made of a material such as silicon dioxide (SiO₂), magnesium fluoride (MgF₂), titanium dioxide (TiO₂), or zinc sulfide (ZnS), or combinations thereof.

[0041] Next, referring to the cross-sectional view 1600 of FIG16, a plurality of color filters (CL) 140 are formed on the upper surface of the antireflective coating layer 130. The plurality of color filters 140 are vertically aligned with a plurality of photodiodes 106 disposed below the antireflective coating layer 130. The plurality of color filters 140 are laterally separated from each other.

[0042] Next, referring to the cross-sectional view 1700 of FIG17, a plurality of microlenses (ML) 150 are formed on a plurality of color filters 140 and are vertically aligned with the plurality of color filters 140. The plurality of microlenses 150 are laterally separated from each other.

[0043] Thus, a semiconductor structure for a back-illuminated pixel sensor 102 is formed, having a metal mesh 120G fully embedded within the trench isolation mesh 110G, wherein the trench isolation mesh 110G and the metal mesh 120G are combined to create a composite metal mesh, thereby advantageously mitigating alignment misalignment between the metal mesh and the trench isolation mesh, as well as crosstalk between adjacent photodiodes.

[0044] Figure 18 is a flowchart illustrating, according to some embodiments, a process implemented in a method 1800 for manufacturing a semiconductor structure 100 for a back-illuminated pixel sensor 102 as shown in Figure 1. While method 1800 is illustrated and described as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted in a limiting manner. For example, some actions may occur in a different order than those illustrated and / or described herein, and / or simultaneously with other actions or events. Furthermore, not all illustrated actions are necessary for implementing one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0045] In some embodiments, the semiconductor structure 100 of the back-illuminated pixel sensor 102 of FIG1 manufactured by method 1800 in FIG1 includes: a semiconductor substrate 104 having a plurality of photodiodes 106 formed therein; a trench isolation grid 110G of isolation material 110' having a plurality of trench isolation units 110 extending vertically from the back surface 104B of the semiconductor substrate 104 into the semiconductor substrate 104 to a first layer "L1" that is the same as or adjacent to its front surface 104F, wherein a trench isolation unit 110 of the plurality of trench isolation units laterally surrounds a photodiode 106 of the plurality of photodiodes 106; and a metal grid 120G of metal material 120' having a plurality of metal units 120. One of the multiple metal units 120 includes a first portion 120A that extends vertically from the upper surface 110F of the trench isolation unit 110 to a first layer "L1" and is laterally surrounded by the trench isolation unit 110, and a second portion 120B that vertically covers the first portion 120A and protrudes from the upper surface of the trench isolation unit 110 into a first dielectric layer 125 disposed on the back surface 104B of the semiconductor substrate 104, to a second layer "L2" below the upper surface of the first dielectric layer 125.

[0046] Referring to Figures 7-8 and 18, method 1800 begins with operation 1802, forming a plurality of trenches 801 extending vertically from the back surface 104B of the semiconductor substrate 104 into the semiconductor substrate 104 to a first layer "L1", the first layer being adjacent to or coplanar with the front surface 104F of the semiconductor substrate 104. The substrate 104 has a plurality of photodiodes 106 formed therein.

[0047] Next, referring to Figures 9-10 and 18, method 1800 proceeds to operation 1804, where an isolation material 110' is deposited on the inner surfaces of the plurality of trenches 801 to form a plurality of trench isolation units 110, and deposited on the remaining back surface 104B of the semiconductor substrate 104. The isolation material 110' can be an oxide material, such as silicon dioxide (SiO₂). In some embodiments, as shown in Figure 9, before depositing the isolation material 110' on the inner surfaces of the plurality of trenches 801 and the remaining back surface 104B of the semiconductor substrate 104 in Figure 10, a barrier film 109 of a high dielectric constant dielectric material 109' is first deposited on the inner surfaces of the plurality of trenches 801 and the remaining back surface 104B of the semiconductor substrate 104. The high dielectric constant dielectric material 109' can be aluminum oxide (AlO), hafnium oxide (HfO), titanium oxide (TiO), tantalum oxide (TaO), or zirconium oxide (ZrO).

[0048] Next, referring to Figures 11 and 18, method 1800 proceeds to operation 1806, where a deposited metal material 120' is filled into a plurality of trenches 801 to form first portions 120A of a plurality of metal units 120, and covers an isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104. The metal material 120' may be aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), or titanium (Ti).

[0049] Next, referring to Figures 12-13 and 18, method 1800 proceeds to operation 1808, forming a second portion 120B of the plurality of metal units 120 covering the first portion 120A of the plurality of metal units 120. Referring to Figure 12, a mask layer having a pattern 1201 is formed on the metal material 120' covering the isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104. Referring to Figure 13, by removing an excess portion of the metal material 120' covering the isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104, exposing the isolation material 110' deposited on the remaining back surface 104B of the semiconductor substrate 104, while retaining the remaining portion of the metal material 120' covering the first portion 120A of the plurality of metal units 120, the second portion 120B of the plurality of metal units 120 covering the first portion 120A of the plurality of metal units 120 is formed.

[0050] Therefore, multiple trench isolation units 110 jointly create a trench isolation grid 110G, and multiple metal units 120 extend completely into the multiple trench isolation units 110 and jointly create a metal grid 120G. The trench isolation grid 110G and the metal grid 120G are combined to create a composite metal grid.

[0051] Therefore, this disclosure relates to a novel semiconductor structure for a back-illuminated image sensor, comprising a composite metal mesh and a novel method for fabricating said structure, thereby advantageously mitigating alignment misalignment between the metal mesh and the trench isolation mesh, as well as crosstalk between adjacent photodiodes, thus advantageously improving the optical performance of the back-illuminated image sensor, such as the modulation transfer function (MTF).

[0052] Accordingly, in some embodiments, this disclosure relates to a semiconductor device comprising: a substrate in which a plurality of photodiodes are formed, wherein a first dielectric layer is disposed on a back surface of the substrate; a trench isolation grid of isolation material, comprising a plurality of trench isolation units extending vertically from the back surface of the substrate to a first layer adjacent to or the same as its front surface, wherein one of the trench isolation units laterally surrounds one of the photodiodes; and a metal grid of metal material, comprising a plurality of metal units, wherein one of the metal units comprises: a first portion extending vertically from the upper surface of the trench isolation unit to the first layer in the trench isolation unit and laterally surrounded by the trench isolation unit, and a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into the first dielectric layer to a second layer below the upper surface of the first dielectric layer. In some embodiments, the trench isolation units comprise deep trench isolation units, and wherein the isolation material of the trench isolation units comprises an oxide material. In some embodiments, the trench isolation cell is lined with a barrier film of a high-dielectric-constant dielectric material, wherein the high-dielectric-constant dielectric material includes aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, or zirconium oxide. In some embodiments, a first portion of the metal cell rests on a shallow trench isolation structure disposed above and adjacent to the front surface of the substrate. In some embodiments, the first portion of the metal cell rests on the front surface of the substrate. In some embodiments, the first portion of the metal cell extends vertically through the substrate to a third layer below the front surface of the substrate and contacts one of a plurality of interconnect metal layers disposed below the front surface of the substrate. In some embodiments, the metal material is aluminum, copper, gold, silver, tungsten, or titanium. In some embodiments, the semiconductor device further includes a high-absorption structure disposed in a portion of the back surface of the substrate and having a serrated profile, a barrier film of a high-dielectric-constant dielectric material disposed on the top surface of the high-absorption structure, and an isolation film of an isolation material disposed on the top surface of the barrier film. In some embodiments, a first dielectric layer covers the top surface of the isolation film. In some embodiments, the top and bottom surfaces of the barrier membrane are both conforming to a serrated profile, and the top and bottom surfaces of the isolation membrane are both conforming to a serrated profile.

[0053] In other embodiments, this disclosure relates to a method comprising: forming a plurality of trenches extending perpendicularly from a back surface of a substrate into a first layer adjacent to or coplanar with a front surface thereon, wherein the substrate has a plurality of photodiodes formed therein; depositing an insulating material on the inner surfaces of the plurality of trenches to form a plurality of trench insulating units, and depositing an insulating material on the remaining back surface of the substrate; depositing a metallic material to fill the plurality of trenches to form a first portion of a plurality of metallic units and covering the insulating material deposited on the remaining back surface of the substrate; and forming a second portion of the plurality of metallic units covering the first portion of the plurality of metallic units. In some embodiments, forming the second portion of the plurality of metallic units comprises: removing an excess portion of the metallic material covering the insulating material deposited on the remaining back surface of the substrate to expose the insulating material deposited on the remaining back surface of the substrate, while retaining the remaining portion of the metallic material covering the first portion of the plurality of metallic units. In some embodiments, removing the excess portion of the metal material includes: forming a patterned mask layer on the metal material covering the insulating material deposited on the remaining back side surface of the substrate; and etching through the mask layer according to the pattern, stopping at the upper surface of the insulating material deposited on the remaining back side surface of the substrate. In some embodiments, a first dielectric layer is deposited over the second portion of the plurality of metal units and on the exposed insulating material deposited on the remaining back side surface of the substrate. In some embodiments, the plurality of trench isolation units collectively create a trench isolation mesh, wherein the first and second portions of the plurality of metal units collectively create a metal mesh. In some embodiments, a barrier film of a high dielectric constant dielectric material is formed on the inner surfaces of the plurality of trenches and on the remaining back side surface of the substrate before depositing the insulating material above the inner surfaces of the plurality of trenches to form the plurality of trench isolation units and before depositing the insulating material on the remaining back side surface of the substrate. In some embodiments, forming the plurality of trenches includes: forming a patterned mask layer above the back surface of the substrate; and etching through the mask layer and into the substrate according to the pattern.

[0054] In yet another embodiment, this disclosure relates to a method comprising: providing a substrate having a plurality of photodiodes formed therein; forming a trench isolation grid comprising an isolation material, wherein forming the trench isolation grid comprises forming a plurality of trench isolation units extending vertically from a back surface into the substrate to a first layer at the same or adjacent to a front surface of the substrate, wherein one of the trench isolation units laterally surrounds one of the plurality of photodiodes; and forming a metal grid comprising a metallic material and a plurality of metal units, wherein forming one of the plurality of metal units comprises: forming a first portion extending vertically from the upper surface of the trench isolation unit into the trench isolation unit to the first layer and being laterally surrounded by the trench isolation unit; and forming a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into a first dielectric layer to a second layer below the upper surface of the first dielectric layer. In some embodiments, a first dielectric layer is formed on the back surface of the substrate to cover at least the second portion of at least one metal unit, wherein the second portion of the metal unit protrudes vertically from the upper surface of the trench isolation unit into the first dielectric layer to a second level below the upper surface of the first dielectric layer. In some embodiments, a high-absorption structure is formed in the back surface of the substrate prior to the formation of the first dielectric layer, wherein the first dielectric layer is deposited over the high-absorption structure.

[0055] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0056] 100: Semiconductor Structure 102: Back-illuminated pixel sensor 104: Semiconductor substrate 104': Semiconductor materials 104B: Backside surface 104F: Front surface 105: Device Area 106: Photodiode 109: Barrier membrane 109': High dielectric constant dielectric material 110: Trench isolation unit 110': Insulation material 110F, 125F: Top surface 110G: Isolation Mesh 112: High absorption structure 115: Shallow trench isolation structure 116: Barrier membrane 118: Separating membrane 120: Metal Unit 120': Metallic materials 120A: Part 1 120B: Part Two 120G: Metal Mesh 125: First dielectric layer 130: Anti-reflective coating layer 140: Color Filter 150: Microlens 160: Back-end process metallization stacking / BEOL metallization stacking 160S, 180S: Dielectric interface 162: Metallization layer 163: Through hole 165, 185: Metal connecting elements 166: Interlayer dielectric layer / ILD layer 168: Contact element 170: Integrated Circuits 180: Carrier substrate 300, 400, 500, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600: Sectional View 600: Back-illuminated image sensor package 801: Trench 1201: Pattern 1800: Method 1802, 1804, 1806, 1808: Operations D1: Depth D2: Second Depth H1: First Height H2: Second Altitude L1: First level L2: Second level L3: Third level P: pixel spacing T: Thickness W1: Width / First Width W2: Second width

Claims

1. A semiconductor device, comprising: A substrate, including a plurality of photodiodes formed therein, wherein a first dielectric layer is disposed above a back surface of the substrate, wherein the substrate includes a plurality of trenches extending from the back surface of the substrate into the substrate; A barrier film is located on the inner surface of the plurality of trenches and on the back surface of the substrate, and contacts the inner surface of the plurality of trenches; a trench isolation grid of isolation material includes a plurality of trench isolation units located on the barrier film, extending vertically from the back surface of the substrate into the plurality of trenches of the substrate to a first layer adjacent to or the same as the front surface of the substrate, wherein one of the plurality of trench isolation units laterally surrounds one of the plurality of photodiodes; And a metal mesh of metallic material, comprising a plurality of metal units, wherein one of the plurality of metal units comprises: a first portion extending vertically from the upper surface of the trench isolation unit into the trench isolation unit to the first layer and being laterally surrounded by the trench isolation unit; and a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into the first dielectric layer to a second layer below the upper surface of the first dielectric layer.

2. The semiconductor device of claim 1, wherein the first portion of a metal unit rests on a shallow trench isolation structure disposed above and adjacent to the front surface of the substrate.

3. The semiconductor device of claim 1, wherein the first portion of a metal unit rests on the front surface of the substrate, wherein the width of the second portion is different from the width of the first portion.

4. The semiconductor device of claim 1, wherein the first portion of the metal unit extends vertically through the substrate to a third layer below the front surface of the substrate and contacts one of a plurality of interconnect metal layers disposed below the front surface of the substrate, wherein the metal unit passes through the trench isolation unit and contacts the barrier film.

5. The semiconductor device as claimed in claim 1, further comprising: A high-absorption structure is disposed in a portion of the back surface of the substrate and has a serrated profile; The barrier film comprises a high dielectric constant dielectric material, and the barrier film is disposed on the top surface of the high absorption structure. And the isolation membrane of the isolation material is disposed on the top surface of the barrier membrane.

6. A method for manufacturing a semiconductor device, comprising: Multiple trenches are formed, extending vertically from the back surface of the substrate into the substrate to a first layer adjacent to or coplanar with the front surface of the substrate, wherein the substrate has multiple photodiodes formed therein; a barrier film is formed on the inner surface of the multiple trenches and the remaining back surface of the substrate, the barrier film contacting the inner surface of the multiple trenches; An isolation material is deposited over the barrier film on the inner surface of the plurality of trenches to form a plurality of trench isolation units, and the isolation material is deposited on the barrier film on the remaining back surface of the substrate; a deposited metallic material is filled into the plurality of trenches to form a first portion of a plurality of metallic units, and covers the isolation material deposited on the remaining back surface of the substrate; And a second portion of the plurality of metal units that forms a first portion covering the plurality of metal units.

7. The manufacturing method as claimed in claim 6, wherein the second portion of forming the plurality of metal units comprises: Excess portion of the metallic material covering the insulating material deposited on the remaining back surface of the substrate is removed to expose the insulating material deposited on the remaining back surface of the substrate, while retaining the remaining portion of the metallic material covering the first portion of the plurality of metal units.

8. The manufacturing method as claimed in claim 6, wherein the barrier film comprises a high dielectric constant dielectric material.

9. The manufacturing method as claimed in claim 6, wherein forming the plurality of trenches comprises: A patterned masking layer is formed above the back surface of the substrate; And according to the pattern, it is etched through the mask layer and into the substrate.

10. A method for manufacturing a semiconductor device, comprising: A substrate having multiple photodiodes formed therein is provided; Multiple trenches are formed, extending from the back surface of the substrate into the substrate; A barrier film is formed on the inner surface of the plurality of trenches and the remaining back surface of the substrate, the barrier film contacting the inner surface of the plurality of trenches; a trench isolation grid comprising an isolation material is formed on the barrier film, wherein forming the trench isolation grid includes forming a plurality of trench isolation units, the plurality of trench isolation units extending vertically from the back surface of the substrate into the substrate to a first layer on the same or adjacent to the front surface of the substrate, wherein one of the plurality of trench isolation units laterally surrounds one of the plurality of photodiodes; And forming a metal mesh comprising metallic material and a plurality of metal units, wherein forming one of the plurality of metal units comprises: forming a first portion extending vertically from the upper surface of the trench isolation unit into the trench isolation unit to the first layer and being laterally surrounded by the trench isolation unit; and forming a second portion vertically covering the first portion and protruding from the upper surface of the trench isolation unit into the first dielectric layer to a second layer below the upper surface of the first dielectric layer.

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