Method for fabricating semiconductor device

Abstract

This invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate including a core region and an input / output (I / O) region, then forming a first gate structure in the core region and a second gate structure in the I / O region, forming a first sidewall next to the first gate structure and a second sidewall next to the second gate structure, wherein the first sidewall and the second sidewall have different widths, and then forming a first source / drain region next to the first sidewall and a second source / drain region next to the second sidewall.

Description

Technical Field

[0001] This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming sidewalls of different thicknesses in the core region and the input / output (I / O) region, respectively. Prior Technology

[0002] In the conventional semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as a standard gate filler material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device drive capability. Therefore, the semiconductor industry is exploring new gate filler materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0003] However, in the current manufacturing process of metal gate transistors, especially in the input / output (I / O) region and core region, the electrical performance is not ideal due to the influence of the predetermined gate dielectric layer thickness. Therefore, how to improve the current metal gate process to solve this problem is an important issue at present. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate including a core region and an input / output (I / O) region, then forming a first gate structure in the core region and a second gate structure in the I / O region, forming a first sidewall next to the first gate structure and a second sidewall next to the second gate structure, wherein the first sidewall and the second sidewall have different widths, and then forming a first source / drain region next to the first sidewall and a second source / drain region next to the second sidewall.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate comprising a core region and an input / output (I / O) region, a first gate structure disposed in the core region and a second gate structure disposed in the I / O region, a first sidewall disposed next to the first gate structure and a second sidewall disposed next to the second gate structure, a first source / drain region disposed next to the first sidewall and a second source / drain region disposed next to the second sidewall, wherein the first sidewall and the second sidewall have different widths. Simple Explanation of the Diagram

[0006] Figures 1 to 7 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 8 to 10 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Implementation

[0007] Please refer to Figures 1 to 7, which are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in Figure 1, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a core region 14 and an input / output (I / O) region 16 are defined on the substrate. In this embodiment, the core region 14 and the I / O region 16 are preferably transistor regions of the same conductivity type, such as both PMOS transistor regions or both NMOS transistor regions. Each core region 14 and I / O region 16 on the substrate 12 has at least one fin structure 20, wherein the bottom of the fin structure 20 is covered by an insulating material such as silicon oxide to form a shallow trench isolation (not shown). It should be noted that although this embodiment takes the fabrication of a non-planar field-effect transistor such as a fin structure as an example, it is not limited to this. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0008] According to one embodiment of the present invention, the fin structure 20 can be fabricated using sidewall image transfer (SIT) technology. The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form sidewalls on each sidewall of the patterned sacrificial layer. The patterned sacrificial layers are then removed, and an etching process is performed under the cover of the sidewalls, transferring the pattern formed by the sidewalls into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0009] In addition, the formation of the fin structure 20 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 20. Alternatively, the fin structure 20 may be formed by first fabricating a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 20. These embodiments of forming the fin structure 20 are all within the scope of this invention.

[0010] Next, gate structures 22 or dummy gates can be formed on the substrate 12 of the core region 14 and the I / O region 16, respectively. In this embodiment, the gate structure 22 is preferably formed by sequentially forming a gate dielectric layer 24, a gate material layer 26, and a selective hard mask (not shown) on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer process, removing part of the gate material layer 26 and part of the gate dielectric layer 24 in a single etching or sequential etching step, and then stripping the patterned photoresist to form at least one gate structure 22 composed of a patterned gate dielectric layer 24 and a patterned gate material layer 26 on the fin structure 20 of the core region 14 and the I / O region 16, respectively. In this embodiment, the gate dielectric layer 24 may contain silicon oxide and the gate material layer 26 may contain polycrystalline silicon, but is not limited thereto.

[0011] Then, at least one sidewall 28, such as an offset spacer, is formed on the sidewall of each gate structure 22. The sidewall 28 located in the core region 14 and the sidewall 28 in the I / O region 16 have the same thickness or width 'a'. The width 'a' of each sidewall 28 is preferably greater than 20 angstroms, for example, between 20 and 25 angstroms. The sidewall 28 is preferably selected from oxygen-free compounds or dielectric materials, such as, but not limited to, silicon nitride (SiN) or silicon carbide (SiC). In this embodiment, the thickness of the sidewall 28 can be defined as the maximum width range of the sidewall 28 extending along the horizontal or X-direction.

[0012] Next, as shown in Figure 2, a processing step 72 is performed to remove some of the sidewalls 28 of the core region 14, but not any of the sidewalls 28 of the I / O region 16. More specifically, in this stage, a patterned mask 74, such as patterned photoresist, can be formed on the I / O region 16 first, and then a processing step 72 is performed, for example, using wet etching or dry etching with the patterned mask 74 as a mask to remove some of the sidewalls 28 of the core region 14, so that the width a of each sidewall 28 of the core region 14 is slightly reduced to width b. Since the width a of the sidewalls 28 of the I / O region 16 is not affected by etching during the etching process due to the masking of the patterned mask 74, the width b of each sidewall 28 of the core region 14 after processing step 72 is preferably slightly smaller than the width a of each sidewall 28 of the I / O region 16. According to one embodiment of the present invention, the width b of each sidewall 28 of the core region 14 is preferably less than 20 angstroms after being thinned by the processing process 72, such as between 15-20 angstroms or more preferably about 15 angstroms, while the width a of the sidewall 28 of the I / O region 16 is maintained at more than 20 angstroms after the processing process, such as between 20-25 angstroms or more preferably about 25 angstroms.

[0013] Then, as shown in Figure 3, the patterned mask 74 is removed first, and another sidewall 78 is formed, for example, the main sidewall next to the sidewall 28. The sidewall 78 located in the core area 14 and the sidewall 78 in the I / O area 16 preferably have the same thickness or width, and the thickness or width of each sidewall 78 is preferably greater than 70 angstroms, for example, between 75-85 angstroms or preferably about 80 angstroms. It is worth noting that the sidewalls 28 and 78 located on the sidewalls of each gate structure 22 in this stage have three different widths. The inner sidewalls 28 of the core region 14 have the smallest width b, the inner sidewalls 28 of the I / O region 16 have an intermediate width a, and the outer sidewalls 78 located on the core region 14 and the I / O region 16 have the largest width c. The width c of each sidewall 78 is preferably more than one, two, three, four, or even five times or more than the width a and / or b of the sidewall 28. These are all within the scope of this invention. In addition, the sidewalls 78 formed in this stage may contain the same or different materials as the sidewalls 28 formed above. For example, the sidewalls 78 may contain silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide or a combination thereof, but are not limited thereto.

[0014] As shown in Figure 4, a source / drain region 30 and / or epitaxial layer 32 can then be formed in the fin-like structures 20 on both sides of the sidewall 78 and / or in the substrate 12, and a metal silicide (not shown) can be selectively formed on the surface of the source / drain region 30 and / or epitaxial layer 32. In this embodiment, the source / drain region 30 and the epitaxial layer 32 may contain different dopants or different materials depending on the conductivity type of the transistor. For example, the source / drain region 30 may contain P-type dopants or N-type dopants, while the epitaxial layer 32 may contain silicon germanide, silicon carbide, or silicon phosphide.

[0015] Next, a contact etch stop layer (CESL) 34 made of silicon nitride is selectively formed on the substrate 12 and covers the gate structure 22. Then, an interlayer dielectric layer 36 is formed on the contact etch stop layer 34. Then, a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 36 and part of the contact etch stop layer 34 and expose the gate material layer 26 made of polysilicon, so that the upper surface of the gate material layer 26 of the core region 14 and the I / O region 16 is flush with the upper surface of the interlayer dielectric layer 36.

[0016] Subsequently, as shown in Figure 5, a metal gate replacement (RMG) process is performed to convert each gate structure 22 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 26 and the gate dielectric layer 24 in the gate structure 22 of the core region 14 and the I / O region 16, so as to form a groove 38 in the interlayer dielectric layer 36.

[0017] As shown in Figure 6, an oxide growth process, such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process, is then performed to form a gate dielectric layer 50 made of silicon oxide in the grooves 38 of the core region 14 and the I / O region 16, respectively. It should be noted that, in order to accommodate the higher voltage of the I / O region 16, the thickness of the gate dielectric layer 50 in the I / O region 16 is preferably greater than the thickness of the gate dielectric layer 50 in the core region 14.

[0018] Subsequently, a high dielectric constant dielectric layer 52, a work function metal layer 54, and a low impedance metal layer 56 are sequentially formed in the groove. Then, a planarization process is performed, for example, by using CMP to remove part of the low impedance metal layer 56, part of the work function metal layer 54, and part of the high dielectric constant dielectric layer 52 to form a metal gate 62 or a gate electrode.

[0019] In this embodiment, the high dielectric constant dielectric layer 52 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. The group consisting of SrBi2Ta2O9 (SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or combinations thereof.

[0020] The work function metal layer 54 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 54 and the low impedance metal layer 56. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 56 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof.

[0021] Next, a portion of the high-dielectric-constant dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistivity metal layer 56 can be removed to form a groove (not shown). Then, a hard mask 58 is filled into the groove, making the hard mask 58 flush with the surface of the interlayer dielectric layer 36. The hard mask 58 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. It should be noted that, in this stage, when etching away a portion of the high-dielectric-constant dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistivity metal layer 56 to form the groove, due to the different material selection ratios, the top surface of the low-resistivity metal layer 56 is preferably slightly higher than the top surfaces of the high-dielectric-constant dielectric layer 52 and the work function metal layer 54.

[0022] Subsequently, as shown in Figure 7, a contact plug process can be performed to form contact plugs 64 that electrically connect the source / drain regions 30 of the core region 14 and the I / O region 16, respectively. Then, a stop layer 66 is formed on the interlayer dielectric layer 36. In this embodiment, the contact plugs 64 can be formed by first removing part of the interlayer dielectric layer 36 and part of the contact holes, etching the stop layer 34 to form contact holes (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact holes. Next, a planarization process, such as CMP, is used to remove part of the metal layer, part of the barrier layer, and even part of the interlayer dielectric layer 36 to form contact plugs 64 in the contact holes, and the upper surface of the contact plugs 64 is preferably flush with the upper surface of the interlayer dielectric layer 36. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride; the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper; and the stop layer 66 preferably comprises an oxide such as tetraethyl orthosilicate (TES), but is not limited thereto. This completes the fabrication of a semiconductor device according to one embodiment of the present invention.

[0023] Please refer to Figures 8 through 10, which are schematic diagrams of a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in Figure 8, compared to the previous embodiment where a portion of the sidewalls 28 of the core region 14 is removed by process 72 before the RMG process or the gate material layer 26 is hollowed out to form the groove 38, thereby reducing its width, according to other embodiments of the present invention, the outer sidewalls 78 can be directly formed next to the sidewalls 28 without etching to remove a portion of the inner sidewalls 28, and then the source / drain region 30, the contact hole etch stop layer 34, and the interlayer dielectric layer 36 are formed sequentially. In other words, the sidewalls next to the gate structure 22 before the groove 38 is formed by hollowing out the gate material layer 26 have only two widths: the sidewalls 28 located inside the core region 14 and the I / O region 16 both have the same width 'a', while the outer sidewalls 78 all include a width 'c'.

[0024] Subsequently, as shown in Figure 9, etching is first used to remove the gate material layer 26 and gate dielectric layer 24 in the gate structure 22 of the core region 14 and I / O region 16 to form a groove 38 in the interlayer dielectric layer 36, forming a patterned mask 74 such as patterned photoresist in the I / O region 16. Then, a processing step 72 is performed, for example, using wet etching or dry etching to remove part of the sidewalls 28 of the core region 14 under the mask of the patterned mask 74, so that the width a of each sidewall 28 of the core region 14 is slightly reduced to width b. From another perspective, although the width of each sidewall of the core region 14 is also reduced from width a to width b in this stage, compared with Figure 2, where the width of the sidewall 28 is reduced to width b by thinning the outer sidewall, this embodiment reduces the width of the sidewall 28 to width b by thinning the inner sidewall.

[0025] Then, as shown in Figure 10, the gate dielectric layer 50, the high dielectric constant dielectric layer 52, the work function metal layer 54, the low impedance metal layer 56, and the hard mask 58 can be formed sequentially in the grooves 38 of the core region 14 and the I / O region 16, in accordance with the process shown in Figures 6 to 7. Contact plugs 64 are formed on both sides of the gate structure 22 to connect the source / drain regions 30, and then a stop layer 66 is formed on the interlayer dielectric layer 36.

[0026] Generally, when fabricating fin-structured field-effect transistors (FETs) with core and I / O regions using current metal gate replacement processes, a thicker gate dielectric layer is formed in the I / O region to match the relatively high voltage of approximately 3.3V in the I / O region. Since both the gate dielectric layer and the innermost sidewalls contain oxygen-containing materials such as silicon oxide, as the thickness of the gate dielectric layer in the I / O region increases, the process of etching away the polysilicon gate material layer during metal gate replacement to form grooves can easily affect the overall gate length (Lg) of the core region. To improve this problem, the present invention preferably uses an oxygen-free dielectric material, such as silicon nitride, as the innermost sidewall 28 closest to the gate electrode or gate structure. Then, according to the embodiments of Figures 1 to 7, a portion of the sidewall 28 of the core region 14 can be removed by process 72 before forming the groove 38, thereby reducing its thickness or width. Alternatively, as in the embodiments of Figures 8 to 10, a portion of the sidewall 28 of the core region 14 can be removed by process 72 after forming the groove 38, thereby adjusting the overall gate length of the subsequent core region. These variations are all within the scope of the present invention. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0027] 12: Base 14: Core Area 16:I / O area 20: Fin-like structure 22: Gate structure 24: Gate dielectric layer 26: Gate material layer 28: Side wall 30: Source / Drain Region 32: Epitaxial layer 34: Contact hole etching stop layer 36: Interlayer dielectric layer 38: Groove 50: Gate dielectric layer 52: High dielectric constant dielectric layer 54: Work function metal layer 56: Low-resistivity metal layer 58: Hard Mask 62: Metal gate 64: Contact plug 66: Stop Layer 72: Processing procedure 74: Patterned Mask 78: Side wall

Claims

1. A method of fabricating a semiconductor device, characterized in that it comprises: providing a substrate including a core region and an input / output (I / O) region; forming a first gate structure in the core region and a second gate structure in the I / O region; forming a first sidewall next to the first gate structure and a second sidewall next to the second gate structure; removing the first gate structure and the second gate structure to form a first groove and a second groove; performing a processing step after forming the first groove and the second groove to remove a portion of the first sidewall, wherein after the processing step, the first sidewall and the second sidewall have different widths; and forming a first source / drain region next to the first sidewall and a second source / drain region next to the second sidewall.

2. The method as described in claim 1, further comprising: forming a third sidewall next to the first sidewall and a fourth sidewall next to the second sidewall; forming an inter-dielectric layer surrounding the third sidewall and the fourth sidewall; and forming a first metal gate in the first groove and a second metal gate in the second groove.

3. The method as described in claim 2 further includes performing a processing step to remove a portion of the first sidewall before forming the third sidewall and the fourth sidewall.

4. The method as described in claim 2, wherein the third sidewall and the fourth sidewall have the same width.

5. The method as described in claim 2, wherein the width of the first sidewall is smaller than the width of the third sidewall.

6. The method as described in claim 2, wherein the width of the second sidewall is smaller than the width of the fourth sidewall.

7. The method as described in claim 1, wherein the width of the first sidewall is smaller than the width of the second sidewall.

8. The method as described in claim 1, wherein the first sidewall and the second sidewall comprise an oxygen-free compound.

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