Hybrid power metal-oxide-semiconductor field-effect transistor and its preparation method

Abstract

A hybrid power MOSFET comprises a drain substrate and a drift layer. The drift layer is divided into a trench structure region and a planar structure region. The trench structure region includes a gate trench, a trench gate electrode located in the gate trench, two first well regions located in the drift layer, and two first sources. The planar structure region is connected in parallel with the trench structure region and includes a planar gate electrode located above the drift layer, at least two second well regions located in the drift layer, and at least two second sources. This invention provides a hybrid power MOSFET with both trench and planar gate electrodes, exhibiting lower on-resistance and better thermal stability. This invention also provides a method for fabricating the hybrid power MOSFET.

Description

Technical Field

[0001] This invention relates to a semiconductor device, particularly a power metal-oxide-semiconductor field-effect transistor. Prior Technology

[0002] To achieve higher output power density and higher switching frequency in power MOSFETs, the planar gate design shown in Figure 1 is generally abandoned in favor of a trench gate design, as shown in Figure 2, which reduces the channel length. The trench gate design not only increases the component density per unit area but also reduces the on-resistance (Rdson) between the source and drain and the input capacitance (Ciss).

[0003] Referring to Figure 3, one of the important specifications of a Power MOSFET is the Safe Operating Area (SOA). The SOA is the region defined in the Power MOSFET's IV characteristic diagram by the on-resistance limit (Rdson limit), package limit, maximum power limit, thermal stability limit, and breakdown voltage limit. A larger SOA ensures the Power MOSFET can operate normally without damage.

[0004] Among these, trench gate designs have relative advantages in areas with limits on on-resistance, package size, maximum power, and breakdown voltage. However, despite these advantages, trench gate designs suffer from poor thermal stability. In contrast, planar gate designs, while less efficient than trench gate designs in other areas and exhibiting higher on-resistance, offer relatively better thermal stability. Therefore, developing a Power MOSFET that simultaneously reduces on-resistance and improves thermal stability while providing a wider safe operating range is a crucial research direction in this field. Summary of the Invention

[0005] Therefore, one of the objectives of this invention is to provide a hybrid power metal-oxide-semiconductor field-effect transistor that can at least overcome the disadvantages of prior art.

[0006] Therefore, the hybrid power metal-oxide-semiconductor (MOSFET) of the present invention comprises a drain substrate and a drift layer. One surface of the drain substrate defines an orthogonal first direction and a second direction. The drift layer is divided into a trench structure region and a planar structure region along the first direction.

[0007] The trench-like structure region includes a gate trench recessed from the top surface of the drift layer, a trench-like gate electrode located in the gate trench, two first well regions located in the drift layer, and two first source electrodes. The first well regions are distributed along the first direction on both sides of the trench-like gate electrode. The first source electrodes are respectively located in the first well regions. The planar structure region is connected in parallel with the trench-like structure region and includes a planar gate electrode located above the drift layer, at least two second well regions located in the drift layer, and at least two second source electrodes. The second well regions are distributed at intervals along the second direction on both sides below the planar gate electrode. The second source electrodes are respectively located in the second well regions.

[0008] Another object of the present invention is to provide a method for preparing a hybrid power metal-oxide-semiconductor field-effect transistor that can at least overcome the disadvantages of prior art.

[0009] Therefore, the method for fabricating the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention includes a drift layer formation step, a trench formation step, a gate electrode formation step, a well region formation step, and a source electrode formation step.

[0010] The drift layer formation step involves forming a drift layer on a drain substrate. One surface of the drain substrate defines an orthogonal first direction and a second direction. The trench formation step involves etching downwards from a top surface of the drift layer to form a gate trench. The gate electrode formation step involves sequentially depositing an oxide material and a gate electrode material on the top surface of the drift layer, removing a portion of the gate electrode material to form a trench gate electrode in the gate trench, and forming a planar gate electrode outside the gate trench. The well region formation step involves forming two first well regions along the first direction on both sides of the trench gate, and two second well regions along the second direction on both sides below the planar gate, through a first type of doping. The source electrode formation step involves forming two first sources in the first well regions and two second sources in the second well regions, through a second type of doping.

[0011] The advantage of this invention is that by forming the trench structure region and the planar structure region connected in parallel on the same drain substrate, a hybrid Power MOSFET with both trench gate and planar gate is formed, thus achieving both lower on-resistance and better thermal stability, and providing a wider safe operating range. Simple Explanation of the Diagram

[0012] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: Figure 1 is a schematic diagram of a conventional metal-oxide-semiconductor field-effect transistor with a planar gate; Figure 2 is a schematic diagram of a conventional metal-oxide-semiconductor field-effect transistor with a trench gate; Figure 3 is a schematic diagram illustrating the safe operating range of a power metal-oxide-semiconductor field-effect transistor; Figure 4 is an incomplete three-dimensional schematic diagram of the first embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention, omitting an inner dielectric layer, a source metal layer and a passivation layer; Figure 5 is a cross-sectional view of a planar structural region of the first embodiment; Figure 6 is a schematic diagram of the IV characteristics of this first embodiment; Figure 7 is a cross-sectional view of a second embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention; Figure 8 is a cross-sectional view of the third embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention; Figure 9 is a flowchart of the preparation method of the first embodiment; and Figures 10-15 are schematic diagrams of the preparation method of the first embodiment. Implementation

[0013] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0014] Referring to Figures 4 and 15, a first embodiment of the device of the present invention includes a drain substrate 1, a drift layer 2, an inner dielectric layer 3, a source metal layer 4, and a passivation layer 5.

[0015] One surface 11 of the drain substrate 1 defines an orthogonal first direction X and a second direction Y, and a direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z. The drain substrate 1, the drift layer 2, the inner dielectric layer 3, the source metal layer 4, and the passivation layer 5 are stacked along the third direction Z. Optionally, the drift layer 2 may have a bottom layer 21 and a top layer 22 stacked on top of each other, wherein the doping concentration of the top layer 22 may be higher than that of the bottom layer 21 to achieve device optimization. The drift layer 2 is divided along the first direction X into a trench structure region A, a planar structure region B, and an intersection region C located between the trench structure region A and the planar structure region B.

[0016] The trench structure region A includes a gate trench A01 recessed from the top surface of the drift layer 2, a trench gate A1 located in the gate trench A01, two first well regions A2 and two first source electrodes A3 located in the drift layer 2, two first conductive layers A4, and a first terminal structure A5. The gate trench A01 of the trench structure region A is defined by a wall A6. The trench gate A1 has a first insulating layer A11 made of insulating oxide that extends and covers the wall A6, and a trench gate electrode A12 and a shielding electrode A13 surrounded by the first insulating layer A11 and spaced apart vertically. The first well regions A2 are distributed on both sides of the trench gate electrode A12 along the first direction X. The first source electrodes A3 are located in the first well regions A2 respectively. The first conductive layers A4 are electrically connected to the first source electrodes A3. The first insulating layer A11 is made of insulating oxide, such as silicon oxide.

[0017] The first terminal structure A5 surrounds the trench gate A1, the first well areas A2, the first source electrodes A3, and the first conductive layers A4, and has a first annular trench A02 recessed from the top surface of the drift layer 2, and a first insulating layer A51 and a first electrode layer A52 located in the first annular trench A02. The first insulating layer A51 is made of insulating oxide, such as silicon oxide.

[0018] Referring to Figures 4 and 5, the planar structure region B is connected in parallel with the trench structure region A, and includes a planar gate B1 located above the drift layer 2, and four second well regions B2, four second sources B3, four second conductive layers B4, a second terminal structure B5, and a third terminal structure B6 located in the drift layer 2. The second well regions B2 are arranged at intervals along the first direction X, and are distributed opposite each other and at intervals on both sides below the planar gate electrode B12 along the second direction Y. The second sources B3 are located in the second well regions B2. The planar gate electrode B12 spans above the second well regions B2 and includes a gate oxide layer B11 and a planar gate electrode B12 disposed on the top surface of the gate oxide layer B11. The gate oxide layer B11 is composed of insulating oxide.

[0019] The second terminal structure B5 surrounds the planar gate B1, the second well regions B2, the second source electrodes B3, and the second conductive layers B4, and has a second annular trench B01 recessed from the top surface of the drift layer 2, and a second insulating layer B51 and a second electrode layer B52 located in the second annular trench B01. The third terminal structure B6 is surrounded by the second terminal structure B5 and extends along the second direction Y, separating the second well regions B2 from the second source electrodes B3. The third terminal structure B6 has an elongated trench B02 recessed from the top surface of the drift layer 2, and a third insulating layer B61 and a third electrode layer B62 located in the elongated trench B02. The planar gate electrode B12 spans over the third terminal structure B6. The second insulating layer B51 and the third insulating layer B61 are made of insulating oxides, such as silicon oxide.

[0020] It should be noted that, for ease of explanation, Figure 4 only shows a portion of the three-dimensional structure of the first embodiment. However, if viewed from a top view, the first terminal structure A5 and the second terminal structure B5 are both ring-shaped, and the third terminal structure B6 is elongated.

[0021] The region in the drift layer 2 located between the first annular groove A02 and the second annular groove B01 is defined as the crossing zone C. Since the crossing zone C has no other structure besides the drift layer 2, it can serve as a buffer to reduce the interaction interference between the trench-type structure area A and the planar structure area B during the switching process, thus reducing malfunctions.

[0022] The projected area TA1 of the trench structure region A on the surface 11 of the drain substrate 1 is larger than the projected area TA2 of the planar structure region B on the surface 11 of the drain substrate 1. Thus, this first embodiment retains the advantages of the trench structure region A in areas such as on-resistance limits, packaging limits, maximum power limits, and breakdown voltage limits, while incorporating the advantages of the planar structure region B in areas of thermal stability limits.

[0023] Preferably, the proportion of the projected area TA1 to the area of ​​the surface 11 of the drain substrate 1 can be greater than or equal to 60%. The proportion of the projected area TA2 to the area of ​​the surface 11 of the drain substrate 1 can be less than or equal to 40%. The proportion of the projected area of ​​the crossing region C to the area of ​​the surface 11 of the drain substrate 1 can be less than or equal to 5%.

[0024] Referring to Figure 4, viewed from the front side, along the first direction X, the spacing P1 between the first annular trench A02 and the gate trench A01, the spacing P2 between the first annular trench A02 and the second annular trench B01, and the spacing P3 between the second annular trench B01 and the elongated trench B02 are the same. Designing these equal spacings P1, P2, and P3 to be identical is for better control of the component's breakdown voltage (BVDSS).

[0025] In this first embodiment, the first sources A3 of the trench-like structure region A are arranged along the first direction X, while the second sources B3 of the planar structure region B are arranged along the second direction Y. Therefore, the channel length of the planar structure region B can be avoided from being limited by the spacing P3. Furthermore, since the channel of the planar structure region B is formed by two pairs of second sources B3 connected in parallel, the effective area of ​​the planar structure region B can also be increased.

[0026] Referring to Figure 15, the inner dielectric layer 3 is disposed above the trench-type structure region A and the planar structure region B, and the source metal layer 4 is located on the top surface of the inner dielectric layer 3. The inner dielectric layer 3 has a plurality of first through-holes 301, a plurality of second through-holes 302, and a plurality of third through-holes 303 extending vertically. The number and position of the first through-holes 301 correspond to the first sources A3, the number and position of the second through-holes 302 correspond to the second sources B3, and the position of the third through-holes 303 correspond to the first electrode layer A52 of the first terminal structure A5, the second electrode layer B52 of the second terminal structure B5, and the third electrode layer B62 of the third terminal structure B6. The source metal layer 4 is electrically connected to the first conductive layer A4, the second conductive layer B4, the first electrode layer A52, the second electrode layer B52, and the third electrode layer B62 through a plurality of conductive plugs 41 filled in the first through-holes 301, the second through-holes 302, and the third through-holes 303, respectively. The passivation layer 5 covers the top surface of the source metal layer 4.

[0027] Figure 6 is a schematic diagram comparing the IV characteristics of a conventional planar gate power MOSFET, a conventional trench gate power MOSFET, and the present first embodiment. The planar gate power MOSFET, represented by a dashed line, has a higher on-resistance, resulting in a relatively small ID when VDS is less than 10V. However, it maintains a relatively high ID within the VDS range of 10~100V, indicating better thermal stability. The trench gate power MOSFET, represented by a dotted link line, has a lower on-resistance and a relatively large ID when VDS is less than 10V. However, its ID drops significantly after VDS exceeds 10V, decaying to 0.01A around 70V, indicating poor thermal stability. The first embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention is shown in solid lines. Because it has a parallel structure of trench gate A1 and planar gate B1 on a single chip, it can theoretically have both low on-resistance and good thermal stability. When VDS is less than 10V, it has an ID comparable to that of a trench gate power MOSFET, and it can still maintain an ID comparable to that of a planar gate power MOSFET in the range of 10~100V.

[0028] It should be noted that in this first embodiment, the number of the second well regions B2 and the second source regions in the planar structure region B is four. However, in other variations of this first embodiment, the number of the second well regions B2 and the second source regions may also be two.

[0029] Referring to Figure 7, the second embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention differs from the first embodiment only in the structural design of the trench gate A1 in the trench structure region A. The following description focuses only on the differences; the similarities will not be repeated.

[0030] The trench gate electrode A1 further comprises a second isolation layer A14, a third isolation layer A15, and a fourth isolation layer A16, sequentially formed from the surface of the first isolation layer A11 and located between the first isolation layer A11 and the shielding electrode A13. The second isolation layer A14 is a nitride, while the third and fourth isolation layers A15 are composed of oxides. The third isolation layer A15 surrounds the shielding electrode A13. The fourth isolation layer A16 is located between the trench gate electrode A12 and the first isolation layer A11, and covers the surface of the trench gate electrode A12 except for its top surface. The third and fourth isolation layers A15 and A16 have a thickness T between the shielding electrode A13 and the trench gate electrode A12, and this thickness T is between 500 and 4000 Å.

[0031] In this second embodiment, since the fourth isolation layer A16 covers the peripheral surface adjacent to the gate electrode and the shielding electrode A13, the trench gate electrode A12 can be isolated from the nitride of the second isolation layer A14. Therefore, the trench gate electrode A12 can be prevented from contacting or being too close to the nitride to cause interaction and affect the device characteristics.

[0032] Referring to Figure 8, the third embodiment of the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention differs from the first embodiment only in the structural design of the first terminal structure A5. The following description focuses only on the different parts; the identical parts will not be repeated.

[0033] The first terminal structure A5 further comprises a protective layer A53, a second insulating layer A54, and a third insulating layer A55, sequentially formed from the surface of the first insulating layer A51 and located between the first insulating layer A51 and the first electrode layer A52. The protective layer A53 is made of nitride and does not contact the first electrode layer A52. The second insulating layer A54 is formed between the protective layer A53 and the first electrode layer A52. The third insulating layer A55 covers the top surfaces of the first electrode layer A52, the protective layer A53, and the second insulating layer A54. The conductive plug 41 passes downward through the third insulating layer A55 and is electrically connected to the first electrode layer A52. The second insulating layer A54 and the third insulating layer A55 are made of oxide.

[0034] In this third embodiment, the nitride of the protective layer A53 can be used to protect the oxide of the first insulating layer A51 during the manufacturing process, thereby preventing further oxidation of the oxide during the thermal process. Furthermore, the nitride of the protective layer A53 does not contact the first electrode layer A52, thus preventing the interaction between the nitride and the first electrode layer A52 from generating induced charges and reducing the operating efficiency and reliability of the trench power transistor.

[0035] The preparation method of the first embodiment is described below with reference to Figures 9-15.

[0036] Referring to Figure 9, the preparation method of the first embodiment includes a drift layer forming step S1, a trench forming step S2, a terminal electrode forming step S3, a gate electrode forming step S4, a well region forming step S5, a source electrode forming step S6, a dielectric layer forming step S7, a metal layer forming step S8, and a passivation layer forming step S9.

[0037] Referring to Figure 10, in the drift layer 2 formation step, the drift layer 2 is formed on the surface 11 of the drain substrate 1. The surface 11 of the drain substrate 1 defines the orthogonal first direction X and the second direction Y. In the trench formation step S2, etching is performed downwards from one top surface of the drift layer 2 to form the gate trench A01, the first annular trench A02, the second annular trench B01, and the elongated trench B02.

[0038] In the terminal electrode formation step S3, an insulating layer material, an electrode material, and the insulating layer material are sequentially deposited on the top surface of the drift layer 2. After removing the insulating layer material and the electrode material other than those in the first annular trench A02, the second annular trench B01, and the elongated trench B02, an electrode material is deposited in the first annular trench A02, the second annular trench B01, and the elongated trench B02 to form the first terminal structure A5, the second terminal structure B5, and the third terminal structure B6.

[0039] Optionally, in the terminal electrode forming step S3, the shielding electrode A13 may also be formed simultaneously in the gate trench A01.

[0040] Referring to Figure 11, in the gate electrode formation step S4, an oxide material 6 is deposited on the top surface of the drift layer 2. An opening 60 is formed in the oxide material 6 at a predetermined region corresponding to the trench gate electrode A12, and then a gate electrode material is deposited. After removing a portion of the gate electrode material located on the surface of the oxide material 6, the trench gate electrode A12 is formed in the gate trench A01, and the planar gate electrode B12 is formed in a predetermined region outside the gate trench A01. The gate electrode material is, for example, but not limited to, polycrystalline silicon.

[0041] Referring to Figure 12, in the well region formation step S5, through a first type of doping, first well regions A2 are formed in the drift layer 2, respectively distributed along the first direction X on both sides of the trench gate electrode A12, and second well regions B2 are distributed in pairs opposite to each other and spaced apart along the second direction Y on both sides below the planar gate electrode B12. In this first embodiment, the first type of doping is P-type doping.

[0042] Referring to Figure 13, in the source formation step S6, first sources A3 are formed in the first well regions A2 via a second type of doping, and second sources B3 are formed in the second well regions B2. In this first embodiment, the second type of doping is N-type doping.

[0043] In step S7 of forming the dielectric layer, an inner dielectric material 7 is deposited on the top surface of the drift layer 2, the trench structure region A, and the planar structure region B. Referring to Figure 14, the inner dielectric material 7 and the oxide material 6 together form the inner dielectric layer 3. In other words, the inner dielectric layer 3 covers the top surface of the drift layer 2, the trench structure region A, and the planar structure region B. The oxide material 6 located below the planar gate electrode B12 is defined as the gate oxide layer B11. Vertically penetrating through-holes 301, 302, and 303 are formed in the inner dielectric layer 3. Specifically, the first through-holes 301 and 302 are elongated trenches.

[0044] In the metal layer formation step S8, the first conductive layer A4 connecting the first source A3 and the second conductive layer B4 connecting the second source B3 are formed through the first through-hole 301 and the second through-hole 302, respectively.

[0045] Referring to Figure 15, a plurality of conductive plugs 41 are formed in the first through-hole 301, the second through-hole 302, and the third through-hole 303, respectively. A source metal layer 4 is deposited on the top surface of the inner dielectric layer 3. The source metal layer 4 is electrically connected to the first conductive layer A4, the second conductive layer B4, the first electrode layer A52, the second electrode layer B52, and the third electrode layer B62 through the conductive plugs 41.

[0046] In the metal layer formation step S8, the method further includes forming a fourth via in the inner dielectric layer 3 and forming a gate metal layer, so that the gate metal layer can be electrically connected to the trench gate electrode A12 and the planar gate electrode B12 through multiple conductive plugs filled in the fourth via (not shown). Since the above steps are known techniques and can be implemented in many ways, and are not the main technical features of this invention, they will not be described in detail.

[0047] In the passivation layer formation step S9, the passivation layer 5 is formed covering the top surface of the source metal layer 4.

[0048] In summary, the hybrid power metal-oxide-semiconductor field-effect transistor of the present invention, by forming the trench structure region A and the planar structure region B connected in parallel on the same drain substrate 1, constitutes a hybrid Power MOSFET that simultaneously has a trench gate A1 and a planar gate B1. Therefore, it can have both lower on-resistance and better thermal stability, and has a wider safe operating range, thus effectively achieving the purpose of the present invention.

[0049] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention.

[0050] 1:Drain substrate 11: Surface 2: Drift Layer 21: Bottom 22: Top Floor 3: Inner dielectric layer 301: First through hole 302: Second through hole 303: Third through hole 4: Source metal layer 41: Conductive plug 5: Passivation layer 6: Oxide materials 60: Opening 7: Inner layer dielectric material A: Ditch-type structural area A01: Gate trench A02: First annular groove A1: Trench-type gate A11: First Isolation Layer A12: Trench-type gate electrode A13: Shielding electrode A14: Second isolation layer A15: Third Isolation Layer A16: Fourth Isolation Layer A2: First Well Area A3: First Source A4: First conductive layer A5: First Terminal Structure A51: First Insulation Layer A52: First electrode layer A53: Protective Layer A54: Second Insulation Layer A55: Third Insulation Layer A6: Enclosure B: Planar structural area B01: Second annular groove B02: Long groove B1: Planar gate B11: Gate oxide layer B12: Planar gate electrode B2: Second Well Area B3: Second source pole B4: Second conductive layer B5: Second Terminal Structure B51: Second Insulation Layer B52: Second electrode layer B6: Third Terminal Structure B61: Third Insulation Layer B62: Third electrode layer C: Crossing Zone P1, P2, P3: Spacing S1: Drift layer formation steps S2: Trench Formation Steps S3: Terminal Electrode Formation Step S4: Gate Electrode Formation Steps S5: Well Formation Steps S6: Source Formation Steps S7: Dielectric layer formation steps S8: Metal Layer Formation Steps S9: Passivation layer formation steps T: Thickness X: First direction Y: Second direction Z: Third-party direction

Claims

1. A hybrid power metal-oxide-semiconductor (MOSFET) comprising a drain substrate and a drift layer, wherein one surface of the drain substrate defines an orthogonal first direction and a second direction, and the drift layer is divided along the first direction into: a trench-type structure region including a gate trench recessed from the top surface of the drift layer, a trench-type gate electrode located in the gate trench, two first well regions located in the drift layer, and two first sources, the first well regions being distributed on both sides of the trench-type gate electrode along the first direction, and the first sources being located in the first well regions; and a planar structure region connected in parallel with the trench-type structure region, including a planar gate electrode located above the drift layer, at least two second well regions located in the drift layer, and at least two second sources, the second well regions being distributed at intervals on both sides below the planar gate electrode along the second direction, and the second sources being located in the second well regions, wherein... The planar structure region includes four second well regions and the same number of second source electrodes as the second well regions. The second well regions are opposite each other along the second direction and are spaced apart along the first direction. The second source electrodes are located in the second well regions respectively, and the planar gate electrode spans over the second well regions.

2. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 1, wherein, The projected area of ​​the trench-type structure region on the surface of the drain substrate is greater than the projected area of ​​the planar structure region on the surface of the drain substrate.

3. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 1, wherein, The gate trench of the trench structure area is defined by a wall and includes a trench electrode having a first insulating layer made of insulating material that extends to cover the wall, and the trench gate electrode and a shielding electrode being surrounded by the first insulating layer and spaced apart vertically.

4. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 3, wherein, The trench electrode also has a second isolation layer and a third isolation layer formed sequentially from the surface of the first isolation layer and located between the first isolation layer and the shielding electrode, and a fourth isolation layer located between the trench gate electrode and the first isolation layer, and covering the surface of the trench gate electrode other than the top surface.

5. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 1, further comprising an inner dielectric layer disposed above the trench structure region and the planar structure region, and a source metal layer located on the top surface of the inner dielectric layer, wherein, The inner dielectric layer is provided with a plurality of vertically penetrating first and second through holes. The trench-type structure region also has two first conductive layers respectively connected to the first source electrodes. The planar structure region also has two second conductive layers respectively connected to the second source electrodes. The source electrode metal layer is electrically connected to the first conductive layers and the second conductive layers through a plurality of conductive plugs located in the first and second through holes.

6. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 1, wherein, The trench-like structure region also includes a first terminal structure surrounding the trench-like gate, the first well regions and the first source electrodes. The first terminal structure has a first annular groove recessed from the top surface of the drift layer, and a first insulating layer and a first electrode layer located in the first annular groove.

7. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 6, wherein, The first terminal structure also has a protective layer and a second insulating layer sequentially formed from the surface of the first insulating layer and located between the first insulating layer and the first electrode layer. The protective layer is made of nitride and does not contact the first electrode layer.

8. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 6, wherein, The planar structure region also includes a second terminal structure surrounding the planar gate electrode, the second well electrode, and the second source electrode, wherein the second terminal structure has a second annular groove recessed from the top surface of the drift layer, and a second insulating layer and a second electrode layer located in the second annular groove.

9. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 8, wherein, The planar structure region also includes a third terminal structure that separates the second well regions from the second sources. The third terminal structure is surrounded by the second terminal structure and has an elongated trench recessed from the top surface of the drift layer, a third insulating layer and a third electrode layer located in the elongated trench, and the planar gate electrode spans over the third terminal structure.

10. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 9, wherein, Along the first direction, the distance between the first annular groove and the gate groove, the distance between the first annular groove and the second annular groove, and the distance between the second annular groove and the elongated groove are the same.

11. The hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 9, wherein, The area between the first annular groove and the second annular groove in the drift layer is defined as a crossing zone.

12. A method for fabricating a hybrid power metal-oxide-semiconductor field-effect transistor, comprising the following steps: a drift layer formation step: forming a drift layer on a drain substrate, wherein one surface of the drain substrate defines an orthogonal first direction and a second direction; a trench formation step: etching downward from a top surface of the drift layer to form a gate trench; a gate electrode formation step: sequentially depositing an oxide material and a gate electrode material on the top surface of the drift layer, forming an opening in the oxide material at a predetermined region corresponding to a trench gate electrode, removing a portion of the gate electrode material, thereby forming a trench gate electrode in the gate trench, and forming a planar gate electrode outside the gate trench; A well region formation step: via a first type of doping, two first well regions are formed in the drift layer, respectively distributed along the first direction on both sides of the trench gate electrode, and four second well regions are distributed at intervals along the second direction on both sides below the planar gate electrode; and a source electrode formation step: via a second type of doping, two first sources are formed in the first well regions, and four second sources are formed in the second well regions, wherein, The second well regions are opposite each other along the second direction and are arranged at intervals along the first direction. The second source electrodes are located in the second well regions respectively, and the planar gate electrode spans over the second well regions.

13. The method for fabricating a hybrid power metal-oxide-semiconductor field-effect transistor as described in claim 12 further comprises the following steps: a dielectric layer forming step, forming an inner dielectric layer covering the top surface of the drift layer, the trench gate electrode, the planar gate electrode, the first well regions, the second well regions, the first source electrodes, and the second source electrodes, and forming a plurality of vertically penetrating first and second vias in the inner dielectric layer; and a metal layer forming step, forming a plurality of first conductive layers respectively connected to the first source electrodes and a plurality of second conductive layers respectively connected to the second source electrodes through the first and second vias, and forming a plurality of conductive plugs in the first and second vias, and depositing a source metal layer on the top surface of the inner dielectric layer, the source metal layer being electrically connected to the first and second conductive layers through the conductive plugs.

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