Semiconductor package and fabricating method thereof

Abstract

A semiconductor device structure and a method for manufacturing a semiconductor device are disclosed. As a non-limiting example, various features of this disclosure provide various semiconductor package structures and methods for manufacturing them, which include a thin, fine-pitch redistribution structure.

Description

Technical Field

[0001] This application relates to a semiconductor package and a method for manufacturing the same.

[0002] Cross-referencing / inclusion of related applications as a reference

[0003] This application relates to U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Same"; U.S. Patent Application Serial No. 14 / 083,779, filed November 19, 2013, entitled "Semiconductor Device with Through-Silicon Through-hole - Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed March 18, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same"; U.S. Patent Application Serial No. 14 / 313,724, filed June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same"; and U.S. Patent Application Serial No. 13 / 753,120, filed July 28, 2014, entitled "Semiconductor Device with Through-Silicon Through-hole - Less Deep Well". The contents of the following U.S. patent applications are incorporated herein by reference in their entirety: U.S. Patent Application Serial No. 14 / 444,450, entitled "Semiconductor Device with Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 524,443, entitled "Semiconductor Device with Reduced Thickness"; U.S. Patent Application Serial No. 14 / 532,532, entitled "Intermediate, Method of Manufacturing Thereof, Semiconductor Package Using Thereof, and Method of Manufacturing the Semiconductor Package"; U.S. Patent Application Serial No. 14 / 546,484, entitled "Semiconductor Device with Reduced Warpage"; and U.S. Patent Application Serial No. 14 / 671,095, entitled "Semiconductor Device and Method of Manufacturing Thereof"; the contents of each of these U.S. patent applications are incorporated herein by reference. Prior Technology

[0004] Current semiconductor packaging methods are inadequate, resulting in excessive costs, reduced reliability, or excessively large package sizes. Further limitations and drawbacks of these conventional methods will become apparent to those skilled in the art upon comparison with the disclosure as set forth in the remainder of the reference figures of this application. Summary of the Invention

[0005] The various features of this disclosure provide a semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, the various features of this disclosure provide various semiconductor package structures and methods for manufacturing them, which include a thin, fine-pitch redistribution structure. Simple Explanation of the Diagram

[0006] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and form part of this specification. These drawings depict examples of this disclosure and, together with the description, are used to explain the various principles of this disclosure. In the drawings: [Figure 1A]-[Figure 1J] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 2] is a flowchart of an example method for manufacturing a semiconductor package based on the various features of this disclosure. [Figure 3A]-[Figure 3B] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figures 4A]-[Figures 4D] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figures 5A]-[Figures 5F] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. Figures 6A-6D are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, according to various features of the present disclosure. [Figures 7A]-[Figures 7L] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, according to various features of the present disclosure. [Figure 8] is a flowchart of an example method for manufacturing a semiconductor package based on the various features of this disclosure. [Figure 9] is a cross-sectional view illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 10A]-[Figure 10B] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figures 11A]-[Figures 11D] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 12A]-[Figure 12B] are cross-sectional views illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, according to various features of the present disclosure. [Figure 13] is a cross-sectional view illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 14] is a cross-sectional view illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 15] is a cross-sectional view illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. [Figure 16] is a cross-sectional view illustrating an example of a semiconductor package and an example of a method for manufacturing a semiconductor package, depicting various features according to the present disclosure. Implementation

[0007] The following discussion is presented by providing various examples of the various features of this disclosure. These examples are not limiting, and therefore the scope of the various features of this disclosure should not necessarily be limited to any particular characteristic of the examples provided. In the following discussion, the terms "for example," "for instance," and "exemplary" are not limiting and are generally synonymous with "illustrative and non-limiting," "for example and non-limiting," and the like.

[0008] As used herein, "and / or" indicates any one or more of the items added in a table column by "and / or". For example, "x and / or y" indicates any element in the set of three elements {(x), (y), (x, y)}. In other words, "x and / or y" indicates "one or both of x and y". As another example, "x, y and / or z" indicates any element in the set of seven elements {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" indicates "one or more of x, y and z".

[0009] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the scope of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will further be understood that when the terms "comprising," "including," "having," and similar terms are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0010] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited to these terms. These terms are merely used to distinguish one element from another. Thus, for example, a first element, a first component, or a first segment discussed below may be referred to as a second element, a second component, or a second segment without departing from the teachings of this disclosure. Similarly, various spatial terms such as "above," "below," "side," and the like may be used in a relative manner to distinguish one element from another. However, it should be understood that components may be oriented in different ways; for example, a semiconductor device may be turned to the side, so that its "top" surface is horizontal and its "side" surface is vertical, without departing from the teachings of this disclosure.

[0011] The various features of this disclosure provide a semiconductor device or package and a method of manufacturing (or fabricating) thereof, which can reduce costs, improve reliability, and / or improve the manufacturability of the semiconductor device.

[0012] The features of this disclosure, as well as other features, will be described in the following description of various exemplary embodiments, or will become apparent from the description. The various features of this disclosure will now be presented with reference to the accompanying drawings, enabling those skilled in the art to easily implement these features.

[0013] Figures 1A-1J are cross-sectional views illustrating an example semiconductor package and an example method of manufacturing a semiconductor package according to various features of this disclosure. The structure shown in Figures 1A-1J may share any or all of the features with similar structures shown in Figures 3A-3B, 4A-4D, 5A-5F, 6A-6D, 7A-7L, 9, 10A-10B, 11A-11D, 12A-12B, 13, 14, 15, and 16. Figure 2 is a flowchart of an example method 200 for manufacturing a semiconductor package according to various features of this disclosure. Figures 1A-1K, for example, can depict an example semiconductor package of various steps (or blocks) of method 200 in Figure 2. Figures 1A-1K and Figure 2 will now be discussed together. It should be noted that the order of the blocks in the example method 200 may vary without departing from the scope of this disclosure.

[0014] The method 200 of this example, in block 205, may include preparing a logic wafer for processing (e.g., for packaging). Block 205 may include preparing a logic wafer for processing in any of a variety of ways, the non-limiting of which are shown herein.

[0015] For example, block 205 may include receiving a logic wafer, for example, from a supplier, from an upstream process at a manufacturing location, etc. The logic wafer may include, for example, a semiconductor wafer comprising a plurality of active semiconductor dies. The semiconductor dies may include, for example, a processor die, a memory die, a programmable logic die, an application-specific integrated circuit die, a general logic die, etc.

[0016] Block 205 may include, for example, forming conductive interconnect structures on the logic wafer. Such conductive interconnect structures may include, for example, conductive pads, planes, bumps or balls, conductive pillars, etc. The forming process may include, for example, attaching a pre-formed interconnect structure to the logic wafer, electroplating the interconnect structure on the logic wafer, etc.

[0017] In one exemplary embodiment, the conductive structures may include conductive pillars (which may be copper and / or nickel) and may include a solder cap (e.g., which may be tin and / or silver). For example, a conductive structure including conductive pillars may include: (a) a bump bottom metallization ("UBM") structure comprising (i) a titanium-tungsten (TiW) layer (which may be referred to as a "seed layer") formed by sputtering, and (ii) a copper (Cu) layer formed by sputtering on the titanium-tungsten layer; (b) a copper pillar formed by electroplating on the UBM; and (c) a solder layer formed on the copper pillar, or a nickel layer formed on the copper pillar and a solder layer formed on the nickel layer.

[0018] Furthermore, in an exemplary embodiment, the conductive structures may include a lead and / or lead-free wafer bump. For example, the lead-free wafer bump (or interconnect structure) may be formed at least in part by: (a) forming a bump bottom metallization (UBM) structure by (i) sputtering to form a titanium (Ti) or titanium-tungsten (TiW) layer, (ii) sputtering to form a copper (Cu) layer on the titanium or titanium-tungsten layer, (iii) electroplating to form a nickel (Ni) layer on the copper layer; and (b) electroplating to form a lead-free solder material on the nickel layer of the UBM structure, wherein the lead-free solder material has a silver (Ag) content of 1% to 4% by weight, and the remainder of the content by weight is tin (Sn).

[0019] Block 205 may include, for example, performing partial or complete thinning of the logic wafer (e.g., grinding, etching, etc.). Block 205 may also include, for example, dicing the logic wafer into individual dies or groups of dies for subsequent mounting. Block 205 may also include receiving the logic wafer from a manufacturing station adjacent to or upstream of one of the manufacturing facilities, from another geographical location, etc. The received logic wafer may be, for example, already fabricated, or additional fabrication steps may be performed.

[0020] Generally, block 205 may include the fabrication of a logic wafer for processing (e.g., for packaging). Therefore, the scope of this disclosure should not be limited to the characteristics of a particular type of logic wafer and / or die processing.

[0021] The method 200 of this example, in block 210, may include the fabrication of a carrier, substrate, or wafer. The fabricated (or received) wafer may be referred to as a redistributed structure wafer or an RD wafer. Block 210 may include the fabrication of an RD wafer for processing in any of various manners, non-limiting examples of which are presented herein.

[0022] The RD wafer may include, for example, an intermediate wafer, a packaging substrate wafer, etc. The RD wafer may include, for example, a redistribution structure formed (e.g., die-by-die) on a semiconductor (e.g., silicon) wafer. The RD wafer may include only electrical paths and not electronic devices (e.g., semiconductor devices). The RD wafer may also include passive electronic devices, but not active semiconductor devices. For example, the RD wafer may include one or more conductive layers or lines formed on or coupled to a substrate or carrier (e.g., directly or indirectly thereon). Examples of the carrier or substrate may include a semiconductor (e.g., silicon) wafer or a glass substrate. Examples of processes used to form conductive layers (e.g., copper, aluminum, tungsten, etc.) on a semiconductor wafer include semiconductor wafer fabrication processes, which may also be referred to herein as back-end processes (BEOL). In an exemplary embodiment, the conductive layers may be deposited on or on a substrate using a sputtering and / or electroplating process. These conductive layers may be referred to as redistribution layers. These redistribution layers may be used to wrap an electrical signal between two or more electrical connections, and / or to wrap an electrical connection with a wider or narrower spacing.

[0023] In one exemplary embodiment, various portions of the redistributed structure (e.g., an interconnect structure that can be attached to an electronic device (e.g., a plane, a line, etc.)) may be formed with a pitch of one sub-micrometer (or a center-to-center spacing) and / or less than one 2-micrometer pitch. In various other embodiments, a pitch of 2-5 micrometers may be used.

[0024] In one exemplary embodiment, a silicon wafer on which the redistribution structure is formed may include a lower grade of silicon than that which can be fully utilized to form the semiconductor grains ultimately attached to the redistribution structure. In another exemplary embodiment, the silicon wafer may be a recycled silicon wafer from a failed semiconductor device wafer manufacturing process. In yet another exemplary embodiment, the silicon wafer may include a thinner silicon layer than that which can be fully utilized to form the semiconductor grains ultimately attached to the redistribution structure. Block 210 may also include receiving the RD wafer from a manufacturing station adjacent to or upstream of one of the manufacturing facilities, from another geographical location, etc. The received RD wafer may, for example, be already fabricated or may require additional fabrication steps.

[0025] Figure 1A is an illustration of an example providing various features of block 210. Referring to Figure 1A, the RD wafer 100A may, for example, include a support layer 105 (e.g., a silicon or other semiconductor layer, a glass layer, etc.). A redistribution (RD) structure 110 may be formed on the support layer 105. The RD structure 110 may, for example, include a substrate dielectric layer 111, a first dielectric layer 113, a first conductive line 112, a second dielectric layer 116, a second conductive line 115, and an interconnect structure 117.

[0026] The substrate dielectric layer 111 may, for example, be on the support layer 105. The substrate dielectric layer 111 may, for example, include an oxide layer, a nitride layer, etc. The substrate dielectric layer 111 may, for example, be formed according to specifications and / or may be natural. The dielectric layer 111 may be referred to as a protective layer. For example, the dielectric layer 111 may be a silicon dioxide layer formed using a low-pressure chemical vapor deposition (LPCVD) process, or may include the silicon dioxide layer.

[0027] The RD wafer 100A may, for example, include first conductive lines 112 and a first dielectric layer 113. The first conductive lines 112 may, for example, include deposited conductive metals (e.g., copper, aluminum, tungsten, etc.). The conductive lines 112 may be formed by sputtering and / or electroplating. The conductive lines 112 may, for example, be formed at a spacing of one or two micrometers (or a center-to-center spacing). The first dielectric layer 113 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It is noted that in various embodiments, the dielectric layer 113 may be formed prior to the first conductive lines 112, for example, by forming vias that are then filled into the first conductive lines 112 or a portion thereof. In an embodiment, for example, including copper conductive lines, a dual damascene process may be used to deposit these lines.

[0028] In an alternative component, the first dielectric layer 113 may comprise an organic dielectric material. For example, the first dielectric layer 113 may comprise bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the features of this disclosure are not limited thereto. The organic dielectric material may be formed using any of a variety of methods (e.g., chemical vapor deposition (CVD)). In this alternative component, the first conductive lines 112 may, for example, be spaced at a pitch of 2-5 micrometers (or center-to-center spacing).

[0029] The RD wafer 100A may, for example, include a second conductive line 115 and a second dielectric layer 116. The second conductive lines 115 may, for example, include deposited conductive metals (e.g., copper, etc.). The second conductive lines 115 may, for example, be connected to individual first conductive lines 112 through individual conductive vias 114 (e.g., in the first dielectric layer 113). The second dielectric layer 116 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative embodiment, the second dielectric layer 116 may include an organic dielectric material. For example, the second dielectric layer 116 may include bis(cis-butenedioic acid)imide / trinitrogen trap (BT), phenolic resins, polyimide (PI), phenylcyclobutene (BCB), polybenzoxazole (PBO), epoxy resins, and equivalents and compounds thereof, but the features of this disclosure are not limited thereto. The second dielectric layer 116 can be formed, for example, using a CVD process, but the scope of this disclosure is not limited thereto.

[0030] Although the two sets of dielectric layers and conductive lines are depicted in Figure 1A, it should be understood that the RD structure 110 of the RD wafer 100A may include any number of such layers and lines. For example, the RD structure 110 may include only one dielectric layer and / or multiple sets of conductive lines, three sets of dielectric layers and / or conductive lines, etc.

[0031] Similar to the logic wafer fabrication in block 205, block 210 may include interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) formed on one surface of the RD structure 110. An example of such interconnect structure 117 is shown in FIG. 1A, wherein the RD structure 110 includes interconnect structure 117, which is shown to be formed on the front (or top) side of the RD structure 110 and electrically connected to individual second conductive lines 115 through conductive vias in the second dielectric layer 116. Such interconnect structure 117 can be used, for example, to couple the RD structure 110 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

[0032] These interconnect structures 117 may include, for example, any of a variety of conductive materials (e.g., any one or a combination of copper, nickel, gold, etc.). These interconnect structures 117 may also include, for example, solder.

[0033] Generally, block 210 may include the fabrication of a redistributed structure wafer (RD wafer). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such fabrication.

[0034] The method 200 of this example may include forming an interconnect structure (e.g., a through-mold via (TMV) interconnect structure) on the RD wafer in block 215. Block 215 may include forming such an interconnect structure in any of a variety of ways.

[0035] These interconnect structures may include any of a variety of features. For example, these interconnect structures may include solder balls or bumps, multi-spherical solder pillars, elongated solder balls, metal (e.g., copper) core balls with a solder layer on a metal core, electroplated pillar structures (e.g., copper pillars, etc.), wire structures (e.g., wire-jointed wires), etc.

[0036] These interconnect structures can include any of various sizes. For example, these interconnect structures can extend from the RD wafer to a height less than the height of the electronic component coupled to the RD wafer (e.g., in block 220). Similarly, these interconnect structures can extend from the RD wafer to a height greater than or equal to the height of the electronic component coupled to the RD wafer. The importance of this relative height will become apparent in the discussion herein (e.g., in discussions of molding thinning, package stacking, top substrate attachment, top redistribution structure formation, etc.). These interconnect structures can also be formed, for example, at various pitches (or center-to-center spacing). For example, these interconnect structures (e.g., conductive pillars or columns) can be plated and / or bonded at a pitch of 150-250 micrometers or less. Similarly, these interconnect structures (e.g., elongated and / or metal-filled solder structures) can be attached at a pitch of 250-350 micrometers or less. Similarly, for example, these interconnect structures (e.g., solder balls) can be attached at a pitch of 350-450 micrometers or less.

[0037] Block 215 may include attaching the interconnect structures in any of a variety of ways. For example, block 215 may include reflowing the interconnect structures onto the RD wafer, electroplating the interconnect structures onto the RD wafer, wire bonding the interconnect structures onto the RD wafer, using conductive epoxy resin to attach pre-formed interconnect structures to the RD wafer, and so on.

[0038] Figure 1B is an illustration of an example of various features of block 215 (e.g., features of interconnect structure formation). In the example component 100B, interconnect structure 121 (e.g., solder ball) is attached (e.g., reflow attachment, attachment using a solder ball drop process, etc.) to RD structure 110 of RD wafer 100A.

[0039] Although the interconnection structure 121 of two columns is shown, various implementations may include a single column, three columns, or any number of columns. As will be discussed herein, various exemplary implementations may not have this interconnection structure 121, and therefore block 215 may be included in exemplary method 200.

[0040] It is noted that although in method 200 of this example, block 215 is performed before the wafer molding operation of block 230, the interconnect structures can alternatively be formed after the wafer molding operation (e.g., forming through-holes in the molding material and then filling such holes with a conductive material). It is also noted that, as shown in FIG. 2, block 215 can, for example, be performed after the die attachment operation of block 220, rather than before die attachment.

[0041] Generally, block 215 may include interconnect structures formed on the RD wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of a particular type of interconnect structure or to the characteristics of any particular manner in which such interconnect structures are formed.

[0042] The method 200 of this example may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) in block 220. Block 220 may include attaching the dies to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

[0043] The semiconductor die may include features of any of various types of semiconductor dies. For example, the semiconductor die may include a processor die, a memory die, an application-specific integrated circuit die, a general logic die, an active semiconductor component, etc. It should be noted that passive components may also be attached to block 220.

[0044] Block 220 may include attaching the semiconductor die using any of a variety of methods (e.g., as prepared in block 205). For example, block 220 may include attaching the semiconductor die using mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.

[0045] Figure 1B is an illustration of an example of various features of block 220, such as die attachment features. For example, a first die 125 (e.g., which may have been diced from a logic wafer fabricated in block 205) is electrically and mechanically attached to the redistribution structure 110. Similarly, a second die 126 (e.g., which may have been diced from a logic wafer fabricated in block 205) is electrically and mechanically attached to the redistribution structure 110. For example, as explained in block 205, the logic wafer (or its dies) may have been fabricated with various interconnect structures formed thereon (e.g., conductive pads, planes, bumps, balls, wafer bumps, conductive pillars, etc.). This structure is generally shown as item 119 in Figure 1B. Block 220 may include, for example, any of a variety of attachment processes (e.g., batch reflow, thermocompression bonding (TCB), conductive epoxy, etc.) to electrically and mechanically attach such an interconnect structure to the redistribution structure 110.

[0046] The first die 125 and the second die 126 may include any of a variety of die features. In one example scenario, the first die 125 may include a processor die, and the second die 126 may include a memory die. In another example scenario, the first die 125 may include a processor die, and the second die 126 may include a coprocessor die. In yet another example scenario, the first die 125 may include a sensor die, and the second die 126 may include a sensor processing die. Although the component 100B in FIG. 1B is shown as having two dies 125, 126, it may have any number of dies. For example, it may have only one die, three dies, four dies, or more than four dies.

[0047] Furthermore, although the first die 125 and the second die 126 are shown attached laterally to the redistribution structure 110 relative to each other, they can also be configured with a vertical assembly. Various non-limiting examples of such a structure are shown and discussed herein (e.g., die stacking on dies, dies attached to opposite substrate sides, etc.). Moreover, although the first die 125 and the second die 126 are shown to have generally similar dimensions, such dies 125, 126 may include different individual features (e.g., die height, coverage area, interconnection spacing, etc.).

[0048] The first die 125 and the second die 126 are depicted as having a generally uniform pitch, but this is not necessarily the case. For example, most or all of the contacts 119 of the first die 125 in a region of the first die coverage area adjacent to the second die 126 and / or most of the contacts 119 of the second die 126 in a region of the second die coverage area adjacent to the first die 125 may have a substantially finer pitch than most or all of the other contacts 119. For example, the first 5, 10, or n columns of contacts 119 of the first die 125 closest to the second die 126 (and / or the second die 126 closest to the first die 125) may have a pitch of 30 micrometers, while other contacts 119 may have a pitch of approximately 80 micrometers and / or 200 micrometers. The RD structure 110 can therefore have corresponding contact structures and / or circuitry at these corresponding pitches.

[0049] Generally, block 220 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular die, or to the characteristics of any particular layout of the polydies, or to the characteristics of any particular manner in which such dies are attached, etc.

[0050] Method 200 of this example may include underfilling (underfilling) in block 220 attaching semiconductor dies and / or other components to the RD structure. Block 225 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are shown herein.

[0051] For example, after the die attachment in block 220, block 225 may include underfilling the semiconductor die with a capillary underfill. For example, the underfill may include a sufficiently viscous reinforcing polymeric material that flows between the attached die and the RD wafer in a capillary action.

[0052] Similarly, for example, block 225 may include filling the semiconductor die with a non-conductive paste (NCP) and / or a non-conductive film (NCF) or tape underfill while the die is being attached to block 220 (e.g., using a thermosetting bonding process). For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) before the semiconductor die is attached.

[0053] As with all the blocks depicted in method 200 of this example, block 225 can be executed at any point in the process of method 200, provided that the space between the grain and the redistributed structure is accessible.

[0054] The underfill can also occur in a different block of method 200 in this example. For example, the underfill can be performed as part of the wafer molding block 230 (e.g., using a molding underfill).

[0055] Figure 1B is an illustration of an example of various features of block 225 (e.g., the features of the underfill). The underfill 128 is disposed between the first semiconductor die 125 and the redistribution structure 110, and between the second semiconductor die 126 and the redistribution structure 110, for example, around the contacts 119.

[0056] Although the underfill 128 is generally depicted as flat, it can be raised and form fillets on the sides of the semiconductor dies and / or other components. In one example, at least one-quarter or at least half of the die side surfaces may be covered by the underfill material. In another example, one or more or all of the entire side surfaces may be covered by the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the dies and other components, and / or between other components may be filled with the underfill material. In one example embodiment, the underfill 128 may cover the entire redistribution structure 110 of the RD wafer. In this example embodiment, when the RD wafer is subsequently diced, such dicing may also cut through the underfill 128.

[0057] Generally, block 225 may include an underfill material attached to the semiconductor die and / or other components of the RD structure in block 220. Therefore, the scope of this disclosure should not be limited to any particular type of underfill or any particular method of performing such underfill.

[0058] The method 200 of this example may include molding the RD wafer (e.g., or an RD structure) in block 230. Block 230 may include molding the RD wafer in any of a variety of ways, of which non-limiting examples are presented herein.

[0059] For example, block 230 may include molded on the top surface of the RD wafer, on the dies and / or other components attached to block 220, on the interconnect structure formed in block 215 (e.g., conductive spheres, ellipsoids, pillars or columns (e.g., electroplated pillars, lines or bonding lines, etc.), etc.), on the underfill formed in block 225, etc.

[0060] Block 230 may include compression molding (e.g., using liquid, powder and / or film) or vacuum molding. Similarly, block 230 may include a transfer molding process (e.g., a wafer-level transfer molding process).

[0061] The molding material may include, for example, any of a variety of characteristics. For instance, the molding material (e.g., epoxy molding compound (EMC), epoxy resin molding compound, etc.) may include a relatively high modulus, for example, to provide wafer support in a subsequent process. Similarly, for example, the molding material may include a relatively low modulus to provide wafer flexibility in a subsequent process.

[0062] As explained herein, for example, with respect to block 225, the molding process of block 230 can provide an underfill material between the die and the RD wafer. In this example, there can be a uniform material between the molding underfill material and the molding material encapsulating the semiconductor die.

[0063] Figure 1C is an illustration of an example of various features (e.g., molding features) of block 230. For example, molding assembly 100C is shown in which molding material 130 covers the interconnect structures 121, the first semiconductor die 125, the second semiconductor die 126, the primer filler 128, and the top surface of the redistribution structure 110. Although the molding material 130 (which may also be referred to herein as encapsulating material) is shown to completely cover the sides and tops of the first semiconductor die 125 and the second semiconductor die 126, this is not necessary. For example, block 230 may include molding techniques using a film-assisted or die-sealing method to keep the tops of the dies free of molding material.

[0064] Generally, the molding material 130 can, for example, directly contact and cover the portions of the grains 125, 126 that are not covered by the primer filler 128. For example, in a scenario where at least a first portion of the sides of the grains 125, 126 is covered by the primer filler 128, the molding material 130 can directly contact and cover a second portion of the sides of the grains 125, 126. The molding material 130 can also, for example, fill the spaces between the grains 125, 126 (e.g., at least a portion of the spaces not yet filled by the primer filler 128).

[0065] Generally, block 230 may include molding the RD wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular molding material, structure, and / or technology.

[0066] Method 200 of this example may include grinding (or thinning) the molding material applied in block 235. Block 235 may include grinding (or thinning) the molding material in any of a variety of ways, of which non-limiting examples are presented herein.

[0067] Block 235 may include, for example, mechanically grinding the molding material to thin it. Such thinning may, for example, preserve the grains and / or interconnect structures as overmolded, or may expose one or more grains and / or one or more interconnect structures.

[0068] Block 235 may include grinding other components besides the molding compound. For example, block 235 may include grinding the tip side (e.g., the back side or non-active side) of the die to which block 220 is attached. Block 235 may also include grinding the interconnect structure formed in block 215. Furthermore, in a scenario where the primer filler applied to block 225 or block 230 extends upward sufficiently, block 235 may also include grinding such primer filler material. Such grinding may, for example, create a flat planar surface at the tip of the material being ground.

[0069] Block 235 could be, for example, a section in which the height of the molding material was originally formed in a plot of desired thickness and is skipped.

[0070] Figure 1D is an illustration of an example of various features of block 235 (e.g., the molding and grinding features). Component 100D is depicted in which the molding material 130 (e.g., relative to the molding material 130 depicted in Figure 1C) is thinned to expose the top surfaces of grains 125, 126. In this example, the grains 125, 126 may also have been ground (or thinned).

[0071] Although, as shown in Figure 1D, the top surface of the molding material is over the interconnect structures 121, and therefore the interconnect structures 121 are not ground, they can still be ground. This exemplary embodiment may, for example, produce a top surface at this stage that includes grains 125, 126, a top surface of the molding material 130, and a top surface of the interconnect structures 121, all on a common plane.

[0072] As explained herein, the molding material 130 can be retained in an overmold configuration to cover the grains 125, 126. For example, the molding material 130 may not be ground, or the molding material 130 may be ground, but not to a height that exposes the grains 125, 126.

[0073] Generally, block 235 may include grinding (or thinning) of the molding material applied to block 230. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular amount or type of grinding (or thinning).

[0074] Method 200 of this example may include stripping the molding material applied in block 230 in block 240. Block 240 may include stripping the molding material in any of a variety of ways, non-limiting examples of which are provided herein.

[0075] As discussed herein, the molding material may cover the interconnect structure formed in block 215. If the molding material covers the interconnect structure and such interconnect structure needs to be exposed (e.g., for subsequent package attachment, top-side redistribution layer formation, top-side multilayer substrate attachment, electrical connection, heat sink connection, electromagnetic shielding connection, etc.), then block 240 may include etching the molding material to expose such interconnect structure.

[0076] Block 240 may, for example, include using laser ablation to expose the interconnect structures through the molding material. Similarly, block 240 may include using soft beam drilling, mechanical drilling, chemical drilling, etc.

[0077] Figure 1D is an illustration of an example of various features of block 240 (e.g., the erosion feature). For example, component 100D is shown to include eroded through-holes 140 extending through the molding material 130 to the interconnect structure 121. Although these eroded through-holes 140 are shown to have vertical sidewalls, it should be understood that the through-holes 140 can include any of a variety of shapes. For example, the sidewalls can be sloping (e.g., having a larger opening on the top surface of the molding material 130 than in the interconnect structure 121).

[0078] Although block 240 is depicted in Figure 2 immediately following wafer molding of block 230 and molding and polishing of block 235, block 240 can be performed at any point after the method 200. For example, block 240 can be performed after the wafer support structure (e.g., to which block 245 is attached) has been removed.

[0079] Generally, block 240 may include the molding material applied to block 230 (e.g., to expose the interconnect structure formed in block 215). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular manner in which such erosion is performed, or to the characteristics of any particular eroded through-hole structure.

[0080] The method 200 of this example, in block 245, may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Block 245 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein.

[0081] The wafer support structure may include, for example, a wafer or fixing device formed of silicon, glass, or various other materials (e.g., dielectric materials). Block 245 may include, for example, using an adhesive, a vacuum fixing device, etc., to attach the molded RD wafer to the wafer support structure. It is noted that, as depicted and explained herein, a redistribution structure may be formed on the top (or back) side of the die and molding material before the wafer support is attached.

[0082] Figure 1E is an illustration of an example of various features of block 245 (e.g., wafer support attachment features). The wafer support structure 150 is attached to the molding material 130 and the top sides of the dies 125, 126. The wafer support structure 150 may be attached using an adhesive, for example, and this adhesive may also be formed in the vias 140 and contact the interconnect structures 121. In another example assembly, the adhesive does not enter the vias 140 and / or does not contact the interconnect structures 121. It should be noted that in an assembly where the tops of the dies 125, 126 are covered by the molding material 130, the wafer support structure 150 may only be directly coupled to the top of the molding material 130.

[0083] Generally, block 245 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer support structure or to the characteristics of any particular manner of attaching a wafer support structure.

[0084] The method 200 of this example may include removing a support layer from the RD wafer in block 250. Block 250 may include removing the support layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0085] As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and / or supported. The support layer may, for example, include a semiconductor material (e.g., silicon). In an example scenario where the support layer comprises a silicon wafer layer, block 250 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all of the silicon from the RD wafer (e.g., at least 90% or 95%), etc.). For example, block 250 may include mechanically grinding almost all of the silicon, followed by a dry or wet chemical etching to remove the remainder (or almost all of the remainder). In an example scenario where the support layer is loosely attached to the RD structure formed (or supported) thereon, block 250 may include pulling or peeling to separate the support layer from the RD structure.

[0086] Figure 1F is an illustration of an example of various features of block 250 (e.g., support layer removal features). For example, the support layer 105 (shown in Figure 1E) is removed from the RD structure 110. In this illustrative example, the RD structure 110 may still include a substrate dielectric layer 111 as discussed herein (e.g., an oxide, nitride, etc.).

[0087] Generally, block 250 may include the removal of a support layer from the RD wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular method of wafer material removal.

[0088] The method 200 of this example may include forming and patterning a dielectric layer of a first redistribution layer (RDL) in block 255 for etching an oxide layer of the RD structure. Block 255 may include forming and patterning the first RDL dielectric layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0089] In an example roughly described here, the RD structure of the RD wafer is generally formed on an oxide layer (or nitride or other dielectric). To enable metal-to-metal attachments to the RD structure, the portion of the oxide layer covering the wiring (or pads or planes) of the RD structure can be removed, for example, by etching. It should be noted that the oxide layer does not necessarily need to be removed or completely removed, as long as it has acceptable conductivity.

[0090] The first RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The first RDL dielectric layer may, for example, comprise a laminated film or other materials. The first RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the first RDL dielectric layer may comprise an inorganic material.

[0091] In one exemplary embodiment, the first RDL dielectric layer may include an organic material (e.g., polyimide, PBO, etc.) formed on a first side of a base dielectric layer of the RD structure, and the base dielectric layer may include an oxide or nitride or other dielectric material.

[0092] The first RDL dielectric layer can be used, for example, as a mask for etching a base dielectric layer, such as an oxide or nitride layer (e.g., in block 260). Similarly, for example, after etching, the first RDL dielectric layer can be retained, for example, to form conductive RDL lines thereon.

[0093] In an alternative scenario (not shown), a temporary masking layer (e.g., a temporary photoresist layer) may be used. For example, after etching, this temporary masking layer may be removed and replaced by a permanent RDL dielectric layer.

[0094] Figure 1G is an illustration of an example of the various features of block 255. For example, the first RDL dielectric layer 171 is formed and patterned on the substrate dielectric layer 111. The patterned first RDL dielectric layer 171 may include, for example, vias 172 through the first RDL dielectric layer 171, and the substrate dielectric layer 111 may be etched through the vias 172 (e.g., in block 260), and a first line (or a portion thereof) may be formed in the vias 172 (e.g., in block 265).

[0095] Generally, block 255 may include, for example, forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer) on the substrate dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of a particular dielectric layer or to the characteristics of a particular manner in which a dielectric layer is formed.

[0096] The method 200 of this example, in block 260, may include etching the substrate dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as the unmasked portion thereof. Block 260 may include performing the etching in any of a variety of ways, of which non-limiting examples are shown herein.

[0097] For example, block 260 may include performing a dry etching process (or a wet etching process) to etch the portion of the substrate dielectric layer (e.g., oxide, nitride, etc.) exposed by a via through the first dielectric layer, which acts as a mask for the etching.

[0098] Figure 1G is an illustration of an example of various features (e.g., dielectric etching features) of block 260. For example, the portion of the substrate dielectric layer 111 shown in Figure 1F that is below the first conductive line 112 has been removed since Figure 1G. This, for example, enables a metal-to-metal contact between the first conductive line 112 and the first RDL line formed in block 265.

[0099] Generally, block 260 may include, for example, etching of the substrate dielectric layer. Therefore, the scope of this disclosure should not be limited to any particular method of performing such etching.

[0100] Method 200 of this example may include forming a first redistribution layer (RDL) line in block 265. Block 265 may include forming the first RDL line in any of a variety of ways, of which non-limiting examples are presented herein.

[0101] As discussed herein, the first RDL dielectric layer (e.g., formed in block 255) can be used for etching (e.g., in block 260) and then retained for the formation of the first RDL lines. Alternatively, the first RDL dielectric layer can be formed and patterned after the etching process. In yet another alternative embodiment discussed herein, the etching process for the substrate dielectric layer can be skipped, for example in an embodiment where the substrate dielectric layer (e.g., a thin oxide or nitride layer) is sufficiently conductive to adequately serve as a conductive path between metal lines.

[0102] Block 265 may include a first conductive line exposed through the patterned first RDL dielectric layer forming the first RDL line to attach to the RD structure. The first RDL line may also be formed on the first RDL dielectric layer. Block 265 may include forming the first RDL line in any of a variety of ways (e.g., by electroplating), but the scope of this disclosure is not limited to any particular feature of forming such a line.

[0103] These first RDL lines may comprise any of various materials (e.g., copper, gold, nickel, etc.). The first RDL lines may, for example, comprise any of various dimensional features. For instance, a typical pitch for the first RDL lines may be 5 micrometers. In an exemplary embodiment, the first RDL lines may be formed at a pitch (e.g., a sub-micrometer pitch, approximately 0.5 micrometers, etc.) where the various lines of the RD structure are formed with a center-to-center spacing approximately or at least an order of magnitude larger than that of the RD wafer.

[0104] Figures 1G and 1H illustrate an example of various features (e.g., RDL line formation features) of block 265. For example, a first portion 181 of the first RDL line may be formed in a via 172 of the first RDL dielectric layer 171 and contact the first conductive line 112 exposed by the via 172 of the RD structure 110. Similarly, for example, a second portion 182 of the first RDL line may be formed on the first RDL dielectric layer 171.

[0105] Generally, block 265 may include lines forming a first redistribution layer (RDL). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular RDL line or to the characteristics of any particular manner in which such an RDL line is formed.

[0106] The method 200 of this example may include forming and patterning a second RDL dielectric layer on the first RDL lines (e.g., formed in block 265) and the first RDL dielectric layer (e.g., formed in block 255) in block 270. Block 270 may include forming and patterning the second dielectric layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0107] For example, block 270 may share any or all of the features with block 255. The second RDL dielectric layer may, for example, be formed using the same material as the first RDL dielectric layer formed in block 255.

[0108] The second RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The second RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the first RDL dielectric layer may comprise an inorganic material.

[0109] Figure 1H is an illustration of an example of the various features of block 270. For example, the second RDL dielectric layer 183 is formed on the first RDL lines 181, 182 and on the first RDL dielectric layer 171. As shown in Figure 1H, vias 184 are formed in the second RDL layer 183, and conductive contacts can be made through the vias 184 to the first RDL lines 182 exposed through such vias 184.

[0110] Generally, block 270 may include forming and / or patterning a second RDL dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular dielectric layer or to the characteristics of any particular manner in which a dielectric layer is formed.

[0111] Method 200 of this example may include forming a second redistribution layer (RDL) circuit in block 275. Block 275 may include forming the second RDL circuit in any of a variety of ways, non-limiting examples of which are presented herein. Block 275 may, for example, share any or all of the features with block 265.

[0112] Block 275 may include forming second RDL lines attached to the first RDL lines (e.g., formed in block 265), which are exposed through vias in the patterned second RDL dielectric layer (e.g., formed in block 270). The second RDL lines may also be formed on the second RDL dielectric layer. Block 275 may include forming the second RDL lines using any of a variety of methods (e.g., by electroplating), but the scope of this disclosure is not limited to any particular method.

[0113] Like the first RDL lines, these second RDL lines can include any of various materials (e.g., copper, etc.). Furthermore, the second RDL lines can, for example, include any of various dimensional features.

[0114] Figures 1H and 1I illustrate an example of various features of block 275. For example, the second RDL lines 191 may be formed within vias 184 in the second RDL dielectric layer 183 to contact the first RDL lines 181 exposed through such vias 184. Furthermore, the second RDL lines 191 may be formed on the second RDL dielectric layer 183.

[0115] Generally, block 275 may include lines forming a second redistribution layer (RDL). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular RDL line or to the characteristics of any particular manner in which such an RDL line is formed.

[0116] The method 200 of this example may include forming and patterning a third RDL dielectric layer on the second RDL line (e.g., formed in block 275) and the second RDL dielectric layer (e.g., formed in block 270). Block 280 may include forming and patterning the third dielectric layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0117] For example, block 280 may share any or all of the features with blocks 270 and 255. The third RDL dielectric layer may be formed, for example, using the same material as the first RDL dielectric layer formed in block 255 (and / or after etching of block 260 and removal of a temporary masking layer), and / or using the same material as the second RDL dielectric layer formed in block 270.

[0118] The third RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The third RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the third RDL dielectric layer may comprise an inorganic material.

[0119] Figure 1I is an illustration of an example of various features of block 280. For example, the third RDL layer 185 may be formed on the second RDL lines 191 and on the second RDL layer 183. As shown in Figure 1I, vias are formed in the third RDL layer 185, through which conductive contacts can be made to the second RDL lines 191 exposed by such vias.

[0120] Generally, block 280 may include forming and / or patterning a third RDL dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular dielectric layer or to the characteristics of any particular manner in which a dielectric layer is formed.

[0121] The method 200 of this example may include forming interconnect structures on the second RDL lines and / or on the third RDL dielectric layer in block 285. Block 285 may include forming the interconnect structures in any of a variety of ways, of which non-limiting examples are presented herein.

[0122] Block 285 may, for example, include forming an underbump metal on a portion of the second RDL line exposed through a via in the third dielectric layer. Block 285 may then, for example, include attaching conductive bumps or balls to the underbump metal. Other interconnect structures may also be used, examples of which are shown herein (e.g., conductive pillars or columns, solder balls, solder bumps, etc.).

[0123] Figure 1I is an illustration of an example of various features of block 285 (e.g., features of interconnect structure formation). For example, interconnect structure 192 is attached to the second RDL lines 191 through vias formed in the third RDL dielectric layer 185. It should be noted that although interconnect structures 192 are depicted as smaller than interconnect structure 121, this disclosure is not so limited. For example, interconnect structures 192 may be the same size as interconnect structure 121 or larger than interconnect structure 121. Furthermore, interconnect structures 192 may be the same type of interconnect structure as interconnect structure 121 or may be a different type.

[0124] Although the redistribution layers formed in blocks 255-285 (which may also be referred to as front redistribution layers (RDL)) are depicted in Figure 1 generally as a fan-out component (e.g., extending beyond the coverage areas of dies 125, 126), they can also be formed as a fan-in component, for example, where interconnect structure 192 does not generally extend beyond the coverage areas of dies 125, 126. Non-limiting examples of such components are presented herein.

[0125] Generally, block 285 may include interconnect structures formed on the second RDL lines and / or on the third RDL dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular interconnect structure or to any particular manner in which the interconnect structure is formed.

[0126] Method 200 of this example may include debonding (or separating) the wafer support attached to block 245 in block 290. Block 290 may include performing such debonding in any of a variety of ways, the non-limiting nature of which is presented herein.

[0127] For example, in an embodiment where the wafer support is adhesively attached, the adhesive can be released (e.g., by heat and / or force). Similarly, chemical release agents can be used. In another embodiment where the wafer support is attached using a vacuum force, the vacuum force can be released. It should be noted that in an embodiment involving adhesives or other substances to facilitate the mounting of the wafer support, block 285 may include removing residues from the electrical components and / or from the wafer support after the debonding process.

[0128] Figures 1I and 1J illustrate an example of various features of block 290. For example, the wafer support 150 depicted in Figure 1I is removed in Figure 1J.

[0129] Generally, block 290 may include debonding the wafer support. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer support, or to any particular method of debonding a wafer support.

[0130] Method 200 of this example may include dicing the wafer in block 295. Block 295 may include dicing the wafer in any of a variety of ways, of which non-limiting examples are presented herein.

[0131] The discussion herein has largely focused on the processing of a single die on the RD wafer. This focus on a single die on the RD wafer is merely for illustrative purposes. It should be understood that all process steps discussed herein can be performed on an entire wafer. For example, each illustration presented in Figures 1A-1J and the other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, before dicing, one component in the illustrated components of the wafer may not be separated from an adjacent component.

[0132] Block 295 may include, for example, individual packages cut from the wafer (e.g., mechanical punching, mechanical sawing, laser cutting, soft beam cutting, plasma cutting, etc.). The final result of such cutting may be, for example, the package shown in FIG1J. For example, the cutting may form a side surface of the package that is a coplanar side surface comprising a plurality of components of the package. For example, any or all of the side surfaces of the molding material 130, the dielectric layer of the RD structure 110, various RDL dielectric layers, the underfill 128, etc., may be coplanar.

[0133] Generally, block 295 may include dicing the wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of dicing a wafer.

[0134] Figures 1 and 2 illustrate the characteristics of various exemplary methods and their variations. The characteristics of other exemplary methods will now be presented with reference to other figures.

[0135] As discussed herein, in the discussion of Figures 1 and 2, block 235 may include grinding (or thinning) the molding material 130 to expose one or more of the grains 125, 126. An example is provided in Figure 1D.

[0136] As discussed, molding and polishing (or thinning) of block 235 is not required, or can be performed to a extent that the tops of dies 125, 126 are still covered by molding material 130. An example is provided in Figure 3. As shown in Figure 3A, the molding material 130 covers the tops of semiconductor dies 125, 126. Note that the interconnect structures 121 may be shorter or taller than dies 125, 126. Continuing the comparison, instead of the resulting package 100J shown in Figure 1J, the resulting package 300B may appear as shown in Figure 3B.

[0137] Furthermore, as discussed herein, in the discussion of Figures 1 and 2, block 215 forming the TMV interconnect structure and block 240 of the TMV molding etch can be skipped. An example is provided in Figure 4. As shown in Figure 4A, the TMV interconnect structure 121 is not formed relative to block 215 and Figure 1B. As shown in Figure 4B, the molding material 130 does not cover the interconnect structure relative to block 230 and Figure 1C.

[0138] Continuing the comparison, as explained herein, molding and polishing (or thinning) of block 235 can be performed to the extent that one or more of the tips of grains 125, 126 are exposed from the molding material 130. Figure 4C is an illustration of an example of this process. Generally, component 400C of Figure 4C is similar to component 100J of Figure 1J, except for the interconnect structure 121 and the etched through-holes that expose these interconnect structures through the molding material 130.

[0139] Similarly, as explained herein, the molding polishing (or thinning) of block 235 can be skipped or performed to a extent that the tops of the dies 125, 126 are covered with molding material 130. Figure 4D illustrates an example of this process. Generally, the component 400D of Figure 4D is similar to the component 100J of Figure 1J, except for the interconnect structure 121 and the etched vias through the molding material 130 to expose these interconnect structures, wherein the molding material 130 covers the dies 125, 126.

[0140] In another example, as explained herein, in the discussion of block 215, these TMV interconnects may include any of a variety of structures, such as a conductive post (e.g., an electroplated post or column, a vertical wire, etc.). Figure 5A is an illustration of one example of a conductive post 521 attached to the RD structure 110. These conductive posts 521 may, for example, be electroplated on the RD structure 110. These conductive posts 521 may also include, for example, lines (e.g., wire-jointed lines) attached (e.g., wire-jointed attachments, soldering, etc.) to the RD structure 110 and extending vertically. These conductive posts 521 may extend from the RD structure 110 to a height greater than the height of the grains 125, 126, equal to the height of one or more of the grains 125, 126, less than the height of the grains 125, 126, etc. In one exemplary embodiment, the pillars may have a height greater than or equal to 200 micrometers and a center-to-center spacing of 100-150 micrometers. It is noted that any number of columns of pillars 521 can be formed. Generally, component 500A of FIG. 5A is similar to component 100B of FIG. 1B, wherein the conductive pillars 521 serve as interconnect structures rather than conductive spheres 121.

[0141] Continuing with this example, Figure 5B depicts the RD structure 110 covered by molding material 130, conductive pillars 521, semiconductor dies 125, 126, and primer filler 128. This molding can be performed, for example, according to block 230 of method 200 of this example. Generally, component 500B of Figure 5B is similar to component 100C of Figure 1C, wherein the conductive pillars 521 serve as interconnect structures instead of conductive balls 121.

[0142] Continuing with the example, Figure 5C depicts the molding material 130 having been thinned (e.g., ground) to a desired thickness. This thinning can be performed, for example, according to block 235 of method 200 of this example. Note, for example, that the conductive pillars 521 and / or semiconductor dies 125, 126 can also be thinned. Generally, component 500D of Figure 5D is similar to component 100D of Figure 1D, wherein the conductive pillars 521 are used as interconnect structures instead of conductive balls 121, and also do not have the etched through-holes 140 of Figure 1D. For example, the thinning of the molding material 130 can expose the tops of the conductive pillars 521. However, if the thinning of the molding material 130 does not expose the tops of the conductive pillars 521, a molding etch operation (e.g., according to block 240) can be performed. Note that although the component is shown as having exposed tops of semiconductor dies 125, 126, these tops are not necessarily exposed. For example, the pillars 521 may be higher than the semiconductor dies 125, 126. This exemplary configuration may, for example, allow the pillars 521 to be exposed and / or protrude from the molding material 130, while the molding material 130 continuously covers the back surface of the semiconductor dies 125, 126, which may, for example, provide protection to the semiconductor dies 125, 126, preventing or reducing warpage, etc.

[0143] In one embodiment where the pillars 521 are formed to have a height smaller than that of the grains 125, 126, the thinning may include first grinding the molding material 130, followed by grinding the back (or non-active) side of the molding material 130 and the grains 125, 126 until the pillars 521 are exposed. At this point, the thinning may be stopped or may continue, for example, by grinding the molding material 130, the grains 125, 126, and the pillars 521.

[0144] Continuing with this example, the component 500C shown in Figure 5C can be further processed by forming a redistribution layer (RDL) 532 on the molding material 130 and the dies 125, 126. Figure 5D illustrates an example of this process. This redistribution layer 532 may also be referred to herein as a backside redistribution (RDL) layer 532. Although the formation of this backside RDL is not explicitly shown in any block of method 200 of this example, this operation can be performed in any of these blocks, for example, after the molding and polishing operation of block 235 and before the wafer support attachment of block 245 (e.g., in block 235, in block 240, in block 245, or between these blocks).

[0145] As shown in Figure 5D, a first back dielectric layer 533 can be formed and patterned on the molding material 130 and the dies 125, 126. The first back dielectric layer 533 can be formed and patterned, for example, in the same or similar manner as the first RDL dielectric layer 171 formed in block 260, although the first RDL dielectric layer 171 is on a different surface. For example, the first back dielectric layer 533 can be formed on the molding material 130 and on the semiconductor dies 125, 126 (e.g., directly above the exposed back surfaces of the dies 125, 126, on the molding material 130 covering the back surfaces of the dies 125, 126, etc.), and vias 534 can be formed in the first back dielectric layer 533 (e.g., by etching, stripping, etc.) to at least expose the tops of the conductive pillars 521. It should be noted that in an exemplary configuration in which the molding material 130 covers the back surface of the semiconductor dies 125, 126, the first back dielectric layer 533 may still be formed, but it is not necessary to do so (for example, the back line 535 discussed below may be formed directly on the molding material 130 instead of on the first back dielectric layer 533).

[0146] Backside traces 535 may be formed on the first backside dielectric layer 533 and in vias 534 of the first backside dielectric layer 533. These backside traces 535 can therefore be electrically connected to the conductive posts 521. These backside traces 535 may be formed, for example, in a manner similar to or the same as the first RDL traces formed in block 265. At least some (if not all) of these backside traces 535 may extend horizontally from the conductive posts 521 to a position directly above the semiconductor dies 125, 126. At least some of these backside traces 535 may also extend from the conductive posts 521 to a position not directly above the semiconductor dies 125, 126.

[0147] A second back dielectric layer 536 may be formed and patterned on the first back dielectric layer 533 and the back traces 535. The second back dielectric layer 536 may be formed and patterned, for example, in the same or similar manner as the second RDL dielectric layer 183 formed in block 270, although the second RDL dielectric layer 183 is on a different surface. For example, the second back dielectric layer 536 may be formed on the first back dielectric layer 533 and on the back traces 535, and vias 537 may be formed in the second back dielectric layer 536 (e.g., by etching, stripping, etc.) to expose the contact areas of the back traces 535.

[0148] Backside interconnect pads 538 (e.g., ball contact pads) may be formed on the second backside dielectric layer 536 and / or in vias 537 of the second backside dielectric layer 536. These backside interconnect pads 538 can thus be electrically connected to the backside lines 535. These backside interconnect pads 538 may be formed, for example, in the same or similar manner as the second RDL lines formed in block 275. These backside interconnect pads 538 may be formed, for example, by forming metal contact pads and / or forming bump bottom metallization (e.g., to enhance subsequent attachment to the backside lines 535 via the interconnect structure).

[0149] Although the back RDL layer 532 is shown as having two back dielectric layers 533, 536 and one back line 535, it should be understood that any number of dielectric layers and / or line layers can be formed.

[0150] As shown, for example, in Figure 5E, after the back RDL layer 532 is formed, a wafer support structure 150 can be attached to the back RDL layer 532 (e.g., directly, using an intermediate adhesive layer, using vacuum force, etc.). The wafer support 150 can be attached, for example, in the same or similar manner as the wafer support 150 attached to block 245. For example, Figure 5E shows the wafer support 150 attached in a manner similar to that of Figure 1E, although it is attached to the RDL layer 532, rather than to the molding layer 130 and the semiconductor dies 125, 126.

[0151] As depicted, for example, in FIG5F, the support layer 105 (shown in FIG5E) can be removed from the RD wafer, a front redistribution layer can be formed on a side of the RD structure 110 opposite to the dies 125, 126, an interconnect structure 192 can be formed, and the wafer support 150 can be removed.

[0152] For example, the support layer 105 can be removed in the same or a similar manner as discussed in relevant blocks 250 and Figures 1E-1F. Similarly, for example, a front redistribution layer can be formed in the same or a similar manner as discussed in relevant blocks 255-280 and Figures 1G-1H. Furthermore, for example, the interconnect structure 192 can be formed in the same or a similar manner as discussed in relevant block 285 and Figure 1I. And, for example, the wafer support 150 can be removed in the same or a similar manner as discussed in relevant block 290 and Figure 1J.

[0153] In another exemplary embodiment, a substrate (e.g., a multilayer substrate, a package substrate, etc.) may be attached to semiconductor dies 125, 126, which may be an alternative to or additional to the backside RDL discussed in related FIG. 5. For example, as illustrated in FIG. 6A, interconnect structures 621 may be formed at a height that would extend to the height of dies 125, 126. It should be noted that this height is not necessarily present, for example in a case where the backside substrate has its own interconnect structure, or where additional interconnect structures are utilized in the context between the interconnect structures 621 and the backside substrate. The interconnect structures 621 may be attached, for example, in the same or similar manner as discussed in related block 215 and FIG. 1B.

[0154] Continuing with this example, as illustrated in Figure 6B, component 600B can be molded, and if necessary, the molded material can be thinned. Such molding and / or thinning can be performed, for example, in the same or similar manner as discussed in the relevant blocks 230 and 235 and Figures 1C and 1D.

[0155] As shown in Figure 6C, a wafer support 150 can be attached, a support layer 105 can be removed, and a front-side RDL can be formed. For example, a wafer support 150 can be attached in the same or similar manner as discussed in relevant block 245 and Figure 1E. Similarly, for example, the support layer 105 can be removed in the same or similar manner as discussed in relevant block 250 and Figure 1F. Similarly, for example, a front-side RDL can be formed in the same or similar manner as discussed in relevant blocks 255-280 and Figures 1G-1H.

[0156] As illustrated in FIG. 6D, interconnect structure 192 can be attached, wafer support 150 can be removed, and back substrate 632 can be attached. For example, interconnect structure 192 can be attached in the same or similar manner as discussed in related block 285 and FIG. 1I. Similarly, wafer support 150 can be removed in the same or similar manner as discussed in related block 290 and FIG. 1J. Again, for example, back substrate 632 can be electrically attached to interconnect structure 621 and / or mechanically attached to molding material 130 and / or dies 125, 126. Back substrate 632 can be attached, for example, in wafer (or panel) form and / or in a single package form, and can be attached, for example, before or after dicing (e.g., as discussed in block 295).

[0157] The methods and components shown in Figures 1-7 and discussed herein are merely non-limiting examples, presented to depict various characteristics of this disclosure. This method and component may also share any or all of the features with the methods and components shown and discussed in the following co-filed U.S. patent applications: U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Same"; U.S. Patent Application Serial No. 14 / 083,779, filed November 19, 2013, entitled "Semiconductor Device with Through-Silicon Through-hole - Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed March 18, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same"; and U.S. Patent Application Serial No. 14 / 313,720, filed June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same". 4; U.S. Patent Application Serial No. 14 / 444,450, filed July 28, 2014, entitled "Semiconductor Device Having a Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 524,443, filed October 27, 2014, entitled "Semiconductor Device Having Reduced Thickness"; U.S. Patent Application Serial No. 14 / 532,532, filed November 4, 2014, entitled "Intermediate, Method of Manufacturing the Thereof, Semiconductor Package Using the Thereof, and Method of Manufacturing the Semiconductor Package"; U.S. Patent Application Serial No. 14 / 546,484, filed November 18, 2014, entitled "Semiconductor Device Having Reduced Warpage"; and U.S. Patent Application Serial No. 14 / 671,095, filed March 27, 2015, entitled "Semiconductor Device and Method of Manufacturing the Thereof"; the contents of each of these U.S. patent applications are incorporated herein by reference in their entirety.

[0158] It should be noted that any or all of the semiconductor packages discussed herein may (but are not necessarily) be attached to a package substrate. Various non-limiting examples of such semiconductor device packages and methods of manufacturing them will now be discussed.

[0159] Figures 7A-7L are cross-sectional views illustrating an example semiconductor package and an example method of manufacturing a semiconductor package according to various features of the present disclosure. The structures shown in Figures 7A-7L may share any or all of the features with similar structures shown in Figures 1A-1J, 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9, 10A-10B, 11A-11D, 12A-12B, 13, and 14. Figure 8 is a flowchart of an example method 800 for manufacturing a semiconductor package according to various features of the present disclosure. This example method 800 may share any or all of the features with, for example, the example method 200 depicted in Figure 2 and discussed herein, and any other methods discussed herein. Figures 7A-7L may, for example, depict an example semiconductor package of various steps (or blocks) of the manufacturing method 800 in Figure 8. Figures 7A-7L and Figure 8 will now be discussed together.

[0160] The method 800 of this example may include, in block 805, the fabrication of a logic wafer for processing (e.g., for packaging). Block 805 may include fabricating a logic wafer for processing in any of a variety of ways, non-limiting examples of which are presented herein. Block 805 may, for example, share any or all of the features with block 205 of the method 200 of the example shown in FIG2 and discussed herein.

[0161] The method 800 of this example may include, in block 810, the fabrication of a redistribution structure wafer (RD wafer). Block 810 may include fabricating an RD wafer for processing using any of a variety of methods, non-limiting examples of which are provided herein. Block 810 may, for example, share any or all of the features with block 210 of the method 200 of the example shown in FIG2 and discussed herein.

[0162] Figure 7A is an illustration of an example providing various features of block 810. Referring to Figure 7A, the RD wafer 700A may, for example, include a support layer 705 (e.g., a silicon layer). A redistribution (RD) structure 710 may be formed on the support layer 705. The RD structure 710 may, for example, include a substrate dielectric layer 711, a first dielectric layer 713, a first conductive line 712, a second dielectric layer 716, a second conductive line 715, and an interconnect structure 717.

[0163] The substrate dielectric layer 711 may, for example, be on the support layer 705. The substrate dielectric layer 711 may, for example, include an oxide layer, a nitride layer, etc. The substrate dielectric layer 711 may, for example, be formed according to specifications, and / or may be natural.

[0164] The RD wafer 700A may, for example, include a first conductive line 712 and a first dielectric layer 713. The first conductive line 712 may, for example, include a deposited conductive metal (e.g., copper, etc.). The first dielectric layer 713 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the first dielectric layer 713 may include an organic dielectric material.

[0165] The RD wafer 700A may, for example, include a second conductive line 715 and a second dielectric layer 716. The second conductive line 715 may, for example, include a deposited conductive metal (e.g., copper, etc.). The second conductive line 715 may, for example, be connected to a separate first conductive line 712 through a separate conductive via 714 (e.g., in the first dielectric layer 713). The second dielectric layer 716 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative embodiment, the second dielectric layer 716 may include an organic dielectric material.

[0166] Although the two sets of dielectric layers and conductive lines are depicted in Figure 7A, it should be understood that the RD structure 710 of the RD wafer 700A may include any number of such layers and lines. For example, the RD structure 710 may include only one dielectric layer and / or one set of conductive lines, three sets of dielectric layers and / or conductive lines, etc.

[0167] Similar to the logic wafer fabrication in block 805, block 810 may include interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) formed on one surface of the RD structure 710. An example of such an interconnect structure 717 is shown in FIG. 7A, wherein the RD structure 710 includes an interconnect structure 717, which is shown to be formed on the front (or top) side of the RD structure 710 and electrically connected to individual second conductive lines 715 through conductive vias in the second dielectric layer 716. Such an interconnect structure 717 may be used, for example, to couple the RD structure 710 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

[0168] These interconnect structures 717 may include, for example, any of a variety of conductive materials (e.g., any one or a combination of copper, nickel, gold, etc.). These interconnect structures 717 may also include, for example, solder.

[0169] Generally, block 810 may include the fabrication of a redistributed structure wafer (RD wafer). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of performing such fabrication.

[0170] The method 800 of this example may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) in block 820. Block 820 may include attaching the dies to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 820 may, for example, share any or all of the features with block 220 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0171] Figure 7B is an illustration of an example of various features of block 820 (e.g., the die attachment). For example, a first die 725 (e.g., which may have been diced from a logic wafer prepared in block 805) is electrically and mechanically attached to the redistribution structure 710. Similarly, a second die 726 (e.g., which may have been diced from a logic wafer prepared in block 805) is electrically and mechanically attached to the redistribution structure 710.

[0172] The first die 725 and the second die 726 may include any of a variety of die features. In one example scenario, the first die 725 may include a processor die, and the second die 726 may include a memory die. In another example scenario, the first die 725 may include a processor die, and the second die 726 may include a coprocessor die. In yet another example scenario, the first die 725 may include a sensor die, and the second die 726 may include a sensor processing die. Although the component 700B in FIG. 7B is shown as having two dies 725, 726, it may have any number of dies. For example, it may have only one die, three dies, four dies, or more than four dies.

[0173] Furthermore, although the first grain 725 and the second grain 726 are shown attached laterally to the redistribution structure 710 relative to each other, they can also be arranged in a vertical assembly. Various non-limiting examples of such assemblies are shown and discussed herein (e.g., grain stacking on grains, grains attached to opposite substrate sides, etc.). Moreover, although the first grain 725 and the second grain 726 are shown to have generally similar dimensions, these grains 725, 726 may include different individual features (e.g., grain height, coverage area, interconnection spacing, etc.).

[0174] The first die 725 and the second die 726 are depicted as having a generally uniform spacing, but this is not necessarily the case. For example, most or all of the contacts of the first die 725 in a region of the first die coverage area adjacent to the second die 726 and / or most of the contacts of the second die 726 in a region of the second die coverage area adjacent to the first die 725 may have a substantially finer spacing than most or all of the other contacts. For example, the first 5, 10, or n columns of contacts of the first die 725 closest to the second die 726 (and / or the second die 726 closest to the first die 725) may have a spacing of 30 micrometers, while other contacts may have a spacing of approximately 80 micrometers and / or 200 micrometers. The RD structure 710 can therefore have corresponding contact structures and / or circuitry at these corresponding spacings.

[0175] Generally, Block 820 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Therefore, the scope of this disclosure should not be limited to the characteristics of any particular die, or to the characteristics of any particular layout of the polydies, or to the characteristics of any particular manner in which such dies are attached, etc.

[0176] The method 800 of this example may include, in block 825, an underfill filling of the semiconductor die and / or other components attached to the RD structure in block 820. Block 825 may include performing such underfill filling in any of a variety of ways, of which non-limiting examples are shown herein. Block 825 may, for example, share any or all of the features with block 225 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0177] Figure 7B is an illustration of an example of various features of block 825 (e.g., the underfill). The underfill 728 is disposed between the first semiconductor die 725 and the redistribution structure 710, and between the second semiconductor die 726 and the redistribution structure 710.

[0178] Although the underfill 728 is generally depicted as flat, it can be raised and form rounded corners on the sides of the semiconductor dies and / or other components. In one example, at least one-quarter or at least half of the die side surfaces may be covered by the underfill material. In another example, one or more or all of the entire side surfaces may be covered by the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. In one example embodiment, the underfill 728 may cover the entire redistribution structure 710 of the RD wafer. In this example embodiment, when the RD wafer is subsequently diced, such dicing may also cut through the underfill 728.

[0179] Generally, block 825 may include an underfill material attached to the semiconductor die and / or other components of the RD structure in block 820. Therefore, the scope of this disclosure should not be limited to any particular type of underfill material or any particular manner in which such underfill material is performed.

[0180] The method 800 of this example may include molding the RD wafer (or RD structure) in block 830. Block 830 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 830 may, for example, share any or all of the features with block 230 of the method 200 of the example shown in FIG2 and discussed herein.

[0181] Figure 7C is an illustration of an example of various features (e.g., molding features) of block 830. For example, the molding assembly 700C is shown in which the molding material 730 covers the first semiconductor die 725, the second semiconductor die 726, the underfill 728, and the top surface of the redistribution structure 710. Although the molding material 730 (which may also be referred to herein as encapsulating material) is shown to completely cover the sides and tops of the first semiconductor die 725 and the second semiconductor die 726, this is not necessary. For example, block 830 may include molding techniques using a film-assisted or die-sealing method to keep the tops of the dies free of molding material.

[0182] Generally, the molding material 730 can, for example, directly contact and cover the portions of the grains 725, 726 that are not covered by the primer filler 728. For example, in a scenario where at least a first portion of the sides of the grains 725, 726 is covered by the primer filler 728, the molding material 730 can directly contact and cover a second portion of the sides of the grains 725, 726. The molding material 730 can also, for example, fill the space between the grains 725, 726 (e.g., at least a portion of the space not yet filled by the primer filler 728).

[0183] Generally, block 830 may include molding the RD wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular molding material, structure, and / or technology.

[0184] The method 800 of this example may include grinding (or thinning) the molding material applied in block 830 in block 835. Block 835 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein. Block 835 may, for example, share any or all of the features with block 235 of the method 200 of the example shown in FIG2 and discussed herein.

[0185] Figure 7D is an illustration of an example of various features of block 835 (e.g., the molding and grinding features). The assembly 700D is depicted as the molding material 730 (e.g., relative to the molding material 730 depicted in Figure 7C) being thinned to expose the top surfaces of grains 725, 726. In this example, the grains 725, 726 may also have been ground (or thinned).

[0186] As explained herein, the molding material 730 can be retained in an overmolded assembly to cover the grains 725, 726. For example, the molding material 730 may be unpolished, or the molding material 730 may be polished, but not to a height that exposes the grains 725, 726.

[0187] Generally, block 835 may include grinding (or thinning) the molding material applied in block 830. Therefore, the scope of this disclosure should not be limited to any particular amount or type of grinding (or thinning).

[0188] The method 800 of this example may include, in block 845, attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Block 845 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 845 may, for example, share any or all of the features with block 245 of the method 200 of the example shown in FIG2 and discussed herein.

[0189] Figure 7E is an illustration of an example of various features of block 845 (e.g., features of wafer support attachment). The wafer support structure 750 is attached to the molding material 730 and the top sides of the dies 725, 726. The wafer support structure 750 may be attached, for example, using an adhesive. It is noted that in an assembly in which the tops of the dies 725, 726 are covered by the molding material 730, the wafer support structure 750 may only be directly coupled to the top of the molding material 730.

[0190] Generally, block 845 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer support structure or to the characteristics of any particular manner of attaching a wafer support structure.

[0191] The method 200 of this example may include removing a support layer from the RD wafer in block 850. Block 850 may include removing the support layer in any of a variety of ways, of which non-limiting examples are shown herein. Block 850 may, for example, share any or all of the features with block 250 of the method 200 of the example shown in FIG2 and discussed herein.

[0192] As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and / or supported. The support layer may, for example, include a semiconductor material (e.g., silicon). In an example scenario where the support layer comprises a silicon wafer layer, block 850 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all of the silicon from the RD wafer (e.g., at least 90% or 95%), etc.). For example, block 850 may include mechanically grinding almost all of the silicon, followed by a dry or wet chemical etching to remove the remainder (or almost all of the remainder). In an example scenario where the support layer is loosely attached to the RD structure formed (or supported) thereon, block 850 may include pulling or peeling to separate the support layer from the RD structure.

[0193] Figure 7F is an illustration of an example of various features of block 850 (e.g., support layer removal features). For example, the support layer 705 (shown in Figure 7E) is removed from the RD structure 710. In this illustrative example, the RD structure 710 may still include a substrate dielectric layer 711 as discussed herein (e.g., an oxide, nitride, etc.).

[0194] Generally, block 850 may include the removal of a support layer from the RD wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular method of wafer material removal.

[0195] The method 800 of this example may include forming and patterning a redistribution layer (RDL) dielectric layer in block 855 for etching an oxide layer of the RD structure. Block 855 may include forming and patterning the RDL dielectric layer in any of a variety of ways, non-limiting examples of which are shown herein. Block 855 may, for example, share any or all of the features with block 255 of method 200 of the example shown in FIG. 2 and discussed herein.

[0196] Figure 7G is an illustration of an example of the various features of block 855. For example, the RDL dielectric layer 771 is formed and patterned on the substrate dielectric layer 711. The patterned RDL dielectric layer 771 may include, for example, vias 772 through the RDL dielectric layer 771, through which the substrate dielectric layer 711 may be etched (e.g., in block 860), and conductive lines (or portions thereof) may be formed (e.g., in block 865) in the vias 772.

[0197] Generally, block 855 may include, for example, forming and patterning a dielectric layer (e.g., an RDL dielectric layer) on the substrate dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of a particular dielectric layer or to the characteristics of a particular manner in which a dielectric layer is formed.

[0198] The method 800 of this example may include etching the substrate dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as the unmasked portion thereof. Block 860 may include performing the etching in any of a variety of ways, of which non-limiting examples are shown herein. Block 860 may, for example, share any or all of the features with block 260 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0199] Figure 7G is an illustration of an example of various features of block 860. For example, the portion of the substrate dielectric layer 711 shown below the first conductive lines 712 in Figure 7F is removed from Figure 7G. This enables, for example, metal-to-metal contact between these first conductive lines 712 and the RDL lines formed in block 865.

[0200] Generally, block 860 may include, for example, etching of the substrate dielectric layer. Therefore, the scope of this disclosure should not be limited to any particular method of performing such etching.

[0201] Method 800 of this example may include forming a redistribution layer (RDL) circuit in block 865. Block 865 may include forming the RDL circuit in any of a variety of ways, non-limiting examples of which are presented herein. Block 865 may, for example, share any or all of the features with block 265 of method 200 of the example shown in Figure 2 and discussed herein.

[0202] Figures 7G and 7H illustrate an example of various features of block 865 (e.g., features of RDL line formation). For example, a first portion 781 of these RDL lines may be formed in a via 772 of the RDL dielectric layer 771 and contact the first conductive line 712 exposed by the via 772 of the RD structure 710. Similarly, for example, a second portion 782 of the first RDL line may be formed on the first RDL dielectric layer 771.

[0203] Generally speaking, block 865 may include redistribution layer (RDL) lines. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular RDL line or to the characteristics of any particular manner in which such an RDL line is formed.

[0204] It should be noted that although the method 800 of this example only shows an RDL dielectric layer at block 855 and only shows an RDL line at block 865, such blocks can be repeated as desired.

[0205] In this example, method 800 can form an interconnect structure on the RDL line in block 885. Block 885 may include any of the interconnect structures formed in various ways, non-limiting examples of which are presented herein. For example, block 885 may share any or all of the features with block 285 of method 200 in the example shown in Figure 2 and discussed herein.

[0206] Block 885 may, for example, form conductive pillars (e.g., metal pillars, copper pillars, solder-capped pillars, etc.) and / or conductive bumps (e.g., solder, etc.) on the RDL line. For example, block 885 may include electroplating conductive pillars, setting or coating conductive bumps, etc.

[0207] Figure 7I is an illustration of an example of various features of block 885 (e.g., features of bump formation). For example, interconnect structure 792 (e.g., which is shown as a solder-capped pillar, such as a copper pillar) is attached to these RDL lines 782.

[0208] Although the redistribution layers formed in blocks 855-885 (which may also be referred to as front redistribution layers (RDL)) are depicted in Figure 7 as generally fan-in components (e.g., generally contained within the coverage areas of dies 725, 726), they can also be formed as fan-out components, for example, where at least a portion of the interconnect structure 792 extends generally beyond the coverage areas of dies 725, 726. Non-limiting examples of such components are presented herein.

[0209] Generally, block 885 may include, for example, interconnect structures formed on the RDL lines and / or on the RDL dielectric layer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular interconnect structure or to any particular manner in which the interconnect structure is formed.

[0210] The method 800 of this example may include debonding (or separating) the wafer support attached to block 845 in block 890. Block 890 may include performing such debonding in any of a variety of ways, the non-limiting features of which are presented herein. For example, block 890 may share any or all of the features with block 290 of method 200 of the example shown in FIG2 and discussed herein.

[0211] Figures 7H and 7I illustrate an example of various features of block 890. For example, the wafer support 750 depicted in Figure 7H is removed in Figure 7I.

[0212] Generally, block 890 may include debonding the wafer support. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular type of wafer support, or to any particular method of debonding a wafer support.

[0213] The method 800 of this example may include dicing the wafer in block 895. Block 895 may include dicing the wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 895 may, for example, share any or all of the features with block 295 of the method 200 of the example shown in FIG2 and discussed herein.

[0214] The discussion herein has largely focused on the processing of a single die of the RD wafer. This focus on a single die of the RD wafer is merely for illustrative purposes. It should be understood that all process steps (or blocks) discussed herein can be performed on an entire wafer. For example, each illustration presented in Figures 7A-7L and the other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, prior to dicing, one component of the illustrated device assembly on the wafer may not be separated from an adjacent device assembly.

[0215] Block 895 may, for example, include individual packages cut from the wafer (e.g., mechanical punching, mechanical sawing, laser cutting, soft beam cutting, plasma cutting, etc.). The final result of such cutting may be, for example, the package shown in FIG. 7I. For example, the cutting may form a side surface of the package that is a coplanar side surface comprising a plurality of components of the package. For example, any or all of the side surfaces of the molding material 730, the dielectric layer of the RD structure 710, the RDL dielectric layer 771, the underfill 728, etc., may be coplanar.

[0216] Generally speaking, block 895 may include dicing the wafer. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular method of dicing a wafer.

[0217] The method 800 of this example, in block 896, may include fabricating a substrate, or a wafer or panel thereof, for attachment of the component 700I to it. Block 896 may include fabricating a substrate in any of a variety of ways, non-limiting examples of which are shown herein. Block 896 may, for example, share any or all of the features with blocks 205 and 210 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0218] The substrate may include features of any of various substrates. For example, the substrate may include a packaging substrate, a motherboard substrate, a multilayer substrate, a molded substrate, a semiconductor substrate, a glass substrate, etc. Block 896 may include, for example, preparing the front surface and / or back surface of the substrate for electrical and / or mechanical attachment. Block 896 may, for example, allow the substrate of a panel to remain in panel form and then cut individual packages later, or allow individual substrates to be cut from a panel at this stage.

[0219] Block 896 may also include receiving the substrate from a manufacturing station adjacent to or upstream of one of the manufacturing facilities, from another geographical location, etc. The received substrate may be, for example, already prepared, or additional preparation steps may be performed.

[0220] Figure 7J is an illustration of an example of the various features of block 896. For example, the component 700J includes a substrate 793 prepared for attachment.

[0221] Generally, block 896 may include the fabrication of a substrate, or a wafer or panel thereof, for attachment to the component 700I. Therefore, the scope of the various features of this disclosure should not be limited to the characteristics of a particular substrate or to any particular manner of fabricating a substrate.

[0222] The method 800 of this example may include attaching a component to the substrate in block 897. Block 897 may include attaching a component (e.g., a component 700I illustrated in FIG. 7I or other components) in any of a variety of ways, non-limiting examples of which are presented herein. Block 897 may, for example, share any or all of the features with block 220 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0223] The component may include any of the features of various components, non-limiting examples of which are presented herein, for example, in all the figures and / or in the related discussion. Block 897 may include attaching the component in any of various ways. For example, block 897 may include attaching the component to the substrate using batch reflow soldering, thermocompression bonding (TCB), conductive epoxy resin, etc.

[0224] Figure 7J is an illustration of an example of various features (e.g., component attachment features) of block 897. For example, component 700I shown in Figure 7I is attached to substrate 793.

[0225] Although not shown in FIG. 7J, in various exemplary embodiments (e.g., as shown in FIG. 7K and 7L), interconnect structures, such as through-mold interconnect structures, can be formed on the substrate 793. In this exemplary embodiment, block 897 may share any or all of the features with block 215 of method 200 shown in FIG. 2 and discussed herein, although with respect to the formation of these interconnect structures on the substrate 793. It is noted that such interconnect structures may be performed before or after the component is attached, or before or after the underfill of block 898.

[0226] Generally speaking, Block 897 includes attaching a component to the substrate. Therefore, the scope of this disclosure should not be limited to any particular component, substrate, or the characteristics of the manner in which a component is attached to a substrate.

[0227] The method 800 of this example may include, in block 898, an assembly with an adhesive filler on the substrate. Block 898 may include any of a variety of adhesive fillers, non-limiting examples of which are shown herein. Block 898 may, for example, share any or all of the features with block 825 and / or block 225 of the method 200 of the example shown in FIG. 2 and discussed herein.

[0228] For example, after the component is attached in block 897, block 898 may include underfilling the attached component with a capillary underfill. For example, the underfill may include a sufficiently viscous, reinforced polymeric material to flow between the component and the substrate in a capillary action.

[0229] Similarly, for example, block 897 may include filling the semiconductor die with a non-conductive paste (NCP) and / or a non-conductive film (NCF) or tape as the component is being attached (e.g., using a thermosetting bonding process). For example, such a primer filling material may be deposited (e.g., printed, sprayed, etc.) before the component is attached.

[0230] As with all the blocks depicted in method 800 of this example, block 898 can be executed at any point in the process of method 800, provided that the space between the component and the substrate is accessible.

[0231] The underfill can also occur at different sections of method 800 in this example. For example, the underfill can be performed on a portion of the substrate molding section 899 (e.g., using a molding underfill).

[0232] Figure 7K is an illustration of an example of various features of block 898 (e.g., the underfill feature). The underfill 794 is disposed between the component 700I and the substrate 793.

[0233] Although the underfill 794 is generally depicted as flat, it may be raised and form rounded corners on the sides of the component 700I and / or other components. In one example scenario, at least one-quarter or at least half of the side surface of the component 700I may be covered by the underfill material. In another example scenario, one or more or all of the entire side surface of the component 700I may be covered by the underfill material. Similarly, for example, a substantial portion of the space directly between the component 700I and other components, and / or between other components (shown in the various figures) may be filled with the underfill material 794. For example, at least half or all of the space between the component 700I and a laterally adjacent component may be filled with the underfill material.

[0234] As shown in Figure 7J, the component 700J may include a first underfill 728 between the dies 725, 726 and the RD structure 710, and a second underfill 794 between the RD structure 710 and the substrate 793. These underfills 728 and 794 may be different, for example. For instance, in an exemplary scenario where the distance between the dies 725, 726 and the RD structure 710 is less than the distance between the RD structure 710 and the substrate 793, the first underfill 728 may comprise a generally smaller filler size (or have a higher viscosity) compared to the second underfill 794. In other words, the second underfill 794 may be less expensive than the first underfill 728.

[0235] Furthermore, the individual primer filling processes performed in blocks 898 and 825 can be different. For example, block 825 may include a capillary primer filling process, while block 898 may include a non-conductive paste (NCP) primer filling process.

[0236] In another example, blocks 825 and 898 may be performed simultaneously in the same underfill process, for example, after block 897. Furthermore, as discussed herein, a molded underfill may also be used. In this example scenario, block 899 may include performing underfill of either or both of blocks 825 and / or 898 during the substrate molding process. For example, block 825 may include performing a capillary underfill, while block 898 is performed as a molded underfill process after block 899.

[0237] Generally, block 898 may include components and / or other elements that are attached to the substrate in block 897 with an adhesive filler. Therefore, the scope of this disclosure should not be limited to any particular type of adhesive filler or any particular method of performing the adhesive filler.

[0238] Method 800 of this example may include molding the substrate in block 899. Block 899 may include performing such molding in any of a variety of ways, non-limiting examples of which are shown herein. Block 899 may, for example, share any or all of the features with block 830 and / or block 230 of method 200 of the example shown in FIG2 and discussed herein.

[0239] For example, block 899 may include being molded on the top surface of the substrate, on the components attached to block 897, or on a TMV interconnect structure (if it is formed on the substrate, such as a conductive sphere, ellipsoid, pillar or column (e.g., electroplated pillar, line or bonding line, etc.)).

[0240] Block 899 may include, for example, transfer molding, compression molding, etc. Block 899 may include, for example, a panel molding process in which a plurality of substrates are connected in a panel and molded together, or block 899 may include individually molding the substrates. In a panel molding process, after the panel is molded, block 899 may include performing a separation process in which the individual substrates are separated from the substrate panel.

[0241] The molding material may include, for example, any of a variety of characteristics. For instance, the molding material (e.g., epoxy molding compound (EMC), epoxy resin molding compound, etc.) may include a relatively high modulus, for example, to provide encapsulation support in a subsequent process. Similarly, for example, the molding material may include a relatively low modulus to provide encapsulation flexibility in a subsequent process.

[0242] Block 899 may, for example, utilize a molding material that is different from the molding material used in block 830. For instance, block 899 may utilize a molding material having a lower modulus than the molding material used in block 830. In this configuration, the central region of the component may be relatively rigid compared to the peripheral regions of the component, thereby providing force absorption in the stronger regions of the component.

[0243] In an exemplary scenario where the molding material 735 of component 700K and the molding material 730 of component 700I are different and / or formed at different stages and / or formed using different types of processes, block 899 (or another block) may include preparing the molding material 730 for adhesion to the molding material 735. For example, the molding material 730 may be physically or chemically etched. The molding material 730 may, for example, be plasma etched. Similarly, for example, trenches, notches, protrusions, or other physical features may be formed on the molding material 730. As another example, an adhesive may be applied to the molding material 730.

[0244] Block 899 may, for example, utilize a molding process of a different type than that used in block 830. In one example scenario, block 830 may utilize a compression molding process, while block 899 utilizes a transfer molding process. In this example scenario, block 830 may utilize a molding material specifically adapted to compression molding, and block 899 may utilize a molding material specifically adapted to transfer molding. Such molding materials may, for example, have significantly different material characteristics (e.g., flow characteristics, curing characteristics, hardness characteristics, particle size characteristics, chemical compound characteristics, etc.).

[0245] As explained herein, for example, regarding block 898, the molding process of block 899 can provide underfill between the component 700I and the substrate 793, and / or can provide underfill between the dies 725, 726 and the RD structure 710. In this example, there can be material uniformity between the molding underfill material and the molding materials of the encapsulating substrate 793 and component 700I and / or the molding materials of the encapsulating RD structure 710 and semiconductor dies 725, 726.

[0246] Figure 7K is an illustration of an example of various features (e.g., molding features) of block 899. For example, the molding assembly 700K is shown in which the molding material 735 covers the interconnect structure 795 and the assembly 700I. Although the molding material 735 (which may also be referred to herein as encapsulating material) is shown to expose the top of the assembly 700I, this is not necessary. For example, block 899 may completely cover the assembly 700I, and a subsequent thinning (or polishing) operation is not required to expose the top of the assembly 700I.

[0247] Generally, the molding material 735 can, for example, directly contact and cover the portion of component 700I not covered by the primer filler 794. For example, in a configuration where at least a first portion of the side of component 700I is covered by the primer filler 794, the molding material 735 can directly contact and cover a second portion of the side of component 700I. Furthermore, the molding material 735 can extend laterally to the edge of the substrate 793, thus forming a side surface coplanar with the substrate 793. Such a component can, for example, be formed using panel molding, followed by individual encapsulation from the panel.

[0248] Generally, block 899 may include molding the substrate. Therefore, the scope of this disclosure should not be limited to the characteristics of any particular molding material, structure, and / or technology.

[0249] The method 800 of this example may include forming interconnect structures on the substrate in block 886, for example, on the side of the substrate opposite to the component attached in block 897. These interconnect structures may include features of any of various types of interconnect structures, such as structures that can be used to connect a semiconductor package to another package or a motherboard. For example, these interconnect structures may include conductive balls (e.g., solder balls) or bumps, conductive pillars, etc.

[0250] Figure 7K is an illustration of an example of various features of block 886 (e.g., the features that form interconnects). For example, these interconnect structures 792 are depicted as planes 791 attached to the substrate 793.

[0251] Generally, block 886 may include interconnect structures formed on the substrate. Therefore, the scope of this disclosure should not be limited to the characteristics of a particular interconnect structure or to any particular manner in which such a structure is formed.

[0252] As discussed herein, the underfill 728 may cover at least a portion of the sides of the dies 725, 726, and / or the underfill 794 may cover at least a portion of the sides of the component 700I. Figure 7L provides an example illustrating one such coverage. For example, the component 700I is shown in which the underfill 728 is a portion of the sides contacting the dies 725, 726. As discussed herein, the underfill 728 may also be cut during a dicing process, resulting in a component 700I including a flat side surface comprising one side surface of the RD structure 710, one side surface of the molding material 730, and one side surface of the underfill 728.

[0253] The component 700L (which may also be referred to as a package) is shown with the underfill 794 contacting a portion of the side of the component 700I (e.g., the side of the RD structure 710, the side of the underfill 728, and the side of the molding material 730). It should be noted that, as discussed herein, in various exemplary embodiments, the underfill 794 may include a molded underfill of the same material as the molding material 735. The molding material 735 is shown as encapsulating the substrate 793, interconnect structure 795, underfill 794, and component 700I. Although the tops of component 700I and interconnect structure 795 are exposed from the molding material 735 in this exemplary illustration, this is not necessarily the case.

[0254] Figures 7 and 8 illustrate the methodological characteristics of various examples and their variations. The methodological characteristics of other examples will now be presented with reference to additional figures.

[0255] As discussed herein, in the discussion of Figures 7 and 8, block 835 may include grinding (or thinning) the molding material 730 to expose one or more of the grains 725, 726. An example is provided in Figure 7D.

[0256] As discussed, molding and polishing (or thinning) of block 835 does not need to be performed, or can be performed to a extent that the tops of the dies 725, 726 are still covered by the molding material 730. An example is provided in Figure 9, wherein the molding material 735 covers the tops of the dies 725, 726 of the component 700I.

[0257] As discussed herein, such as in relation to block 897 and Figures 7K and 7L, interconnect structures may be formed on the substrate in various exemplary embodiments. One example is provided in Figure 9. For instance, although the tops of the die interconnect structures 795 are initially covered by the molding material 735, through-holes 940 are etched into the molding material 735 to expose the interconnect structures 795.

[0258] Furthermore, as discussed in Figures 7 and 8 herein, in various exemplary embodiments, the TMV interconnect structure does not need to be formed on the substrate. One example is provided in Figure 10A. As shown in Figure 10A, unlike Figure 7K, no TMV interconnect structure 795 is formed there. Also, as shown in Figure 10A, unlike Figure 1K, the molding material 735 does not cover the interconnect structure.

[0259] Similarly, as explained herein, the molding and polishing (or thinning) of block 899 can be skipped, or can be performed to the extent that the top of at least one of component 700I and / or dies 725, 726 is covered with molding material 735. Figure 10A is an illustration of an example of this process. Generally, component 1000A of Figure 10A is similar to component 700K of Figure 7K minus interconnect structure 795, and wherein molding material 735 covers component 700I.

[0260] Furthermore, as explained herein, molding and polishing (or thinning) of block 899 can be performed to the extent that the tops of one or more of the components 700I and / or the grains 725, 726 are exposed from the molding material 735 (and / or molding material 730). Figure 10B is an illustration of an example of this process. Generally, the component 1000B of Figure 10B is similar to the component 700K of Figure 7K, minus the interconnect structure 795.

[0261] In another example, as explained herein, in the discussion of block 897, these TMV interconnects may include any of a variety of structures, such as a conductive post (e.g., an electroplated post or column, a vertical wire, etc.). Figure 11A is an illustration of one example of a conductive post 1121 attached to the substrate 793. These conductive posts 1121 may, for example, be electroplated on the substrate 793. These conductive posts 1121 may also include, for example, wire-attached (e.g., wire-bonded attachment, soldering, etc.) wires (e.g., wire-bonded wires) attached to the substrate 793 and extending vertically. These conductive posts 1121 may extend from the substrate 793 to a height greater than that of the grains 725, 726, equal to the height of one or more of the grains 725, 726, less than the height of the grains 725, 726, etc. It is noted that any number of posts 1121 may be formed. Generally speaking, component 1100A of Figure 11A is similar to component 700K of Figure 7K (minus the molding compound 735), which has conductive pillars 1121 as interconnection structures instead of elongated conductive balls 795.

[0262] Continuing with this example, Figure 11B depicts a substrate 793 covered with molding material 735, conductive pillars 1121, component 700I (e.g., semiconductor dies 725, 726), and primer filler 794. This molding can be performed, for example, according to block 899 of the method 800 of this example. Generally, component 1100B of Figure 11B is similar to component 700K of Figure 7K, having conductive pillars 1121 as interconnect structures instead of elongated conductive spheres 795, and having molding material 735 that has not been thinned or has not been thinned sufficiently to expose component 700I.

[0263] Continuing with the example, Figure 11C depicts the molding material 735 having been thinned (e.g., ground) to a desired thickness. This thinning can be performed, for example, according to block 899 of method 800 of this example. Note, for example, that the conductive pillars 1121 and / or components 700I (e.g., comprising molding material 730 and / or semiconductor dies 725, 726) can also be thinned. For example, thinning of the molding material 735 can expose the tips of the conductive pillars 1121. However, if thinning of the molding material 735 does not expose the tips of the conductive pillars 1121, a molding etch operation can be performed. Note that although component 1100C is shown as having exposed tips of the semiconductor dies 725, 726 of component 700I, these tips are not necessarily exposed.

[0264] Generally speaking, the component 1100C of Figure 11C is similar to the component 700K of Figure 7K, which has conductive pillars 1121 as interconnection structures instead of elongated conductive balls 795.

[0265] Continuing with this example, component 1100C shown in FIG. 11C can be further processed by forming a redistribution layer (RDL) 1132 on the molding material 735 and component 700I (e.g., comprising the molding material 730 and / or its semiconductor dies 725, 726). FIG. 11D illustrates an example of this processing. This redistribution layer 1132 may also be referred to herein as a backside redistribution (RDL) layer 1132. Although the formation of this backside RDL is not explicitly shown in one of the blocks of method 800 in this example, this operation can be performed in any of those blocks, for example, after the molding and polishing operation of block 899 (if performed).

[0266] As shown in FIG11D, a first back dielectric layer 1133 may be formed and patterned on the molding material 735 and the component 700I (e.g., comprising the molding material 730 and / or its semiconductor dies 725, 726). The first back dielectric layer 1133 may be formed and patterned, for example, in the same or similar manner as the RDL dielectric layer 771 formed in block 855, although on a different surface. For example, the first back dielectric layer 1133 may be formed on the molding material 735 and / or on the component 700I (e.g., including the molding material 730 and / or its semiconductor dies 725, 726), for example, directly formed on the exposed back surface of the dies 725, 726, on the molding material 730 and / or 735 covering the back surface of the dies 725, 726, etc., and the through-hole 1134 may be formed in the first back dielectric layer 1133 (e.g., by etching, stripping, etc.) to at least expose the top of the conductive post 1121.

[0267] Backside traces 1135 may be formed on the first backside dielectric layer 1133 and in vias 1134 of the first backside dielectric layer 1133. These backside traces 1135 can therefore be electrically connected to the conductive posts 1121. These backside traces 1135 may be formed, for example, in a manner similar to or the same as the RDL traces 782 formed in block 865. At least some (if not all) of these backside traces 1135 may extend from the conductive posts 1121 to a position directly above the component 700I (e.g., containing the molding material 730 and / or its semiconductor dies 725, 726). At least some of these backside traces 1135 may also extend from the conductive posts 1121 to a position not directly above the component 700I (e.g., containing the molding material 730 and / or its semiconductor dies 725, 726).

[0268] A second back dielectric layer 1136 can be formed and patterned on the first back dielectric layer 1133 and the back traces 1135. The second back dielectric layer 1136 can be formed and patterned, for example, in the same or similar manner as the RDL dielectric layer 771 formed in block 855, although on a different surface. For example, the second back dielectric layer 1136 can be formed on the first back dielectric layer 1133 and on the back traces 1135, and vias 1137 can be formed in the second back dielectric layer 1136 (e.g., by etching, stripping, etc.) to expose the contact areas of the back traces 1135.

[0269] Backside interconnect pads 1138 (e.g., ball contacts, planes, terminals, etc.) may be formed on the second backside dielectric layer 1136 and / or in vias 1137 of the second backside dielectric layer 1136. These backside interconnect pads 1138 can thus be electrically connected to the backside wiring 1135. These backside interconnect pads 1138 may be formed, for example, in the same or similar manner as the RDL wiring formed in block 865. These backside interconnect pads 1138 may be formed, for example, by forming metal contact pads and / or forming bump bottom metallization (e.g., to reinforce subsequent attachment to the backside wiring 1135 via other interconnect structures).

[0270] Although the back RDL layer 1132 is shown as having two back dielectric layers 1133, 1136 and one back wiring layer 1135, it should be understood that any number of dielectric and / or wiring layers can be formed.

[0271] Although not shown in FIG11D, interconnect structures may be formed on the substrate 793, for example on a side of the substrate 793 opposite to the component 700I and the molding material 735, as discussed herein, for example, in relation to block 886 and FIG7K.

[0272] In another exemplary embodiment, a substrate (e.g., a multilayer substrate, a package substrate, etc.) may be attached to the component 700I (e.g., including the semiconductor dies 725, 726 and the molding material 730) and the molding material 735, for example as an alternative to or additional to the backside RDL discussed in the related Figures 11A-11D.

[0273] For example, as illustrated in Figure 12A, these interconnect structures 795 may be formed at a height that will extend at least to the height of the component 700I. It should be noted that this height is not necessarily present, for example, in a scenario where the back substrate has its own interconnect structure, or where additional interconnect structures are utilized between the interconnect structures 795 and the back substrate. These interconnect structures 795 may, for example, be attached in the same or similar manner as discussed in the relevant block 897 and Figure 7K.

[0274] Continuing with this example, as illustrated in Figure 12A, the component 1200A can be molded using a molding material 735, and if necessary, the molding material 735 can be thinned. Such molding and / or thinning can be performed, for example, in the same or similar manner as discussed in the relevant block 899 and Figure 7K.

[0275] As shown in Figure 12B, a back substrate 1232 can be attached. For example, the back substrate 1232 can be electrically connected to the interconnect structure 795 and / or mechanically attached to the molding material 735 and / or component 700I (e.g., molding material 730 and / or semiconductor dies 725, 726). The back substrate 1232 can be attached, for example, in a panel form and / or a single package form, and can be attached, for example, before or after monolithization.

[0276] As discussed herein, after the component 700I is attached to the substrate 793, the substrate 793 and / or component 700I may be covered with a molding material. Alternatively or additionally, the substrate 793 and / or component 700I may be covered with a cap or a stiffener. Figure 13 provides an illustrative example. Figure 13 generally shows the component 700J of Figure 7J with an added cap 1310 (or stiffener).

[0277] The cover 1310 may include, for example, metal and provide electromagnetic shielding and / or heat dissipation. For example, the cover 1310 may be electrically coupled to a ground line on the substrate 793 to provide shielding. The cover 1310 may be coupled to the substrate 793, for example, using solder and / or conductive epoxy. Although not shown, a thermal interface material may be formed in a gap 1315 between the component 700I and the cover 1310.

[0278] Although most of the examples shown and discussed herein generally only demonstrate the attachment of component 700I to substrate 793, other components (e.g., active and / or passive components) may also be attached to substrate 793. For example, as shown in FIG. 14, a semiconductor die 1427 may be attached (e.g., flip-chip bonding, wire bonding, etc.) to substrate 793. The semiconductor die 1427 is attached to substrate 793 in a manner laterally adjacent to component 700I. Following this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) may then be formed.

[0279] In another exemplary embodiment, other components may be coupled to the top side of component 700I in a vertically stacked assembly. Figure 15 illustrates an example of such component 1500C. A third die 1527 and a fourth die 1528 (e.g., their non-active sides) may be attached to the top of component 700I. This attachment may be performed, for example, using an adhesive. Bonding pads on the active sides of the third die 1527 and the fourth die 1528 may then be wire-bonded to the substrate 793. Note that in a scenario where an RDL and / or substrate is attached to component 700I, the third die 1527 and / or the fourth die 1528 may be flip-chip bonded to such RDL and / or substrate. Following this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) may then be formed.

[0280] In yet another exemplary embodiment, another component may be coupled to the bottom side of the substrate. Figure 16 illustrates an example of such a component. A third die 1699 is attached to the bottom side of the substrate 793, for example, in a gap between interconnect structures on the bottom side of the substrate 793. Following this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) may then be formed.

[0281] The methods and components shown in Figures 8-16 and discussed herein are merely non-limiting examples, presented to depict various characteristics of this disclosure. This method and component may also share any or all of the features with the methods and components shown and discussed in the following co-filed U.S. patent applications: U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Same"; U.S. Patent Application Serial No. 14 / 083,779, filed November 19, 2013, entitled "Semiconductor Device with Through-Silicon Through-hole - Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed March 18, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same"; and U.S. Patent Application Serial No. 14 / 313,720, filed June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same". 4; U.S. Patent Application Serial No. 14 / 444,450, filed July 28, 2014, entitled "Semiconductor Device Having a Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 524,443, filed October 27, 2014, entitled "Semiconductor Device Having Reduced Thickness"; U.S. Patent Application Serial No. 14 / 532,532, filed November 4, 2014, entitled "Intermediate, Method of Manufacturing the Thereof, Semiconductor Package Using the Thereof, and Method of Manufacturing the Semiconductor Package"; U.S. Patent Application Serial No. 14 / 546,484, filed November 18, 2014, entitled "Semiconductor Device Having Reduced Warpage"; and U.S. Patent Application Serial No. 14 / 671,095, filed March 27, 2015, entitled "Semiconductor Device and Method of Manufacturing the Thereof"; the contents of each of these U.S. patent applications are incorporated herein by reference in their entirety.

[0282] The discussion herein includes numerous illustrative figures illustrating various parts of a semiconductor package assembly. For clarity of illustration, these figures do not show all features of each exemplary assembly. Any of the exemplary components presented herein may share any or all of the features with any or all of the other components presented herein. For example, and without limitation, any or part of the components related to the examples shown and discussed in Figures 1-7 may be incorporated into any of the components related to the examples discussed in Figures 8-16. Conversely, any of the components related to the components shown and discussed in Figures 8-16 may be incorporated into the components related to the components shown and discussed in Figures 1-7.

[0283] In summary, the various features of this disclosure provide a semiconductor device or package structure and a method for manufacturing it. Although the foregoing description has been illustrated with reference to certain features and examples, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt a particular situation or material to the teachings of this disclosure without departing from its scope. Therefore, it is intended that this disclosure is not limited to the specific examples disclosed, but rather that it encompasses all examples falling within the scope of the appended claims.

[0284] 100A: Redistributed Structure (RD) Wafer 100B: Component 100C: Molded Components 100D: Components 100J: Package 105: Support layer 110: Redistribution (RD) Structure 111: Substrate dielectric layer 112: First conductive line 113: First dielectric layer 114: Conductive through-hole 115: Second conductive line 116: Second dielectric layer 117: Interconnection Structure 119:Contact 121: Interconnection Structure 125: First grain 126: Second grain 128: Base glue filler 130: Molding material 140: Through hole 150: Wafer support structure 171: First RDL dielectric layer 172: Through-hole 181: The first part of the first RDL line 182: The second part of the first RDL line 183: Second RDL dielectric layer 184: Through-hole 185: Third RDL layer 191: Second RDL Line 192: Interconnection Structure 200: Method Blocks 205, 210, 215, 220, 225, 230, 235, 240, 245, 250, 255, 260, 265, 270, 275, 280, 285, 290, 295: 300B: Package 400C: Component 400D: Components 500A: Component 500B: Component 500C: Components 500D: Components 521: Conductive post 532: Redistribution Layer (RDL) 533: First back dielectric layer 534: Through-hole 535: Back panel wiring 536: Second back dielectric layer 537: Through-hole 538: Backside interconnect pad 600B: Component 621: Interconnection Structure 632: Back substrate 700A:RD Wafer 700B: Component 700C: Molded Components 700D: Components 700I: Component 700J: Component 700K: Components 700L: Components 705: Support layer 710: Redistribution (RD) Structure 711: Substrate dielectric layer 712: First conductive circuit 713: First dielectric layer 714: Conductive Through-Hole 715: Second conductive line 716: Second dielectric layer 717: Interconnection Structure 725: First semiconductor die 726: Second semiconductor die 728: Base Rubber Filler 730: Molding material 735: Molding Material 750: Wafer support structure 771:RDL dielectric layer 772: Through-hole 781: The first part of the first RDL line 782: The second part of the first RDL line 791: Plane 792: Interconnection Structure 793:Substrate 794: Base filler 795: Interconnection Structure 800: Method Blocks 805, 810, 820, 825, 830, 835, 845, 850, 855, 860, 865, 885, 886, 890, 895, 896, 897, 898, 899: 940: Through-hole 1000A: Component 1000B: Component 1100A: Component 1100B: Component 1100C: Component 1121: Conductive post 1132: Redistribution Layer (RDL) 1133: First back dielectric layer 1134: Through-hole 1135: Back panel wiring 1136: Second back dielectric layer 1137: Through-hole 1138: Backside interconnect pad 1200A: Component 1232: Back substrate 1310: Lid 1315: Gap 1427: Semiconductor die 1500C: Components 1527: Third grain 1528: Fourth grain 1699: Third grain

Claims

1. A semiconductor device comprising: An upper redistribution structure includes one or more upper redistribution structure dielectric layers, one or more upper redistribution structure conductive layers, an upper redistribution structure top side, an upper redistribution structure bottom side, and an upper redistribution structure lateral side located between the upper redistribution structure top side and the upper redistribution structure bottom side; a semiconductor die includes a semiconductor die top side and a semiconductor die bottom side; a die interconnect structure that electrically couples the semiconductor die to the one or more upper redistribution structure conductive layers along the semiconductor die bottom side and via the upper redistribution structure top side, and creates a gap between the semiconductor die bottom side and the upper redistribution structure top side; and an upper underfill filler in the gap between the semiconductor die bottom side and the upper redistribution structure top side, wherein the upper underfill filler contacts and encapsulates one or more of the die interconnect structures; The lower redistribution structure includes one or more lower redistribution structure dielectric layers, one or more lower redistribution structure conductive layers, a lower redistribution structure top side, a lower redistribution structure bottom side, and a lower redistribution structure lateral side located between the lower redistribution structure top side and the lower redistribution structure bottom side; and interconnection structures between the upper redistribution structure bottom side and the lower redistribution structure top side, wherein each interconnection structure includes an interconnection structure top side coupled to the one or more upper redistribution structure conductive layers, and wherein each interconnection structure includes an interconnection structure bottom side coupled to the one or more lower redistribution structure conductive layers.

2. The semiconductor device as claimed in claim 1, comprising: The first encapsulating material is located above the top side of the upper redistribution structure; And wherein the first encapsulating material laterally surrounds the semiconductor grain.

3. The semiconductor device as claimed in claim 2, wherein: The first encapsulation material includes a first encapsulation material top side; and the first encapsulation material top side exposes the top side of the semiconductor die.

4. The semiconductor device as claimed in claim 2, comprising: The second sealing material above the top side of the lower redistribution structure; And wherein the second encapsulating material is laterally distributed around the first encapsulating material and the upper redistribution structure.

5. The semiconductor device as claimed in claim 1, comprising a reinforcing member located above the top side of the semiconductor die.

6. The semiconductor device of claim 1, comprising a reinforcing member, wherein the bottom side of the reinforcing member is coupled to the top side of the lower redistribution structure.

7. The semiconductor device as claimed in claim 6, wherein the reinforcing member laterally surrounds the interconnect structure.

8. The semiconductor device as claimed in claim 6, wherein the reinforcing member covers the top side of the semiconductor die.

9. The semiconductor device of claim 8, wherein the reinforcing member is coupled to the top side of the semiconductor die.

10. The semiconductor device of claim 1, comprising a lower underfill located between the bottom side of the upper redistribution structure and the top side of the lower redistribution structure.

11. The semiconductor device of claim 4, wherein the top side of the first encapsulating material and the top side of the second encapsulating material are coplanar.

12. The semiconductor device of claim 4, wherein the top side of the semiconductor die and the top side of the second encapsulating material are coplanar.

13. A semiconductor device comprising: Lower redistribution structure; Upper redistribution structure; Semiconductor grains; A die interconnect structure coupling the bottom side of the semiconductor die to the top side of the upper redistribution structure; an upper underfill between the bottom side of the semiconductor die and the top side of the upper redistribution structure; an interconnect structure coupling the bottom side of the upper redistribution structure to the top side of the lower redistribution structure; an external encapsulation material above the lower redistribution structure, wherein the external encapsulation material laterally surrounds the upper redistribution structure, the upper underfill, and the interconnect structure; and a reinforcing member coupled to the top side of the lower redistribution structure, wherein the reinforcing member laterally surrounds the interconnect structure.

14. The semiconductor device as claimed in claim 13, comprising: An internal encapsulating material is located above the upper redistribution structure; And wherein the internal encapsulating material laterally surrounds the semiconductor grain.

15. The semiconductor device of claim 14, wherein the outer encapsulating material laterally surrounds the inner encapsulating material.

16. The semiconductor device of claim 13, wherein the reinforcing member covers the top side of the semiconductor die.

17. The semiconductor device of claim 16, wherein the reinforcing member is coupled to the top side of the semiconductor die.

18. The semiconductor device of claim 13, comprising a lower underfill located between the bottom side of the upper redistribution structure and the top side of the lower redistribution structure.

19. A method of providing a semiconductor device, the method comprising: A top redistribution structure is provided, the top redistribution structure including one or more top redistribution structure dielectric layers, one or more top redistribution structure conductive layers, a top redistribution structure top side, a bottom redistribution structure bottom side, and a lateral side of the top redistribution structure located between the top side and the bottom side of the top redistribution structure; a semiconductor die is provided, the semiconductor die including a semiconductor die top side and a semiconductor die bottom side; A die interconnect structure is provided that electrically couples the semiconductor die to one or more upper redistribution structure conductive layers along the bottom side of the semiconductor die and via the top side of the upper redistribution structure, creating a gap between the bottom side of the semiconductor die and the top side of the upper redistribution structure; an upper underfill is provided in the gap between the bottom side of the semiconductor die and the top side of the upper redistribution structure, wherein the upper underfill contacts and encapsulates one or more of the die interconnect structures; A lower redistribution structure is provided, the lower redistribution structure including one or more lower redistribution structure dielectric layers, one or more lower redistribution structure conductive layers, a lower redistribution structure top side, a lower redistribution structure bottom side, and a lower redistribution structure lateral side located between the lower redistribution structure top side and the lower redistribution structure bottom side; and an interconnection structure is provided between the upper redistribution structure bottom side and the lower redistribution structure top side, wherein each interconnection structure includes an interconnection structure top side coupled to the one or more upper redistribution structure conductive layers, and wherein each interconnection structure includes an interconnection structure bottom side coupled to the one or more lower redistribution structure conductive layers.

20. The method of claim 19, comprising providing a reinforcing member coupled to the top side of the lower redistribution structure.

21. A semiconductor device comprising: A first redistribution structure includes an accumulation redistribution structure comprising a top side, a bottom side, a lateral side between the top side and the bottom side, a first dielectric layer, and a first conductive layer; a semiconductor die comprising a top side and a bottom side, wherein the bottom side of the semiconductor die faces the top side of the accumulation redistribution structure and is coupled to the top side of the accumulation redistribution structure, and wherein the bottom side of the semiconductor die includes a conductive pad electrically coupled to the first conductive layer of the accumulation redistribution structure; an interconnect structure comprising a top side and a bottom side, wherein the bottom side of the interconnect structure is coupled to the top side of the accumulation redistribution structure and electrically coupled to the first conductive layer of the accumulation redistribution structure, and wherein the top side of the interconnect structure extends vertically at least as high as the top side of the semiconductor die; an encapsulation material located on the top side of the accumulation redistribution structure, wherein the encapsulation material laterally surrounds the semiconductor die, and wherein the encapsulation material includes a top side, a bottom side facing the accumulation redistribution structure, and a lateral side between the top side and the bottom side of the encapsulation material; And a second redistribution structure comprising a multilayer substrate including a top side, a bottom side, a first dielectric layer and a first conductive layer, wherein the bottom side of the second redistribution structure is coupled to the top side of the interconnect structure, wherein the bottom side of the first dielectric layer is located above the top side of the semiconductor die and contacts the top side of the encapsulation material, and wherein the bottom side of the first conductive layer is electrically coupled to the top side of the interconnect structure.

22. The semiconductor device of claim 21, wherein the interconnect structure includes a copper core solder structure.

23. The semiconductor device of claim 21, wherein the interconnect structure comprises elongated conductive balls.

24. The semiconductor device as claimed in claim 21, wherein: The interconnect structure includes a core of first metal surrounded by a second metal; And the encapsulating material surrounds the core laterally.

25. The semiconductor device of claim 21, wherein the top side of the semiconductor die is exposed from the top side of the encapsulating material.

26. The semiconductor device of claim 21, wherein the bottom side of the multilayer substrate is mechanically attached to the top side of the semiconductor die.

27. The semiconductor device of claim 21, wherein the bottom side of the multilayer substrate is mechanically attached to the top side of the encapsulating material.

28. The semiconductor device as claimed in claim 21, wherein: The laminated substrate of the second redistribution structure includes a lateral side between the top side and the bottom side of the laminated substrate; The lateral side of the laminated substrate, the lateral side of the encapsulating material, and the lateral side of the accumulation redistribution structure are coplanar.

29. The semiconductor device of claim 21, wherein the semiconductor die includes a lateral side located between the top side and the bottom side of the semiconductor die.

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