Data receiving device and method

Abstract

A data receiving device is used to receive data signals. The data receiving device includes an amplifier, a comparator, a flip-flop, a control unit, a multiplexer, and a clock data recovery circuit. The amplifier amplifies the data signal. The comparator compares the data signal with a reference voltage signal to generate a comparison result signal. The flip-flop generates a trigger result signal based on the comparison result signal and in response to a clock signal. The control unit generates a multiplexing control signal based on the trigger result signal. The multiplexer selects the amplified data signal as the output signal based on the multiplexing control signal. The clock data recovery circuit latches the output signal after receiving it.

Description

Technical Field

[0001] This case relates to data receiving technology, and in particular to a data receiving device and method. Prior Technology

[0002] In existing technologies, clock and data recovery (CDR) circuits are widely used in various high-speed data communication standards, such as MPHY, PCIe, USB, and SerDes. Their basic principle is to utilize the clock component embedded in the data signal to directly recover the clock required by the receiver from the data, thereby correcting the timing phase and compensating for jitter generated during transmission, ensuring correct data sampling.

[0003] In the MPHY protocol, the high-speed reception process can generally be divided into three stages: Prepare, Sync, and High-Speed ​​Data Reception (HS-Data). During the Prepare stage, the transmitter continuously outputs a differential positive signal (DIF-P) to trigger the receiver's termination and complete impedance adjustment to prepare for receiving high-speed signals. Following the Prepare stage, during the Sync stage, the transmitter sends a SYNC pattern signal for the receiver's clock data recovery circuit to perform a tracking operation, ensuring that its clock phase is synchronized with the transmitter. Then, during the High-Speed ​​Data Reception stage, the receiver can begin receiving valid high-speed data.

[0004] Figure 1A is a schematic diagram of a data receiving device 2 in the prior art. Please refer to Figure 1A. The data receiving device 2 includes a phase-locked loop (PLL) 20, a multiplexer 21, a clock data recovery circuit 22, and a timer 23. The PLL 20 is coupled to the first input terminal A of the multiplexer 21. The output terminal C of the multiplexer 21 is coupled to the clock input terminal clk of the clock data recovery circuit 22. The timer 23 is coupled to the locking terminal L of the clock data recovery circuit 22. The PLL 20 provides the clock signal PLL_clk to the first input terminal A. The second input terminal B of the multiplexer 21 receives the data signal Data provided by the transmitting end. The control terminal S of the multiplexer 21 receives the enable signal Pt_en. When the enable signal Pt_en is 0, the multiplexer 21 outputs the clock signal PLL_clk received at the first input terminal A to the clock input terminal clk of the clock data recovery circuit 22. When the enable signal Pt_en is 1, the multiplexer 21 outputs the data signal Data received at its second input B to the clock input clk of the clock data recovery circuit 22. The timer 23 provides the lock signal CDR_lock to the lock terminal L of the clock data recovery circuit 22.

[0005] Figure 1B is a timing diagram illustrating the locking process of the clock data recovery circuit 22. Please refer to Figures 1A and 1B. In stage PH1, before time T0, the data signal Data is a low-speed signal for the preparation phase. In stage PH2, between time T0 and time T1, the data signal Data is a synchronization mode signal for the synchronization phase. In stage PH3, after time T1, the data signal Data is a high-speed signal for the high-speed data reception phase. During normal operation of the clock data recovery circuit 22, it is necessary to lock either the clock signal PLL_clk or the data signal Data to lock the phase. According to the MPHY protocol, during the preparation phase (i.e., stage PH1), the transmitter has not yet started transmitting high-speed data; therefore, the control enable signal Pt_en needs to be set to 0 to lock the clock data recovery circuit 22 to the local clock signal PLL_clk. When the synchronization mode signal begins transmission (i.e., at time T0), the control enable signal Pt_en is set to 1, and the clock data recovery circuit 22 will begin locking the data signal Data. After the clock data recovery circuit 22 tracks and locks (i.e., chases and locks) the data signal Data for a period of time (i.e., at time point T2), the timer 23 will pull up the lock signal CDR_lock. At this time, the phase and frequency of the clock data recovery circuit 22 are synchronized with the high-speed data, and it can start receiving high-speed data.

[0006] However, in the MPHY protocol, the receiver cannot know in advance the exact time when the low-speed signal (preparation phase) transitions to the high-speed signal (synchronization phase), so it must be detected by the circuit. In certain specific cases, the receiver may not be able to accurately detect the time when the high-speed signal begins transmission, causing the system to control the enable signal Pt_en to 1 before the high-speed signal has started transmission, thus causing the clock data recovery circuit 22 to incorrectly track the low-speed data of the preparation phase. Figure 2 is a schematic diagram of the clock data recovery circuit 22 incorrectly tracking the low-speed signal. Please refer to Figure 2. The enable signal Pt_en is pulled high to 1 at time T3, causing the clock data recovery circuit 22 to incorrectly track the low-speed data signal Data of phase PH1.

[0007] To address the issue of the clock data recovery circuit 22 erroneously locking onto low-speed data, existing technologies employ the "maximum time specification method," which delays the enable signal Pt_en to the maximum preparation time specified in the MPHY protocol (for example, in G5, 1UI = 1 / 23.32G = 43ps, and the maximum preparation time is 240SI = 2400UI = 2400 × 43ps = 103ns). While this method ensures that the clock data recovery circuit 22 does not erroneously lock onto low-speed signals, it also wastes synchronization mode signals, increasing the lock time required by the clock data recovery circuit 22 at the receiver. Since the lock time of the clock data recovery circuit 22 is one of the most crucial competitive factors in MPHY technology, this method exhibits significant performance limitations. Summary of the Invention

[0008] In some embodiments, a data receiving device is used to receive data signals. The data receiving device includes an amplifier, a comparator, a flip-flop, a control unit, a multiplexer, and a clock data recovery circuit. The amplifier amplifies the data signal. The comparator compares the data signal with a reference voltage signal to generate a comparison result signal. The flip-flop generates a trigger result signal based on the comparison result signal and in response to a clock signal. The control unit generates a multiplexing control signal based on the trigger result signal. The multiplexer selects the amplified data signal as an output signal based on the multiplexing control signal. The clock data recovery circuit latches the output signal after receiving it.

[0009] In some embodiments, the data receiving device further includes a timer. The timer is used to calculate the time for the clock data recovery circuit to lock onto the output signal of the amplified data signal, and when the time reaches a time threshold, outputs a completion signal to the clock data recovery circuit.

[0010] In some embodiments, the activation of the flip-flop is controlled by a control signal. The control unit is further used to provide the control signal.

[0011] In some embodiments, the data receiving device further includes a phase-locked loop (PLL). The PLL is used to provide a clock signal. The clock data recovery circuit is further used to lock the clock signal when no output signal amplified by an amplifier is received.

[0012] In some embodiments, the control unit is further configured to calculate the number of logic transitions of the output signal of the amplified data signal within a time period after the clock data recovery circuit receives the completion signal. When the number of logic transitions is less than a threshold, the control unit is further configured to first disable the multiplexing control signal, and then re-enable the multiplexing control signal after disabling it, so that the clock data recovery circuit can re-lock onto the output signal of the amplified data signal.

[0013] In some embodiments, the control unit is further configured to generate a multiplexing control signal when a trigger result signal is not received within a predetermined time.

[0014] In some embodiments, the predetermined time is a 240-symbol interval.

[0015] In some embodiments, the control unit is a finite state machine.

[0016] In some embodiments, a data receiving method includes: receiving a data signal; amplifying the data signal; comparing the data signal with a reference voltage signal to generate a comparison result signal; generating a trigger result signal based on the comparison result signal and in response to a clock signal; generating a multiplexing control signal based on the trigger result signal; selecting the amplified data signal as an output signal based on the multiplexing control signal; and inputting the output signal to a clock data recovery circuit so that the clock data recovery circuit locks the output signal after receiving it.

[0017] In some embodiments, the data receiving method further includes: calculating the time of the output signal of the clock data recovery circuit locked to the amplified data signal; and when the time reaches a time threshold, outputting a completion signal to the clock data recovery circuit.

[0018] In some embodiments, the step of generating a trigger result signal based on a clock signal according to a comparison result signal is enabled by a control signal, and the control signal is provided by a control unit that generates a multiplexing control signal based on the trigger result signal.

[0019] In some embodiments, the data receiving method further includes: after the clock data recovery circuit receives a completion signal, calculating the number of logic transitions of the output signal of the amplified data signal within a time period; and when the number of logic transitions is less than a threshold number, first disabling the multiplexing control signal, and then re-enabling the multiplexing control signal after disabling it, so that the clock data recovery circuit re-locks the output signal of the amplified data signal.

[0020] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this invention. Simple Explanation of the Diagram

[0021] Figure 1A is a schematic diagram of a data receiving device in the prior art. Figure 1B is a schematic diagram of the timing of the clock data recovery circuit for tracking and locking. Figure 2 is a schematic diagram of the clock data recovery circuit for error tracking of low-speed signals. Figure 3 is a block diagram of one embodiment of a data receiving device. Figure 4 is a flowchart of one embodiment of the data receiving method. Figure 5 shows the waveform diagrams of the data signal at the first and second points. Figure 6 is a flowchart of another embodiment of the data receiving method. Figure 7 is a flowchart of another embodiment of the data receiving method. Implementation

[0022] Figure 3 is a block diagram of one embodiment of the data receiving device 1. Please refer to Figure 3. The data receiving device 1 includes an amplifier 10, a comparator 11, a flip-flop 12, a control unit 13, a multiplexer 14, and a clock data recovery circuit 15. The amplifier 10 is coupled to the transmitting end Tx and the multiplexer 14. The comparator 11 is coupled to the transmitting end Tx and the flip-flop 12. The control unit 13 is coupled to the flip-flop 12 and the multiplexer 14. The clock data recovery circuit 15 is coupled to the multiplexer 14.

[0023] In some embodiments, the data receiving device 1 is used to receive the data signal S1 sent by the transmitting end Tx.

[0024] In some embodiments, the flip-flop 12 is a D-type flip-flop.

[0025] In some embodiments, the control unit 13 is a finite state machine.

[0026] In some embodiments, amplifier 10 amplifies only high-speed signals.

[0027] In some embodiments, amplifier 10 is coupled to the first input of multiplexer 14. Comparator 11 is coupled to the input of flip-flop 12. Control unit 13 is coupled to the output of flip-flop 12 and the control terminal of multiplexer 14. Clock data recovery circuit 15 is coupled to the output of multiplexer 14.

[0028] Figure 4 is a flowchart of one embodiment of the data receiving method. Please refer to Figures 3 and 4. After the data receiving device 1 receives the data signal S1 transmitted by the transmitting end Tx (step S01), the comparator 11 compares the data signal S1 with the reference voltage signal Vref to generate a comparison result signal S2 (step S02), and the amplifier 10 amplifies the data signal S1 (step S03). Next, the flip-flop 12 generates a trigger result signal S3 based on the comparison result signal S2 and in response to the clock signal CLK (step S04). Next, the control unit 13 generates a multiplexing control signal S4 based on the trigger result signal S3 (step S05). Next, the multiplexer 14 selects the data signal S1 amplified by the amplifier 10 as the output signal S5 based on the multiplexing control signal S4 (step S06). Finally, the clock data recovery circuit 15 locks the output signal S5 after receiving it (step S07).

[0029] Step S02 is explained in detail here. Figure 5 shows the waveforms of data signal S1 at the first point P1 and the second point P2. Please refer to Figures 4 and 5. In the stage PH4 before time point T4, data signal S1 is a low-speed signal in the preparation stage. In the stage PH5 before time point T4, data signal S1 is a high-speed synchronization mode signal in the synchronization stage. When data signal S1 enters the synchronization stage from the preparation stage, a low-speed negative edge is generated at the first point P1 before amplifier 10. Since the synchronization mode signal is a high-speed signal, it is severely attenuated before amplifier 10 during transmission, causing the voltage of data signal S1 in the synchronization stage to be close to 0 volts (V) at the first point P1. Therefore, in step S02, comparator 11 compares the data signal S1 before amplification by amplifier 10 (i.e., the data signal S1 at the first point P1) with the reference voltage signal Vref to generate a comparison result signal S2. When the reference voltage signal Vref is greater than the data signal S1, it indicates that the data signal S1 has entered the synchronization stage from the preparation stage, and comparator 11 generates the comparison result signal S2. In some embodiments, the reference voltage signal Vref may be, but is not limited to, 200mV. In some embodiments, comparator 11 generates the comparison result signal S2 by outputting a high-level signal (i.e., outputting logic 1).

[0030] In some embodiments, when the data signal S1 is a high-speed signal, its frequency is between 2.9 GHz and 23.2 GHz, but this application is not limited thereto.

[0031] It should be specifically noted that in some embodiments, since amplifier 10 only amplifies high-speed signals, in some embodiments, at the second point P2 after amplifier 10, only the data signal S1 during the synchronization phase will be effectively amplified. The voltage of the data signal S1 at the second point P2 during the preparation phase will also approach 0V, just like the voltage of the data signal S1 at the first point P1 during the synchronization phase. However, since the data signal S1 during the preparation phase may contain noise, which is mostly high-speed signal, it will also be amplified, causing a risk of misjudgment. Therefore, in step S02, comparator 11 compares the data signal S1 before amplification by amplifier 10 (i.e., the data signal S1 at the first point P1) rather than the data signal S1 after amplification by amplifier 10 (i.e., the data signal S1 at the second point P2) with the reference voltage signal Vref to generate the comparison result signal S2.

[0032] In some embodiments, the data receiving device 1 further includes a phase-locked loop 17. The phase-locked loop 17 is coupled to the flip-flop 12 and the multiplexer 14. The phase-locked loop 17 is used to provide a clock signal CLK.

[0033] In some embodiments, the phase-locked loop 17 is coupled to the clock input terminal of the flip-flop 12 and the second input terminal of the multiplexer 14.

[0034] In step S04, when the flip-flop 12 receives the comparison result signal S2 from its input terminal (if the flip-flop 12 is a D-type flip-flop, its input terminal is the D terminal of the D-type flip-flop), the flip-flop 12 responds to the clock signal CLK received at its clock input terminal and generates a trigger result signal S3 at its output terminal.

[0035] In step S05, when the control unit 13 receives the trigger result signal S3, the control unit 13 generates a multiplexing control signal S4. In some embodiments, the control unit 13 generates the multiplexing control signal S4 by outputting a high-level signal (i.e., outputting logic 1). In some embodiments, when the control unit 13 does not receive the trigger result signal S3, the control unit 13 outputs a low-level signal (i.e., outputting logic 0).

[0036] The multiplexer 14 is described in detail here. When the control terminal of the multiplexer 14 receives a low-level signal (i.e., 0), the multiplexer 14 outputs the signal received at the second input terminal to its output terminal. When the control terminal of the multiplexer 14 receives a high-level signal (i.e., 1), the multiplexer 14 outputs the signal received at the first input terminal to its output terminal. Therefore, in step S06, when the multiplexer 14 receives a high-level multiplexing control signal S4 at its control terminal, the multiplexer 14 selects the data signal S1 amplified by the amplifier 10 as the output signal S5.

[0037] It should be specifically noted that, in some embodiments, when the control unit 13 does not receive the trigger result signal S3, the control unit 13 outputs a low-level signal (i.e., 0). Furthermore, when the control terminal of the multiplexer 14 receives the low-level signal, the multiplexer 14 outputs the signal received at its second input terminal to its output terminal. Therefore, in some embodiments, when the multiplexer 14 receives the low-level signal output by the control unit 13 at its control terminal, the multiplexer 14 selects the clock signal CLK as the output signal S5.

[0038] In step S07, after receiving the output signal S5 from the output terminal of the multiplexer 14, the clock data recovery circuit 15 begins to lock onto the output signal S5. As mentioned earlier, when the control unit 13 receives the trigger result signal S3, the clock data recovery circuit 15 locks onto the output signal S5, which is the data signal S1 amplified by the amplifier 10. When the control unit 13 does not receive the trigger result signal S3, the clock data recovery circuit 15 locks onto the output signal S5, which is the clock signal CLK. In some embodiments, the clock input terminal of the clock data recovery circuit 15 is coupled to the output terminal of the multiplexer 14.

[0039] Through steps S02 to S06, before the clock data recovery circuit 15 locks the output signal S5 (step S07), the amplified data signal S1 will only be activated when the data receiving device 1 actually detects the start of the synchronization phase (i.e., a valid comparison result signal S2 and a trigger result signal S3). This effectively prevents the clock data recovery circuit 15 from erroneously locking to the low-speed signal of the preparation phase, and ensures that the data receiving device 1's locking of the amplified data signal S1 only occurs during the synchronous mode signal transmission, thereby reducing the risk of mis-locking and avoiding wasting the synchronous mode signal time of the data signal S1, thus improving the overall data reception efficiency.

[0040] In some embodiments, the activation of the flip-flop 12 is controlled by the control signal S8. In some embodiments, the control unit 13 is further used to provide the control signal S8. In some embodiments, the control unit 13 is further coupled to the reset terminal of the flip-flop 12, and the flip-flop 12 receives the control signal S8 provided by the control unit 13 from its reset terminal. In some embodiments, since the activation of the flip-flop 12 is controlled by the control signal S8, the control unit 13 must have provided the control signal S8 to the flip-flop 12 to activate the flip-flop 12 before the flip-flop 12 executes step S04.

[0041] Figure 6 is a flowchart of another embodiment of the data receiving method. Please refer to Figures 3 and 6. In some embodiments, the data receiving device 1 further includes a timer 16. The timer 16 is coupled to the clock data recovery circuit 15. In some embodiments, the timer 16 is used to calculate the time for the clock data recovery circuit 15 to lock onto the output signal S5 of the data signal S1 amplified by the amplifier 10 (step S08), and when the time reaches a time threshold, outputs a completion signal S7 to the clock data recovery circuit 15 (step S09). In some embodiments, the timer 16 is coupled to the locking terminal of the clock data recovery circuit 15. In some embodiments, the timer 16 outputs the completion signal S7 by outputting a high-level signal. In some embodiments, after the clock data recovery circuit 15 receives the completion signal S7, it indicates that the phase and frequency of the clock data recovery circuit 15 are now synchronized with the data signal S1, which is a high-speed synchronization mode signal, and it can begin to receive the data signal S1 in the high-speed data reception stage.

[0042] In some embodiments, data signal S1 conforms to the MPHY protocol.

[0043] In some embodiments, amplifier 10, comparator 11, flip-flop 12, multiplexer 14, clock data recovery circuit 15, and phase-locked loop 17 are disposed on the physical medium attachment (PMA) 18 of the receiver. Control unit 13 and timer 16 are disposed on the physical coding sublayer (PCS) 19 of the receiver.

[0044] Figure 7 is a flowchart of another embodiment of the data receiving method. Please refer to Figures 3 and 7. In some embodiments, although the reference voltage signal Vref and comparator 11 can effectively filter most of the noise in the data signal S1 and avoid misjudging the preparation stage of the data signal S1 as the synchronization stage, there may still be situations where the noise amplitude exceeds the voltage of the reference voltage signal Vref (e.g., 200mV), causing the high-level multiplexing control signal S4 to be activated prematurely. Therefore, in some embodiments, to improve robustness, the control unit 13 is further used to calculate the number of logic transitions of the output signal S5 of the data signal S1 amplified by amplifier 10 within a time period after the clock data recovery circuit 15 receives the completion signal S7 (step S10). When the number of logic transitions is less than the threshold number, the control unit 13 is further used to first disable the multiplexing control signal S4, and then re-enable the multiplexing control signal S4 after disabling it, so that the clock data recovery circuit 15 re-locks the output signal S5 (step S11).

[0045] Steps S10 and S11 are explained in detail below. First, the number of logic transitions is the number of times the output signal S5 changes from 0 to 1 or from 1 to 0. Furthermore, according to the MPHY protocol, the synchronization mode signal should have a specified number of logic transitions. Therefore, the number of logic transitions of the output signal S5 of the data signal S1 amplified by amplifier 10 should be greater than a certain number to confirm that the signal locked by the clock data recovery circuit 15 is a synchronization mode signal. If the number of logic transitions of the output signal S5 of the data signal S1 amplified by amplifier 10 is insufficient, the control unit 13 should determine that the clock data recovery circuit 15 has not successfully locked the synchronization mode signal, and must first disable and then re-enable the multiplexing control signal S4 to allow the clock data recovery circuit 15 to re-lock the synchronization mode signal, ensuring that high-speed data can be correctly received.

[0046] In some embodiments, according to the MPHY protocol, a 10-bit synchronous mode signal should have at least 7 logic transitions. Therefore, in some embodiments, when data signal S1 is 40-bit parallel data at the PMA end, the number of logic transitions for data signal S1 should be greater than 28. In other words, in some embodiments, the threshold number is 28.

[0047] In some embodiments, besides the possibility that the noise amplitude of the data signal S1 may exceed the voltage of the reference voltage signal Vref, causing the high-level multiplexing control signal S4 to be activated prematurely, the flip-flop 12 may also fail to provide the trigger result signal S3 due to malfunction. Therefore, in some embodiments, the control unit 13 is further configured to automatically generate the multiplexing control signal S4 when the trigger result signal S3 is not received within a predetermined time, to ensure that the data receiving device 1 can normally receive the data signal S1. In some embodiments, the predetermined time is 240 symbol intervals (SI).

[0048] In summary, in some embodiments, the data receiving device 1, by executing steps S02 to S06, can perform effective stage identification and signal detection before the clock data recovery circuit 15 locks the output signal S5 (step S07) to determine whether the data signal S1 has entered the synchronization stage from the preparation stage. Specifically, when the comparator 11 detects that the data signal S1 is lower than the reference voltage signal Vref and outputs the comparison result signal S2, the flip-flop 12 generates a trigger result signal S3 based on the comparison result signal S2, and the control unit 13 generates a multiplexing control signal S4 based on the trigger result signal S3. Finally, the multiplexer 14 switches its output source to the data signal S1 amplified by the amplifier 10 as the output signal S5 and transmits it to the clock data recovery circuit 15. This effectively prevents the clock data recovery circuit 15 from erroneously locking onto the low-speed signal during the preparation stage, and ensures that the data receiving device 1 locks onto the amplified data signal S1 only during synchronous mode signal transmission, thereby reducing the risk of mislocking and avoiding wasting the synchronous mode signal time of the data signal S1, thus improving the overall data receiving efficiency.

[0049] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

[0050] 1,2: Data receiving device 10: Amplifier 11: Comparator 12: Flipper 13: Control Unit 14,21: Multiplexer 15,22: Clock data recovery circuit 16,23: Timer 17, 20: Phase-locked loop 18: Physical medium attachment layer 19: Entity Coding Sublayer A: First input terminal B: Second input terminal C: Output terminal S: Control terminal L: Locking end clk: Clock input terminal S1,Data: Data signal S2: Comparison result signal S3: Trigger result signal S4: Multiplexing control signal S5: Output signal S7: Completion Signal S8: Control signal Vref: Reference voltage signal CLK, PLL_clk: Clock signal CDR_lock: Lock signal Pt_en: Enable signal Tx: Sending end P1: First point P2: Second point T0~T4: Time points PH1~PH5: Stages S01~S11: Steps

Claims

1. A data receiving apparatus for receiving a data signal, comprising: an amplifier for amplifying the data signal; a comparator for comparing the data signal with a reference voltage signal to generate a comparison result signal; a flip-flop for generating a trigger result signal based on the comparison result signal and in response to a clock signal; a control unit for generating a multiplexing control signal based on the trigger result signal; a multiplexer for selecting the amplified data signal as an output signal based on the multiplexing control signal; and a clock data recovery circuit for locking the output signal after receiving the output signal; wherein the control unit is further configured to generate the multiplexing control signal when the trigger result signal is not received within a predetermined time.

2. The data receiving apparatus as claimed in claim 1 further comprises: a timer for calculating a time during which the clock data recovery circuit locks onto the output signal of the data signal amplified by the amplifier, and outputting a completion signal to the clock data recovery circuit when the time reaches a time threshold.

3. The data receiving apparatus as claimed in claim 1, wherein the activation of the flip-flop is controlled by a control signal, and the control unit further provides the control signal.

4. The data receiving apparatus as claimed in claim 1 further comprises: a phase-locked loop for providing the clock signal; wherein the clock data recovery circuit is further configured to lock the clock signal when the output signal, which is the data signal amplified by the amplifier, is not received.

5. The data receiving apparatus as claimed in claim 2, wherein the control unit is further configured to, after the clock data recovery circuit receives the completion signal, calculate the number of logic transitions of the output signal of the data signal amplified by the amplifier within the time period; wherein when the number of logic transitions is less than a threshold number, the control unit is further configured to first disable the multiplexing control signal, and then re-enable the multiplexing control signal after disabling it, so that the clock data recovery circuit re-locks the output signal of the data signal amplified by the amplifier.

6. The data receiving apparatus as claimed in claim 1, wherein the predetermined time is a 240-symbol interval.

7. The data receiving apparatus as claimed in claim 1, wherein the control unit is a finite state machine.

8. A data receiving method, comprising: receiving a data signal; amplifying the data signal; comparing the data signal with a reference voltage signal to generate a comparison result signal; generating a trigger result signal based on the comparison result signal and in response to a clock signal; generating a multiplexing control signal based on the trigger result signal; selecting the amplified data signal as an output signal based on the multiplexing control signal; and inputting the output signal to a clock data recovery circuit so that the clock data recovery circuit locks the output signal after receiving the output signal; wherein the step of generating the trigger result signal based on the comparison result signal under the clock signal is enabled by a control signal, and the control signal is provided by a control unit that generates the multiplexing control signal based on the trigger result signal; wherein the control unit is further configured to generate the multiplexing control signal when the trigger result signal is not received within a predetermined time.

9. The data receiving method as described in claim 8 further comprises: calculating a time for the clock data recovery circuit to lock onto the output signal of the amplified data signal; and when the time reaches a time threshold, outputting a completion signal to the clock data recovery circuit.

10. The data receiving method as claimed in claim 8, wherein the clock data recovery circuit is further configured to lock the clock signal when the output signal, which is an amplified data signal, is not received.

11. The data receiving method as described in claim 9 further comprises: after the clock data recovery circuit receives the completion signal, calculating the number of logic transitions of the output signal of the amplified data signal within the time period; and when the number of logic transitions is less than a threshold number, first disabling the multiplexing control signal, and then re-enabling the multiplexing control signal after disabling it, so that the clock data recovery circuit re-locks the output signal of the amplified data signal.

12. The data receiving method as described in claim 8, wherein the predetermined time is a 240-symbol interval.

13. The data receiving method as described in claim 8, wherein the control unit is a finite state machine.

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