Circuit test point generating method and system thereof

Abstract

This invention provides a method and system for generating circuit test points, comprising: obtaining circuit layout information and setting rules; generating a circuit diagram based on the layout information; obtaining a plurality of center lines of a plurality of traces in the circuit diagram; setting a plurality of test points on each of the center lines; determining whether the test points on each of the center lines conform to a setting rule, and removing a portion of the test points that do not conform to the setting rule while retaining the other portion of the test points that conform to the setting rule; arranging and combining the other portion of the test points on each of the center lines according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculating the test point coverage rate of each of the candidate circuit test point diagrams; and determining the candidate circuit test point diagram with the highest test point coverage rate as the target circuit test point diagram. This improves the setting coverage rate of the test points.

Description

Technical Field

[0001] This invention relates to a method and system for generating test points, and more particularly to a method and system for generating circuit test points. Prior Technology

[0002] When testing printed circuit boards (PCBs), test points are set on the board, and probes are used to contact these test points to confirm the continuity of components. Ideally, test points should be placed at all component pins on the board to ensure that all components are tested. However, the test point placement must comply with trace and component spacing specifications to ensure that the probes can reliably perform tests when the test points are actually placed on the board.

[0003] Existing test point setting tools only provide one test point generation function, which sets test points at the component pins on the circuit board. In order to ensure that the test point settings comply with the routing and spacing specifications between components, the aforementioned test point setting tools cannot set test points at all component pins. Therefore, their test point coverage is low, that is, the number of components with test points at the same time is not high.

[0004] In view of this, developing a circuit test point generation method and system that can generate multiple test point arrangements and combinations and can place test points on circuit traces has become a worthwhile research and development goal for relevant industry players. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a circuit test point generation method and system, which sets multiple test points on the center line of the trace through a processor, generates multiple test point setting methods, and finds the target circuit test point diagram with the best test point setting method based on the test point coverage of the multiple test point setting methods.

[0006] According to one embodiment of the present invention, a method for generating circuit test points is provided, comprising: obtaining layout information and a setting rule for a circuit from a database by a processor, wherein the layout information includes routing information; generating a circuit diagram of the circuit by the processor based on the layout information; obtaining a plurality of center lines of a plurality of routing lines in the circuit diagram by the processor based on the routing information; setting a plurality of test points on each of these center lines by the processor; determining whether the test points of each of these center lines conform to the setting rule, and removing a portion of the test points that do not conform to the setting rule while retaining the other portion of the test points that conform to the setting rule; wherein the setting rule includes a test point spacing limit; arranging and combining the other portion of the test points of each of these center lines according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculating a test point coverage rate for each of these candidate circuit test point diagrams; and determining the candidate circuit test point diagram with the highest multiple test point coverage rate as a target circuit test point diagram by the processor.

[0007] Therefore, the circuit test point generation method of the present invention can generate a target circuit test point map with extremely high test point coverage.

[0008] According to one embodiment of the present invention, a circuit test point generation system is provided, comprising a database and a processor. The database is used to store layout information and a setting rule for a circuit. The layout information includes routing information. The processor is signal-connected to the database and obtains the layout information of the circuit from the database. The processor is configured to perform operations including the following steps: generating a circuit diagram of the circuit based on the layout information; obtaining a plurality of center lines of a plurality of routing lines of the circuit diagram based on the routing information; setting a plurality of test points on each of these center lines; determining whether the test points of each of these center lines conform to the setting rule, and removing a portion of the test points that do not conform to the setting rule while retaining the other portion of the test points that conform to the setting rule. The setting rule includes a test point spacing limit; arranging and combining the other portion of the test points of each of these center lines according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculating a test point coverage rate for each of these candidate circuit test point diagrams; determining the highest multiple test point coverage rate among the candidate circuit test point diagrams as a target circuit test point diagram.

[0009] Therefore, the circuit test point generation system of the present invention is highly flexible and can be applied to circuit boards of different specifications. Simple Explanation of the Diagram

[0010] Figure 1 illustrates a flowchart of a circuit test point generation method according to a first embodiment of the present invention; Figure 2 is a partial schematic diagram of a circuit diagram based on the circuit test point generation method in Figure 1; Figure 3 is a schematic diagram of the center line of the trace according to the circuit test point generation method in Figure 1; Figure 4 is another schematic diagram illustrating the centerline of the traces according to the circuit test point generation method in Figure 1; Figure 5 is a partial schematic diagram of the target circuit test point diagram according to the circuit test point generation method in Figure 1; Figure 6 illustrates a flowchart of a circuit test point generation method according to a second embodiment of the present invention; and Figure 7 illustrates a schematic diagram of a circuit test point generation system according to a third embodiment of the present invention. Implementation

[0011] Please refer to Figures 1 through 5. Figure 1 is a flowchart illustrating a circuit test point generation method 100 according to a first embodiment of the present invention; Figure 2 is a schematic diagram of a portion of the circuit diagram F1 according to the circuit test point generation method 100 of Figure 1; Figure 3 is a schematic diagram of the center line C4 of the trace L4 according to the circuit test point generation method 100 of Figure 1; Figure 4 is another schematic diagram of the center lines C1, C2, C3, C4, C5, C6, and C7 of the traces according to the circuit test point generation method 100 of Figure 1; and Figure 5 is a schematic diagram of a portion of the target circuit test point diagram F2 according to the circuit test point generation method 100 of Figure 1. The circuit test point generation method 100 includes steps 110, 120, 130, 140, 150, 160, and 170. Step 110: A processor 220 (see Figure 7) retrieves layout information D1 and setting rule R1 (see Figure 7) of a circuit from a database 210 (see Figure 7). The layout information D1 includes circuit board information, component location information, and routing information. Step 120: The processor 220 generates a circuit diagram F1 based on the layout information D1. Step 130: The processor 220 retrieves multiple center lines C1, C2, C3, C4, C5, C6, and C7 of the multiple traces (not shown) of the circuit diagram F1 based on the routing information. Step 140: The processor 220 sets multiple test points P, P0, P1, P2, and P3 on each of these center lines C1 to C7. Step 150: The processor 220 determines whether the test points P, P0, P1, P2, and P3 of each of the center lines C1 to C7 conform to setting rule R1, and removes the test points P and P0 that do not conform to setting rule R1, while retaining the test points P1, P2, and P3 that conform to setting rule R1. Setting rule R1 includes a test point spacing restriction. Step 160: The processor 220 arranges and combines the test points P1, P2, and P3 of each of the center lines C1 to C7 according to setting rule R1 to generate a complex candidate circuit test point diagram, and calculates the test point coverage rate of each of these candidate circuit test point diagrams. Step 170: The processor 220 determines the candidate circuit test point diagram with the highest complex test point coverage rate as a target circuit test point diagram F2.

[0012] In other words, the layout information D1 can be the layout file of the circuit, the circuit board information can include the geometry of the circuit board, the component location information can include the type and layout location of the component E1 in the circuit, and the routing information can include the wire diameter, setting location, and connected component E1 of the routing in the circuit, but the present invention is not limited thereto.

[0013] In Figure 2, step 120 converts the layout information D1 into a visual graphical object, which is displayed in the form of a circuit diagram F1.

[0014] Step 130 involves identifying the center lines C1 to C7 for each trace. Step 140 involves setting multiple test points P, P0, P1, P2, and P3 on the center lines C1 to C7 for each trace. For example, the center line C4 of trace L4 and the test points P, P0, P1, P2, and P3 set on it can be shown in Figure 3.

[0015] The measurement point spacing limit includes a measurement point spacing limit between measurement points, a measurement point spacing limit between a measurement point and an adjacent trace, a measurement point spacing limit between a measurement point and an adjacent component, and a measurement point spacing limit between a measurement point and a circuit board hole, but the present invention is not limited thereto. The measurement point spacing limit indicates that the distance between two adjacent test points on different center lines C1~C7 is greater than a first preset distance. The measurement point spacing limit between adjacent traces indicates that the distance between one of the test points P, P0, P1, P2, P3 and an adjacent trace is greater than a second preset distance. The measurement point spacing limit between adjacent components indicates that the distance between one of these test points P, P0, P1, P2, P3 and a component E1 in the circuit is greater than a third preset distance. The measurement point spacing limit between circuit board holes indicates that the distance between one of the test points P, P0, P1, P2, P3 and a hole H in the circuit is greater than a fourth preset distance. In step 150, test points P and P0 on the center line C4 of trace L4 are removed according to setting rule R1. In the first embodiment, the first preset spacing, the second preset spacing, the third preset spacing and the fourth preset spacing can be adjusted according to the circuit board rules, but the present invention is not limited thereto.

[0016] Taking test points P, P0, P1, P2, and P3 on the center line C4 of trace L4 as an example, if the distance between test points P and P0 on center line C4 and at least one of the adjacent traces (corresponding to the traces on center lines C3 and C5) is too close, it indicates that the current test points P and P0 do not meet the distance limit between test points and adjacent traces. If component E1 is located around test point P, and the distance between component E1 and test point P is too close, it indicates that the current test point P does not meet the distance limit between test points and adjacent components. If a hole H is located around test point P0, and the distance between the aforementioned hole H and test point P0 is too close, it indicates that the current test point P0 does not meet the distance limit between test points and circuit board holes.

[0017] After the test points P and P0 that do not conform to setting rule R1 in the center line C4 of the L4 route are removed, the test points P1, P2, and P3 on the center line C4 that conform to setting rule R1 can be seen as shown in Figure 4. Specifically, multiple test points conforming to setting rule R1 are also provided on the center lines C1~C3 and C5~C7 (not shown in the figure).

[0018] In step 160, test points P1, P2, and P3 are considered as candidate test points for the centerline C4 of trace L4. During the permutation and combination process, all candidate test points for centerline C4 are selected, and any test points P1 to P3 that do not conform to setting rule R1 are removed. The test point coverage of all candidate circuit test point diagrams is then calculated to generate candidate circuit test point diagrams. For example, Table 1 shows six candidate circuit test point diagrams (test point diagrams 1-6) generated by permuting and combining test points P1 and P2 on the centerlines C1 to C3 of the trace and test points P1, P2, and P3 on the centerline C4 of trace L4. Here, "1" indicates selected test points P1, P2, and P3; "0" indicates unselected test points P1, P2, and P3; and "1-" indicates selected test points P1, P2, and P3 that were removed because they did not conform to setting rule R1. In the first candidate circuit test point diagram, the permuted test points include test point P1 on center line C1, test point P1 on center line C2, test point P1 on center line C3, and test point P1 on center line C4. Table 2 series shows the test point coverage of the six candidate circuit test point diagrams in Table 1. The test point coverage can be calculated by dividing the number of traces with test points P1, P2, and P3 by the total number of traces. Table 1 Centerline Centerline C1 Centerline C2 Centerline C3 Centerline C4 test points P1 P2 P1 P2 P1 P2 P1 P2 P3 Measurement point diagram 1 1 0 1- 0 1 0 1 0 0 Measurement point diagram 2 1 0 1- 0 1 0 0 1 0 Measurement point diagram 3 1 0 1- 0 1 0 0 0 1 Measurement point diagram 4 1 0 1 0 0 1- 1 0 0 Measurement point diagram 5 1 0 1 0 0 1- 0 1 0 Measurement point diagram 6 1 0 1 0 0 1 0 0 1 Table 2 Candidate circuit measurement point diagram Total number of wiring Number of traces with test points Measurement point coverage Measurement point diagram 1 4 3 75% Measurement point diagram 2 4 3 75% Measurement point diagram 3 4 3 75% Measurement point diagram 4 4 3 75% Measurement point diagram 5 4 3 75% Measurement point diagram 6 4 4 100%

[0019] Step 170 selects the candidate circuit measurement point diagram with the highest measurement point coverage as the target circuit measurement point diagram F2. As shown in Table 1 and Table 2, the sixth candidate circuit measurement point diagram in Table 1 (i.e., measurement point diagram 6) has the highest measurement point coverage. Therefore, the sixth candidate circuit measurement point diagram is selected as the target circuit measurement point diagram F2, as shown in Figure 5.

[0020] Therefore, the circuit test point generation method 100 of the present invention can automatically generate a target circuit test point diagram F2 with extremely high test point coverage, reducing the pre-processing time for planning the placement of test points P1, P2, and P3 in the testing process and the modification time for manually adding test points P1, P2, and P3 due to low test point coverage.

[0021] Please refer to Figures 1 through 6. Figure 6 is a flowchart illustrating a circuit test point generation method 100a according to a second embodiment of the present invention. Circuit test point generation method 100a includes steps 110, 120, 130, 140, 150, 160, 170, and 180. In the second embodiment, steps 110, 120, 130, 140, 150, 160, and 170 are performed identically to steps 110, 120, 130, 140, 150, 160, and 170 of the circuit test point generation method 100 in the first embodiment, and will not be described again. Specifically, circuit test point generation method 100a may further include step 180. Step 180 involves the processor 220 setting at least one prohibited test point placement area in the circuit diagram F1 of the circuit. The prohibited placement area for measuring points does not include any of these measuring points P, P0, P1, P2, and P3; that is, these measuring points P, P0, P1, P2, and P3 are located outside the prohibited placement area for measuring points.

[0022] In other words, step 180 can set a prohibited testing point area in the circuit diagram F1 of Figure 2. After the prohibited testing point area is set, the test points P, P0, P1, P2, and P3 set in step 140 for each center line C1~C7 cannot be set within the prohibited testing point area, but can only be set within the circuit board, and outside the prohibited testing point area. Step 180 can be performed after step 130 and before step 140, but the present invention is not limited thereto. Therefore, the circuit test point generation method 100a of the present invention is highly flexible and can be applied to circuit boards of different specifications.

[0023] Please refer to Figures 1 through 7, with Figure 7 illustrating a schematic diagram of a circuit test point generation system 200 according to a third embodiment of the present invention. The circuit test point generation system 200 includes a database 210 and a processor 220. The database 210 stores layout information D1 and a setting rule R1 for a circuit. The layout information D1 includes circuit board information, component location information, and routing information. The processor 220 is signal-connected to the database 210 and obtains the circuit layout information D1 from the database 210. The processor 220 is configured to implement the circuit test point generation methods 100 and 100a of the first and second embodiments, generating a circuit diagram F1 based on the layout information D1 and removing test points P and P0 that do not conform to the setting rule R1, thereby generating a target circuit test point diagram F2 with high test point coverage. However, the present invention is not limited thereto. Thus, the circuit test point generation system 200 of the present invention can set test points P, P1, P2, and P3 on the routing, improving the test point coverage.

[0024] Specifically, the database 210 may be a memory, a temporary register or other data storage element, and the processor 220 may be a microprocessor or a central processing unit, but the present invention is not limited thereto.

[0025] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0026] 100,100a: Method for generating circuit test points 110, 120, 130, 140, 150, 160, 170, 180: Steps 200: Circuit Test Point Generation System 210: Database 220: Processor C1, C2, C3, C4, C5, C6, C7: Center lines D1: Layout Information E1: Component F1: Circuit Diagram F2: Target Circuit Measurement Point Diagram H: Hole position L4: Wiring P, P0, P1, P2, P3: Test points R1: Set rules

Claims

1. A method for generating circuit test points, comprising: obtaining layout information and a setting rule for a circuit from a database by a processor, wherein the layout information includes routing information; generating a circuit diagram of the circuit by the processor based on the layout information; obtaining a plurality of center lines of a plurality of routing lines of the circuit diagram by the processor based on the routing information; setting a plurality of test points on each of the center lines by the processor; determining whether the test points of each of the center lines conform to the setting rule by the processor, and removing a portion of the test points that do not conform to the setting rule while retaining another portion of the test points that conform to the setting rule, wherein the setting rule includes a test point spacing limit; arranging and combining the other portion of the test points of each of the center lines by the processor according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculating a test point coverage rate of each of the candidate circuit test point diagrams; and determining the highest of the plurality of test point coverage rates among the candidate circuit test point diagrams as a target circuit test point diagram by the processor.

2. The circuit test point generation method as described in claim 1 further comprises: setting at least one test point prohibition area in the circuit diagram of the circuit by the processor; wherein, These test points are located outside the prohibited placement area for at least one test point.

3. The circuit test point generation method as described in claim 1, wherein one of the other portions of the test points is regarded as a candidate test point for each of the center lines, and when arranging and combining them, a plurality of the candidate test points of the center lines are selected, and one of the candidate test points that does not conform to the setting rules is removed to generate one of the candidate circuit test point diagrams.

4. The circuit test point generation method as described in claim 1, wherein the test point spacing limitation includes a test point spacing limitation, the test point spacing limitation indicating that the distance between adjacent test points of each of the center lines is greater than a first preset spacing.

5. The circuit test point generation method as described in claim 4, wherein the test point spacing limitation further comprises: an adjacent trace spacing limitation, indicating that the spacing between one of the test points and one of the adjacent traces is greater than a second preset spacing; a test point and adjacent component spacing limitation, indicating that the spacing between one of the test points and a component of the circuit is greater than a third preset spacing; and a test point and circuit board hole spacing limitation, indicating that the spacing between one of the test points and a hole of the circuit is greater than a fourth preset spacing.

6. A circuit test point generation system, comprising: a database for storing layout information and a setting rule for a circuit, wherein the layout information includes routing information; and a processor signal-connected to the database and obtaining the layout information of the circuit from the database, the processor being configured to perform an operation comprising the following steps: generating a circuit diagram of the circuit based on the layout information; obtaining a plurality of center lines of a plurality of routing lines of the circuit diagram based on the routing information; setting a plurality of test points on each of the center lines; determining whether the test points of each of the center lines conform to the setting rule, and removing a portion of the test points that do not conform to the setting rule while retaining another portion of the test points that conform to the setting rule, wherein the setting rule includes a test point spacing limit; According to the setting rules, the other part of the test points of each of the center lines is arranged and combined to generate a plurality of candidate circuit test point diagrams, and a test point coverage rate of each of the candidate circuit test point diagrams is calculated; and the highest of the plurality of test point coverage rates in the candidate circuit test point diagrams is determined as a target circuit test point diagram.

7. The circuit test point generation system as described in claim 6, wherein the processor sets at least one test point prohibition area in the circuit diagram of the circuit, and the test points are located outside the at least one test point prohibition area.

8. The circuit test point generation system as described in claim 6, wherein one of the other portions of the test points is regarded as a candidate test point for each of the center lines, and when arranging and combining them, a plurality of the candidate test points of the center lines are selected, and one of the candidate test points that does not conform to the setting rules is removed to generate one of the candidate circuit test point diagrams.

9. The circuit test point generation system as claimed in claim 6, wherein the test point spacing limitation includes a test point-to-test point spacing limitation, the test point-to-test point spacing limitation indicating that the distance between adjacent test points of each of the center lines is greater than a first preset spacing.

10. The circuit test point generation system as claimed in claim 9, wherein the test point spacing limitation further comprises: an adjacent trace spacing limitation, indicating that the spacing between one of the test points and an adjacent trace is greater than a second preset spacing; a test point and adjacent component spacing limitation, indicating that the spacing between one of the test points and a component of the circuit is greater than a third preset spacing; and a test point and circuit board hole spacing limitation, indicating that the spacing between one of the test points and a hole of the circuit is greater than a fourth preset spacing.

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