Semiconductor device

Abstract

This disclosure provides a semiconductor device including a substrate, a first gate structure and a second gate structure, a dummy gate structure, a diffusion isolation structure, and at least one resistance switching element. The substrate includes a cell region having a plurality of active fins disposed thereon. The active fins extend in a first direction, are arranged in a second direction, and are doped with an N-type dopant. The first and second gate structures are spaced apart from each other on the substrate and extend in the second direction. The dummy gate structure is located on the substrate between the first and second gate structures and extends in the second direction. The diffusion isolation structure is located in the substrate below the dummy gate structure, extends in the second direction, and includes an oxide layer. The resistance switching element is located above the first and second gate structures and the dummy gate structure, and between the dummy gate structure and the first or second gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor memory device. Prior Technology

[0002] Semiconductor memory is a semiconductor component used to store data in computers or electronic products. It can be broadly classified into volatile memory and non-volatile memory. Volatile memory is memory whose stored data is lost when the power supply is interrupted, while non-volatile memory has the characteristic that its stored data is not lost due to power supply interruption. Resistive random access memory (RRAM) is a type of non-volatile memory, characterized by low operating voltage, low power consumption, and high write speed, making it suitable for use in the memory structure of many electronic devices.

[0003] In the 1T1R architecture composed of RRAM and transistor, the N-type field effect transistor (N-FET) is often used as the transistor in the 1T1R architecture because its electron mobility is greater than that of the hole mobility of the P-type field effect transistor (P-FET).

[0004] However, as electronic devices move towards miniaturization and users' performance requirements for electronic devices gradually increase, those skilled in the art continue to improve the 1T1R architecture to meet current or future expectations. Summary of the Invention

[0005] The present invention provides a semiconductor device that improves hole mobility by providing a diffusion isolation structure below a dummy gate structure in the architecture of a P-type field-effect transistor, thereby helping to improve the performance of the semiconductor device.

[0006] An embodiment of the present invention provides a semiconductor device comprising a substrate, a first gate structure, a second gate structure, a dummy gate structure, a diffusion isolation structure, and at least one resistance switching element. The substrate includes a cell region having a plurality of active fins disposed thereon, wherein the plurality of active fins are doped with N-type dopant, extend in a first direction, and are arranged in a second direction intersecting the first direction. The first gate structure and the second gate structure are disposed on the substrate, spaced apart from each other in the first direction, and extend in the second direction. The dummy gate structure is disposed on the substrate, between the first gate structure and the second gate structure, and extends in the second direction. The diffusion isolation structure is buried in the substrate, below the dummy gate structure, extends in the second direction, and includes oxide. The resistance switching element is disposed above the first gate structure, the second gate structure, and the dummy gate structure, and is positioned between the first gate structure and the dummy gate structure, or between the second gate structure and the dummy gate structure.

[0007] In some embodiments, the diffusion isolation structure overlaps with the dummy gate structure in a third direction perpendicular to the first and second directions.

[0008] In some embodiments, the top surface of the diffusion isolation structure is positioned at the level of its active fins protruding from it.

[0009] In some embodiments, the semiconductor device further includes a first drain and a second drain. The first drain is located in the active fin and between the first gate structure and the dummy gate structure. The second drain is located in the active fin and between the second gate structure and the dummy gate structure.

[0010] In some embodiments, the first drain electrode and the second drain electrode comprise SiGe.

[0011] In some embodiments, the semiconductor device further includes a first source and a second source. The first source is in an active fin, wherein a first gate structure is disposed between the first source and the first drain. The second source is in an active fin, wherein a second gate structure is disposed between the second source and the second drain.

[0012] In some embodiments, the first source and the second source comprise SiGe.

[0013] In some embodiments, at least one of the resistor switching elements includes a first resistor switching element and a second resistor switching element. The first resistor switching element is disposed between a first gate structure and a dummy gate structure. The second resistor switching element is disposed between a second gate structure and a dummy gate structure. The first resistor switching element and the second resistor switching element are arranged offset from each other in a first direction.

[0014] In some embodiments, the bottom surface of the dummy gate structure is positioned at a lower level than the bottom surface of the first gate structure or the second gate structure.

[0015] In some embodiments, the top surface of the dummy gate structure is positioned at a level approximately equal to the top surface of the first gate structure or the second gate structure.

[0016] Based on the above, in the aforementioned semiconductor device, under the architecture of a P-type field-effect transistor (with the active fin doped with N-type dopants), the design of providing a diffusion break structure below the dummy gate structure enhances the hole mobility, thereby helping to improve the performance of the semiconductor device. Simple Explanation of the Diagram

[0017] Figure 1 is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 is a schematic cross-sectional view taken along line A-A' in Figure 1. Figure 3 is a cross-sectional schematic diagram of a resistor switching element according to an embodiment of the present invention. Implementation

[0018] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0019] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element present. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may mean that there are other elements between the two elements.

[0020] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0021] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0022] Figure 1 is a top view of a semiconductor device according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1. Figure 3 is a cross-sectional view of a resistor switching element according to an embodiment of the present invention.

[0023] Referring to Figures 1 and 2, the semiconductor device 10 includes a substrate SUB1, a first gate structure GS1, a second gate structure GS2, a dummy gate structure DGS1, a diffusion isolation structure SDB1, and at least one resistance switching element (e.g., a first resistance switching element RSE1 and / or a second resistance switching element RSE2).

[0024] The substrate SUB1 includes a cell region CR1 on which a plurality of active fins AF1 are disposed, wherein the plurality of active fins AF1 extend in a first direction D1 and are arranged in a second direction D2 intersecting the first direction D1. In some embodiments, the first direction D1 may be perpendicular to the second direction D2. In this embodiment, the semiconductor device 10 includes a P-type field-effect transistor, that is, the active fins AF1 are doped with N-type dopants. In some embodiments, the substrate SUB1 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. When the semiconductor device 10 includes a P-type field-effect transistor, the semiconductor material may be doped with N-type dopants to give the substrate SUB1 an N-type conductivity type.

[0025] A first gate structure GS1 and a second gate structure GS2 are disposed on a substrate SUB1, spaced apart from each other in a first direction D1, and extending in a second direction D2. The first gate structure GS1 may include a first gate layer GL1 extending in the first direction D1 and first gate spacers SW1 on opposite side walls of the first gate layer GL1 in the first direction D1. The second gate structure GS2 may include a second gate layer GL2 extending in the first direction D1 and second gate spacers SW2 on opposite side walls of the second gate layer GL2 in the first direction D1.

[0026] The first gate layer GL1 and the second gate layer GL2 may each comprise any material suitable as a gate, such as polycrystalline silicon in a polycrystalline silicon gate or metallic materials and high-dielectric-constant materials in a metallic gate. The metallic materials may include titanium nitride (TiN), tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials. The high-dielectric-constant materials may include dielectric materials having a high dielectric constant. For example, a dielectric material with a high dielectric constant may be a material with a dielectric constant greater than that of silicon oxide (approximately 3.9). In some embodiments, the high dielectric constant material may include HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al2O3, Si3N4, SiON, or combinations thereof.

[0027] The first gate spacer SW1 and the second gate spacer SW2 may each comprise any material suitable as a gate spacer, such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), or combinations thereof.

[0028] A dummy gate structure DGS1 is disposed on a substrate SUB1, between a first gate structure GS1 and a second gate structure GS2, and extends in a second direction D2. The dummy gate structure DGS1 may include a dummy gate layer DGL1 extending in the first direction D1 and dummy gate spacers DSW1 on opposite sidewalls of the dummy gate layer DGL1 in the first direction D1. The dummy gate layer DGL1 may include any of the aforementioned materials suitable as gates. In some embodiments, the dummy gate layer DGL1 may be made of the same material as the first gate layer GL1 and / or the second gate layer GL2. The dummy gate spacer DSW1 may include any of the aforementioned materials suitable as gate spacers. In some embodiments, the dummy gate spacer DSW1 may be made of the same material as the first gate spacer SW1 and / or the second gate spacer SW2.

[0029] In this embodiment, the bottom surface of the dummy gate structure DGS1 can be positioned at a level lower than the bottom surface of the first gate structure GS1 or the second gate structure GS2. In this embodiment, the top surface of the dummy gate structure DGS1 can be positioned at a level approximately equal to the top surface of the first gate structure GS1 and / or the second gate structure GS2. The dummy gate spacer DSW1 can include a first portion on the top surface of the substrate SUB1 and a second portion embedded in the substrate SUB1. In some embodiments, the thickness of the first portion of the dummy gate spacer DSW1 in the first direction D1 can be greater than the thickness of the second portion of the dummy gate spacer DSW1 in the first direction D1.

[0030] The diffusion isolation structure SDB1 can be embedded in the substrate SUB1, below the dummy gate structure DGS1, extending in the second direction D2, and includes oxide. In this embodiment, the diffusion isolation structure SDB1 can be a shallow trench isolation (STI) structure filled with oxide. When the first gate structure GS1 and the second gate structure GS2 are gate structures of P-type field-effect transistors, the oxide-containing diffusion isolation structure SDB1 can provide compressive strain to the channels of the P-type field-effect transistors, thereby improving the hole mobility and thus helping to improve the performance of the semiconductor device 10. On the other hand, in this embodiment, the diffusion isolation structure SDB1 is designed below the dummy gate structure DGS1 and disposed between the first gate structure GS1 and the second gate structure GS2. That is, the diffusion isolation structure SDB1 is a single diffusion break (SDB) structure, which can help save layout area and help increase the device density in the semiconductor device 10.

[0031] In this embodiment, the diffusion isolation structure SDB1 may overlap with the dummy gate structure DGS1 in a third direction D3 perpendicular to the first direction D1 and the second direction D2. In this embodiment, the top surface of the diffusion isolation structure SDB1 may be positioned at the level where the active fin AF1 protrudes. In some embodiments, the diffusion isolation structure SDB1 may include a sidewall that is coplanar with the sidewall of the second portion of the dummy gate spacer DSW1 (i.e., the portion of the first dummy gate spacer DSW1 embedded in the substrate SUB1).

[0032] Referring to Figure 1, at least one resistance switching element (e.g., a first resistance switching element RSE1 and / or a second resistance switching element RSE2) is disposed above the first gate structure GS1, the second gate structure GS2, and the dummy gate structure DGS1, and is positioned between the first gate structure GS1 and the dummy gate structure DGS1, or between the second gate structure GS2 and the dummy gate structure DGS1. In this embodiment, at least one resistance switching element may include a first resistance switching element RSE1 and a second resistance switching element RSE2. The first resistance switching element RSE1 may be disposed between the first gate structure GS1 and the dummy gate structure DGS1. The second resistance switching element RSE2 may be disposed between the second gate structure GS2 and the dummy gate structure DGS1. In this embodiment, the first resistance switching element RSE1 and the second resistance switching element RSE2 are arranged offset from each other in a first direction D1.

[0033] In some embodiments, as shown in FIG3, the resistance switching element (e.g., a first resistance switching element RSE1 or a second resistance switching element RSE2) may include a bottom electrode LE1, a top electrode UE1, and a variable resistance layer RVL1 between the bottom electrode LE1 and the top electrode UE1. The bottom electrode LE1 and the top electrode UE1 may each include a metallic material, a metal nitride, or other suitable conductive material. The metallic material may include at least one of the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride may include a nitride formed from a metal of at least one of the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The variable resistance layer RVL1 may include a metal oxide. For example, the variable resistance layer RVL1 may include at least one of the group consisting of TiO2, NiO, HfO, HfO2, ZrO, ZrO2, Ta2O5, ZnO, WO3, CoO and Nb2O5.

[0034] In this embodiment, the semiconductor device 10 may further include a first drain DE1 and a second drain DE2 disposed in the active fin AF1. The first drain DE1 is disposed between the first gate structure GS1 and the dummy gate structure DGS1. The second drain DE2 is disposed between the second gate structure GS2 and the dummy gate structure DGS1. In this embodiment, when the first drain DE1 and the second drain DE2 are drains of a P-type field-effect transistor, the first drain DE1 and the second drain DE2 may each be doped with a P-type dopant to give the first drain DE1 and the second drain DE2 a P-type conductivity. In this embodiment, the first drain DE1 and the second drain DE2 may include SiGe, which can further apply lateral compressive strain to the channel of the P-type field-effect transistor to further improve the hole mobility, thereby helping to improve the performance of the semiconductor device 10.

[0035] In this embodiment, the semiconductor device 10 may further include a first source SE1 and a second source SE2 disposed in the active fin AF1, wherein a first gate structure GS1 may be disposed between the first source SE1 and the first drain DE1, and a second gate structure GS2 may be disposed between the second source SE2 and the second drain DE2. In this embodiment, when the first source SE1 and the second source SE2 are sources of a P-type field-effect transistor, the first source SE1 and the second source SE2 may each be doped with a P-type dopant to give the first source SE1 and the second source SE2 a P-type conductivity. In this embodiment, the first source SE1 and the second source SE2 may include SiGe, which can further apply lateral compressive strain to the channel of the P-type field-effect transistor to further improve the hole mobility, thereby helping to improve the performance of the semiconductor device 10.

[0036] In some embodiments, as shown in FIG1, the first resistance switching element RSE1 and the second resistance switching element RSE2 may be respectively disposed on opposite sides of the dummy gate structure DGS1 in the first direction D1, and the first drain DE1 and the second drain DE2 may also be respectively disposed on opposite sides of the dummy gate structure DGS1 in the first direction D1 corresponding to the first resistance switching element RSE1 and the second resistance switching element RSE2. In other words, when the first resistance switching element RSE1 and the second resistance switching element RSE2 are respectively disposed between the dummy gate structure DGS1 and the first gate structure GS1 and between the dummy gate structure DGS1 and the second gate structure GS2, the first drain DE1 and the second drain DE2 may be disposed near the proximal end of the dummy gate structure DGS1, which is closer to the first source SE1 and the second source SE2 in the top view direction.

[0037] In some embodiments, as shown in Figures 2 and 3, the semiconductor device 10 may further include an insulating layer ILD0 disposed on a substrate SUB1 and covering a first gate structure GS1, a second gate structure GS2, and a dummy gate structure DGS1, and an insulating layer ULK1 disposed on the insulating layer ILD0 and wherein a resistance switching element (e.g., a first resistance switching element RSE1) is disposed therein. In this embodiment, the insulating layer ILD0 may be an interlayer dielectric layer. The insulating layer ULK1 may be an inter-metal dielectric layer. In some embodiments, the insulating layer ILD0 may include a material with a dielectric constant greater than that of the insulating layer ULK1. For example, when the insulating layer ULK1 includes a low-k material with a dielectric constant less than that of silicon oxide (e.g., about 3.9), the insulating layer ILD0 may include a dielectric material with a dielectric constant greater than that of the low-k material, such as silicon oxide. Alternatively, when the insulating layer ULK1 includes an ultra-low-k material with a dielectric constant less than about 2.6, the insulating layer ILD0 may use a dielectric material with a dielectric constant greater than that of the ultra-low-k material, such as tetraethyl orthosilicate (TEOS).

[0038] In some embodiments, as shown in Figures 2 and 3, the semiconductor device 10 may further include a conductive contact CT1 disposed in the insulating layer ILD0 and electrically connected to the first drain DE1 and the second drain DE2. The conductive contact CT1 may include a suitable conductive material such as a metal, a metal nitride, or a metal alloy. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. Metal nitrides may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof. In some embodiments, as shown in Figures 2 and 3, the conductive contact CT1 may electrically connect the bottom electrode LE1 of the first resistance switching element RSE1 to the first drain DE1.

[0039] In some embodiments, as shown in Figures 2 and 3, the semiconductor device 10 may further include an insulating layer NDC1 disposed between the insulating layer ILD0 and the insulating layer ULK1. The insulating layer NDC1 may contain a nitrogen-doped carbon material. In this embodiment, as shown in Figure 3, a first resistance switching element RSE1 may be disposed in the insulating layer ULK1 and the insulating layer NDC1 may be disposed between the first resistance switching element RSE1 and the insulating layer ULK1.

[0040] In some embodiments, as shown in Figures 1 to 3, the semiconductor device 10 may further include a conductive layer M1 disposed in an insulating layer ULK1 and a conductive via V0. In some embodiments, the conductive layer M1 may be electrically connected to the top electrode UE1 of a resistance switching element (e.g., a first resistance switching element RSE1 or a second resistance switching element RSE2). In some embodiments, the conductive via V0 may electrically connect the conductive layer M1 to a conductive contact CT1. The conductive layer M1 and the conductive via V0 may each comprise a suitable conductive material such as a metal, a metal nitride, or a metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The metal nitride may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

[0041] In summary, in the semiconductor device of the above embodiments, under the architecture of a P-type field-effect transistor (with the active fin doped with N-type dopant), the design of providing a diffusion break structure below the dummy gate structure improves the hole mobility, thereby helping to improve the performance of the semiconductor device.

[0042] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0043] 10: Semiconductor devices AF1: Active fin CR1: Cellular region CT1: Conductive contact D1: First Direction D2: Second Direction D3: Third direction DE1: First Absorption DE2: Second Absorption Pole DGL1: Virtual gate layer DGS1: Virtual gate structure DSW1: Dummy gate spacer GL1: First gate layer GS1: First gate structure GL2: Second gate layer GS2: Second gate structure ILD0: Insulating layer LE1: Bottom electrode M1: Conductive layer NDC1: Insulating layer RSE1: First resistance switching element RSE2: Second resistance switching element RVL1: Variable Resistance Layer SDB1: Diffusion Isolation Structure SE1: First Source SE2: Second Source SUB1: Base SW1: First gate spacer SW2: Second gate spacer UE1: Top Electrode ULK1: Insulation layer V0: Conductive via

Claims

1. A semiconductor device, comprising: a substrate including a cell region having a plurality of active fins disposed thereon, wherein the active fins are doped with an N-type dopant, extend in a first direction and are arranged in a second direction intersecting the first direction; a first gate structure and a second gate structure disposed on the substrate, spaced apart from each other in the first direction and extending in the second direction; a dummy gate structure disposed on the substrate, between the first gate structure and the second gate structure and extending in the second direction; a diffusion isolation structure embedded in the substrate, below the dummy gate structure, extending in the second direction and comprising an oxide; and at least one resistor switching element disposed above the first gate structure, the second gate structure and the dummy gate structure, and disposed between the first gate structure and the dummy gate structure, or between the second gate structure and the dummy gate structure.

2. The semiconductor device of claim 1, wherein the diffusion isolation structure overlaps with the dummy gate structure in a third direction perpendicular to the first direction and the second direction.

3. The semiconductor device of claim 1, wherein the top surface of the diffusion isolation structure is positioned at the level from which the active fin protrudes.

4. The semiconductor device as claimed in claim 1, further comprising: The first drain electrode is located in the active fin and between the first gate structure and the dummy gate structure; And a second drain electrode, in the active fin and between the second gate structure and the dummy gate structure.

5. The semiconductor device of claim 4, wherein the first drain and the second drain comprise SiGe.

6. The semiconductor device as claimed in claim 4, further comprising: A first source electrode, wherein the first gate structure is disposed between the first source electrode and the first drain electrode in the active fin; And a second source electrode, wherein the second gate structure is disposed between the second source electrode and the second drain electrode in the active fin.

7. The semiconductor device of claim 6, wherein the first source and the second source comprise SiGe.

8. The semiconductor device of claim 1, wherein at least one of the resistor switching elements comprises: A first resistance switching element is disposed between the first gate structure and the dummy gate structure; And a second resistance switching element, disposed between the second gate structure and the dummy gate structure, wherein the first resistance switching element and the second resistance switching element are arranged offset from each other in the first direction.

9. The semiconductor device of claim 1, wherein the bottom surface of the dummy gate structure is positioned at a level lower than the bottom surface of the first gate structure or the second gate structure.

10. The semiconductor device of claim 1, wherein the top surface of the dummy gate structure is positioned at a level approximately equal to the top surface of the first gate structure or the second gate structure.

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