Integrated chip and method of forming the same

Abstract

This disclosure, in some embodiments, relates to an integrated wafer including a dielectric structure over a substrate. The dielectric structure includes a first plurality of dielectric layers and a second plurality of dielectric layers stacked alternately. The dielectric structure has a plurality of side surfaces that at least partially define a plurality of lateral recesses perpendicularly aligned to the first plurality of dielectric layers. A capacitor structure is disposed on the plurality of side surfaces and includes a first conductive layer, a second conductive layer, and a capacitor dielectric layer between the first and second conductive layers. An etch-stop structure is in the dielectric structure and extends perpendicularly from the top surface of the dielectric structure to the bottom dielectric layer of the first plurality of dielectric layers. The etch-stop structure laterally covers and surrounds the capacitor structure and abuts the plurality of side surfaces.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated wafer and a method for forming the same. Prior Technology

[0002] Integrated wafers are formed on semiconductor dies comprising millions or billions of transistor devices. These transistor devices are configured to act as switches and / or generate power gain to enable logic functions for the integrated wafer (e.g., forming a processor configured to perform logic functions). Integrated wafers also include passive devices such as capacitors, resistors, inductors, transformers, etc. Passive devices are widely used to control integrated wafer characteristics such as gain, time constant, etc. Summary of the Invention

[0003] This invention provides an integrated wafer, the integrated wafer including a dielectric structure disposed on a substrate, the dielectric structure having a first plurality of dielectric layers and a second plurality of dielectric layers stacked alternately with a first plurality of dielectric layers, the dielectric structure having a plurality of side surfaces that at least partially define a plurality of lateral recesses perpendicularly aligned with the first plurality of dielectric layers; a capacitor structure disposed on the plurality of side surfaces and having a first conductive layer, a second conductive layer, and a capacitor dielectric layer between the first and second conductive layers; and an etch stop structure in the dielectric structure and extending perpendicularly from the top surface of the dielectric structure to a bottom dielectric layer in the first plurality of dielectric layers, the etch stop structure laterally covering the capacitor structure and adjacent to the plurality of side surfaces.

[0004] This invention provides a method for forming an integrated wafer, the method comprising forming a first conductive structure on a substrate; forming a dielectric structure on the first conductive structure, the dielectric structure having a first plurality of dielectric layers alternately stacked with a second plurality of dielectric layers; forming an etch stop structure in the dielectric structure, the etch stop structure having opposing inner sidewalls disposed on opposite sides of an inner segment of the dielectric structure, the etch stop structure separating the inner segment from an outer segment of the dielectric structure; performing an etching process on the dielectric structure to form a trench in the inner segment of the dielectric structure; and forming a capacitor structure in the trench, the capacitor structure having the plurality of protrusions extending laterally from a central region of the trench to individual sidewalls of the opposing inner sidewalls of the etch stop structure.

[0005] This invention provides a method for forming an integrated wafer, the method comprising: forming a first conductive structure on a substrate; forming a dielectric structure on the first conductive structure, the dielectric structure having a first plurality of dielectric layers of a first material interleaved between a second plurality of dielectric layers having a second material different from a first material; performing a first etching process on the dielectric structure to form a pair of first openings in the dielectric structure and on opposite sides of the first conductive structure; forming an etch stop structure in the pair of first openings; performing a second etching process on the dielectric structure to form second openings between opposite sidewalls of the etch stop structures and on the first conductive structure; performing a third etching process on the dielectric structure to extend the second openings and form a plurality of side surfaces in the second plurality of dielectric layers that at least partially define trenches, the plurality of side surfaces being stacked perpendicularly to each other and adjacent to the etch stop structures; and forming a first conductive layer, a capacitor dielectric layer, and a second conductive layer in the trenches and along the plurality of side surfaces. Simple Explanation of the Diagram

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. The drawings are drawn to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate the relationships between various structures and / or devices within the embodiments. It should be noted that the drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a cross-sectional view of some integrated wafer embodiments, which have capacitor structures disposed in trenches of a dielectric structure and etch stop structures in and around the trenches of the dielectric structure. Figures 2A and 2B illustrate top views of some embodiments of the integrated wafer of Figure 1. Figures 3A and 3B illustrate cross-sectional views of some additional integrated wafer embodiments, which have capacitor structures disposed within trenches of a dielectric structure and etch stop structures in and around the trenches of the dielectric structure. Figure 3C illustrates a cross-sectional view of some integrated wafer embodiments, including a plurality of capacitor structures in the plurality of trenches of the dielectric structure and a plurality of etch stop structures in the dielectric structure and around the trenches. Figure 4 illustrates a cross-sectional view of some other embodiments of the integrated wafer of Figure 1. Figure 5 illustrates a cross-sectional view of an image sensor integrated wafer according to some additional embodiments, which has a capacitor structure disposed in a trench of a dielectric structure and an etch stop structure in the dielectric structure and around the trench. Figures 6 to 19 illustrate cross-sectional views of embodiments of methods for forming integrated wafers having capacitor structures disposed within trenches of dielectric structures and etch stop structures in and around the trenches of dielectric structures. Figure 20 illustrates a flowchart of some embodiments of a method for forming an integrated wafer having a capacitor structure disposed in a trench within a dielectric structure and an etch stop structure in and around the trench within the dielectric structure. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of apparatus and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein for ease of description to describe the relationship between one device or feature as shown in the figures and another device or feature. Spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0009] A capacitor is a passive device used in a wide variety of integrated wafer applications. For example, complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) may include lateral overflow integration capacitors (LOFICs) to increase the high dynamic range (HDR) of the CIS. A capacitor comprises a capacitor dielectric between a first conductive electrode and a second conductive electrode. The capacitance of the capacitor is proportional to the overlap area between the first and second conductive electrodes. To achieve the capacitance required for integrated wafer applications, the capacitor footprint can be relatively large and consume a significant area above the substrate of the integrated wafer. As the minimum feature size of integrated wafers shrinks, the size of the capacitor cannot be reduced without decreasing its capacitance.

[0010] To increase capacitance while maintaining or reducing the capacitor's coverage area, the capacitor can be formed in a trench with a dielectric structure having multiple side surfaces. The dielectric structure includes a first plurality of dielectric layers staggered between a second plurality of dielectric layers. The first plurality of dielectric layers have different etch selectivity than the second plurality of dielectric layers. The multiple side surfaces define multiple lateral recesses extending from the central region of the trench and configured at different vertical heights aligned with the first plurality of dielectric layers. The capacitor pads the multiple side surfaces and has a relatively large overlap area between its conductive electrodes (e.g., compared to a capacitor formed in a trench with straight sidewalls), thereby increasing the capacitor's capacitance. During manufacturing, the multiple side surfaces can be formed by a wet etching process. However, local loading effects and / or flow field variations during wet etching can cause inconsistent etching of the dielectric structure across the height of the trench. For example, the upper layers in the first plurality of dielectric layers may be over-etched compared to the lower layers, resulting in undesirable and unpredictable narrowing of the trench. This can lead to significant variations in the width of the multiple lateral recesses across the height of the trench, adversely affecting capacitor formation and / or performance. For example, capacitors may be prone to delamination in certain areas of the trench (e.g., in relatively wide recesses where it is difficult to properly deposit capacitor layers), capacitors may be formed with tolerances exceeding predetermined capacitance values, and / or capacitors may be short-circuited to another directly adjacent capacitor. Consequently, the device yield and / or performance of the integrated wafer can be reduced.

[0011] This disclosure relates to an integrated wafer including a capacitor structure disposed within a trench of a dielectric structure and an etch-stop structure laterally surrounding the capacitor structure within the trench. The dielectric structure includes a first plurality of dielectric layers staggered between a second plurality of dielectric layers. The trench of the dielectric structure is at least partially defined by a plurality of side surfaces that define a plurality of lateral recesses perpendicularly aligned with the first plurality of dielectric layers. The etch-stop structure extends perpendicularly from a top surface of the dielectric structure to a bottom dielectric layer of the dielectric structure. The trench is disposed between inner opposing sidewalls of the etch-stop structure, wherein the outer points of the plurality of lateral recesses are defined by corresponding sidewalls of the inner opposing sidewalls. The capacitor structure includes first and second electrodes separated by a capacitor dielectric. The capacitor structure is disposed in the trench and extends from the plurality of side surfaces to the inner opposing sidewalls of the etch-stop structure. During the fabrication of the capacitor structure, the etch-stop structure is formed in the dielectric structure, and subsequently, etching (e.g., wet etching) is performed on the dielectric structure to form the plurality of side surfaces defining the trench. The etch-stop structure mitigates over-etching (e.g., over-etching in the lateral direction) of the first plurality of dielectric layers. As a result, the plurality of lateral recesses vertically aligned with the first plurality of dielectric layers have a more uniform width across the height of the trench. This mitigates the unpredictable narrowing of the capacitor structure across the height of the trench and helps control the size of the capacitor structure. Therefore, the capacitor structure can be formed with predictable dimensions and problems caused by over-etching can be mitigated, thereby increasing the performance of the integrated wafer.

[0012] Figure 1 illustrates a cross-sectional view 100 of some embodiments of an integrated wafer, having a capacitor structure 132 disposed within a trench 120 of a dielectric structure 118 and an etch stop structure 122 in the dielectric structure 118 and around the trench 120.

[0013] In some embodiments, the integrated wafer includes a transistor 104 disposed on a substrate 102. A lower interlayer dielectric (ILD) structure 108 is disposed on the substrate 102. A first via 106 and a lower conductive structure 110 are disposed within the lower ILD structure 108. A lower etch stop layer 112 is disposed on the lower ILD structure 108. A dielectric structure 118 is disposed on the lower ILD structure 108. The dielectric structure 118 includes a first plurality of dielectric layers 114 and a second plurality of dielectric layers 116, which are interleaved between the first plurality of dielectric layers 114. The second plurality of dielectric layers 116 includes a plurality of lateral protrusions 116a stacked perpendicularly to each other. The lateral protrusions 116a include a plurality of side surfaces 116b, 116c. A trench 120 is disposed in the dielectric structure 118 and extends from a top surface 118t of the dielectric structure 118 to a top surface 110t of the lower conductive structure 110. The plurality of side surfaces 116b, 116c at least partially define a plurality of lateral recesses 115 of trench 120, which extend outward from the central region of trench 120. The plurality of lateral recesses 115 are perpendicularly separated from each other and aligned with corresponding layers in the first plurality of dielectric layers 114. The first plurality of dielectric layers 114 have a first etch rate when etched with an etchant, which is greater than a second etch rate when the second plurality of dielectric layers 116 are etched with the same etchant. This allows a wet etching process using the etchant to form the plurality of lateral protrusions 116a and to remove the first plurality of dielectric layers 114 from within trench 120.

[0014] A capacitor structure 132 is disposed within a trench 120 and includes a diffusion barrier layer 124, a first conductive layer 126, a capacitor dielectric layer 128, and a second conductive layer 130. The capacitor structure 132 is lining the trench 120 and is disposed along the plurality of side surfaces 116b, 116c. The capacitor structure 132 includes a plurality of protrusions disposed on opposite sides of the capacitor structure 132 and within the plurality of lateral recesses 115. Because the capacitor structure 132 is disposed along the plurality of side surfaces 116b, 116c, the surface area of ​​the capacitor structure 132 is increased (e.g., increased compared to another capacitor structure having continuous straight sidewalls), thereby increasing the capacitance of the capacitor structure 132 within a fixed vertical distance defined by the height of the trench 120.

[0015] An etch stop structure 122 is disposed in a dielectric structure 118. In some embodiments, the etch stop structure 122 extends vertically from the top surface 118t of the dielectric structure 118 to the bottom surface 118b of the dielectric structure 118. The etch stop structure 122 laterally surrounds the trench 120. A capacitor structure 132 extends from the side surfaces 116b, 116c of the second plurality of dielectric layers 116 to the inner sidewall 122is of the etch stop structure 122. Each of the plurality of lateral protrusions 116a extends from the corresponding inner sidewall 122is of the etch stop structure 122 toward the central region of the trench 120. A plurality of gaps 114g are disposed along the inner sidewall 122is of the etch stop structure 122 and are staggered between the plurality of lateral protrusions 116a. The height of an individual gap 114g is defined by the thickness of the adjacent dielectric layer of the first plurality of dielectric layers 114 adjacent to the outer sidewall 122os of the etch stop structure 122. The maximum thickness of one of the plurality of lateral protrusions 116a is defined by the thickness of the adjacent dielectric layers of the second plurality of dielectric layers 116 adjacent to the outer sidewall 122os of the etch stop structure 122. In some embodiments, the etch stop structure 122 comprises a conductive material (e.g., titanium nitride).

[0016] During the fabrication of the integrated wafer, an etch stop structure 122 is formed in a dielectric structure 118. An initial opening is formed in the dielectric structure 118 between the inner sidewalls 122is of the etch stop structure 122, wherein the initial opening defines a central region of a trench 120. Wet etching is performed on the dielectric structure 118, thereby enlarging the initial opening and defining the trench 120. During wet etching, the first plurality of dielectric layers 114 are etched faster than the second plurality of dielectric layers 116, thereby defining the plurality of side surfaces 116b, 116c and the plurality of lateral recesses 115. During wet etching, the etch stop structure 122 has a significantly lower etch rate than both the first plurality of dielectric layers 114 and the second plurality of dielectric layers 116, thereby preventing problems that could lead to lateral over-etching (e.g., problems attributable to localized loading effects and / or flow field changes during wet etching). For example, during wet etching, the etch stop structure 122 prevents etching of the first plurality of dielectric layers 114 in areas outside the outer sidewalls 122os of the etch stop structure 122. Therefore, the etch stop structure 122 mitigates over-etching during wet etching and confines the trench 120 within the inner sidewalls 122is of the etch stop structure 122. As a result, the capacitor structure 132 can be deposited in the trench 120 with a uniform profile. Therefore, the capacitor structure 132 has relatively high capacitance and is formed at predictable dimensions, thereby improving the overall performance of the integrated wafer.

[0017] In some embodiments, the etch stop structure 122 includes a conductive material and is electrically coupled to the first conductive layer 126 and the lower conductive structure 110. In some embodiments, the capacitor structure 132 includes one or more inner surfaces defining a cavity 134. A horizontal segment 122h of the etch stop structure 122 extends laterally across the top surface 118t of the dielectric structure 118, in a direction away from and towards the trench 120. The upper portion of the capacitor structure 132 covers the horizontal segment 122h of the etch stop structure 122. A cover structure 140 is disposed on the dielectric structure 118 and covers the capacitor structure 132. The cover structure includes a first passivation layer 136, a second passivation layer 138a, and sidewall spacers 138b. The first passivation layer 136 is disposed on the second conductive layer 130 and along a bias 128o covering the capacitor dielectric layer 128, wherein the second conductive layer 130 is biased inward toward the trench 120. A second passivation layer 138a is disposed on a first section of the first passivation layer 136, the first section covering the second conductive layer 130. A sidewall spacer 138b is disposed on a second section of the first passivation layer 136, the second section covering the bias 128o.

[0018] A first upper dielectric layer 144 covers the cover structure 140 and the dielectric structure 118. An upper etch stop layer 146 covers the first upper dielectric layer 144, and a second upper dielectric layer 150 covers the upper etch stop layer 146. An upper interconnect via 142 is disposed within the first upper dielectric layer 144 and coupled to the second conductive layer 130. An upper interconnect conductor 148 is disposed within the second upper dielectric layer 150 and coupled to the upper interconnect via 142.

[0019] Figures 2A and 2B illustrate top views 200a and 200b of some embodiments of the integrated wafer of Figure 1. Figure 2A illustrates top view 200a taken along line A-A' of Figure 1. Figure 2B illustrates top view 200b taken along line B-B' of Figure 1.

[0020] As shown in top view 200a, along the plane of cut line A-A', trench 120 is defined by lateral protrusions 116a that laterally surround trench 120 in a closed loop. In some embodiments, lateral protrusions 116a are disposed on the inner periphery of etch stop structure 122 that laterally surrounds lateral protrusions 116a in a closed loop. In some embodiments, lateral protrusions 116a comprise the same material as one of a second plurality of dielectric layers 116 disposed on the outer periphery of etch stop structure 122. In some embodiments, diffusion barrier layer 124, first conductive layer 126, capacitor dielectric layer 128, and second conductive layer 130 are each annular in top view and may be, for example, concentric with each other. In some embodiments, etch stop structure 122 is annular and extends around the periphery of capacitor structure 132 in top view. Second conductive layer surrounds cavity 134.

[0021] As shown in top view 200b, along the plane of cut line B-B', the inner periphery of etch stop structure 122 laterally covers the capacitor structure in a closed loop. In some embodiments, diffusion barrier layer 124 of capacitor structure 132 contacts etch stop structure 122.

[0022] Figure 3A illustrates a cross-sectional view 300a of some additional embodiments of an integrated wafer having a capacitor structure 132 disposed within a trench 120 of a dielectric structure 118 and an etch stop structure 122 in the dielectric structure 118 and surrounding the trench 120.

[0023] The integrated wafer includes a lower interlayer dielectric structure 108 disposed on a substrate 102. In some embodiments, the plurality of lower conductive structures 110a, 110b are disposed within the interlayer dielectric structure 108. In some embodiments, the plurality of lower conductive structures 110a, 110b may include one or more of copper, tungsten, ruthenium, aluminum, titanium nitride, tantalum nitride, or the like. A lower etch stop layer 112 is disposed on the lower interlayer dielectric structure 108. In some embodiments, the lower etch stop layer 112 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. A dielectric structure 118 is disposed on the lower interlayer dielectric structure 108 and covers the lower etch stop layer 112. In some embodiments, the dielectric structure 118 may have a thickness in the range of about 500 nanometers to 3 micrometers or some other suitable value. The dielectric structure 118 includes a first plurality of dielectric layers 114 and a second plurality of dielectric layers 116 interleaved between the first plurality of dielectric layers 114. In some embodiments, the first plurality of dielectric layers 114 may include nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), or the like. In some embodiments, the second plurality of dielectric layers 116 may include oxides, undoped silicate glass (USG), phosphosilicate glass (PSG), or the like. In some embodiments, the first plurality of dielectric layers 114 may have a thickness 114t in the range of about 50 nm to 200 nm, about 50 nm to 100 nm, about 100 nm to 200 nm, or some other suitable value. In some embodiments, the second plurality of dielectric layers 116 may have a thickness 116t in the range of about 100 nanometers to 600 nanometers, about 100 nanometers to 350 nanometers, about 350 nanometers to 600 nanometers, or some other suitable value. In some embodiments, the thickness 114t of the first plurality of dielectric layers 114 is smaller than the thickness 116t of the second plurality of dielectric layers 116.

[0024] An etch stop structure 122 is disposed within a vertical opening 305 extending from the top surface 118t of the dielectric structure 118 to the bottom surface 118b of the dielectric structure 118. In some embodiments, the etch stop structure 122 includes a pair of vertical segments 122v and a pair of horizontal segments 122h. The vertical segments 122v are disposed in the vertical opening 305 on opposite sides of the trench 120 disposed in the dielectric structure 118. The etch stop structure 122 separates the inner segment of the dielectric structure 118 from the outer segment of the dielectric structure 118, wherein the inner segment of the dielectric structure 118 is disposed between a pair of inner sidewalls 122is of the etch stop structure 122, and the outer segment of the dielectric structure 118 is disposed outside a pair of outer sidewalls 122os of the etch stop structure 122. In some embodiments, the vertical openings 305 each have a width in the range of about 100 nanometers to 250 nanometers or some other suitable value. In some embodiments, the vertical segment 122v has a height in the range of about 500 nanometers to 3 micrometers or some other suitable value. In some embodiments, the horizontal segments 122h of the etch stop structure 122 may each have a width in the range of about 50 nanometers to 600 nanometers or some other suitable value. In some embodiments, the etch stop structure 122 may include, for example, nitrides (e.g., titanium nitride, tantalum nitride, etc.), tantalum (Ta), tungsten (W), or the like. In various embodiments, the material of the etch stop structure 122 is different from that of the lower etch stop layer 112, the first plurality of dielectric layers 114, and the second plurality of dielectric layers 116.

[0025] In some embodiments, the pair of inner sidewalls 122is, the pair of outer sidewalls 122os, the pair of vertical segments 122v, and the pair of horizontal segments 122h are defined from a cross-sectional view. For example, if the etch stop structure 122 is circular / elliptical when viewed from above, the pair of vertical segments 122v is a single continuous vertical segment that appears annular when viewed from above; therefore, the term "pair" of vertical segments 122v refers to the nature of this single continuous structure as depicted in the cross-sectional view.

[0026] Trench 120 extends from the top surface 118t of dielectric structure 118 to the top surface 110at of first lower conductive structure 110a. In some embodiments, trench 120 may have a thickness ranging from about 100 nm to 300 nm, 100 nm to 600 nm, 150 nm to 1 μm, or some other suitable value. Trench 120 is defined by the plurality of side surfaces 116b, 116c of dielectric structure 118 and the inner sidewall 122is of etch stop structure 122. The plurality of side surfaces 116b, 116c may be surfaces of a second plurality of dielectric layers 116 and / or may define the upper and lower surfaces of the plurality of lateral protrusions 116a. In some embodiments, when viewed in a top view, each of the plurality of lateral protrusions 116a extends continuously along the inner periphery of etch stop structure 122 in a closed path. Adjacent lateral protrusions in the plurality of lateral protrusions 116a are perpendicularly separated from each other by a vertical distance equal to or greater than the thickness 114t of adjacent corresponding dielectric layers in the plurality of dielectric layers 114. In some embodiments, the vertical distance of the plurality of gaps 114g may be in the range of about 50 nanometers to 200 nanometers or some other suitable value. In some embodiments, individual lateral protrusions in the plurality of lateral protrusions 116a include a pair of side surfaces in the plurality of side surfaces 116b, 116c that extend from corresponding sidewalls in the inner sidewall 122is of the etch stop structure 122. In some embodiments, one or more of the side surfaces 116b, 116c are measured at an obtuse angle relative to the corresponding sidewalls in the inner sidewall 122is of the etch stop structure 122. In some embodiments, the pair of side surfaces in the plurality of side surfaces 116b, 116c meet at a point within the trench 120, which is in a region laterally offset from the inner sidewall 122is. In some embodiments, the plurality of side surfaces 116b, 116c may have a horizontal length in the range of about 50 nanometers to 400 nanometers or some other suitable value.

[0027] A capacitor structure 132 is disposed within a trench 120. In some embodiments, the capacitor structure 132 liners the trench 120 and extends along the plurality of side surfaces 116b, 116c and inner sidewall 122is of the etch stop structure 122 to the top surface 110at of the first lower conductive structure 110a. In some embodiments, the capacitor structure 132 includes an upper section above the horizontal section 122h of the etch stop structure 122. The capacitor structure 132 includes a diffusion barrier layer 124, a first conductive layer 126 disposed along the diffusion barrier layer 124, a second conductive layer 130, and a capacitor dielectric layer 128 between the first conductive layer 126 and the second conductive layer 130. In some embodiments, the capacitor structure 132 has one or more inner surfaces defining a cavity 134 within the trench 120. In some embodiments, the capacitor structure 132 has opposing outer sidewalls 132s aligned with opposing sidewalls of the horizontal section 122h of the etch stop structure 122. The capacitor structure 132, disposed within the trench 120 along the plurality of side surfaces 116b, 116c, increases the surface area between the first conductive layer 126 and the second conductive layer 130 along the height of the trench 120, thereby increasing the capacitance of the capacitor structure 132. The etch-stop structure 122 slows down or prevents over-etching during the formation of the trench 120, resulting in a more uniform width of the lateral protrusions 116a across the height of the trench 120. As a result, the capacitor structure 132 has a uniform profile across the height of the trench 120, thereby increasing the overall performance of the integrated wafer.

[0028] In some embodiments, the diffusion barrier layer 124 may be, for example, titanium nitride, tantalum nitride, tantalum, tungsten, some other suitable material, or any combination thereof. The diffusion barrier layer 124 may have a thickness in the range of about 10 angstroms (Å) to 1000 Å or some other suitable value. In some embodiments, the first conductive layer 126 and the second conductive layer 130 may be, for example, copper, aluminum, tantalum, tungsten, titanium, tantalum nitride, titanium nitride, some other suitable material, or any combination thereof. In some embodiments, the first conductive layer 126 may include the same metal or a different metal as the second conductive layer 130. The first conductive layer 126 and the second conductive layer 130 may each have a thickness in the range of about 10 Å to 1000 Å or some other suitable value. In some embodiments, the first conductive layer 126 may have the same thickness as the second conductive layer 130, while in other embodiments, the first conductive layer 126 may have a different thickness than the second conductive layer 130. In some embodiments, the capacitor dielectric layer 128 may be, for example, or include zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride, silicon dioxide, silicon carbide, some other suitable dielectric material, or any combination thereof. The capacitor dielectric layer 128 may have a thickness in the range of about 5 Å to 1000 Å or some other suitable value.

[0029] A cover structure 140 is disposed over a capacitor structure 132. The cover structure 140 includes a first passivation layer 136, a second passivation layer 138a, and sidewall spacers 138b. The first passivation layer 136 covers the second conductive layer 130. The second passivation layer 138a covers the first passivation layer 136. The sidewall spacers 138b cover the first passivation layer 136 at a bias of 128° and extend continuously in a closed path around the inner sidewalls of the first passivation layer 136 when viewed in a top view. In a cross-sectional view, the sidewall spacers 138b are configured as a pair on opposite sides of the first passivation layer 136. In some embodiments, the first passivation layer 136 may be, for example, silicon oxide or other suitable materials. In some embodiments, the second passivation layer 138a may be, for example, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the sidewall spacer 138b may include the same material as the second passivation layer 138a; in other embodiments, the sidewall spacer 138b may include a different material than the second passivation layer 138a.

[0030] In some embodiments, interconnect vias 310a and interconnect conductors 310b are disposed within the dielectric structure 118 at locations laterally separated from the trench 120 by an etch stop structure 122. In some embodiments, the interconnect conductors 310b are separated from the etch stop structure 122 by a distance 314d, which is in the range of approximately 100 nanometers to 1 micrometer or some other suitable value. The interconnect via 310a contacts the bottom of the interconnect conductors 310b and contacts the top surface 110bt of the second lower conductive structure 110b. In some embodiments, the interconnect via 310a and / or the interconnect conductors 310b extend vertically through at least two of the first plurality of dielectric layers 114 and at least two of the second plurality of dielectric layers 116, respectively.

[0031] A first upper dielectric layer 144 covers the cover structure 140. An upper etch stop layer 146 covers the first upper dielectric layer 144, and a second upper dielectric layer 150 covers the upper etch stop layer 146. In some embodiments, a first upper interconnect via 142a extends through the first upper dielectric layer 144, the second passivation layer 138a, and the first passivation layer 136 to contact the second conductive layer 130 of the capacitor structure 132. A second upper interconnect via 142b extends through the first upper dielectric layer 144 to contact the interconnect conductor 310b. In some embodiments, the plurality of upper interconnect conductors 148a, 148b are disposed in the second upper dielectric layer 150 and cover the first and second upper interconnect vias 142a, 142b. In some embodiments, an etch stop layer 312 is disposed within the dielectric structure 118. In some embodiments, the etch stop layer 312 may be disposed between a first dielectric layer 114a and a second dielectric layer 114b of the first plurality of dielectric layers 114. In some embodiments, the bottom surface of the interconnect conductor 310b is below the top surface of the etch stop layer 312. In some embodiments, the etch stop layer 312 includes one or more lateral protrusions disposed between the inner sidewalls 122is of the etch stop structure 122, wherein the one or more lateral protrusions have a pair of side surfaces defining a portion of the trench 120.

[0032] Figure 3B illustrates a cross-sectional view 300b of some other embodiments of the integrated wafer of Figure 3A, wherein a first upper layer interconnect via 142a is laterally biased in the middle region of the capacitor structure 132. In some embodiments, the cavity 134 is defined by the plurality of inner surfaces of the second conductive layer 130 and the lower surface of the cover structure 140. In various embodiments, the first upper layer interconnect via 142a is laterally biased in the center 134c of the cavity 134.

[0033] Figure 3C illustrates a cross-sectional view 300c of some embodiments of the plurality of capacitor structures included in the plurality of trenches of the dielectric structure and the plurality of etch stop structures in and around the trenches of the integrated wafer.

[0034] The integrated wafer includes a substrate 102 disposed beneath a lower interlayer dielectric structure 108 comprising the plurality of lower conductive structures 110. A lower etch stop layer 112 covers the lower interlayer dielectric structure 108. A dielectric structure 118 covers the lower etch stop layer 112. The plurality of trenches 120a, 120b are disposed within the dielectric structure 118. The plurality of capacitor structures 132a, 132b are disposed within the trenches 120a, 120b in the dielectric structure 118. The plurality of etch stop structures 122a, 122b are disposed in the dielectric structure 118 and are separated from each other by a distance 322. For example, the distance 322 may be in the range of about 100 nanometers to 1 micrometer or some other suitable value. In some embodiments, a first capacitor structure 132a is disposed in a first trench 120a defined and / or surrounded by the first etch stop structure 122a. The second capacitor structure 132b is disposed in the second trench 120b, which is limited and / or surrounded by the second etch stop structure 122b. The plurality of upper interconnect vias 142 are disposed in the first upper dielectric layer 144 and cover the plurality of capacitor structures 132a, 132b and the interconnect conductors 310b laterally biased against the second etch stop structure 122b. The plurality of upper interconnect conductors 148 are disposed in the second upper dielectric layer 150 and cover the plurality of upper interconnect vias 142.

[0035] By employing a first etch stop structure 122a laterally surrounding the first trench 120a and a second etch stop structure 122b laterally surrounding the second trench 120b, problems caused by over-etching during the formation of the trenches 120a and 120b can be mitigated. For example, the etch stop structures 122a and 122b prevent over-etching in the lateral direction during the fabrication of the trenches 120a and 120b, thus isolating the trenches 120a and 120b from each other (e.g., across at least a distance 322). Therefore, the etch stop structures 122a and 122b confine the trenches 120a and 120b and facilitate the proper formation of capacitor structures 132a and 132b within the trenches 120a and 120b, thereby improving the overall performance of the integrated wafer. The etch stop structures 122a, 122b also facilitate isolation from interconnect structures (e.g., interconnect wires 310b) and / or other structures in the dielectric structure 118 that are adjacent to the capacitor structures 132a, 132b.

[0036] Figure 4 illustrates a cross-sectional view 400 of some other embodiments of the integrated wafer of Figure 1, wherein the dielectric structure 118 includes the plurality of inner sidewalls, which are spaced apart between the inner sidewalls 122is of the etch stop structure 122.

[0037] In some embodiments, one or more of the plurality of lateral protrusions 116a include a first side surface 116b, a second side surface 116c, and an inner sidewall 116d between the first and second side surfaces 116b, 116c. In some embodiments, the width 402 of the groove 120 between the first pair of protrusions in the plurality of lateral protrusions 116a is greater than the second width 404 of the groove 120 between the second pair of protrusions in the plurality of lateral protrusions 116a. In such embodiments, the first pair of protrusions is vertically positioned above the second pair of protrusions. In some embodiments, the first sidewall height 406 of an individual lateral protrusion in the first pair of protrusions is greater than the second sidewall height 408 of an individual lateral protrusion in the second pair of protrusions. In various embodiments, the width of the cavity 134 may decrease in the direction from the top of the cavity 134 toward the substrate 102.

[0038] In some embodiments, the plurality of lateral protrusions 116a are perpendicularly separated from each other by the plurality of gaps 114g. The plurality of gaps 114g includes a first gap 114g1 and a second gap 114g2. In some embodiments, the first gap 114g1 may have a thickness or height greater than the second gap 114g2. In other embodiments, the thickness or height of the first gap 114g1 is the same as the thickness or height of the second gap 114g2. In some embodiments, the thickness of the plurality of gaps 114g may be defined by the thickness of adjacent dielectric layers in the first plurality of dielectric layers 114 disposed along the outer sidewall 122os of the etch stop structure 122. In other embodiments, the thickness of the plurality of gaps 114g may be greater than the thickness of adjacent dielectric layers in the first plurality of dielectric layers 114. A capacitor structure 132 extends along the trench 120 and conforms to the shape of the plurality of lateral protrusions 116a, and fills at least a portion of the gaps 114g. In some embodiments, the capacitor structure 132 includes a vertical segment that extends continuously across each of the plurality of gaps 114g.

[0039] Figure 5 illustrates a cross-sectional view 500 of some embodiments of an image sensor integrated wafer, the image sensor integrated wafer having a capacitor structure 132 disposed within a trench 120 of a dielectric structure 118 and an etch stop structure 122 in the dielectric structure 118 and around the trench 120. [ ]

[0040] In some embodiments, the image sensor integrated wafer includes a lower interlayer dielectric structure 502 disposed on a substrate 102. In some embodiments, the lower interlayer dielectric structure 502 includes the plurality of conductive contacts 518, the plurality of interconnect wires 520, the plurality of interconnect vias 522, the plurality of interlayer dielectric etch stop layers 516, and the plurality of gate structures 506g, 510g, 512g, and 514g. The plurality of interlayer dielectric etch stop layers 516 are disposed at different levels of the plurality of interconnect wires 520. The interlayer dielectric etch stop layers 516 may be, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or the like. A lower etch stop layer 112 covers the lower interlayer dielectric structure 502 and separates the dielectric structure 118 from the lower interlayer dielectric structure 502. An etch stop structure 122 is disposed within the dielectric structure 118 and laterally surrounds a trench 120 within the dielectric structure 118. A capacitor structure 132 is disposed within the trench 120, wherein a section of the capacitor structure 132 within the trench is laterally restricted by the etch stop structure 122. The capacitor structure 132 may be configured as a lateral overflow integration capacitor (LOFIC). [ ]

[0041] Image sensing device 504, floating diffusion well 508, and the plurality of transistors 510, 512, 514 are disposed on and / or within substrate 102. Isolation structure 524 is disposed in substrate 102 and between transistors 510, 512, 514. In some embodiments, image sensing device 504 includes a first region having a first doping type (e.g., n-type doping), the first region being adjacent to a second region having a second doping type different from the first doping type (e.g., p-type doping). Image sensing device 504 may be, for example, a photodiode. The plurality of gate structures 506g, 510g, 512g, 514g have a gate dielectric layer disposed on the top surface 102a of substrate 102 and gate electrodes disposed on the gate dielectric layer. In some embodiments, sidewall spacers are disposed on opposite sides of the gate electrodes. [ ]

[0042] In some embodiments, a transmission transistor gate structure 506g is laterally disposed between the image sensing device 504 and the floating diffusion well 508. The transmission transistor gate structure 506g is configured to control the transfer of charge from the image sensing device 504 to the floating diffusion well 508. The floating diffusion well 508 is coupled to a source follower transistor gate structure 512g and a first source / drain region of the capacitor switching transistor 510. In some embodiments, a source follower transistor 512 is coupled between a column select transistor 514 and a voltage node (e.g., a node coupled to a power supply), wherein the source follower transistor is configured to buffer and amplify the voltage at the floating diffusion well 508. The column select transistor 514 is configured to selectively deliver the buffered and amplified voltage from the source follower transistor 512 to an output terminal. A second source / drain region of the capacitor switching transistor 510 is coupled to a capacitor structure 132. [ ]

[0043] In some embodiments, the capacitor switching transistor 510 is configured to switch the image sensing device 504 between a low conversion gain mode and a high conversion gain mode. For example, when operating in a low conversion gain mode, the capacitor switching transistor 510 is closed (e.g., on), such that the capacitor structure 132 is coupled to the floating diffusion well 508. In this case, charge at the floating diffusion well 508 overflows into the capacitor structure 132. When operating in a high conversion gain mode, the capacitor switching transistor 510 is open (e.g., off), such that the capacitor structure 132 is isolated from the floating diffusion well 508. The plurality of gate structures 506g, 510g, 512g, 514g, the source / drain regions of the plurality of transistors 510, 512, 514, and the capacitor structure 132 are operatively coupled to each other via the plurality of conductive contacts 518, the plurality of interconnect wires 520, and the plurality of interconnect vias 522. The source / drain region can refer to either the source or the drain, individually or collectively, depending on the context. [ ]

[0044] Figures 6 through 19 illustrate cross-sectional views of methods for forming an integrated wafer according to some embodiments, the integrated wafer having a capacitor structure disposed within trenches of a dielectric structure and an etch stop structure in the dielectric structure and around the trenches. Although Figures 6 through 19 are described with respect to a method, it should be understood that the structures disclosed in Figures 6 through 19 are not limited to this method, but can exist independently of the method.

[0045] As shown in the cross-sectional view 600 of FIG6, a lower interlayer dielectric structure 108 and a lower conductive structure 110 are formed on a substrate 102. In some embodiments, the substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material. In some embodiments, the lower conductive structure 110 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process) or some other suitable process. In this embodiment, the lower conductive structure 110 may be formed by depositing the lower interlayer dielectric structure 108 on the substrate 102, selectively etching the lower interlayer dielectric structure 108 to define trenches within the lower interlayer dielectric structure 108, forming a conductive material (e.g., copper, aluminum, etc.) within the trenches, and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove excess conductive material from the lower interlayer dielectric structure 108.

[0046] As further shown in Figure 6, a lower etch stop layer 112 is deposited on the lower interlayer dielectric structure 108, and a dielectric structure 118 is formed on the lower etch stop layer 112. In some embodiments, the lower etch stop layer 112 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination thereof. In some embodiments, the dielectric structure 118 includes a first plurality of dielectric layers 114 and a second plurality of dielectric layers 116, the second plurality of dielectric layers 116 being stacked alternately with the first plurality of dielectric layers 114. The first plurality of dielectric layers 114 are a first material, and the second plurality of dielectric layers 116 are a second dielectric material different from the first material. The first material and the second material have different etch selectivity relative to the etchant. For example, the first material may have a first etch rate when exposed to the etchant, and the second material may have a second etch rate when exposed to the etchant. In some embodiments, the first plurality of dielectric layers 114 may include nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), or the like. In some embodiments, the second plurality of dielectric layers 116 may include oxides, undoped silicate glass (USG), phosphosilicate glass, or the like. In some embodiments, the first plurality of dielectric layers 114 may be formed to a first thickness, and the second plurality of dielectric layers 116 may be formed to a second thickness greater than the first thickness. In some embodiments, the first plurality of dielectric layers 114, the second plurality of dielectric layers 116, and the lower etch stop layer 112 may be formed by a plurality of deposition processes (e.g., PVD, CVD, PE-CVD, ALD, or similar processes). [ ]

[0047] As shown in the cross-sectional view 700 of FIG7, a pair of vertical openings 305 are formed within the dielectric structure 118. The vertical openings 305 extend from the top surface 118t of the dielectric structure 118 to the bottom surface 118b of the dielectric structure 118, passing through the first plurality of dielectric layers 114 and the second plurality of dielectric layers 116. In some embodiments, in a top view, the vertical openings 305 are part of a single annular opening that extends continuously into a closed loop. In some embodiments, the vertical openings 305 may be formed by exposing the dielectric structure 118 to one or more etchants 704 according to a mask 702 during an etching process. In some embodiments, the one or more etchants 704 may include dry etchants (e.g., reactive ion etching (RIE) etchants, plasma etchants, or the like). In some embodiments, the one or more etchants 704 may have etching chemistry including one or more of fluorine (F), tetrafluoromethane (CF4), ozone (O2), or octafluorocyclobutane (C4F8), or the like. In some embodiments, the mask 702 may include a photosensitive material (e.g., photoresist), a rigid mask, or the like. [ ]

[0048] As shown in the cross-sectional view 800 of FIG8, an etch stop structure 122 is deposited within a vertical opening 305. In some embodiments, the etch stop structure 122 covers the dielectric structure 118 and includes a pair of vertical segments 122v extending from the top surface 118t of the dielectric structure 118 to the bottom surface 118b of the dielectric structure 118. In some embodiments, the etch stop structure 122 may include a nitride (e.g., titanium nitride), tantalum (Ta), tungsten (W), or the like. In some embodiments, the etch stop structure 122 may be formed by the plurality of deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or the like). [ ]

[0049] As shown in the cross-sectional view 900 of FIG9, an initial opening 906 is formed within the dielectric structure 118. The initial opening 906 extends through the horizontal segment 122h of the etch stop structure 122, the first plurality of dielectric layers 114, the second plurality of dielectric layers 116, and the lower etch stop layer 112 to the top surface 110t of the lower conductive structure 110. In some embodiments, the initial opening 906 may be formed by exposing the dielectric structure 118 and the etch stop structure 122 to one or more etchants 904 according to the mask 902 during a dry etching process. In some embodiments, the one or more etchants 904 may include dry etchants (e.g., reactive ion etching (RIE) etchants), plasma etchants, or the like. In some embodiments, the one or more etchants 904 may have etching chemistry including one or more of fluorine (F), tetrafluoromethane (CF4), ozone (O2), or octafluorocyclobutane (C4F8), or the like. In some embodiments, the mask 902 may include a photosensitive material (e.g., photoresist), a rigid mask, or the like. [ ]

[0050] As shown in the cross-sectional view 1000 of FIG. 10, a wet etching process is performed on the dielectric structure 118 to extend the initial opening 906 in the dielectric structure 118 and form a trench 120 in the dielectric structure 118. In some embodiments, the trench 120 may be referred to as an opening, a capacitor opening, or the like. The wet etching process laterally etches the first plurality of dielectric layers 114 at a rate different from that of the second plurality of dielectric layers 116 to form the trench 120 having opposite sides with a serrated profile. The wet etching process forms a plurality of lateral protrusions 116a in the second plurality of dielectric layers 116, which have a plurality of side surfaces 116b, 116c. In some embodiments, a region of the first plurality of dielectric layers 114 within the inner sidewall 122is of the etch stop structure 122 is removed during the wet etching process to expose the plurality of side surfaces 116b, 116c of the lateral protrusions 116a. Along the inner sidewall 122is of the etch stop structure 122, each of the lateral protrusions 116a is perpendicularly spaced from each other by a plurality of gaps 114g. Each of the gaps 114g has a thickness or height defined by adjacent dielectric layers of a first plurality of dielectric layers 114 disposed along the corresponding outer sidewall 122os of the etch stop structure 122. In some embodiments, the trench 120 may have a generally rectangular shape when viewed from a top view. In other embodiments, the trench may have a generally circular shape, a generally square shape, or similar when viewed from a top view. [ ]

[0051] In some embodiments, a wet etching process may be performed by exposing the etch stop structure 122 and the dielectric structure 118 to one or more wet etchants 1004. In some embodiments, the one or more wet etchants 1004 may include hydrofluoric acid (e.g., liquid HF or gaseous HF), ammonium fluoride (NH4F), or the like. The wet etching process may be a buffered oxide etch (BOE), wherein the one or more wet etchants 1004 comprise a diluted hydrofluoric acid (HF) solution buffered with ammonium fluoride (NH4F). In various embodiments, the one or more wet etchants 1004 may selectively etch nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG) in a range of about 5:1, and may etch oxides, undoped silicate glass (USG), and phosphosilicate glass. The wet etching process is configured to etch a first plurality of dielectric layers 114 at a first etch rate and a second plurality of dielectric layers 116 at a second etch rate. In various embodiments, the first etch rate is greater than the second etch rate. For example, the first etch rate is at least 5 times greater than the second etch rate. In some embodiments, one or more wet etchants 1004 may be stopped on a metal nitride (e.g., titanium nitride), tantalum (Ta), tungsten (W), or the like to prevent over-etching in the lateral direction. In various embodiments, the etch stop structure 122 has a third etch rate during the wet etching process, which is substantially less than both the first and second etch rates. In some embodiments, the first etch rate is at least 35 times greater than the third etch rate, in the range of 35 to 100 times greater than the third etch rate, or some other suitable value. In a further embodiment, the second etch rate is at least 20 to 50 times greater than the third etch rate. [ ]

[0052] The etch stop structure 122 provides a boundary to prevent lateral over-etching of the first plurality of dielectric layers 114 and the second plurality of dielectric layers 116 in the region outside the outer sidewalls 122os of the etch stop structure 122. Therefore, the etch stop structure 122 mitigates or prevents problems caused by lateral over-etching by confining the wet etching process to the space between the inner sidewalls 122is of the etch stop structure 122, thereby increasing the uniformity of the trench 120 profile across the height of the trench 120. [ ]

[0053] As shown in the cross-sectional view 1100 of FIG11, a stack of capacitor layers 1102 is formed within trench 120 and covers etch stop structure 122. The stack of capacitor layers 1102 includes a diffusion barrier layer 124, a first conductive layer 126 disposed along the diffusion barrier layer 124, a capacitor dielectric layer 128 on the first conductive layer 126, and a second conductive layer 130 on the capacitor dielectric layer 128. The capacitor dielectric layer 128 separates the first conductive layer 126 from the second conductive layer 130. Each layer of the stack of capacitor layers 1102 conforms to the plurality of side surfaces 116b, 116c and the plurality of gaps 114g within the trench 120 defined by the vertical segment 122v. In some embodiments, the stack of capacitor layers 1102 seals the cavity 134 in the trench 120. In some embodiments, the diffusion barrier layer 124, the first conductive layer 126, the capacitor dielectric layer 128, and the second conductive layer 130 may have a thickness in the range of about 10 angstroms (Å) to 1000 Å or some other suitable value, and may be formed by a plurality of ALD processes, a plurality of PVD processes, a plurality of CVD processes, or similar processes. [ ]

[0054] As shown in the cross-sectional view 1200 of FIG12, a first passivation layer 136 and a second passivation layer 138a are formed on the stack of capacitor layers 1102. In some embodiments, the first passivation layer 136 may include silicon oxide and the second passivation layer 138a may include silicon nitride. In some embodiments, the first passivation layer 136 and the second passivation layer 138a may each be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or similar process).

[0055] As shown in the cross-sectional view 1300 of FIG13, an etching process is performed on a second conductive layer 130 stacked with a second passivation layer 138a, a first passivation layer 136, and a capacitor layer 1102. In some embodiments, one or more etchants 1304 may be used in a dry etching process to perform the etching process according to a mask 1302. In some embodiments, the one or more etchants 1304 may include dry etchants (e.g., reactive ion etching (RIE) etchants, plasma etchants, or the like). In some embodiments, the one or more etchants 1304 may have etching chemistry including one or more fluorine (F), tetrafluoromethane (CF4), ozone (O2), or octafluorocyclobutane (C4F8), or the like. In some embodiments, the mask 1302 may include a photosensitive material (e.g., photoresist), a rigid mask, or the like.

[0056] As shown in the cross-sectional view 1400 of FIG14, a third passivation layer 1402 and a fourth passivation layer 1404 are formed on the second passivation layer 138a. In some embodiments, the third passivation layer 1402 may comprise the same material as the first passivation layer 136 and the fourth passivation layer 1404 may comprise the same material as the second passivation layer 138a. In some embodiments, the third passivation layer 1402 and the fourth passivation layer 1404 may each be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or similar process).

[0057] As shown in the cross-sectional view 1500 of Figure 15, an etching process is performed on a stack of a fourth passivation layer (1404 in Figure 14), a third passivation layer (1402 in Figure 14), an etch stop structure 122, and at least a portion of a capacitor layer (1102 in Figure 14) to define a cover structure 140 and a capacitor structure 132. The cover structure 140 includes a first passivation layer 136, a second passivation layer 138a, and sidewall spacers 138b. In some embodiments, the etching process may be performed using one or more etchants 1502, which may include dry etchants (e.g., reactive ion etching (RIE) etchants, plasma etchants, or the like). In some embodiments, the one or more etchants 1502 may have etching chemistry including one or more fluorine (F), tetrafluoromethane (CF4), ozone (O2), or octafluorocyclobutane (C4F8) or the like. The etching process may, for example, be, a blanket etching process.

[0058] As shown in the cross-sectional view 1600 of FIG16, a first upper dielectric layer 144 is formed on the cover structure 140 and the dielectric structure 118. In some embodiments, the first upper dielectric layer 144 may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process or similar process).

[0059] As shown in the cross-sectional view 1700 of FIG17, an upper interconnect via 142 is formed within a first upper dielectric layer 144. The upper interconnect via 142 extends through the first upper dielectric layer 144 and the overlay structure 140 to contact the second conductive layer 130. In some embodiments, the upper interconnect via 142 may be formed by selectively etching the first upper dielectric layer 144 to define a trench within the first upper dielectric layer 144, forming a conductive material (e.g., copper, aluminum, etc.) within the trench, and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove excess conductive material from the first upper dielectric layer 144.

[0060] As shown in the cross-sectional view 1800 of FIG18, an upper etch stop layer 146 and a second upper dielectric layer 150 are formed on the first upper dielectric layer 144. In some embodiments, the upper etch stop layer 146 may be, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, or any combination thereof, or other suitable dielectric materials. The second upper dielectric layer 150 may be, for example, an oxide (e.g., silicon dioxide) or some other dielectric material. In some embodiments, the upper etch stop layer 146 and the second upper dielectric layer 150 may each be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, or similar processes).

[0061] As shown in the cross-sectional view 1900 of FIG19, an upper layer interconnect conductor 148 is formed within the second upper dielectric layer 150 and the upper etch stop layer 146 to contact the upper layer interconnect via 142. In some embodiments, the upper layer interconnect conductor 148 can be formed by selectively etching the upper etch stop layer 146 and the second upper dielectric layer 150 to define trenches within the upper etch stop layer 146 and the second upper dielectric layer 150, forming conductive material (e.g., copper, aluminum, etc.) within the trenches, and performing a planarization (CMP) process to remove excess conductive material above the second upper dielectric layer 150.

[0062] Figure 20 illustrates a flowchart of a method for forming an integrated wafer according to some embodiments, the integrated wafer having a capacitor structure disposed in a trench of a dielectric structure and an etch stop structure in the dielectric structure and surrounding the trench.

[0063] Although the disclosed method 2000 is illustrated and described herein as a series of actions or events, it should be understood that the order in which such actions or events are illustrated should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all illustrated actions are required to implement one or more of the states or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed as one or more separate actions and / or stages.

[0064] In step 2002, a dielectric structure is formed on a lower conductive structure covering the substrate. The dielectric structure includes a first plurality of dielectric layers and a second plurality of dielectric layers stacked alternately with the first plurality of dielectric layers. Figure 6 illustrates a cross-sectional view 600 corresponding to some embodiments of step 2002.

[0065] In step 2004, a first dry etching process is performed on the dielectric structure to form a pair of vertical openings in the dielectric structure. Figure 7 illustrates a cross-sectional view 700 corresponding to some embodiments of step 2004.

[0066] In step 2006, an etch stop structure is deposited in the vertical opening and on top of the dielectric structure. Figure 8 illustrates a cross-sectional view 800 corresponding to some embodiments of step 2006.

[0067] In step 2008, a second dry etching process is performed on the dielectric structure to form an initial opening in the dielectric structure between the inner sidewalls of the etch-stop structure. Figure 9 illustrates a cross-sectional view 900 corresponding to some embodiments of step 2008.

[0068] In step 2010, a wet etching process is performed on the dielectric structure to expand the initial opening and form the plurality of side surfaces in the dielectric structure, thereby defining trenches between the inner sidewalls of the etch-stop structure. Figure 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of step 2010.

[0069] In step 2012, a capacitor structure is formed within the trench and along the plurality of side surfaces. Figure 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of step 2012.

[0070] In step 2014, a cover structure and interconnect vias are formed on the capacitor structure. Figures 12 to 17 illustrate cross-sectional views 1200-1700 corresponding to some embodiments of step 2014.

[0071] Therefore, in some embodiments, this disclosure relates to an integrated wafer having a capacitor structure disposed in a trench of a dielectric structure and an etch stop structure in the dielectric structure and on the opposite side of the trench.

[0072] In some embodiments, this disclosure relates to an integrated wafer. The integrated wafer includes a dielectric structure disposed on a substrate, the dielectric structure having a first plurality of dielectric layers and a second plurality of dielectric layers stacked alternately with a first plurality of dielectric layers, the dielectric structure having a plurality of side surfaces that at least partially define a plurality of lateral recesses perpendicularly aligned with the first plurality of dielectric layers; a capacitor structure disposed on the plurality of side surfaces and having a first conductive layer, a second conductive layer, and a capacitor dielectric layer between the first and second conductive layers; and an etch-stop structure in the dielectric structure and extending perpendicularly from the top surface of the dielectric structure to a bottom dielectric layer in the first plurality of dielectric layers, the etch-stop structure laterally covering the capacitor structure and adjacent to the plurality of side surfaces.

[0073] In some embodiments, the capacitor structure extends continuously along the plurality of side surfaces to the sidewall of the etch stop structure.

[0074] In some embodiments, the second plurality of dielectric layers includes a plurality of lateral protrusions disposed on the sidewalls of the etch stop structure, wherein the plurality of side surfaces are the surfaces of the plurality of lateral protrusions, and wherein adjacent lateral protrusions among the plurality of lateral protrusions are vertically separated from each other by a vertical distance equal to or greater than the thickness of the corresponding dielectric layer in the first plurality of dielectric layers.

[0075] In some embodiments, in a cross-sectional view, the etch stop structure includes a pair of vertical segments disposed on opposite sides of the capacitor structure, and in a top view, the etch stop structure is annular and extends around the outer perimeter of the capacitor structure.

[0076] In some embodiments, the lateral thickness of a particular vertical segment in the pair of vertical segments is greater than the thickness of the first conductive layer and the thickness of the second conductive layer.

[0077] In some embodiments, the etch stop structure is coupled to the first conductive layer.

[0078] In some embodiments, the etch stop structure includes titanium nitride, tungsten, or tantalum.

[0079] In some embodiments, in a cross-sectional view, the etch stop structure includes a pair of horizontal segments disposed on opposite sides of the vertical segment of the capacitor structure, wherein the pair of horizontal segments cover the dielectric structure and the lower segment of the capacitor structure within the dielectric structure.

[0080] In other embodiments, this disclosure relates to a method of forming an integrated wafer. The method includes forming a first conductive structure on a substrate; forming a dielectric structure on the first conductive structure, the dielectric structure having a first plurality of dielectric layers stacked alternately with a second plurality of dielectric layers; forming an etch stop structure in the dielectric structure, the etch stop structure having opposing inner sidewalls disposed on opposite sides of an inner segment of the dielectric structure, the etch stop structure separating the inner segment from an outer segment of the dielectric structure; performing an etching process on the dielectric structure to form a trench in the inner segment of the dielectric structure; and forming a capacitor structure in the trench, the capacitor structure having the plurality of protrusions extending laterally from a central region of the trench to individual sidewalls of the opposing inner sidewalls of the etch stop structure.

[0081] In some embodiments, the etching process defines a plurality of surfaces in the second plurality of dielectric layers that extend from the middle region of the trench to the etch stop structure.

[0082] In some embodiments, the etching process removes the inner regions of the first plurality of dielectric layers from the inner segments of the dielectric structure.

[0083] In some embodiments, the etch stop structure includes opposing outer walls in the dielectric structure, and wherein the outer regions of the first plurality of dielectric layers contact the opposing outer walls of the etch stop structure.

[0084] In some embodiments, the height of the capacitor structure is greater than the height of the etch stop structure.

[0085] In some embodiments, the method further includes forming a cover structure over the capacitor structure, wherein the cover structure includes a passivation layer over the capacitor structure and a pair of sidewall spacers on opposite sides of the passivation layer.

[0086] In some embodiments, the method further includes: forming an upper dielectric layer over the capacitor structure; and forming a second conductive structure within the upper dielectric layer, wherein the second conductive structure is coupled to the capacitor structure.

[0087] In some other embodiments, this disclosure relates to a method of forming an integrated wafer. The method includes forming a first conductive structure on a substrate; forming a dielectric structure on the first conductive structure, the dielectric structure having a first plurality of dielectric layers of the first material interleaved between a second plurality of dielectric layers of a second material having a material different from the first material; performing a first etching process on the dielectric structure to form a pair of first openings in the dielectric structure and on opposite sides of the first conductive structure; forming an etch stop structure in the pair of first openings; performing a second etching process on the dielectric structure to form second openings between opposite sidewalls of the etch stop structures and on the first conductive structure; performing a third etching process on the dielectric structure to extend the second openings and form a plurality of side surfaces in the second plurality of dielectric layers that at least partially define trenches, the plurality of side surfaces being stacked perpendicularly to each other and adjacent to the etch stop structures; and forming a first conductive layer, a capacitor dielectric layer, and a second conductive layer in the trenches and along the plurality of side surfaces.

[0088] In some embodiments, during the third etching process, the first plurality of dielectric layers have a greater etching rate than the second plurality of dielectric layers.

[0089] In some embodiments, during the third etching process, the second plurality of dielectric layers have a greater etching rate than the etch-stop structure.

[0090] In some embodiments, the second etching process includes dry etching and the third etching process includes wet etching.

[0091] In some embodiments, the plurality of side surfaces define a plurality of protrusions within the second plurality of dielectric layers, which extend from the etch stop structure toward the central region of the trench.

[0092] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0093] 100, 1000, 1100, 1500, 1600, 1700, 1800, 1900, 300a, 300b, 300c, 400, 500, 600, 700, 800, 900: Sectional Views 102:Substrate 102a, 110at, 110bt, 110t, 118t: Top surface 104: Transistor 106: First through hole 108, 502: Lower layer interlayer dielectric structure 110, 110a, 110b: Lower conductive structure 110b: Second lower conductive structure 112: Lower Etching Stop Layer 114: First Multiple Dielectric Layers 114a: First dielectric layer 114b: Second dielectric layer 114g: gap 114g1: First gap 114g2: Second gap 114t, 116t: Thickness 115: Lateral concave portion 116: Second Multiple Dielectric Layers 116a: Lateral protrusion 116b, 116c: Side surfaces 116d: Inner wall 118: Dielectric Structure 118b: Bottom surface 120: Trench 120a: First trench 120b: Second trench 122: Etching Stop Structure 122a: First etch stop structure 122b: Second etch stop structure 122h: Horizontal section 122is: Inner wall 122os, 132s: Lateral wall 122v: Vertical segment 124: Diffusion barrier layer 126: First conductive layer 128: Capacitor dielectric layer 128o: bias 130: Second conductive layer 132: Capacitor Structure 132a: First capacitor structure 132b: Second capacitor structure 134: Cavity 134c: Center 136: First passivation layer 138a: Second passivation layer 138b: Sidewall spacer 140: Covering Structure 142: Upper layer internal connection through hole 142a: First upper layer internal interconnection via 142b: Second upper layer internal interconnection via 144: First upper dielectric layer 146: Upper Etching Stop Layer 148, 148a, 148b: Upper layer internal connection wires 150: Second upper dielectric layer 200a, 200b: Top view 305: Vertical opening 310a: Internal wiring through hole 310b: Internal wiring conductor 312: Etching Stop Layer 314d, 322: Distance 402: Width 404: Second width 406: Height of the first sidewall 408: Height of the second sidewall 504: Image Sensing Device 506g: Transmission transistor gate structure 506g, 510g, 512g, 514g: Gate structure 508: Floating Diffusion Well 510: Capacitor Switching Transistor 510, 512, 514: Transistors 512: Source follower transistor 512g: Source follower transistor gate structure 514: Column Select Transistor 516: Interlayer dielectric etch stop layer 518: Conductive Contacts 520: Internal wiring conductor 522: Internal wiring through hole 524: Isolation Structure 704, 904, 1004, 1304, 1502: Etching agents 906: Initial opening 1102: Capacitor Layer 1302, 702, 902: Curtain 1402: Third passivation layer 1404: Fourth passivation layer 2000: Method 2002, 2004, 2006, 2008, 2010, 2012, 2014: Steps

Claims

1. An integrated chip, comprising: A dielectric structure disposed above a substrate, wherein the dielectric structure includes a first plurality of dielectric layers and a second plurality of dielectric layers stacked alternately with the first plurality of dielectric layers, wherein the dielectric structure includes a plurality of side surfaces, the side surfaces at least partially defining a plurality of lateral recesses perpendicularly aligned with the first plurality of dielectric layers; a capacitor structure disposed on the plurality of side surfaces and including a first conductive layer, a second conductive layer, and a capacitor dielectric layer between the first conductive layer and the second conductive layer. And an etch stop structure disposed in the dielectric structure and extending vertically from the top surface of the dielectric structure to the bottom dielectric layer of the first plurality of dielectric layers, wherein the etch stop structure laterally covers the capacitor structure and is adjacent to the plurality of side surfaces.

2. The integrated wafer as claimed in claim 1, wherein the second plurality of dielectric layers includes a plurality of lateral protrusions disposed on the sidewalls of the etch stop structure, wherein the plurality of side surfaces are surfaces of the plurality of lateral protrusions, and wherein adjacent lateral protrusions among the plurality of lateral protrusions are vertically separated from each other by a vertical distance equal to or greater than the thickness of the corresponding dielectric layer in the first plurality of dielectric layers.

3. The integrated wafer as claimed in claim 1, wherein, in a cross-sectional view, the etch stop structure includes a pair of vertical segments disposed on opposite sides of the capacitor structure, and in a top view, the etch stop structure is annular and extends around the outer perimeter of the capacitor structure.

4. A method for forming an integrated wafer, comprising: A first conductive structure is formed above the substrate; A dielectric structure is formed over the first conductive structure, wherein the dielectric structure comprises alternating stacks of a first plurality of dielectric layers and a second plurality of dielectric layers; an etch stop structure is formed in the dielectric structure, wherein the etch stop structure comprises opposing inner sidewalls disposed on opposite sides of an inner segment of the dielectric structure, wherein the etch stop structure separates the inner segment from an outer segment of the dielectric structure; an etching process is performed on the dielectric structure to form a trench in the inner segment of the dielectric structure; and a capacitor structure is formed in the trench, wherein the capacitor structure comprises a plurality of protrusions extending laterally from a central region of the trench to individual sidewalls of the opposing inner sidewalls of the etch stop structure.

5. The method of claim 4, wherein the etching process removes the inner regions of the first plurality of dielectric layers from the inner segments of the dielectric structure.

6. The method as described in claim 4, wherein the height of the capacitor structure is greater than the height of the etch stop structure.

7. A method for forming an integrated wafer, comprising: A first conductive structure is formed above the substrate; A dielectric structure is formed over a first conductive structure, wherein the dielectric structure includes a first plurality of dielectric layers having a first material, interleaved between a second plurality of dielectric layers having a second material different from the first material; a first etching process is performed on the dielectric structure to form a pair of first openings in the dielectric structure and on opposite sides of the first conductive structure; an etch stop structure is formed within the pair of first openings; a second etching process is performed on the dielectric structure to form second openings between opposite sidewalls of the etch stop structures and over the first conductive structure; a third etching process is performed on the dielectric structure to enlarge the second openings and form a plurality of side surfaces within the second plurality of dielectric layers, which at least partially define trenches, wherein the plurality of side surfaces are stacked perpendicularly to each other and adjacent to the etch stop structures; and a first conductive layer, a capacitor dielectric layer, and a second conductive layer are formed within the trenches and along the plurality of side surfaces.

8. The method of claim 7, wherein during the third etching process, the first plurality of dielectric layers have a greater etching rate than the second plurality of dielectric layers.

9. The method of claim 8, wherein during the third etching process, the second plurality of dielectric layers have an etch rate greater than that of the etch stop structure.

10. The method of claim 7, wherein the second etching process comprises dry etching and the third etching process comprises wet etching.

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