Embedded multimedia card host device and loopback test method thereof

Abstract

The embedded multimedia card host device includes: a feedback test control circuit that generates a first pseudo-random sequence data and a data selection signal corresponding to a first transmission mode, and verifies the feedback test data according to a third clock signal to generate a flag signal; a transmitter circuit that samples the above two according to a transmit clock signal to output a second pseudo-random sequence data and a first clock signal; a receiver circuit that receives the above two via an input / output interface and outputs a third pseudo-random sequence data and a second clock signal; a delay phase-locked loop that outputs the second clock signal as a receive clock signal; a demultiplexer that processes the third pseudo-random sequence data according to the receive clock signal to generate feedback test data; and a delay circuit that delays the receive clock signal to generate the third clock signal.

Description

Technical Field

[0001] This case relates to an embedded multimedia card host device, and in particular to an embedded multimedia card host device capable of performing feedback tests without using a phase correction mechanism, and its feedback test method. Prior Technology

[0002] Existing testing methods for embedded multimedia card devices largely rely on external embedded multimedia cards or software operations for data transmission testing, and require procedures such as clock phase correction to obtain stable data reception timing. However, such testing methods are not only cumbersome but also increase testing costs and time. Furthermore, existing loopback tests mostly depend on physical devices, making it difficult to complete the functional verification of the transmission and reception channels solely through the embedded multimedia card device. Therefore, providing a loopback testing mechanism that does not require a physical card and does not involve software operations such as phase correction has become a pressing technical challenge. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention, but not limited to, is to provide an embedded multimedia card host device and its feedback testing method that can perform feedback testing without using a phase correction mechanism, thereby improving the problems of the prior art.

[0004] In some embodiments, the embedded multimedia card host device includes a loopback test control circuit, a transmitter circuit, a receiver circuit, a delay phase-locked loop, a demultiplexer, and a delay circuit. In a loopback test mode, the loopback test control circuit generates a first pseudo-random sequence data and a first data selection signal corresponding to a first transmission mode. In this loopback test mode, the transmitter circuit samples the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and samples the first data selection signal according to the transmit clock signal to output a first clock signal. In this loopback test mode, the receiver circuit receives the second pseudo-random sequence data and the first clock signal from the transmitter circuit via an input / output interface, outputs the second pseudo-random sequence data as a third pseudo-random sequence data, and outputs the first clock signal as a second clock signal. In this feedback test mode, the delay-locked loop (PLL) outputs the second clock signal as a receive clock signal using a bypass mechanism. In a second transmission mode, the PLL delays an external data selection signal from an external device to generate the receive clock signal. In this feedback test mode, the demultiplexer processes the third pseudo-random sequence data based on the receive clock signal to generate feedback test data. In this feedback test mode, the delay circuit delays the receive clock signal to generate a third clock signal. In this feedback test mode, the feedback test control circuit further verifies the feedback test data based on the third clock signal to generate a flag signal indicating a feedback test result.

[0005] In some embodiments, a loopback test method is performed by an embedded multimedia card host device. The loopback test method includes: in a loopback test mode, generating a first pseudo-random sequence data and a first data selection signal corresponding to a first transmission mode; in the loopback test mode, sampling the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and sampling the first data selection signal according to the transmit clock signal to output a first clock signal; in the loopback test mode, receiving the second pseudo-random sequence data and the first clock signal via an input / output interface, outputting the second pseudo-random sequence data as a third pseudo-random sequence data, and outputting the first clock signal as a second clock signal. In the loopback test mode, the second clock signal is output as a receive clock signal via a delay-locked loop (PLL) in the embedded multimedia card host device using a bypass mechanism. The PLL in a second transmission mode delays an external data selection signal from an external device to generate the receive clock signal. In the loopback test mode, the third pseudo-random sequence data is processed according to the receive clock signal to generate loopback test data. In the loopback test mode, the receive clock signal is delayed to generate a third clock signal. And in the loopback test mode, the loopback test data is verified according to the third clock signal to generate a flag signal indicating a loopback test result.

[0006] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0007] [Figure 1] is a schematic diagram of an embedded multimedia card host device according to some embodiments of this case; [Figure 2A] is a schematic diagram showing the received data waveform, received clock signal, and output data waveform of the embedded multimedia card host device in Figure 1 in HS200 mode according to some embodiments of this case; [Figure 2B] is a schematic diagram showing the received data waveform, received clock signal, and output data waveform of the embedded multimedia card host device in Figure 1 in HS400 mode according to some embodiments of this case; [Figure 3] is a waveform diagram of the sampling timing used by the embedded multimedia card host device in some embodiments of this case under the feedback test; [Figure 4] is a schematic diagram of an embedded multimedia card host device according to some embodiments of this case; [Figure 5] is an operational waveform diagram of the embedded multimedia card host device of Figure 4 in loopback test mode, according to some embodiments of this case; [Figure 6] is a waveform diagram showing the operation of the embedded multimedia card host device of Figure 4 in loopback test mode according to some embodiments of this case; and [Figure 7] is a flowchart of a feedback test method according to some embodiments of this case. Implementation

[0008] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0009] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0010] Figure 1 is a schematic diagram of an embedded Multimedia Card (eMMC) host device 100 according to some embodiments of the present invention. The eMMC host device 100 includes a phase-locked loop 110, a delay phase-locked loop 120, a transmitter circuit 130, an input / output interface 140, and a receiver circuit 150.

[0011] Phase-locked loop 110 provides a transmit clock signal TXCK and a receive clock signal RXCK1 corresponding to a first transmission mode. Delayed phase-locked loop 120 corrects for the clock signal CKR provided by phase-locked loop 110 and generates a receive clock signal RXCK2 corresponding to a second transmission mode. In some embodiments, the data rate of the first transmission mode is lower than the data rate of the second transmission mode. For example, the first transmission mode may be an HS200 mode, and the second transmission mode may be an HS400 mode, wherein the data rate of the HS200 mode is approximately half that of the HS400 mode.

[0012] The transmitter circuit 130 has multiple channels, which sequentially correspond to multiple bits DIN1[0]~DIN1

[11] of the input data DIN1 and multiple bits DIN0[0]~DIN0

[11] of the input data DIN0. For example, the transmitter circuit 130 includes multiple transmitters 131[0]~131

[11] , which correspond to multiple channels respectively. Transmitter 131[0] receives bits DIN1[0] of the input data DIN1 and bits DIN0[0] of the input data DIN0 according to the transmit clock signal TXCK. Transmitter 131[1] receives bits DIN1[1] of the input data DIN1 and bits DIN0[1] of the input data DIN0 according to the transmit clock signal TXCK. Similarly, it should be understood that transmitter 131

[11] receives bits DIN1

[11] of the input data DIN1 and bits DIN0

[11] of the input data DIN0 according to the transmit clock signal TXCK.

[0013] The eMMC host device 100 can be coupled to an external device 101 via an input / output interface 140. The input / output interface 140 includes multiple signal pads IO[0] to IO

[11] , which correspond to the aforementioned multiple channels. For example, signal pad IO[0] is coupled to transmitter 131[0] to receive bits DIN1[0] and DIN0[0] sampled by transmitter 131[0] and transmit these two bits to external device 101. Signal pad IO[1] is coupled to transmitter 131[1] to receive bits DIN1[1] and DIN0[1] sampled by transmitter 131[1] and transmit these two bits to external device 101. Similarly, it should be understood that the signal pad IO

[11] is coupled to the transmitter 131

[11] to receive the bits DIN1

[11] and DIN0

[11] sampled by the transmitter 131

[11] , and transmit these two bits to the external device 101. Alternatively, the external device 101 may send data to the receiver circuit 150 via multiple signal pads IO[0]~IO

[11] .

[0014] In some embodiments, multiple bits DIN0[0]~DIN0[7] and multiple bits DIN1[0]~DIN1[7] are valid data, bits DIN0[8] and DIN1[8] are data strobe signals, bits DIN0[9] and DIN1[9] are command data, bits DIN0

[10] and DIN1

[10] are clock signals, and bits DIN0

[11] and DIN1

[11] are reset signals. In practical applications, multiple bits DIN0[0]~DIN0[7], multiple bits DIN1[0]~DIN1[7] and multiple bits DIN0[9] and DIN1[9] are the main data for the interaction between the eMMC host device 100 and the external device 101, and its data rate can be up to 400 megabits per second (MB / s) (i.e., the data rate of the aforementioned HS400 mode). The data selection communication number defined by bits DIN0[8] and DIN1[8] and the clock signal defined by bits DIN0

[10] and DIN1

[10] are sampling clock signals that the eMMC host device 100 and the external device 101 can provide to each other. For example, the eMMC host device 100 provides a sampling clock signal to the external device 101 via bits DIN0

[10] and DIN1

[10] , so that the external device 101 can receive data or commands from the eMMC host device 100 according to this sampling clock signal. Similarly, the eMMC host device 100 can receive data from the external device 101 in the second transmission mode according to the external data selection communication number DSO transmitted by the external device 101 via the signal pad IO[8].

[0015] Similarly, receiver circuit 150 has multiple channels, which sequentially correspond to multiple signal pads IO[0] to IO

[11] . For example, receiver circuit 150 includes multiple receivers 151[0] to 151

[11] and multiple demultiplexers 152[0] to 152

[11] . Receiver 151[0] receives data provided by external device 101 from signal pad IO[0] and transmits the received data to demultiplexer 152[0]. Receiver 151[1] receives data provided by external device 101 from signal pad IO[1] and transmits the received data to demultiplexer 152[1]. And so on, it can be seen that receiver 151

[11] receives data provided by external device 101 from signal pad IO

[11] and transmits the received data to demultiplexer 152

[11] .

[0016] In the first transmission mode, demultiplexer 152[0] processes the data transmitted from receiver 151[0] according to the received clock signal RXCK1 (for example, deserializing it) to generate bits DO0[0] of output data DO0 and bits DO1[0] of output data DO1. In the first transmission mode, demultiplexer 152[1] processes the data transmitted from receiver 151[1] according to the received clock signal RXCK1 to generate bits DO0[1] of output data DO0 and bits DO1[1] of output data DO1. Similarly, in the first transmission mode, demultiplexer 152

[11] processes the data transmitted from receiver 151

[11] according to the received clock signal RXCK1 to generate bits DO0

[11] of output data DO0 and bits DO1

[11] of output data DO1. Receiver 151[8] can receive the external data selection signal DSO from external device 101 via signal pad IO[8] and transmit the external data selection signal DSO to delay phase-locked loop 120. Delay phase-locked loop 120 can delay the external data selection signal DSO to generate a receive clock signal RXCK2 corresponding to the second transmission mode. Thus, in the second transmission mode, multiple demultiplexers 152[0]~151

[11] can process the data received by multiple receivers 151[0]~151

[11] according to the receive clock signal RXCK2 to generate multiple bits of output data DO0[0]~DO0

[11] and multiple bits of output data DO1[0]~DO1

[11] .

[0017] In other words, when operating in the first transmission mode, the receiver circuit 150 mainly processes the received data based on the received clock signal RXCK1, which is generated by the phase-locked loop 110. Conversely, when operating in the second transmission mode, the receiver circuit 150 mainly processes the received data based on the received clock signal RXCK2, which is generated based on the external data selection signal DSO received from the external device 101 by the signal pad IO [8].

[0018] Figure 2A is a schematic diagram showing the received data waveform, received clock signal RXCK1, and output data waveform of the eMMC host device 100 in Figure 1 in HS200 mode according to some embodiments of this case. The received data waveform 201 may be the waveform of the data sent by the external device 101 to multiple signal pads IO[0]~IO

[11] . The output data waveform 202 may be the waveform of the output data DO0 read by the eMMC host device 100 according to the received clock signal RXCK1.

[0019] As mentioned earlier, in HS200 mode, the received clock signal RXCK1 is generated by the phase-locked loop 110. Since the phase difference between the received clock signal RXCK1 and the data transmitted by the external device 101 is unknown, the eMMC host device 100 can adjust the phase of the received clock signal RXCK1 through a certain training procedure, aligning the rising edge of the received clock signal RXCK1 with the middle of each data point (e.g., data D0 and data D1) in the received data waveform 201. This ensures that the receiver circuit 150 can correctly sample data D0 and data D1. Thus, the receiver circuit 150 can output data D0 and data D1 as output data DO0. In HS200 mode, the frequency of the received clock signal RXCK1 is 200 MHz, and the data rate of the received data waveform 201 is 200 Mb / s.

[0020] Figure 2B is a schematic diagram illustrating the received data waveform, received clock signal RXCK2, and output data waveform of the eMMC host device 100 in Figure 1 in HS400 mode according to some embodiments of this case. In this example, output data waveform 202 can be the waveform of output data DO0 read by the eMMC host device 100 according to the received clock signal RXCK2, and output data waveform 203 can be the waveform of output data DO1 read by the eMMC host device 100 according to the received clock signal RXCK2. In HS400 mode, the frequency of the received clock signal RXCK2 is 200MHz, while the data rate of the received data waveform 201 is increased to 400Mb / s.

[0021] As mentioned earlier, in HS400 mode, receiver circuit 150 primarily processes the received data based on the received clock signal RXCK2. Delayed phase-locked loop 120 corrects the received clock signal RXCK2, ensuring that the rising and falling edges of RXCK2 are aligned with the middle of data D0 and data D1 in data waveform 201. This guarantees that receiver circuit 150 can correctly sample data D0 and data D1. Thus, receiver circuit 150 can output data D0 and data D1 as output data DO0.

[0022] Figure 3 shows the waveform of the sampling timing used by the eMMC host device in some embodiments of this invention under loopback testing. Based on the first transmission mode (e.g., HS200 mode) and the second transmission mode (e.g., HS400 mode) described above, some embodiments of this invention propose an eMMC host device (e.g., eMMC host device 400 in Figure 4) that combines the data rate of the input data in the first transmission mode with the generation path of the sampling clock signal (e.g., the receive clock signal RXCK2) in the second transmission mode to perform a loopback test in a loopback test mode, thereby verifying whether the internal transceiver functions of the eMMC host device are correct.

[0023] As mentioned earlier, in the aforementioned HS200 mode, the data rate of input data DIN0 (or input data DIN1) is set to 200MHz. The eMMC host device can utilize the sampling clock signal generation path in HS400 mode to configure a corresponding data selection signal DS1 (as shown in Figure 4), and set the delay phase-locked loop 120 to a bypass mode to process the data selection signal DS1 using a bypass mechanism, i.e., without performing additional delay processing or phase correction on the data selection signal DS1. For example, in this bypass mode, the delay phase-locked loop 120 can directly output the data selection signal DS1 as the aforementioned receive clock signal RXCK2. In this way, the rising edge of the clock signal can be naturally aligned to the middle of each data entry in input data DIN0 (or input data DIN1) for correct sampling. Detailed operation and setting methods will be explained later.

[0024] Figure 4 is a schematic diagram of an eMMC host device 400 according to some embodiments of this case. The eMMC host device 400 includes a feedback test control circuit 405, a phase-locked loop 410, a delay phase-locked loop 420, a transmitter circuit 430, an input / output interface 440, a receiver circuit 450, a demultiplexer 460, and a delay circuit 470.

[0025] In the feedback test mode, the feedback test control circuit 405 generates pseudo-random sequence data PT1 and data selection signal DS1 corresponding to the first transmission mode, and outputs the pseudo-random sequence data PT1 as input data DIN0 and input data DIN1 respectively. That is, in this example, each of the input data DIN0 and input data DIN1 is the same as the pseudo-random sequence data PT1. In some embodiments, the pseudo-random sequence data PT1 may be, but is not limited to, pseudo-random binary sequence (PRBS) data.

[0026] Phase-locked loop 410 corresponds to phase-locked loop 110 in Figure 1 and can be used to generate the transmit clock signal TXCK. Transmitter circuit 430 corresponds to transmitter circuit 130 in Figure 1, and in the feedback test mode, it samples pseudo-random sequence data PT1 according to the transmit clock signal TXCK to output pseudo-random sequence data PT2, and selects communication signal DS1 according to the sampled data of the transmit clock signal TXCK to output clock signal CK1.

[0027] For ease of explanation and simplification, Figure 4 only shows the circuit part related to the feedback test mode. For detailed overall settings, please refer to the system architecture of Figure 1. In some embodiments, the transmitter circuit 430 includes a transmitter group 431 and a transmitter 431[8], and the transmitter group 431 corresponds to the plurality of transmitters 131[0]~131[7] and 131[9] in Figure 1. Multiple transmitters (not shown) in transmitter group 431 can sample a pseudo-random sequence PT1 based on the transmit clock signal TXCK (i.e., multiple bits DIN0[0]~DIN0[7] and DIN0[9] (labeled as DIN0[9, 7:0]) in input data DIN0 and multiple bits DIN1[0]~DIN1[7] and DIN1[9] (labeled as DIN1[9, 7:0]) in input data DIN1), and output the sampled data value as a pseudo-random sequence PT2 to input / output interface 440. In the feedback test mode, transmitter 431[8] selects a communication signal DS1 based on the data sampled by the transmit clock signal TXCK to output clock signal CK1. Similarly, input / output interface 440 includes signal pad group 441 and signal pad IO[8], wherein signal pad group 441 corresponds to multiple signal pads IO[0]~IO[7] and IO[9] in FIG1.

[0028] In some embodiments, the loopback test control circuit 405 sets a first specific bit and a second specific bit to complementary first and second logic values ​​in loopback test mode to generate a data select signal DS1, wherein the first and second specific bits are signal pads in the input / output interface 440 for receiving external data select signals from the external device 101. For example, in loopback test mode, the loopback test control circuit 405 may set bit DIN0[8] to logic value 0 and bit DIN1[8] to logic value 1 to generate data select signal DS1. As previously described, bits DIN0[8] and DIN1[8] are signal pads IO[8] in the input / output interface 440, which are used to receive external data select signals DS0 from the external device 101.

[0029] In the feedback test mode, receiver circuit 450 receives pseudo-random sequence data PT2 and clock signal CK1 via input / output interface 440. For example, receiver circuit 450 may include receiver group 451 and receiver 451[8], wherein receiver group 451 corresponds to multiple receivers 151[0]~151[7] and 151[9] in FIG1, which can receive pseudo-random sequence data PT2 and output it as pseudo-random sequence data PT3, and receiver 451[8] can receive clock signal CK1 and output it as clock signal CK2. Delay phase-locked loop 420 corresponds to delay phase-locked loop 120 in FIG1, and outputs clock signal CK2 as received clock signal RXCK2 in the feedback test mode. That is, in the feedback test mode, the delay phase-locked loop 420 can be configured as a bypass mode, and the clock signal CK2 is output as the received clock signal RXCK2 by the bypass mechanism, that is, the clock signal CK2 is directly output as the received clock signal RXCK2 without adjusting the clock signal CK2. The demultiplexer 460 processes the pseudo-random sequence data PT3 according to the received clock signal RXCK2 in the feedback test mode (for example, to deserialize the pseudo-random sequence data PT3) to generate feedback test data (for example, multiple bits DO0[0]~DO0[7] and DO0[9] in the output data DO0; labeled as DO0[9, 7:0]). The delay circuit 470 can delay the received clock signal RXCK2 in the feedback test mode to generate the clock signal CK3.

[0030] Thus, in the loopback test mode, the loopback test control circuit 405 can verify the loopback test data DO0[9, 7:0] according to the clock signal CK3 to generate a flag signal SF that can be used to indicate the loopback test result. In some embodiments, the loopback test control circuit 405 can confirm whether at least a portion of the bits in the loopback test data DO0[9, 7:0] conforms to a pseudo-random sequence according to the clock signal CK3 to verify the loopback test data DO0[9, 7:0]. In other embodiments, the loopback test control circuit 405 can confirm whether the loopback test data DO0[9, 7:0] is the same as the pseudo-random sequence data PT1 according to the clock signal CK3 to verify the loopback test data DO0[9, 7:0]. In some embodiments, the loopback test control circuit 405 can be implemented by multiple digital circuits, wherein the timing of the digital circuit portion (e.g., data verification circuit 405C) used to verify the loopback test data DO0[9, 7:0] can be set by the clock signal CK3.

[0031] For example, if the feedback test control circuit 405 confirms that the feedback test data DO0[9, 7:0] is not pseudo-random sequence data or is different from the pseudo-random sequence data PT1, it means that the received feedback test data DO0[9, 7:0] contains an error. Under this condition, the feedback test control circuit 405 can generate a flag signal SF with a logic value of 0 to indicate that the feedback test result is failed. Alternatively, if the feedback test control circuit 405 confirms that the feedback test data DO0[9, 7:0] is pseudo-random sequence data or is the same as the pseudo-random sequence data PT1, it means that the received feedback test data DO0[9, 7:0] is correct. Under this condition, the feedback test control circuit 405 can generate a flag signal SF with a logic value of 1 to indicate that the feedback test result is passed.

[0032] In some embodiments, the feedback test control circuit 405 includes a clock generation circuit 405A, a test data generation circuit 405B, and a data verification circuit 405C. The clock generation circuit 405A generates a data selection signal DS1 in feedback test mode (e.g., setting bits DIN0[8] and DIN1[8] to logic values ​​0 and 1, respectively). The test data generation circuit 405B generates pseudo-random sequence data PT1 in feedback test mode. In some embodiments, the test data generation circuit 405B may be implemented by a pseudo-random sequence generator circuit. The data verification circuit 405C verifies the feedback test data DO0[9, 7:0] according to the clock signal CK3 in feedback test mode to generate a flag signal SF. In some embodiments, the data verification circuit 405C may be implemented by a pseudo-random sequence detector circuit.

[0033] In some embodiments, in loopback test mode, the eMMC host device 400 can generate a sufficient number (e.g., but not limited to, 50) of pseudo-random sequence data PT1 via the aforementioned multiple circuits, and collect a corresponding number of loopback test data DO0[9, 7:0] accordingly, and generate a flag signal SF from the corresponding number of loopback test data DO0[9, 7:0], thereby obtaining loopback test results with higher reliability.

[0034] In some embodiments, the pseudo-random sequence data PT1 may be a PRBS7 sequence, which may sequentially include a pattern sign, a PRBS7 sequence, and a pattern end. The pattern sign may be low-speed identification data, the PRBS7 sequence may be a high-speed (e.g., 200 Mbps) PRBS7 sequence body, and the pattern end bit is a logical value of 0. The above configuration of the pseudo-random sequence data PT1 is merely an example, and this application is not limited thereto.

[0035] Figure 5 is an operational waveform diagram of the eMMC host device of Figure 4 in loopback test mode according to some embodiments of this case. The input / output interface 440 may include multiple channels corresponding to multiple signal pads IO[0] to IO

[11] , and the receiver circuit 450 may receive pseudo-random sequence data PT1 via multiple channels corresponding to multiple signal pads IO[0] to IO[7] and IO[9]. In some embodiments, the transmitter circuit 430 transmits pseudo-random sequence data PT2 to the receiver circuit 450 simultaneously via all channels corresponding to multiple signal pads IO[0] to IO[7] and IO[9] in loopback test mode. For example, as shown in Figure 5, multiple bits of input data DIN1[9, 7:0] and multiple bits of input data DIN0[9, 7:0] are set as multiple bits in pseudo-random sequence data PT1, such that multiple bits DIN1[9, 7:0] and multiple bits DIN0[9, 7:0] have multiple data values ​​P, R, B, S, 7 and PT of pseudo-random sequence data PT1. By sampling by transmitter circuit 430, the signals on multiple signal pads IO[0]~IO[7] and IO[9] are also sequentially multiple data values ​​P, R, B, S, 7 and PT. In this way, transmitter circuit 430 can simultaneously transmit pseudo-random sequence data PT2 to receiver circuit 450 through all channels corresponding to multiple signal pads IO[0]~IO[7] and IO[9].

[0036] Furthermore, as shown in Figure 5, the feedback test control circuit 405 can set bit DIN1[8] to logic value 1 and bit DIN0[8] to logic value 0, thereby defining the data selection communication number DS1. By alternately sampling bit DIN0[8] and bit DIN1[8] (the sampling result is equivalent to the data selection communication number DS1), the transmitter circuit 430 can generate a clock signal CK1 to the signal pad IO[8], and the phase of the clock signal CK1 is opposite to the phase of the transmitted clock signal TXCK. Thus, it can be seen that the rising edge of the clock signal CK1 can naturally align with the middle of the multiple data values ​​P, R, B, S, 7 and PT of the pseudo-random sequence data PT2.

[0037] Similarly, receiver circuit 450 can receive pseudo-random sequence data PT2 and output pseudo-random sequence data PT3 (its transmission delay is negligible, so its timing relationship can be the same as that of pseudo-random sequence data PT2). On the other hand, receiver circuit 450 can receive clock signal CK1 and output clock signal CK2. Delayed phase-locked loop 420 can operate in bypass mode and directly output clock signal CK2 as received clock signal RXCK2, so that demultiplexer 460 can deserialize pseudo-random sequence data PT3 according to received clock signal RXCK2 to generate feedback test data DO0 [9, 7:0]. On the other hand, delay circuit 470 can delay received clock signal RXCK2 to generate clock signal CK3. In this way, feedback test control circuit 405 can verify feedback test data DO0 [9, 7:0] according to clock signal CK3, thereby generating flag signal SF. In this example, the feedback test control circuit 405 confirms that the feedback test data DO0[9, 7:0] conforms to the pseudo-random sequence or is the same as the pseudo-random sequence data PT1, and therefore generates a flag signal SF with a logic value of 1, thereby indicating that the feedback test result is passed.

[0038] The above-described test involves simultaneous feedback testing across multiple channels to quickly confirm whether the transmit and receive functions between the multiple channels are operating correctly. In other embodiments, the eMMC host device 400 may also perform feedback testing channel by channel to more accurately identify transmission channels that may have errors.

[0039] Figure 6 is an operational waveform diagram of the eMMC host device of Figure 4 in loopback test mode according to some embodiments of this case. In some embodiments, the transmitter circuit 430 transmits pseudo-random sequence data PT2 to the receiver circuit 450 sequentially via one of a plurality of channels corresponding to a plurality of signal pads IO[0]~IO[7] and IO[9] in loopback test mode. For example, as shown in Figure 6, the loopback test control circuit 405 can perform loopback test channel by channel (i.e., bit by bit, from low bit to high bit). For example, in loopback test mode, the loopback test control circuit 405 can set the bits DIN1[0] of input data DIN1 and the bits DIN0[0] of input data DIN0 to pseudo-random sequence data PT1, and set the remaining bits DIN1[1]~DIN1[7] and DIN1[9] of input data DIN1 and the remaining bits DIN0[1]~DIN0[7] and DIN0[9] of input data DIN0 to logic value 0. In this way, the transmitter circuit 430 transmits pseudo-random sequence data PT2 to the receiver circuit 450 via the channel corresponding to the signal pad IO[0] in the feedback test mode. Under this condition, the feedback test control circuit 405 can obtain a corresponding bit DO0[0] in the feedback test data (at this time, other bits DO0[1]~DO0[7] and DO0[9] are logic values ​​0), and can verify the bit DO0[0] according to the clock signal CK3 to generate the flag signal SF[0] corresponding to the first bit.

[0040] Next, in the loopback test mode, the loopback test control circuit 405 can set the bits DIN1[1] of the input data DIN1 and the bits DIN0[1] of the input data DIN0 to multiple bits of the pseudo-random sequence data PT1 (labeled as PRBS7 sample), and set the remaining bits DIN1[0], DIN1[2]~DIN1[7] and DIN1[9] of the input data DIN1 and the remaining bits DIN0[0], DIN0[2]~DIN0[7] and DIN0[9] of the input data DIN0 to the logic value 0. In this way, the transmitter circuit 430 will transmit the pseudo-random sequence data PT2 to the receiver circuit 450 through the channel corresponding to the signal pad IO[1] in the loopback test mode. Under these conditions, the return test control circuit 405 can obtain a corresponding bit DO0[1] in the return test data (at this time, other bits DO0[0], DO0[2]~DO0[7] and DO0[9] are logic values ​​0), and can verify the bit DO0[1] according to the clock signal CK3 to generate the flag signal SF[1] corresponding to the second bit.

[0041] Similarly, the feedback test control circuit 405 can provide pseudo-random sequence data PT1 channel by channel, so that the transmitter circuit 430 can also sequentially transmit pseudo-random sequence data PT2 to the receiver circuit 450 channel by channel. In this way, the feedback test control circuit 405 can generate multiple flag signals SF[0]~SF[7] and SF[9] that can indicate the feedback test results channel by channel. Among the multiple flag signals SF[0]~SF[7] and SF[9], if any signal is a logic value of 0, it means that the feedback test result of that channel is failed; conversely, if any signal is a logic value of 1, it means that the feedback test result of that channel is passed. In this way, feedback tests can be performed quickly channel by channel. In addition, in the test method of FIG6, the generation method of the received clock signal RXCK2 and the clock signal CK3 is the same as that of the example in FIG5, so it will not be repeated here.

[0042] Figure 7 is a flowchart illustrating a loopback test method 700 according to some embodiments of this invention. In some embodiments, the loopback test method 700 may be performed by, but is not limited to, the eMMC host device 400 of Figure 4.

[0043] In operation S710, in a loopback test mode, a first pseudo-random sequence data and a first data selection signal corresponding to a first transmission mode are generated. In operation S720, in the loopback test mode, the first pseudo-random sequence data is sampled according to a transmit clock signal to output a second pseudo-random sequence data, and the first data selection signal is sampled according to the transmit clock signal to output a first clock signal. In operation S730, in the loopback test mode, the second pseudo-random sequence data and the first clock signal are received via an input / output interface, the second pseudo-random sequence data is output as a third pseudo-random sequence data, and the first clock signal is output as a second clock signal. In operation S740, in the loopback test mode, the second clock signal is output as a receive clock signal via a delay-locked loop in the embedded multimedia card host device using a bypass mechanism, wherein the delay-locked loop delays an external data selection signal from an external device in a second transmission mode to generate the receive clock signal. In operation S750, in this loopback test mode, the third pseudo-random sequence data is processed according to the received clock signal to generate loopback test data. In operation S760, in this loopback test mode, the received clock signal is delayed to generate a third clock signal. In operation S770, in this loopback test mode, the loopback test data is verified according to the third clock signal to generate a flag signal indicating a loopback test result.

[0044] The descriptions of the various operations of the feedback test method 700 can be found in the foregoing embodiments, and therefore will not be repeated here. The aforementioned operations are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operational methods and scope of the embodiments of this invention, the various operations in the feedback test method 700 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, one or more operations in the feedback test method 700 may be performed simultaneously or partially simultaneously.

[0045] In summary, the eMMC host device and its feedback test method provided in some embodiments of this invention can utilize the data rate of the first transmission mode and the generation path of the sampling clock signal of the second transmission mode to configure the test input data and generate a sampling clock signal with a better sampling point. Thus, feedback testing can be performed directly using the aforementioned test input data and sampling clock signal without the need for an additional phase adjustment mechanism, resulting in highly reliable test results. Furthermore, the above-described testing process does not require the insertion of a physical memory card, improving testing convenience.

[0046] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make variations to the technical features of this case based on the express or implied content of this case. All such variations may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0047] 100,400: Embedded Multimedia Card (eMMC) Host Device 101: External Devices 110, 410: Phase-locked loop 120, 420: Delayed phase-locked loop 130, 430: Transmitter circuit 131[0]~131

[11] , 431[8]: transmitter 140, 440: Input / output interfaces 150, 450: Receiver circuit 151[0]~151

[11] , 451[8]: Receiver 152[0]~152

[11] , 460: Demultiplexer 201: Received data waveform 202, 203: Output data waveforms 405: Feedback Test Control Circuit 405A: Clock Generation Circuit 405B: Test Data Generation Circuit 405C: Data Verification Circuit 431: Launcher Group 441: Signal Pad Group 451: Receiver Group 470: Delay circuit 700: Feedback Test Method CK1, CK2, CK3, CKR: Clock signals D0, D1, D2, D3: Data DIN0, DIN1: Input data DIN0[0]~DIN0

[11] , DIN1[0]~DIN1

[11] , DIN0[9, 7:0],DIN1[9, 7:0]:bits DO0, DO1: Output data DO0[0]~DO0

[11] , DO1[0]~DO1

[11] : bits DO0[9, 7:0]: Send back test data DS1: Select Communication Number DSO: External Data Selection Communication Number IO[0]~IO

[11] : Signal pads P, B, R, S, 7, PT: Data values PT1, PT2, PT3: Pseudo-random sequence data RXCK1, RXCK2: Receive clock signal S710, S720, S730, S740, S750, S760, S770: Operation SF, SF[0]~SF[7], SF[9]: Flag signal TXCK: Transmit clock signal

Claims

1. An embedded multimedia card host device, comprising: a loopback test control circuit, which generates a first pseudo-random sequence data and a first data selection signal corresponding to a first transmission mode in a loopback test mode; a transmitter circuit, which, in the loopback test mode, samples the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and samples the first data selection signal according to the transmit clock signal to output a first clock signal; a receiver circuit, which, in the loopback test mode, receives the second pseudo-random sequence data and the first clock signal from the transmitter circuit via an input / output interface, outputs the second pseudo-random sequence data as a third pseudo-random sequence data, and outputs the first clock signal as a second clock signal; and a delay-locked loop, which, in the loopback test mode, outputs the second clock signal as a receive clock signal using a bypass mechanism, wherein the delay-locked loop performs delay processing on an external data selection signal from an external device in a second transmission mode to generate the receive clock signal; A demultiplexer, in the loopback test mode, processes the third pseudo-random sequence data according to the received clock signal to generate loopback test data; and a delay circuit, in the loopback test mode, delays the received clock signal to generate a third clock signal; wherein, in the loopback test mode, the loopback test control circuit further verifies the loopback test data according to the third clock signal to determine a loopback test result, and generates a flag signal according to the loopback test result.

2. The embedded multimedia card host device as claimed in claim 1, wherein a data rate of the first transmission mode is lower than a data rate of the second transmission mode.

3. The embedded multimedia card host device as claimed in claim 1, wherein the first transmission mode is HS200 mode and the second transmission mode is HS400 mode.

4. The embedded multimedia card host device of claim 1, wherein the loopback test control circuit sets a first specific element and a second specific element to a complementary first logic value and a second logic value, respectively, in the loopback test mode to generate the first data selection signal, and the first specific element and the second specific element are transmitted to a signal pad in the input / output interface for receiving the external data selection signal.

5. The embedded multimedia card host device of claim 1, wherein the loopback test control circuit comprises: a clock generation circuit that generates the first data selection signal in the loopback test mode; a test data generation circuit that generates the first pseudo-random sequence data in the loopback test mode; and a data verification circuit that verifies the loopback test data according to the third clock signal in the loopback test mode to generate the flag signal.

6. The embedded multimedia card host device of claim 5, wherein the data verification circuit verifies the returned test data by confirming, based on the third clock signal, whether at least a portion of the bits in the returned test data conforms to a pseudo-random sequence.

7. The embedded multimedia card host device as claimed in claim 5, wherein the data verification circuit verifies the returned test data by confirming whether the returned test data is the same as the first pseudo-random sequence data based on the third clock signal.

8. The embedded multimedia card host device of claim 1, wherein the transmitter circuit transmits the second pseudo-random sequence data to the receiver circuit simultaneously via a plurality of channels in the loopback test mode.

9. The embedded multimedia card host device of claim 1, wherein the transmitter circuit transmits the second pseudo-random sequence data to the receiver circuit sequentially via one of a plurality of channels in the loopback test mode.

10. A loopback test method, executed by an embedded multimedia card host device, the loopback test method comprising: in a loopback test mode, generating a first pseudo-random sequence data and a first data selection signal corresponding to a first transmission mode; in the loopback test mode, sampling the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and sampling the first data selection signal according to the transmit clock signal to output a first clock signal; in the loopback test mode, receiving the second pseudo-random sequence data and the first clock signal via an input / output interface, outputting the second pseudo-random sequence data as a third pseudo-random sequence data, and outputting the first clock signal as a second clock signal; in the loopback test mode, outputting the second clock signal as a receive clock signal via a delay-locked loop in the embedded multimedia card host device using a bypass mechanism, wherein the delay-locked loop in a second transmission mode delays an external data selection signal from an external device to generate the receive clock signal; In the loopback test mode, the third pseudo-random sequence data is processed according to the received clock signal to generate loopback test data; in the loopback test mode, the received clock signal is delayed to generate a third clock signal; and in the loopback test mode, the loopback test data is verified according to the third clock signal to determine a loopback test result, and a flag signal is generated according to the loopback test result.

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