Method and system for formation of stabilized tetragonal barium titanate

Abstract

This invention provides an electro-optic device, including a substrate and a waveguide on the substrate. The waveguide includes: a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayer layers; a waveguide core adjacent to the layer stack; a waveguide cladding layer; and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayer layers maintain a first lattice structure at room temperature and extremely cold temperatures. The plurality of electro-optic material layers maintain a second lattice structure and crystalline phase at room temperature and extremely cold temperatures.

Description

Technical Field

[0001] Cross-reference to other applications: This application claims priority to U.S. Provisional Patent Application No. 62 / 927,373, filed October 29, 2019, for “METHOD AND SYSTEM FOR FORMATION OF STABILIZED TETRAGONAL BARIUM TITANATE”, which is incorporated herein by reference in its entirety for all purposes.

[0002] This disclosure relates to a method and system for forming stabilized tetragonal barium titanate. Prior Technology

[0003] Electro-optical (EO) devices, such as EO modulators and switches, are used in various optical systems, including optical communication and optical computing systems. For example, optical phase modulators can be used in integrated optical systems, optical communication transmitters, or transceivers. EO modulators or switches can utilize various EO effects, such as free-carrier electrorefraction, free-carrier electroabsorption, the Pockels effect, and the Kerr effect, to modify the properties of light during operation, such as changing the phase or amplitude of light propagating through certain paths in the EO modulator or switch. EO devices using materials with higher EO effects can have lower control voltages, lower power consumption, and typically operate at higher speeds. Summary of the Invention

[0004] The techniques disclosed herein generally relate to electro-optic (EO) devices. More specifically, the embodiments disclosed herein relate to techniques for achieving high EO effects in EO devices (e.g., optical switches or optical modulators) at cryogenic temperatures, such as extremely cold temperatures. In one particular embodiment, an EO device comprising a stack of EO materials characterized by a high electro-optic coefficient at cryogenic temperatures (e.g., extremely cold temperatures) is utilized to improve the modulation and / or switching performance of the EO device at cryogenic temperatures. The EO material stack may include interleaved and interlocked thin EO material layers and interlayers. When the EO materials in the EO material layers are used in bulk, the crystal structure of the EO materials can be changed at different operating temperatures, while the interlayers may have a lattice structure that does not change at the operating temperature. Thus, when the operating temperature changes, the thin EO material layers interlocked to the interlayers can maintain their lattice structure and therefore their EO coefficients. The techniques disclosed herein can be used in a variety of photonic and optoelectronic devices operating at cryogenic temperatures.

[0005] According to some embodiments, the electro-optic device may include a substrate and a waveguide on the substrate. The waveguide may include a stack of layers, the stack including a plurality of electro-optic material layers interleaved with a plurality of interlayer layers. The waveguide may also include a waveguide core, a waveguide cladding layer, and a pair of electrodes electrically contacting the plurality of electro-optic material layers adjacent to the stack. The plurality of interlayer layers may be arranged to maintain a first lattice structure at room temperature and extremely cold temperatures. The plurality of electro-optic material layers may maintain a second lattice structure and crystalline phase at room temperature and extremely cold temperatures. In some embodiments, the plurality of interlayer layers and the plurality of electro-optic material layers may be characterized by a tetragonal lattice structure at extremely cold temperatures. In some embodiments, the plurality of electro-optic material layers may be characterized by in-plane polarization at extremely cold temperatures.

[0006] In some embodiments of the electro-optic device, the plurality of electro-optic material layers may include ferroelectric crystals or ferroelectric thin films. Ferroelectric crystals may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. In some embodiments, the plurality of electro-optic material layers may be characterized by a Burkes coefficient greater than 300 pm / V at extremely cold temperatures. The plurality of interlayers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaMoO3, BaNbO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, SrNbO3, or SrZrO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of interlayers may be equal to or less than 20:1.

[0007] In some embodiments of the electro-optic device, the waveguide core may include one or more of a plurality of electro-optic material layers. The waveguide cladding layer may be in solid contact with one of the plurality of electro-optic material layers and may be characterized by a coefficient of thermal expansion and an optical refractive index different from those of the electro-optic material layers. The waveguide cladding layer may include at least one of, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, or HfO2.

[0008] In some embodiments, the EO device may further include an epitaxial seed layer between the substrate and the waveguide. The epitaxial seed layer may include at least one of, for example, MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, SrMoO3, or SrZrO3. In some embodiments, the EO device may further include a buffer layer between the epitaxial seed layer and the substrate. Each of these electrodes may be in solid contact with each of the plurality of electro-optic material layers. In some embodiments, a waveguide cladding layer may be located between the substrate and the layer stack. The waveguide may be a segment of a Mach-Chenld interferometer, a resonator, an optical switch, an electro-optic modulator, etc.

[0009] According to some embodiments, a wafer may include a substrate and a stack of layers on the substrate. The stack of layers may include a plurality of electro-optic material layers and a plurality of interlayers interleaved with the plurality of electro-optic material layers. The plurality of interlayers may maintain a first lattice structure at room temperature and extremely cold temperatures, and the plurality of electro-optic material layers may maintain a second lattice structure and crystalline phase at room temperature and extremely cold temperatures. In some embodiments, the first lattice structure and the second lattice structure may be the same lattice structure, such as a tetragonal lattice structure. In some embodiments, the wafer may also include an epitaxial seed layer between the substrate and the stack of layers, wherein the epitaxial seed layer may include at least one of, for example, MgO, LaAlO3, BaHfO3, BaZrO3, SrHfO3, SrTiO3, or SrZrO3. In some embodiments, the wafer may also include an oxide layer of the substrate between the epitaxial seed layer and the substrate.

[0010] In some embodiments of the wafer, the plurality of electro-optic material layers may include at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3. The plurality of interlayers may include at least one of MgO, LaAlO3, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrZrO3, or SrNbO3. In some embodiments, the ratio between the thickness of each of the plurality of electro-optic material layers and the thickness of each of the plurality of interlayers may be equal to or less than 20:1.

[0011] According to some embodiments, the method may include the following steps: depositing a seed layer on a substrate; epitaxially depositing a first electro-optic material layer on the seed layer; annealing the substrate, seed layer, and first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer; depositing a first interlayer comprising a material capable of maintaining a first lattice structure at room temperature and extremely cold temperatures on the first electro-optic material layer; depositing a second electro-optic material layer on the first interlayer; and annealing the second electro-optic material layer and the first interlayer. The first and second electro-optic material layers may include a second lattice structure characterized by a third lattice structure at an extremely cold temperature, different from that at room temperature. In some embodiments, the third lattice structure and the first lattice structure may be the same lattice structure, such as a cubic lattice structure. In some embodiments, the ratio between the thickness of the first electro-optic material layer and the thickness of the first interlayer may be equal to or less than 20:1.

[0012] In some embodiments, the step of annealing the substrate, seed layer, and first electro-optic material layer may include annealing at a temperature higher than the softening temperature of the oxide buffer layer. The method may also include the following steps: depositing a second interlayer containing a material that maintains a first lattice structure at room temperature and extremely cold temperatures on the second electro-optic material layer, depositing a third electro-optic material layer on the second interlayer, and annealing the third electro-optic material layer and the second interlayer.

[0013] In some embodiments, the method may also include the steps of: patterning a third electro-optic material layer to form a waveguide core, and depositing a dielectric overlay layer on the waveguide core. The step of patterning the third electro-optic material layer may include etching the third electro-optic material layer using a second interlayer as an etch stop layer. In some embodiments, the method may also include etching trenches in the first, second, and third electro-optic material layers and the first and second interlayers, and filling these trenches with a conductive material. The step of etching these trenches may include etching the first, second, and third electro-optic material layers using an oxide buffer layer as an etch stop layer.

[0014] In some embodiments, the method may include forming a waveguide on a third electro-optic material layer. In some embodiments, the step of forming a waveguide on the third electro-optic material layer may include forming a waveguide core on the third electro-optic material layer and depositing a dielectric cladding layer on the waveguide core. In some embodiments, the step of forming a waveguide core on the third electro-optic material layer may include depositing a layer of high refractive index material on the third electro-optic material layer and patterning the layer of high refractive index material. In some embodiments, the step of forming a waveguide core on the third electro-optic material layer may include depositing a dielectric layer on the third electro-optic material layer, depositing a layer of high refractive index material on the dielectric layer, and patterning the layer of high refractive index material. In some embodiments, the step of forming a waveguide on the third electro-optic material layer may include bonding a wafer including the waveguide to the third electro-optic material layer.

[0015] This disclosure achieves numerous benefits over the prior art. For example, examples of the methods, apparatus, and systems disclosed herein can maintain the lattice structure and thus the EO coefficients (e.g., the tetragonal phase and Burkes coefficient of BaTiO3) of ferroelectric materials at extremely low temperatures, such as ultracold temperatures, thereby improving the performance of EO devices such as EO switches or EO modulators at ultracold temperatures. Thus, the reduced electric field or bias signal can be used to achieve the desired refractive index modulation and / or phase modulation for optical modulation or switching, thereby reducing power consumption and increasing device efficiency and / or speed. Furthermore, the embodiments disclosed herein enable a larger effective refractive index change at low temperatures compared to the prior art. Therefore, the device length can be reduced, thereby reducing optical losses and physical size of the EO device. These and other embodiments, as well as many of their advantages and features, are described in more detail below in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0016] Figure 1A is a simplified diagram illustrating an example of an optical switch including a Mach-Zehnder interferometer according to certain embodiments. Figure 1B is a cross-sectional view of an example of a phase adjustment section in an implementation of the optical switch illustrated in Figure 1A according to certain embodiments;

[0017] Figure 2 illustrates the effective Pockels coefficients for ABO3 perovskite crystals (e.g., BaTiO3 crystals) with different lattice orientations at temperatures from about 4 K to about 340 K, according to certain embodiments.

[0018] Figures 3A to 3D illustrate the phase transitions of BaTiO3 at different temperatures according to certain embodiments;

[0019] Figure 4 is a simplified flowchart illustrating an example of a method for manufacturing an EO device including an EO material layer according to certain embodiments, wherein the EO material layer is characterized by a substantially constant EO coefficient from room temperature to extremely cold temperatures;

[0020] Figure 5A illustrates an example of a substrate having a seed layer grown thereon, according to certain embodiments;

[0021] Figure 5B illustrates the intralayer stress and lattice orientation of a ferroelectric material epitaxially deposited on a seed layer according to certain embodiments;

[0022] Figure 5C illustrates the intralayer stress and lattice orientation of a ferroelectric material epitaxially deposited on a seed layer after high-temperature oxidation annealing, according to certain embodiments;

[0023] Figure 5D illustrates the internal stress and lattice orientation of a ferroelectric material interlayered with interlayers in an engineered wafer according to certain embodiments;

[0024] Figure 5E illustrates the internal stress and lattice orientation of the ferroelectric material interleaved with the interlayer in the waveguide structure according to certain embodiments;

[0025] Figure 6 illustrates, according to certain embodiments, an improvement in crystal quality after annealing as shown by ion channels in an example of an epitaxial layer before and after annealing;

[0026] Figure 7 illustrates an example of X-ray diffraction data showing the relaxation of the lattice constant in an epitaxial layer at high temperature, according to certain embodiments;

[0027] Figure 8 is a simplified cross-sectional view of one example of a waveguide structure according to certain embodiments, comprising an EO material layer that maintains a tetragonal crystalline phase at extremely cold temperatures;

[0028] Figure 9 is a simplified cross-sectional view of another example of a waveguide structure according to certain embodiments, including an EO material layer that maintains a tetragonal crystalline phase at extremely cold temperatures;

[0029] Figure 10 is a simplified cross-sectional view of yet another example of a waveguide structure comprising an EO material layer that maintains a tetragonal crystalline phase at extremely cold temperatures, according to certain embodiments;

[0030] Figure 11 is a simplified flowchart illustrating an example of a method for manufacturing an engineering wafer and / or an EO device including an EO material layer according to certain embodiments, wherein the EO material layer is characterized by a substantially constant EO coefficient from room temperature to extremely cold temperatures; and

[0031] Figure 12 is a simplified system block diagram of an example of a hybrid quantum computing system including an electro-optic device according to certain embodiments. Implementation

[0032] The techniques disclosed herein generally relate to electro-optic (EO) devices. More specifically, the embodiments disclosed herein relate to techniques for achieving high EO effects in EO materials (e.g., ferroelectric materials) at cryogenic temperatures such as extremely cold temperatures, and for utilizing the high EO effects of EO materials in EO devices such as optical modulators and switches to reduce power consumption and improve efficiency and speed during operation of EO devices at cryogenic temperatures. The embodiments are provided in the context of integrated optical systems including active optics devices only by way of example, but the techniques disclosed herein are not limited to these examples and have broad applicability to a wide range of optical and optoelectronic systems. Various inventive embodiments are described herein, including methods, processes, materials, wafers, systems, devices, etc.

[0033] Compared to devices using materials with relatively low EO coefficients, EO devices using materials with higher EO effects can operate at lower control voltages, lower power consumption, and higher speeds. In some applications, such as linear optical quantum computing, EO devices can operate at extremely low temperatures, such as cryogenic temperatures (e.g., about 4 K). The EO effect of the Burkes coefficient of some EO materials can be significantly degraded at low temperatures. For example, BaTiO3 (BTO) can be used in EO switches due to its high Burkes coefficient (e.g., greater than about 900 picoseconds / volt at room temperature) and compatibility with silicon CMOS processes. However, the Burkes coefficient of BTO at about 4 K can be reduced to about one-third of that at room temperature. Therefore, the efficiency of EO switches can be significantly reduced at cryogenic temperatures. As defined herein, room temperature is a temperature around 20 °C and more specifically, a temperature between 18 °C and 22 °C. As defined herein, extreme cold is a temperature below -150°C and more specifically, a temperature between -150°C and -273°C.

[0034] According to some embodiments, the degradation of the EO effect (e.g., the Burkes coefficient) of certain EO materials at low temperatures can be caused by crystalline phase transitions in the EO material lattice at different temperatures. For example, BTO can undergo a crystalline phase transition from a tetragonal phase at room temperature to an orthorhombic phase below room temperature, and subsequently to a rhombic phase toward extremely cold temperatures. The crystalline phase transition from the tetragonal phase to the rhombic phase can contribute to the degradation of the Burkes effect from room temperature to extremely cold temperatures. Thus, according to some embodiments, the EO effect of EO materials can be maintained at a high level (e.g., close to room temperature) at low temperatures by maintaining the tetragonal lattice structure of the EO material. In some embodiments, this can be achieved, for example, by interlocking thin layers and interlayers of the EO material, which do not undergo lattice structure (or crystalline phase) and polarization changes when the operating temperature drops from room temperature to extremely cold temperatures, or undergo crystalline phase transitions at temperatures different from those of the EO material, thereby hindering the crystalline phase transition of the EO material. Interlayers help maintain stress within the EO material and prevent changes in lattice structure and polarization as operating temperatures decrease. Therefore, the EO coefficient of the EO material can be maintained at a level close to room temperature. Consequently, EO devices, including those with staggered structures, can maintain high efficiency and speed at extremely cold temperatures.

[0035] According to certain embodiments, the active photonic devices described herein can utilize high electro-optic effects, such as the Burkes effect, to efficiently modulate and / or switch optical signals at low temperatures. For example, the techniques disclosed herein can be applied to optical modulators in which the intensity of transmitted light can be modulated according to, for example, a sine or square function, and to optical switches in which light can be selected from one of one or more input ports (e.g., a waveguide) and output to one of one or more output ports (e.g., a waveguide).

[0036] According to certain embodiments, EO materials can be used in devices with different waveguide structures and / or waveguide structures manufactured by different processes. For example, EO materials can be used as waveguide cores, lower cladding layers, and / or upper cladding layers in waveguide structures. In various embodiments, waveguide cores can be deposited on or etched in an EO material layer, or formed on a semiconductor substrate and subsequently bonded to a wafer or device including an EO material layer.

[0037] Several exemplary embodiments are described below with respect to the accompanying drawings that form a part of this specification. The following description is merely illustrative of embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the subsequent description of the embodiments will provide those skilled in the art with enabling descriptions for implementing one or more embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments can be practiced without such specific details. The drawings and descriptions are not intended to be limiting. The terms “exemplary” or “illustrative” are used herein to mean “serving as an example, illustration, or description.” Any embodiment or design described herein as “exemplary” or “illustrative” is not necessarily considered superior or advantageous over other embodiments or designs.

[0038] Silicon photonic integrated circuits (PICs) offer better performance than electrical integrated circuits (EICs) (e.g., lower losses, higher speeds, higher bandwidths, and thermal insulation) and can be used in quantum communication or quantum computing, where photons can be used as qubits due to their quantum nature and optical interconnects can be used to provide higher bandwidth for digital data transfer between extremely cold processors and room temperature environments. However, the performance of PICs at extremely cold temperatures may require improvement in part due to the lack of effective EO modulation for optical switching and / or optical modulation at low temperatures. For example, some integrated optical switches operating at extremely cold temperatures use thermo-optical phase shifters or plasma dispersion switches, which can suffer from some inherent limitations. Thermo-optical switches that use heat to change the refractive index of materials can require significant cooling power and may have low bandwidth and low switching speeds. Plasma dispersed switches can use highly doped levels to compensate for charge carrier freezing at low temperatures, and thus small resonators can be used in plasma dispersed switches. These small resonators can have high resistance, high insertion loss, and low bandwidth.

[0039] Some electro-optic (EO) materials exhibit a linear electro-optic effect, where the refractive index of the material changes proportionally to the strength of the electric field applied to it. This linear electro-optic effect is called the Burkes effect and can occur in non-centrosymmetric crystalline materials such as lithium niobate (LiNbO3), lithium tantalate (LiTaO3), potassium dideuterium phosphate (KDP), barium β-borate (BBO), and potassium titanyl phosphate (KTP), as well as some compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP). EO switches based on the Burkes effect can exhibit low propagation loss, high bandwidth, and low quiescent power consumption at room temperature. Furthermore, EO switches based on the EO Burkes effect are not inherently limited by thermo-optic and plasma dispersion effects at extremely cold temperatures.

[0040] [No.] [1A] [Figure] is a simplified diagram illustrating an example of an optical switch 100 including a Mach-Chenld interferometer 120 according to certain embodiments. In the example shown in Figure 1, the optical switch 100 includes two input ports (input port 1 and input port 2) and two output ports (output port 1 and output port 2). The input ports and output ports of the optical switch 100 may be implemented, for example, using optical waveguides that can operate to support single-mode or multimode beams. The optical switch 100 may be implemented using a Mach-Chenld interferometer 120, which is integrated with a set of 50 / 50 beam splitters (or directional couplers), such as a first 50 / 50 beam splitter 105 and a second 50 / 50 beam splitter 107. As illustrated in Figure 1, input ports 1 and 2 may be optically coupled to the first 50 / 50 beam splitter 105, which may receive light from input port 1 or input port 2. The first 50 / 50 beam splitter 105 can guide approximately 50% of the input light from input port 1 into the first waveguide 110 and approximately 50% of the input light from input port 1 into the second waveguide 112 via evanescent coupling. Similarly, the first 50 / 50 beam splitter 105 can guide approximately 50% of the input light from input port 2 into the first waveguide 110 and approximately 50% of the input light from input port 2 into the second waveguide 112. Thus, the input light from the input port can be split approximately uniformly and guided to the first waveguide 110 and the second waveguide 112.

[0041] The Mach-Chenold interferometer 120 may include a phase adjustment section 122, which includes a waveguide 124 and an electrode 126. A voltage signal V0 can be applied across the waveguide 124 by the electrode 126 in the phase adjustment section 122 to adjust the refractive index of the waveguide 124 and thus the phase delay of the light after passing through the phase adjustment section 122. Because the light in the first waveguide 110 and the second waveguide 112 is in phase after propagating through the first 50 / 50 beam splitter 105, the phase adjustment in the phase adjustment section 122 can introduce a predetermined phase difference between the light propagating in the waveguides 130 and 132. As will be apparent to those skilled in the art, the phase relationship between the light propagating in waveguides 130 and 132 can result in the output light being present at output port 1 (e.g., when the beams are in phase) or at output port 2 (e.g., when the beams are out of phase), thereby providing a switching function when the light is directed to output port 1 or output port 2 based on a voltage signal V0 applied at phase adjustment section 122. Although a single active arm is illustrated in Figure 1, in some other embodiments, both arms of the Mach-Childe interferometer 120 may include phase adjustment sections.

[0042] As illustrated in Figure 1, electro-optical switching technology, compared to all-optical switching technology, involves applying an electrical bias voltage (e.g., voltage signal V0 in Figure 1) across the active region of the switch to produce optical changes. The electric field or current generated by the applied bias voltage can cause changes in one or more optical properties of the active region, such as the refractive index or light absorption. In addition to the power dissipated by the current flow (when the current is generated by the applied bias voltage), energy can also be dissipated by the creation of an electric field, which can have an energy density of E²κ / 8π (cgs units), where E is the electric field and κ is the dielectric constant.

[0043] Although one example of a Mach-Childe interferometer implementation is illustrated in Figure 1, other switching architectures and / or other phase adjustment devices can be used in various embodiments, including ring resonator designs, disk resonator designs, Mach-Childe modulators, generalized Mach-Childe modulators, etc. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0044] The phase adjustment described above can be achieved using EO effects such as the Burkes effect and / or the Kerr effect. The Burkes effect alters or produces birefringence in an optical medium subjected to an electric field, where birefringence is proportional to the applied electric field. The Burkes effect can occur in crystals lacking inversion symmetry, such as perovskite crystals, ferroelectric crystals, or other non-centrosymmetric media such as electrically polarized polymers or glasses. In the Kerr effect, the change in refractive index (or birefringence) is proportional to the power (e.g., squared) of the applied electric field. All materials can exhibit the Kerr effect, but some materials can have a higher Kerr effect compared to others. Generally, the Burkes effect can be a much higher EO effect than the Kerr effect.

[0045] Ferroelectric crystals typically exhibit spontaneous polarization, which can be redirected by an electric field or stress. Spontaneous polarization can be induced by non-centrosymmetric crystal structures, which are stable within a certain temperature range. Some examples of ferroelectric crystals exhibiting the Burkes effect include BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), (Sr,Ba)Nb2O6 (SBN), and so on. For example, barium titanate (BTO) has a relatively large Burkes coefficient at room temperature. Furthermore, BTO can be grown on large Si substrates and integrated into Si photonic platforms using silicon CMOS processes. Therefore, BTO is used in various electronic applications due to its excellent ferroelectric properties, high dielectric constant, low dielectric loss, chemical and mechanical stability, and CMOS process compatibility.

[0046] [No.] [1B] [Figure] is a cross-sectional view of an example of a phase adjustment section 150 (e.g., phase adjustment section 122) in an embodiment of the optical switch 100 illustrated in Figure 1A according to certain embodiments. The phase adjustment section 150 may utilize the EO effect, such as the Burkes effect described above. The phase adjustment section 150 may include a substrate 152, an optional buffer layer 154, a seed layer 156, an EO material layer 158, a waveguide core 162, a waveguide cladding layer 160, and an electrode 164. The EO material layer 158 may have a high Burkes coefficient and may include, for example, perovskite ferroelectrics or other ferroelectric crystals, such as barium titanate (BaTiO3 or BTO) as described herein.

[0047] Substrate 152 may include a semiconductor substrate, such as a silicon wafer, germanium wafer, silicon-on-germanium wafer, silicon-on-insulator (SOI) wafer, etc. Seed layer 156 may have a lattice structure similar to that of EO material layer 158, and may include, for example, MgO, BaHfO3, BaZrO3, LaAlO3, SrHfO3, SrTiO3, SrMoO3, or SrZrO3. Seed layer 156 may be deposited (e.g., epitaxially grown) on substrate 152. In some embodiments, buffer layer 154 may be positioned between seed layer 156 and substrate 152. Buffer layer 154 may include, for example, an oxide layer of the substrate, such as a SiO2 layer. In one example, buffer layer 154 (e.g., SiO2) may be formed by high-temperature oxidation annealing of seed layer 156 (e.g., SrTiO3) and substrate 152 (e.g., Si) in an oxygen environment.

[0048] An EO material layer 158 may be epitaxially deposited on a seed layer 156. A waveguide core 162 may be formed directly on top of the EO material layer 158 by, for example, deposition and photolithography, or indirectly on the EO material layer 158 with a buffer layer between the EO material layer 158 and the waveguide core 162. This buffer layer may be used to prevent interaction between the EO material layer 158 and the waveguide core 162, and / or serve as an etch stop layer for the formation of the waveguide core 162. The waveguide core 162 may include, for example, Si, SiN, SiGe, EO materials (e.g., BTO), etc. A waveguide cladding layer 160 may include a dielectric material having a lower refractive index than the waveguide core 162, such as oxides, nitrides, or oxides of oxynitrides, oxides of carbon, etc. (e.g., SiO2, Si3N4, SiON, SiCO, etc.), and may be deposited on the waveguide core 162. The trench can be etched into the waveguide cladding layer 160 and filled with a conductive material such as metal to form an electrode 164. The electrode 164 can be used to apply a bias voltage and thus an electric field across the EO material layer 158 to modulate the refractive index of the EO material layer used for phase adjustment.

[0049] As described above, some perovskite ferroelectrics, such as barium titanate, can exhibit large Burkes coefficients at room temperature. The Burkes coefficient of perovskite ferroelectric materials can vary with different lattice orientations. Furthermore, the Burkes coefficient of perovskite ferroelectric materials can differ at different operating temperatures. For example, at low temperatures, the Burkes coefficient of ferroelectric materials can decrease significantly.

[0050] [No.] [2] [Figure] Examples of effective Burkes coefficients for BaTiO3 with different lattice orientations at temperatures from about 4 K to about 340 K, as reported, for example, in Felix Eltes et al., "An integrated Cryogenic Optical Modulator", J. App. Phys. (2019). In Figure 2, the x-axis corresponds to the operating temperature between 4 K and 340 K, and the y-axis corresponds to the Burkes coefficient (in pm / V). Curve 210 shows the corresponding Burkes coefficients for a BTO layer with a 45° lattice orientation at different temperatures. Curve 220 shows the corresponding Burkes coefficients for a BTO layer with a 22.5° lattice orientation at different temperatures. Curve 230 shows the corresponding Burkes coefficients for a BTO layer with a 67.5° lattice orientation at different temperatures. Curve 240 shows the corresponding Burkes coefficients for a BTO layer with a 90° lattice orientation at different temperatures. Curves 210-240 show that the Burkes effect of BTO is anisotropic, and therefore the EO effect can vary with the orientation of the lattice in the BTO layer of the EO device.

[0051] Curves 210-240 also illustrate the temperature dependence of the Burkes coefficient. For example, Figure 2 shows that when the lattice orientation in the BTO layer is at approximately 45°, the Burkes coefficient can be highest between approximately 200 K and approximately 260 K, such as at approximately 240 K, where the Burkes coefficient can be greater than 700 pm / V. Below approximately 240 K, the order of the Burkes coefficient gradually decreases to approximately 200 pm / V at 4 K, which is less than one-third of the Burkes coefficient at room temperature. Furthermore, a rapid decrease in the Burkes coefficient can occur between approximately 140 K and approximately 100 K.

[0052] Although the Burkes coefficient of BaTiO3 decreases significantly at 4 K compared to its Burkes coefficient at room temperature, the value (e.g., approximately 200 pm / V) is still greater than that of some other materials at room temperature. The effect of the reduced Burkes coefficient on the energy efficiency of EO switching can be partially compensated by the decrease in the dielectric constant of BaTiO3 at low temperatures. Furthermore, the reduced conductivity of BaTiO3 at low temperatures can help reduce the quiescent power consumption of BaTiO3 devices in extremely cold environments.

[0053] To improve the performance of EO devices based on the Burkes effect at extremely cold temperatures, it may be necessary to maintain a high room-temperature Burkes coefficient of the EO material at these temperatures. According to some embodiments, the reduction in the Burkes effect can be determined at least in part by changes in strain and polarization of the crystal with temperature variations, as well as by phase transitions and polarization changes at certain temperatures, because, as described above, the Burkes effect can occur in crystals lacking inversion symmetry (e.g., non-centrosymmetric), and the non-zero elements of the Burkes tensor can depend on crystal symmetry. Therefore, if the EO material can maintain its room-temperature crystal structure at extremely cold temperatures, the Burkes coefficient of the EO material at these temperatures can be improved.

[0054] [No.] [3A] [Image up to number] [3D] [Figure] Illustrate the crystallization phase transitions of ABO3 perovskite crystals (e.g., BaTiO3) at different temperatures. Barium titanate (BaTiO3) can typically be in a paraelectric phase without net polarization above the Curie temperature (e.g., at about 120 °C). [No.] [3A] [Figure] shows the cubic crystal structure 310 of BaTiO3 above the Curie temperature. Large barium ions (A ions) typically occupy the corner positions. Small titanate ions (B ions) are typically located at the center of the cube. Oxygen anions are typically located at the center of the faces. Unlike many other oxide crystals, oxygen anions in perovskite crystals do not form a close-packed structure. Therefore, the crystal structure of perovskite crystals (e.g., BaTiO3) can be altered by temperature variations and stress within the perovskite crystal. At approximately the Curie temperature, the crystal can undergo a phase transition (also known as a displacement phase transition) and can adopt a polar tetragonal phase in the temperature range from approximately 5 °C to approximately 120 °C.

[0055] [No.] [3B] [Figure] illustrates a polar tetragonal crystal structure 320 in BaTiO3 within a temperature range of approximately 5°C to approximately 120°C. The polar tetragonal crystal structure 320 can be formed upon cooling from the Curie temperature. The formation of the tetragonal structure allows for permanent polarization of the unit cell, which can lead to spontaneous polarization along the c-axis, which can be parallel to the six equivalent polarizations in the cubic crystal structure 310. <100> Any one of the axes. Therefore, a polar tetragonal phase can have 6 stable polarization directions parallel to the edge of the unit cell, resulting in 6 dissimilar crystal variants.

[0056] [No.] [3C] [Figure] Illustrate the orthorhombic crystal structure 330 of BaTiO3 in a temperature range from about -90°C to about 5°C. As shown in Figure 3C, after further cooling below about 5°C, the unit cell of BaTiO3 can be separated by the following diagonal lines ( <110> The direction 332 is further elongated and twisted, and the tetragonal crystal structure 320 can be changed into an orthorhombic crystal structure 330. Twelve equivalent crystal structures can exist in the cubic crystal structure 310. <110> The orientation can lead to 12 possible polar orientations in the orthorhombic phase. The orthorhombic phase can be stable from about 5°C down to about -90°C.

[0057] [No.] [3D] [Figure] Illustrate the orthorhombic hexahedral crystal structure 340 in BaTiO3 at temperatures below approximately -90°C. As shown in Figure 3D, upon further cooling below approximately -90°C, the unit cell of BaTiO3 undergoes changes along the body diagonal ( <111> Another twist in direction 342 results in an orthorhombic hexahedral symmetry structure. This can exist along the cubic crystal structure 310. <111> The eight equivalent polar directions in the orthorhombic hexahedral phase of the direction.

[0058] Therefore, bulk BaTiO3 crystals can transform from a tetragonal phase at room temperature to an orthorhombic phase at approximately 270 K or below, and subsequently to an orthorhombic hexahedral phase at approximately 180 K or below. Such crystal structures and phase transitions are observed in many perovskite ferroelectrics. Phase transitions can alter the elements of the Burkes tensor and modify the order of magnitude of the effective Burkes coefficients.

[0059] As described above, crystal structure and phase transitions can also influence the available polarization directions. At the microstructural level, regions with uniform electrical polarization can form domains, where each domain comprises a single crystal variant. The interfaces between domains are called domain walls. Ferroelectric crystals can employ stable minimum energy configurations of domains and domain walls. In many cases, the overall minimum is unattainable and the stable state can be a local energy minimum, and energy minimization can result in crystals with multiple domains separated by domain walls, which are oriented to minimize energy by maintaining compatibility of strain and polarization across the walls.

[0060] Therefore, the Burkes coefficient of the EO material at extremely cold temperatures can be improved by maintaining the room-temperature crystal structure and polarization orientation at extremely cold temperatures. For example, according to some embodiments, the EO material layer may include interleaved and interlocked thin EO material layers and interlayers. The interlayers may have a lattice structure that does not change at the operating temperature. Thus, when the operating temperature changes as described above with respect to Figures 3A to 3D, the thin EO material layers interlocked to the interlayers can maintain their lattice structure and polarization orientation, and therefore the EO coefficient, without undergoing a phase transition.

[0061] [No.] [4] [Figure] is a simplified flowchart 400 illustrating an example of a method for manufacturing an EO device including an EO material layer according to certain embodiments, the EO material layer being characterized by a substantially constant EO coefficient from room temperature to extremely cold temperatures. Although Figure 4 describes the operations in a sequential flow, some of the operations may be performed in parallel or concurrently. Some operations may be performed in a different order. Operations may have additional steps not included in the figure. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with another operation.

[0062] At block 410, a seed layer (e.g., seed layer 156) may be deposited on a substrate (e.g., substrate 152). As described above, the substrate may be a semiconductor wafer, such as a single-crystal silicon wafer, germanium wafer, silicon-on-germanium wafer, silicon-on-insulator (SOI) wafer, etc. The substrate may include semiconductor wafers of various sizes, such as 4-inch, 6-inch, 8-inch, 10-inch, 12-inch, or larger. Generally, it is desirable to use larger wafers to improve productivity. For example, a 12-inch silicon wafer may be used as a substrate.

[0063] The seed layer may have a lattice structure similar to that of the EO material used in an EO device, and may include, for example, SrTiO3 (STO), MgO, or LaAlO3. The seed layer may be epitaxially deposited or grown on a substrate using, for example, molecular beam epitaxy (MBE). In one embodiment, Sr and Ti may be deposited on the surface of a silicon wafer in an oxygen environment to form an amorphous SrTiO3 layer, and the amorphous SrTiO3 layer may be crystallized at a higher temperature to form an epitaxial SrTiO3 layer. The lattice mismatch between Si and STO may be about 2%, and high-quality STO may be most in sync with silicon when the thickness of the STO layer is less than, for example, about 5 nm.

[0064] [No.] [5A] [Figure] illustrates an example of a substrate 510 (e.g., a semiconductor wafer) having an epitaxial seed layer 520 according to certain embodiments. In the example shown in Figure 5, the substrate 510 may include a silicon or SOI wafer. The epitaxial seed layer 520 may include a homogeneous epitaxial STO layer, which may have a thickness of, for example, a few nanometers or tens of nanometers, such as less than about 8 nm or less than about 5 nm.

[0065] Referring back to Figure 4, at square 420, a first thin EO material layer can be deposited on the seed layer by, for example, epitaxial deposition. The first thin EO material layer may include, for example, ferroelectric or perovskite ferroelectric materials, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The first thin EO material layer may have a thickness of less than, for example, 100 nm. The lattice mismatch between BTO and silicon may be about 4%, and when the thickness of the BTO layer is less than about 100 nm, the BTO layer may be partially cohomogeneous with the Si / STO layer, which can lead to compressive stress in the BTO layer. Therefore, the first thin EO material layer (e.g., BTO) deposited on the seed layer may exhibit out-of-plane polarization due to compressive stress.

[0066] [No.] [5B] [Figure] illustrates the internal stress and lattice orientation of layer 530 of EO material epitaxially deposited on seed layer 520 according to certain embodiments. As described above, EO materials may include, for example, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. As deposited, layer 530 of EO material (e.g., BTO on STO / Si) may primarily comprise domains having a tetragonal crystal structure 525, wherein the c-direction of the tetragonal crystal structure 525 is perpendicular to layer 530 due to compressive stress as illustrated in Figure 5B (i.e., out-of-plane polarization). Layer 530 may be a thin layer, such as less than 100 nm or thinner, so that the ferroelectric material in layer 530 is locked to an interlayer having a tetragonal crystal structure at low temperatures.

[0067] At block 430 in Figure 4, the substrate, seed layer, and first thin EO material layer may be annealed at a higher temperature, such as above the melting point of SiO2, in an oxygen environment. For example, the annealing temperature may be higher than 600°C, such as 750°C or higher. High-temperature annealing helps release stress and forms a buffer layer at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). The buffer layer may include an oxide layer, such as a SiO2 layer. For example, silicon at the interface between the substrate and the seed (e.g., STO) layer may be oxidized at a high-temperature annealing temperature and in an oxygen environment to form a SiO2 layer. When the annealing temperature is higher than the melting point of the buffer layer (e.g., about 600°C), the buffer layer (e.g., SiO2) may soften, and thus the seed layer and the first thin EO material layer may be decoupled from the substrate and stress in the seed layer and the first thin EO material layer may be released. Therefore, the stress in the EO material (e.g., BTO) can be transformed from compressive stress into intrinsic stress during high-temperature annealing due to the softening of SiO2, and the quality of the seed layer and the first thin EO material layer can be improved.

[0068] There can be a large difference in the coefficient of thermal expansion (CTE) between BTO (e.g., about 3.5E-6 / ℃) and silicon (e.g., about 2.6E-6 / ℃) at high temperatures. Therefore, when the buffer layer (e.g., SiO2) hardens below 550℃ during cooling, the large CTE difference between silicon and BTO can cause the stress in BTO to undergo a transformation from intrinsic stress to tensile stress. Consequently, at room temperature, the net or dominant stress in BTO can change from compressive stress to tensile stress, which can change the polarization from out-of-plane polarization to in-plane orientation. Therefore, the annealing temperature can be selected so that BTO can exhibit in-plane polarization after cooling under tensile stress and due to the stress caused by the large difference in CTE between BTO and silicon.

[0069] [No.] [5C] [Figure] illustrates the internal stress and lattice orientation of a layer 530 of EO material epitaxially deposited on a seed layer 520 after high-temperature oxidation annealing, according to certain embodiments. As illustrated, due to the tensile stress in layer 530 after annealing as described above, the ferroelectric material (e.g., BTO on STO / Si) layer 530 may primarily comprise domains having a tetragonal crystal structure 535, wherein the c-direction of the tetragonal crystal structure 535 is parallel to layer 530 (i.e., in-plane polarization). Figure 5C also shows a buffer layer 540, such as an oxide layer (e.g., SiO2) formed by oxidation of the substrate during high-temperature oxidation annealing.

[0070] [No.] [6] [Figure] This illustrates the improved crystal quality after annealing of an example of an epitaxial layer (e.g., a SrTiO3 epitaxial layer) measured using Rashof Backscattering Spectroscopy (RBS) according to certain embodiments. In the RBS / channel, atoms displaced from their lattice sites can interact with the channel beam, resulting in an increase in scattering yield. Curve 610 in Figure 6 shows the total number (energy of the backscattered particles) detected in different channels of backscattering from the SrTiO3 epitaxial layer before annealing. As illustrated, before annealing, the SrTiO3 epitaxial layer comprises many displaced Sr and Ti atoms. Curve 620 in Figure 6 shows the total number of backscattered particles detected in different channels of backscattering from the SrTiO3 epitaxial layer after annealing. Curve 620 shows a significant reduction in the number or percentage of displaced Sr and Ti atoms, and thus a significant improvement in the quality of the crystallized SrTiO3 epitaxial layer. Although not shown in Figure 6, the quality of the BTO epitaxial layer can be similarly improved by the annealing process.

[0071] [No.] [7] [Figure] This illustrates an example of X-ray diffraction data showing the relaxation of the heterogeneous lattice constant of an epitaxial layer (e.g., a SrTiO3 epitaxial layer) at high temperatures. The SrTiO3 epitaxial layer can be deposited on a silicon wafer, for example, using MBE. Figure 7 shows that at temperatures below approximately 600°C, the heterogeneous thermal lattice expansion can be a linear function of temperature. The heterogeneous lattice constant can begin to relax at approximately 600°C, indicating that STO is under compressive stress below approximately 600°C, and that the compressive stress can be released at temperatures above 600°C.

[0072] Referring back to Figure 4, at square 440, a thin interlayer can be deposited on the first EO material layer (e.g., a BTO layer), and a thin EO material layer (e.g., another BTO layer) can be deposited on the interlayer. The interlayer and EO material layers can also be annealed using the high-temperature oxidation annealing described above to relax the BTO, improve crystal quality, and ensure in-plane polarization in the thin BTO layer. The thin interlayer and thin EO material layers can be alternately deposited and annealed in each of multiple process cycles to form an interleaved and interlocked stack of interlayer and EO material layers until the total thickness of the EO material layers reaches the target thickness.

[0073] In various embodiments, the interlayer may comprise a crystal structure similar to that of EO materials and may not undergo a phase transition at low temperatures. Thus, at extremely cold temperatures, the interlayer may have a crystal structure similar to the room-temperature crystal structure of EO materials. The interlayer may comprise certain oxides, such as, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrZrO3, or other oxides having a lattice constant close to that of the tetragonal crystal structure of BTO. The interlayer may restrict the transformation of BTO from its tetragonal phase at room temperature to other phases at lower temperatures.

[0074] [No.] [5D] [Figure] illustrates the internal stress and lattice orientation of interlayered EO material layers in an example of an engineered wafer 500 according to certain embodiments. In the example shown in Figure 5D, the engineered wafer 500 may include a substrate 510 (e.g., a silicon wafer), a buffer layer 540 (e.g., a SiO2 buffer layer), a seed layer 520 (e.g., an STO layer having a thickness of less than about 8 nm), and a plurality of thin EO material layers 530, 532, 534, etc., such as thin BTO layers each having a thickness of less than about 100 nm. Between the plurality of thin EO material layers 530, 532, and 534 are a plurality of interlayers 550, 552, etc., such as layers of MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrZrO3, SrNbO3, or other oxides. Each interlayer 550 or 552 may have a thickness of less than, for example, about 10 nm, and may be used to separate thin BTO layers from each other and to impose tensile stress on the thin BTO layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each interlayer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. The net or dominant stress in the EO material layer may be tensile stress. As described above, the stack of layers including staggered interlayers and thin EO material layers may have been annealed in a high-temperature annealing process to relax the EO material, improve material quality, and ensure in-plane polarization in the EO material layer as shown by the tetragonal crystal structure 535 (e.g., the c-axis of the crystal structure is parallel to the EO material layer).

[0075] As described above, the stacking of interleaved and interlocked thin EO material layers and interlayers (e.g., BTO / MgO stacks) can maintain tensile stress in the EO material at low temperatures, thus maintaining the tetragonal crystal structure of the EO material at low temperatures (e.g., extremely cold temperatures) due to tensile stress. Therefore, the EO effect, such as the Burkes effect, of the EO material at extremely cold temperatures can be close to the Burkes effect of the EO material at room temperature.

[0076] At block 450, the waveguide can be formed on or bonded to a stack of staggered thin EO material layers and interlayers. For example, in some embodiments, waveguide layers such as silicon, SiGe, or Si3N4 layers can be deposited directly on the stack. The silicon, SiGe, or Si3N4 layers can be patterned using photolithography to form the waveguide core, and a cladding layer (also called a capping layer) can then be deposited on the waveguide core to form the waveguide. The silicon, SiGe, or Si3N4 layers can also be deposited indirectly on the stack with an intermediate buffer layer. The buffer layer prevents interaction between the waveguide core and the EO material and / or acts as an etch stop layer for patterning the waveguide layer. In some embodiments, the waveguide core and the upper and / or lower cladding layers may be formed on a second substrate and subsequently bonded to a stack of interleaved thin EO material layers and interlayers (e.g., engineering wafer 500), wherein the substrate of engineering wafer 500 may later be removed by, for example, horizontal wet etching (e.g., using a sacrificial layer) or other lift-off techniques such as laser lift-off. In some embodiments, some of the thin EO material layers may be used to form the waveguide core.

[0077] The cladding layer of the waveguide may include a dielectric material or an EO material having a refractive index lower than that of the waveguide core. The cladding layer may include, for example, Si3N4, oxides (e.g., SiO2, Al2O3, and MgO), high-κ materials (e.g., hafnium oxide (HfO2), etc.). In some embodiments, an amorphous dielectric cladding layer with compressive stress (e.g., Si3N4, SiO2, Al2O3, etc.) may be deposited at temperatures below about 550°C on a stack of staggered thin EO material layers and interlayers. The cladding layer may apply tensile stress to the stack of staggered thin EO material layers and interlayers to further maintain the tetragonal phase of the EO material. The cladding layer may also be used as a dielectric layer for wafer-to-wafer or die-to-wafer bonding. In some embodiments, the cladding layer may be used as an etch stop layer for certain etch processes. Examples of waveguide structures and EO device configurations using stacks of staggered thin EO material layers and interlayers are described in detail below.

[0078] [No.] [5E] [Figure] illustrates the layer stress and lattice orientation of the EO material interleaved with the waveguide structure 505 according to certain embodiments. As illustrated, the waveguide core 560 may be adjacent to the engineered wafer 500 and may be covered by a waveguide cladding layer 570. The waveguide cladding layer 570 may include an amorphous dielectric cladding layer (e.g., Si3N4, SiO2, Al2O3, etc.) and may apply tensile stress to the stack of thin EO material layers to maintain the tetragonal phase of the EO material at low temperatures. For example, SiO2 and BTO may have very different CTE characteristics at low temperatures (e.g., cryogenic temperatures), wherein the CTE of SiO2 may become negative at low temperatures (i.e., expand as the temperature decreases). Thus, when cooled to cryogenic temperatures, the SiO2 cladding layer may apply tensile stress to the BTO layer due to the large difference in CTE between the BTO layer and the SiO2 cladding layer. Therefore, the dominant stress in the EO material layer may be tensile stress at temperatures ranging from room temperature to cryogenic temperatures. Therefore, the EO material layer can maintain a tetragonal crystal structure and in-plane polarization, wherein the c-axis of the crystal structure can be parallel to the EO material layer.

[0079] At block 460, electrical connections can be made to the stacked EO material layers to apply voltage signals to them. For example, trenches can be etched into the cladding layer and extend through the stacked EO material layers. A thin conductive liner material, such as TiN or Ti and TiN, can first be coated on the trench sidewalls to promote adhesion and prevent diffusion. Subsequently, a conductive electrode material (e.g., W or Co) can fill the trenches to form electrodes for the EO device. Alternatively, a conductive barrier material (e.g., TaN) and a liner (e.g., Ta, Co, or Ru) can first be coated on the trench sidewalls to deposit Cu conductive electrodes. In this way, each of the EO material layers can contact an electrode and receive a voltage signal to change the refractive index of the EO material layer due to the electric field induced by the voltage signal.

[0080] [No.] [8] [Figure] is a simplified cross-sectional view of an example of a waveguide structure 800 according to certain embodiments, including EO material layers capable of maintaining a tetragonal crystalline phase at extremely cold temperatures. The waveguide structure 800 may include a first portion 802 and a second portion 804 bonded together, for example, by wafer-to-wafer fusion bonding. The first portion 802 may include a stack of thin EO material layers 830, 832, 834, and 836 interleaved with interlayers 840, 842, and 844. As described above with respect to Figures 4 and 5B through 5D, the EO material layers 830, 832, 834, and 836 may include ferroelectric crystals such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. The interlayers 840, 842, and 844 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides.

[0081] The EO material layers and interlayers can be formed alternately, such that the EO material layers and interlayers can be staggered and interlocked to form a staggered stack of layers. The EO material layers and interlayers can be thin layers, wherein the ratio between the thickness of each EO material layer and the thickness of each interlayer can be less than about 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer can be about 100 nm or less, and the thickness of each interlayer can be about 10 nm or less. The total thickness of the multiple EO material layers in the stack can be greater than a certain value, such as greater than about 300 nm. The staggered stack of layers can be formed on a seed layer 820, which can then be deposited on, for example, a semiconductor substrate (e.g., a silicon substrate) (not shown in Figure 8), as described above. A buffer layer 810 can be formed between the seed layer 820 and the semiconductor substrate using, for example, a high-temperature oxidation annealing process described above.

[0082] Part 804 may include a waveguide formed on a substrate 860, which may be a semiconductor substrate (e.g., a silicon-treated wafer) or a glass, quartz, ceramic, or metal substrate. The waveguide may include a waveguide core 870 and a waveguide cladding layer 880. The waveguide core 870 may include a material with a high refractive index, such as silicon, SiN, SiGe, etc. The waveguide cladding layer 880 may include a dielectric material having a refractive index lower than that of the waveguide core 870. The waveguide cladding layer 880 may include an amorphous dielectric cladding layer such as Si3N4, SiO2, Al2O3, MgO, SiON, SiCN, SiCON, SiCO, etc. The waveguide cladding layer 880 may be used as a dielectric layer for wafer-to-wafer bonding and die transfer. When bonded to the first portion 802, the waveguide cladding layer 880 can apply tensile stress to the stack of interleaved thin EO material layers and interlayers to maintain the tetragonal phase of the EO material at the low temperatures described above. The second portion 804 of the waveguide structure 800 may also include other passive or active devices formed on top of the substrate 860.

[0083] After the first portion 802 and the second portion 804 are bonded together, the semiconductor substrate on which the stacked thin EO material layers 830, 832, 834, and 836 and the interlayer layers 840, 842, and 844 are formed can be thinned or removed by means of, for example, back polishing, back grinding, horizontal wet etching, lift-off techniques (e.g., laser lift-off). The trench can then be etched down in the first portion 802 from the buffer layer 810 side to the interface between the first portion 802 and the second portion 804, wherein the waveguide cladding layer 880 can be used as an etch stop layer for the etching process. Conductive materials such as Ti, TiN, and TaN can be deposited together with electrode metals (e.g., Cu, W, Co, etc.) to fill the trench and form the electrode 850.

[0084] Electrode 850 can be used to apply voltage signals to thin EO material layers 830, 832, 834, and 836 via edge contacts rather than surface contacts. Edge contacts can apply voltage signals directly to the EO material layers without passing through interlayers, which may have a dielectric constant different from that of the EO material. For example, MgO may have a lower dielectric constant than BTO. Therefore, edge contacts can help eliminate field interference caused by differences in dielectric constants through the interlayers. In some embodiments, the interlayer (e.g., a BST layer) may have a dielectric constant similar to that of the EO material (e.g., BTO), and surface contacts can be used to apply voltage signals to the EO material layers.

[0085] [No.] [9] [Figure] is a simplified cross-sectional view of another example of a waveguide structure 900 according to certain embodiments, including an EO material layer capable of maintaining a tetragonal crystalline phase at extremely cold temperatures. The waveguide structure 900 may include a substrate 910, which may be similar to substrate 152 or 510 described above. In one example, substrate 910 includes a large (e.g., 12'') silicon wafer. The waveguide structure 900 may also include a buffer layer 922 and a seed layer 920 on substrate 910. Buffer layer 922 may be similar to buffer layers 154, 540, or 810 described above. One example of buffer layer 922 is a SiO2 layer. Seed layer 920 may be similar to seed layers 156, 520, or 820 described above. One example of seed layer 920 is an STO layer. As described above, the buffer layer 922 can be formed by high-temperature oxidation annealing of a seed layer 920 deposited on a substrate 910 (e.g., a silicon wafer), wherein the substrate 910 can be oxidized at the interface between the seed layer 920 and the substrate 910 to form the buffer layer 922 between the seed layer 920 and the substrate 910.

[0086] Waveguide structure 900 may include multiple EO material layers 930, 932, 934, etc., and multiple interlayers 940, 942, etc. As described above, EO material layers 930, 932, and 934 may include ferroelectric crystals, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. Intercalation layers 940 and 942 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides. EO material layers and intercalation layers may be alternately deposited on top of seed layer 920, such that the EO material layers and intercalation layers are staggered and interlocked to form a stack of staggered layers. EO material layers and intercalation layers may be thin layers, wherein the ratio between the thickness of each EO material layer and the thickness of each intercalation layer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer may be about 100 nm or less, and the thickness of each intercalation layer may be about 10 nm or less. The total thickness of the multiple EO material layers in the stack may be greater than a certain value, such as greater than about 300 nm.

[0087] The waveguide, including a waveguide core 950 and a cladding layer 960, can be formed on a stack of interlaced layers as described above with respect to, for example, block 450 in Figure 4 and Figure 5E. The waveguide core 950 may include, for example, Si, SiGe, or SiN, and the cladding layer 960 may include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, HfO2, etc.

[0088] The trench can then be etched down from the cladding layer 960 to the seed layer 920 or buffer layer 922 in a stack of cladding layers 960 and staggered layers. This buffer layer can be used as an etch stop layer for the etching process. A conductive material such as a metal (e.g., Cu, W, Co, etc.) can be deposited or otherwise filled into the trench to form electrode 970. As described above with respect to Figure 8, electrode 970 can be used to apply voltage signals to EO material layers 930, 932, and 934 via edge contacts rather than surface contacts to avoid field interference caused by interlayers 940 and 942, which may have a dielectric constant different from that of EO material layers 930, 932, and 934.

[0089] [No.]

[10] [Figure] is a simplified cross-sectional view of yet another example of a waveguide structure 1000 according to certain embodiments, including an EO material layer capable of maintaining a tetragonal crystalline phase at extremely cold temperatures. The waveguide structure 1000 may include a substrate 1010, which may be similar to substrates 152, 510, or 910 described above. The waveguide structure 1000 may also include a buffer layer 1022 and a seed layer 1020 on the substrate 1010. The buffer layer 1022 may be similar to buffer layers 154, 540, 810, or 922 described above. One example of the buffer layer 1022 is a SiO2 layer. The seed layer 1020 may be similar to seed layers 156, 520, 820, or 920 described above. One example of the seed layer 1020 is an STO layer. As described above, the buffer layer 1022 can be formed by high-temperature oxidation annealing of the seed layer 1020 deposited on the substrate 1010 (e.g., silicon wafer), wherein the substrate 1010 can be oxidized at the interface between the seed layer 1020 and the substrate 1010 to form the buffer layer 1022 between the seed layer 1020 and the substrate 1010.

[0090] The waveguide structure 1000 may include multiple EO material layers 1030, 1032, 1034, 1036, etc., and multiple interlayers 1040, 1042, 1044, etc. As described above, the EO material layers 1030, 1032, 1034, and 1036 may include ferroelectric crystals, such as BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), (Pb(Zr,Ti)O3 (PZT), (Pb,La)(Zr,Ti)O3 (PLZT), etc. Intercalation layers 1040, 1042, and 1044 may include, for example, MgO, BST, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, or other oxides. EO material layers and intercalation layers may be alternately deposited on top of seed layer 1020, such that the EO material layers and intercalation layers are staggered and interlocked to form a stack of staggered layers. EO material layers and intercalation layers may be thin layers, wherein the ratio between the thickness of each EO material layer and the thickness of each intercalation layer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. In one example, the thickness of each EO material layer may be about 100 nm or less, and the thickness of each intercalation layer may be about 10 nm or less. The total thickness of the multiple EO material layers in the stack may be greater than a certain value, such as greater than about 300 nm.

[0091] The waveguide structure 1000 may further include a waveguide, which includes a cladding layer 1050 and a waveguide core, the waveguide core including some of the interleaved layers. In the example shown in Figure 10, the waveguide core may include EO material layers 1034 and 1036 and interlayers 1042 and 1044, which may be patterned by, for example, photolithography. In some embodiments, interlayers 1044 and 1042 may be used as etch-stop layers for etching EO material layers 1034 and 1036. For example, interlayer 1044 may be used as an etch-stop layer for etching EO material layer 1036 using a first formulation, interlayer 1044 may then be etched using a second formulation, and interlayer 1042 may be used as an etch-stop layer for etching EO material layer 1034 using the first formulation. In this way, the waveguide core may be formed as a platform structure including some EO material layers and interlayers.

[0092] The cladding layer 1050 may be formed on the waveguide core as described above with respect to, for example, block 450 of Figure 4 and Figure 5E. The cladding layer 1050 may include, for example, Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, HfO2, etc. Trenches may be etched down from the cladding layer 1050 to a seed layer 1020 or a buffer layer 1022 in some of the layers in the stack of cladding layer 1050 and interleaved layers. This buffer layer may serve as an etch stop layer for etching trenches. A conductive material such as a metal (e.g., Cu, W, Co, etc.) may be deposited or otherwise filled into the trenches to form electrodes 1060. As described above, electrodes 1060 may be used to apply voltage signals to EO material layers 1030 and 1032 via edge contacts, and / or to EO material layers 1034 and 1036.

[0093] The waveguide structures 800, 900, and 1000 described above may each include a stack of interleaved layers, which include alternating EO material layers and interlayers. The EO material layers and interlayers may be thin and may have similar lattice structures at room temperature, and thus may be interlocked after the manufacturing process. The interlayer may include a material that does not undergo a phase transition when the operating temperature changes. Therefore, when the operating temperature changes, for example, to an extremely cold temperature, the interlocking between the thin EO material layer and the interlayer prevents a phase transition in the EO material layer. Thus, the EO material layer can substantially maintain its room-temperature lattice structure (e.g., tetragonal phase) and polarization (e.g., in-phase polarization) and consequently EO effects (e.g., Burkes coefficients) at extremely cold temperatures. Waveguide structures 800, 900, and 1000 can be used in optical switches such as the Mach-Chenld interferometer 120 or optical switch 100 described above, EO modulators, or other active photonic devices that operate at low temperatures using phase adjustment or refractive index modulation.

[0094] In the various embodiments of the waveguide structures and EO devices disclosed herein, a single lateral mode waveguide (e.g., having a waveguide core width in the submicron to micron range) or a multimode waveguide (having a wider waveguide core supporting two or more lateral modes) can be utilized. Various materials, layers, and structures can be formed using, for example, epitaxial growth, deposition, layer transfer, etc., to fabricate the EO device. Although techniques for modifying the Burkes effect at extremely cold temperatures are described in some embodiments, the techniques disclosed herein can be used to modify other EO effects at different temperatures. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0095] [No.]

[11] [Figure] is a simplified flowchart 1100 illustrating an example of a method for manufacturing an engineering wafer and / or an EO device comprising an EO material layer characterized by a substantially constant EO coefficient from room temperature to extremely cold temperatures, according to certain embodiments. Although Figure 11 describes the operations in a sequential flow, some of the operations may be performed in parallel or concurrently. Some operations may be performed in a different order. Operations may have additional steps not included in the figure. Some operations may be optional and therefore may be omitted in various embodiments. Some operations may be performed together with another operation.

[0096] At block 1110, the operation may include depositing a seed layer on a substrate. The substrate may include, for example, a semiconductor substrate (e.g., a silicon wafer), a glass substrate, a quartz substrate, a ceramic substrate, etc., as described above. The seed layer may be epitaxially grown on the substrate using, for example, MBE technology, and may include, for example, SrTiO3 (STO), MgO, or LaAlO3.

[0097] At block 1120, the operation may include epitaxially depositing a first electro-optic material layer onto the seed layer using, for example, MBE technology. The seed layer may have a lattice structure similar to that of the first EO material layer and / or the substrate, and may include, for example, ferroelectric or perovskite ferroelectric materials, such as BTO, BST, PZT, PLZT, etc. The material in the first EO material layer may have a tetragonal lattice structure at room temperature, and when used in bulk, its lattice structure and crystalline phase may be altered at low temperatures. The first EO material layer may have a thickness of less than, for example, 100 nm.

[0098] At block 1130, the operation may include annealing the substrate, seed layer, and first electro-optic material layer in an oxygen environment to form an oxide buffer layer between the substrate and the seed layer. Annealing may be performed at a temperature, for example, above the softening temperature of the oxide buffer layer, such as above 600°C (e.g., 750°C or higher). High-temperature annealing can help form an oxide buffer layer (e.g., SiO2) at the interface between the substrate (e.g., Si) and the seed layer (e.g., STO). When the annealing temperature is above the softening temperature of the oxide buffer layer, the oxide buffer layer can soften, and thus the seed layer and the first EO material layer can be decoupled from the substrate and stress in the seed layer and the first EO material layer can be released.

[0099] At block 1140, the operation may include depositing a first interlayer on the first electro-optic material layer. The first interlayer may include a crystal structure similar to that of the first EO material layer and may not undergo a phase transition at low temperatures. Thus, the first interlayer may include a material that can maintain the first lattice structure at room temperature and extremely cold temperatures (e.g., at about 4 K). The first interlayer may include at least one of, for example, MgO, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrNbO3, SrTiO3, SrZrO3, etc.

[0100] At block 1150, the operation may include depositing a second electro-optic material layer on the first interlayer. The second electro-optic material layer may be similar to the first electro-optic material layer. At block 1160, the operation may include annealing the second electro-optic material layer and the first interlayer in a high-temperature annealing process to relax the second EO material layer, improve material quality, and ensure in-plane polarization in the second EO material layer.

[0101] In some embodiments, the additional interlayer and EO material layer may be deposited alternately until the total thickness of the EO material layer is greater than a desired value. In some embodiments, the additional layer including the staggered interlayer and EO material layer may be annealed in a high-temperature annealing process. The first, second, and additional interlayers may have a thickness of less than, for example, about 10 nm, and may be used to separate the EO material layers from each other and to impose tensile stress on the EO material layers to limit phase transitions in the EO material layers. In some embodiments, the ratio between the thickness of each EO material layer and the thickness of each interlayer may be less than about 20:1, 10:1, 8:1, 5:1, or lower. Because the interlayers may not change their lattice structure and crystalline phase at lower temperatures (e.g., cryogenic temperatures), the interlayers can limit the EO material layers from changing their room-temperature lattice structure and crystalline phase at lower temperatures. Thus, the EO material layer may have a high EO effect (e.g., the Burkes effect) at lower temperatures. For example, the EO material layer may include BTO and may have a Burkes coefficient greater than 300 pm / V at cryogenic temperatures.

[0102] Optionally, at block 1170, the waveguide may be formed on a stack of interleaved interlayers and EO material layers. The waveguide may be a segment of a Mach-Chenld interferometer, resonator, optical switch, electro-optic modulator, etc. In some embodiments, the waveguide may include a waveguide core comprising a dielectric material or a semiconductor material, or one or more electro-optic material layers. In some embodiments, the waveguide may include a waveguide cladding layer that is in solid contact with one of the plurality of electro-optic material layers and may be characterized by a coefficient of thermal expansion different from that of the electro-optic material layers. The waveguide cladding layer may include, for example, at least one of Si3N4, SiO2, Al2O3, MgO, SiCN, SiON, SiCO, SiOCN, or HfO2.

[0103] In some embodiments, the step of forming a waveguide may include patterning one or more electro-optic material layers to form a waveguide core, and depositing a dielectric cladding layer on the waveguide core. The step of patterning one or more electro-optic material layers may include using an interlayer as an etch stop layer to etch one or more electro-optic material layers. In some embodiments, the step of forming a waveguide may include depositing a layer of high refractive index material on a stack of layers including an interlayer and an EO material layer, patterning the high refractive index material layer to form a waveguide core, and depositing a dielectric cladding layer on the waveguide core. In some embodiments, the step of forming a waveguide may include bonding a wafer including the waveguide to a stack of layers including an interlayer and an EO material layer. In some embodiments, the method may also include etching trenches in the stack of layers including the interlayer and EO material layers, and filling the trenches with a conductive material. In some embodiments, the step of etching trenches in the stack of layers may include using an oxide buffer layer as an etch stop layer.

[0104] [No.]

[12] [Figure] is a simplified system block diagram of an example of a hybrid quantum computing system 1200 including an electro-optical device (e.g., a switch) according to certain embodiments. For operation at cryogenic temperatures, such as liquid helium temperatures, embodiments of the invention integrate the electro-optical switch discussed herein into a system including a cooling system. Thus, embodiments of the invention provide hybrid computing systems, for example, as illustrated in Figure 12. The hybrid quantum computing (QC) system 1200 includes a user interface device 1204 communicatively coupled to a hybrid quantum computing subsystem 1206. The user interface device 1204 can be any type of user interface device, such as a terminal including a display, keyboard, mouse, touchscreen, etc. Additionally, the user interface device itself can be a computer such as a personal computer (PC), laptop, tablet, etc.

[0105] In some embodiments, user interface device 1204 provides an interface through which a user can interact with hybrid QC subsystem 1206. For example, user interface device 1204 may run software such as a text editor, interactive development environment (IDE), command prompt, graphical user interface, etc., allowing the user to program or otherwise interact with the QC subsystem to run one or more quantum algorithms. In other embodiments, hybrid QC subsystem 1206 may be pre-programmed and user interface device 1204 may simply provide an interface for the user to initiate quantum computing, monitor progress, and receive results from hybrid QC subsystem 1206. Hybrid QC subsystem 1206 further includes classical computing system 1208 coupled to one or more quantum computing chips 1210. In some instances, classical computing system 1208 and quantum computing chips 1210 may be coupled to other electronic components 1212, such as pulsed pump lasers, microwave oscillators, power supplies, networking hardware, etc.

[0106] In some embodiments utilizing ultracold operation, the quantum computing system 1209 may be housed within an ultracold cryostat, such as ultracold cryostat 1214. In some embodiments, the quantum computing chip 1210 may include one or more constituent chips, such as a hybrid electronics chip 1216 and an integrated photonic chip 1218, which may include various waveguide structures and / or EO devices disclosed herein. Signals may be routed on and off the chip in many ways, such as via optical interconnects 1220 and other electronic interconnects 1222. Additionally, the hybrid quantum computing system 1200 may utilize quantum computing processes, such as measurement-based quantum computing (MBQC) utilizing one or more cluster states of qubits.

[0107] Those familiar with this technology will readily recognize that substantial variations can be made depending on the specific implementation. For example, custom hardware may be used, and / or specific components may be implemented in hardware, software (including portable software, such as small applications, etc.), or both. Furthermore, connections to other computing devices, such as network input / output devices, can be utilized.

[0108] Referring to the accompanying drawings, components that may include memory may include non-transitory machine-readable media. As used herein, the terms "machine-readable media" and "computer-readable media" represent any storage medium involved in providing data that enables a machine to operate in a particular manner. In the embodiments provided above, various machine-readable media may relate to providing instructions / code to a processor and / or other means(s) for execution. Alternatively or additionally, machine-readable media may be used to store and / or carry such instructions / code. In many implementations, computer-readable media are physical and / or tangible storage media. This media may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and / or optical media, punched cards, paper tape, any other physical media having a perforated pattern, RAM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash EPROM, any other memory chip or cartridge, a carrier wave as described below, or any other media from which a computer can read instructions and / or codes.

[0109] The methods, systems, and apparatuses discussed herein are examples. Various embodiments may be omitted, substituted, or have various programs or components added as appropriate. For example, features described with respect to certain embodiments may be combined in various other embodiments. Different forms and elements of embodiments may be combined in a similar manner. The various components of the figures provided herein may be embodied in hardware and / or software. Furthermore, as technology evolves, many elements are examples that do not limit the scope of this disclosure to those particular embodiments.

[0110] It has been shown that, sometimes, primarily for the sake of common use, such signals are conveniently referred to as bits, information, values, elements, symbols, characteristics, variables, terms, numbers, digits, etc. However, it should be understood that all such or similar terms are associated with appropriate physical quantities and are merely convenient notations. Unless otherwise specifically stated, it will be understood from the foregoing discussion that throughout this specification, the use of terms such as "processing," "operation," "calculation," "decision," "determination," "identification," "association," "measurement," "execution," etc., refers to the operation or process of a specific device such as a special purpose computer or similar special purpose electronic computing device. Therefore, in the context of this specification, a special purpose computer or similar special purpose electronic computing device can manipulate or transform signals that are generally represented as physical electronic, electrical, or magnetic quantities within the memory, registers, or other information storage, transmission, or display devices of the special purpose computer or similar special purpose electronic computing device.

[0111] Those skilled in this art will understand that the information and signals used to convey the messages described herein can be represented using any of the various processes and technologies described above. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced in the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0112] As used herein, the terms "and," "or," and "and / or" can have a variety of meanings, which are expected to be relied upon at least in part by the context in which such terms are used. Generally, "or," when used in relation to a list such as A, B, or C, is intended to mean A, B, and C as included herein, and A, B, or C as excluded herein. Additionally, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and the claimed object is not limited to this example. Furthermore, the term "at least one of..." when used in relation to a list such as A, B, or C, can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0113] Throughout this specification, references to "an example," "a particular example," "some examples," or "exemplary examples" refer to specific features, structures, or characteristics described in conjunction with features and / or examples, which may be included in at least one feature and / or example of the claimed object. Therefore, the phrases "in an example," "a particular example," "some examples," "some implementations," or other similar expressions appearing throughout this specification in various places do not necessarily all refer to the same feature, example, and / or limitation. Furthermore, specific features, structures, or characteristics may be found in combinations of one or more examples and / or features.

[0114] In some implementations, operation or processing may involve the physical manipulation of physical quantities. Typically, though not always, such quantities may take the form of electrical or magnetic signals capable of being stored, transmitted, combined, compared, or otherwise manipulated. It has been shown that, sometimes, primarily for common use, such signals are conveniently referred to as bits, data, values, elements, symbols, characteristics, items, numbers, digits, etc. However, it should be understood that all such or similar terms are associated with the appropriate physical quantity and are merely convenient notations. Unless otherwise specifically stated, as will be apparent from the discussion herein, it will be understood that throughout this specification, the use of terms such as "processing," "operation," "calculation," "decision," etc., refers to the operation or process of a specific device such as a special-purpose computer, a special-purpose computing device, or a similar special-purpose electronic computing device. Therefore, in the context of this specification, a special purpose computer or similar special purpose electronic computing device is capable of manipulating or transforming signals, which generally represent physical, electronic, or magnetic quantities within the memory, register, or other information storage, transmission, or display device of the special purpose computer or similar special purpose electronic computing device.

[0115] In the preceding detailed description, many specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without such specific details. In other instances, methods and apparatus known to those of ordinary skill have not been described in detail so as not to obscure the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, but may also include all forms within the scope of the appended claims and their equivalents.

[0116] 100: Optical switch 105: First 50 / 50 beam splitter 107: Second 50 / 50 beam splitter 110: First Waveguide 112: Second Waveguide 120: Mach-Chander interferometer 122: Phase Adjustment Section 124: Waveguide 126: Electrode 130: Waveguide 132: Waveguide 150: Phase Adjustment Section 152:Substrate 154: Optional Buffer Layer 156: Seed layer 158:EO material layer 160: Waveguide cladding 162: Waveguide Core 164: Electrode 210~240: Curve 310: Cubic crystal structure 320: Polar tetragonal crystal structure 330: Orthorhombic crystal structure 332: Face diagonal ( <110> )direction 340: Orthorhombic hexahedral crystal structure 342: Body diagonal ( <111> )direction 400: Simplified Flowchart 410~460: Square 500: Engineering Wafer 510:Substrate 520: Epitaxial Seed Layer 525: Tetragonal crystal structure 530: Layer / Thin EO material layer 532, 534: Thin EO material layer 535: Tetragonal crystal structure 540: Buffer layer 550, 552: Interlayer 560: Waveguide Core 570: Waveguide cladding 610: Curve 800: Waveguide structure 802: Part One 804: Part Two 810: Buffer layer 820: Seed layer 830, 832, 834, 836: Thin EO material layer 840, 842, 844: Thin interlayer 850: Electrode 860:Substrate 870: Waveguide Core 880: Waveguide cladding 900: Waveguide structure 910:Substrate 920: Seed layer 922: Buffer layer 930, 932, 934: EO material layer 940, 942: Interlayer 950: Waveguide Core 960: Coating layer 970: Electrode 1000: Waveguide structure 1010:Substrate 1020: Seed layer 1022: Buffer layer 1030, 1032, 1034, 1036: EO material layers 1040, 1042, 1044: Interlayer 1050: Coating layer 1060: Electrode 1100: Simplified Flowchart 1110~1170: Square 1200: Hybrid Quantum Computing System 1204: User Interface Device 1206: Hybrid Quantum Computing Subsystem 1208: Classical Computing Systems 1210: Quantum Computing Chip 1212: Other electronic components 1214: Extremely Cold Thermostat 1216: Hybrid Electronic Chips 1218: Integrated Photonic Chip 1220: Optical interconnects 1222: Other electronic interconnects V0: Voltage signal

Claims

1. A hybrid quantum computing system, comprising: a classical computing system; and one or more quantum computing chips coupled to the classical computing system, wherein the one or more quantum computing chips include one or more electro-optic devices, each of the one or more electro-optic devices comprising: One substrate; A buffer layer, coupled to the substrate and configured to at least partially relieve the stress of the plurality of electro-optic material layers; A waveguide is disposed above the substrate; a stack is disposed on top of the waveguide and includes a plurality of electro-optic material layers, the plurality of electro-optic material layers being under tensile stress and characterized by a first lattice structure and a crystalline phase, wherein the electro-optic material layers are interleaved with a plurality of interlayers, the plurality of interlayers being characterized by a second lattice structure; and a waveguide core is disposed on top of a portion of the stack.

2. The hybrid quantum computing system as claimed in claim 1, wherein the plurality of interlayers maintain the second lattice structure at a room temperature and an extremely cold temperature, and wherein the plurality of electro-optic material layers are under tensile stress and maintain the first lattice structure and crystalline phase at the room temperature and the extremely cold temperature.

3. The hybrid quantum computing system as described in claim 1, further comprising at least one electronic component.

4. The hybrid quantum computing system as claimed in claim 3, wherein the at least one electronic component comprises at least one of a pulsed pump laser or a microwave oscillator.

5. The hybrid quantum computing system as claimed in claim 1, wherein each of the one or more quantum computing chips comprises at least one of a hybrid electronic chip or an integrated photonic chip.

6. The hybrid quantum computing system as described in claim 1 further includes a user device communicatively coupled to the classical computing system or at least one of the one or more quantum computing chips.

7. The hybrid quantum computing system as described in claim 1, further comprising: Network hardware coupled to one or more quantum computing chips.

8. The hybrid quantum computing system as described in claim 1, wherein the second lattice structure comprises a tetragonal crystal structure.

9. The hybrid quantum computing system as claimed in claim 1 further includes a cryostat, wherein the one or more quantum computing chips are housed within the cryostat, and the cryostat is configured to operate between approximately 340K and 4K.

10. The hybrid quantum computing system as claimed in claim 1, wherein the plurality of electro-optic material layers comprises at least one of BaTiO3, (Ba,Sr)TiO3, Pb(Zr,Ti)O3, or (Pb,La)(Zr,Ti)O3.

11. The hybrid quantum computing system as claimed in claim 1, wherein the plurality of interlayers comprises at least one of MgO, (Ba,Sr)TiO3, BaHfO3, BaZrO3, SrHfO3, SrZrO3, or SrNbO3.

12. A method for operating a hybrid quantum computing system, the method comprising: Provide a classic computing system; Provided is one or more quantum computing chips coupled to the classical computing system, wherein the one or more quantum computing chips include one or more electro-optic devices, each of the one or more electro-optic devices including: a substrate; a buffer layer coupled to the substrate and configured to at least partially relieve stress on a plurality of electro-optic material layers; a waveguide disposed above the substrate; a layer stack disposed on top of the waveguide and including the plurality of electro-optic material layers under tensile stress and characterized by a first lattice structure and a crystalline phase, wherein the electro-optic material layers are interleaved with a plurality of interlayers, the plurality of interlayers being characterized by a second lattice structure; and a waveguide core disposed on top of a portion of the layer stack; and using the one or more quantum computing chips to perform one or more quantum computing processes.

13. The method as described in claim 12, further comprising: Provide an extremely cold thermostat; And to house one or more quantum computing chips in the ultracold thermostat.

14. The method as described in claim 12, further comprising: The temperature of one or more quantum computing chips is reduced to approximately 4K.

15. The method as described in claim 14, wherein reducing the temperature of the one or more quantum computing chips occurs before performing the one or more quantum computing processes using the one or more quantum computing chips.

16. The method as described in claim 12, further comprising: The temperature of one or more quantum computing chips is raised to approximately 340K.

17. The method of claim 12, wherein the plurality of interlayers maintain the second lattice structure at a room temperature and an extremely cold temperature, and wherein the plurality of electro-optic material layers are under tensile stress and maintain the first lattice structure and crystalline phase at the room temperature and the extremely cold temperature.

18. The method as described in claim 12, further comprising: A user device is provided, which is communicatively coupled to the classical computing system or at least one of the one or more quantum computing chips.

19. The method as described in claim 12, further comprising: Provide network hardware coupled to one or more quantum computing chips.

20. The method as described in claim 19, wherein the network hardware is coupled to the one or more quantum computing chips via a plurality of optical interconnects.

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