Integrated circuit and method for forming integrated circuit

Abstract

An integrated circuit includes a first circuit operating at a first supply voltage; a first power circuit selectively supplying the first supply voltage to the first circuit; a second circuit operating at a second supply voltage; a second power circuit selectively supplying the second supply voltage to the second circuit; a first interconnect structure formed in a first of a plurality of metallization layers above a main surface, wherein the first interconnect structure is used to electrically couple the first power circuit to the first circuit; and a second interconnect structure formed in the first metallization layer, wherein the second interconnect structure is used to electrically couple a second power circuit to the second circuit, wherein the first interconnect structure and the second interconnect structure are electrically isolated from each other by at least one isolation structure.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to an integrated circuit and a method for forming an integrated circuit, particularly to an integrated circuit having an interconnection structure and a method for forming an integrated circuit. Prior Technology

[0002] Integrated circuit (IC) design encompasses a range of techniques for optimizing power management and improving device performance. Power management techniques can be implemented to reduce energy consumption, minimize heat generation, or extend the lifespan of electronic devices. For example, techniques such as dynamic voltage and frequency scaling (DVFS) adjust power supply and operating frequency based on workload for efficient energy use. In some IC (or memory) designs, headers can be partitioned to supply power to different functions, circuits, or devices. Power supply partitioning can be based on the functional division of multiple power regions, such as non-active power (NAP) and switching rails. Adjacent devices or circuits within an IC can share power resources, for example, from the same power lines. Summary of the Invention

[0003] Some embodiments disclosed herein provide an integrated circuit comprising a first circuit, a first power circuit, a second circuit, a second power circuit, a first interconnect structure, and a second interconnect structure. The first circuit operates with a first supply voltage. The first circuit is formed in a first region along a main surface of a substrate. The first power circuit selectively provides the first supply voltage to the first circuit. The first power circuit is formed in a second region along the main surface. The second circuit operates with a second supply voltage. The second circuit is formed in a third region along the main surface. The second power circuit selectively provides the second supply voltage to the second circuit. The second power circuit is formed in a fourth region along the main surface. The first interconnect structure is formed in a first of a plurality of metallization layers above the main surface. The first interconnect structure electrically couples the first power circuit to the first circuit. The second interconnect structure is formed in the first metallization layer. The second interconnect structure electrically couples the second power circuit to the second circuit. The first interconnect structure and the second interconnect structure are electrically isolated from each other by at least one isolation structure.

[0004] Some embodiments disclosed herein provide an integrated circuit comprising a plurality of circuits, a plurality of power circuits, and a plurality of interconnect structures. Each of the plurality of circuits operates at at least one of a first supply voltage or a second supply voltage. The plurality of circuits are formed along a main surface of a substrate. Each of the plurality of power circuits selectively provides at least one of the first supply voltage or the second supply voltage to one of the plurality of circuits individually. The plurality of power circuits are formed along the main surface. The plurality of interconnect structures are formed in one of a plurality of metallization layers above the main surface, in a first metallization layer. Each of the plurality of interconnect structures electrically couples one of the plurality of power circuits to at least one of the plurality of circuits. The plurality of interconnect structures are electrically isolated from each other by at least one isolation structure.

[0005] Some embodiments disclosed herein provide a method for forming an integrated circuit, the method comprising the steps of: providing a substrate including a main surface; forming a plurality of transistors in a plurality of active regions along the main surface of the substrate, wherein the plurality of transistors form a first circuit in a first region of the plurality of active regions, a first power circuit in a second region of the plurality of active regions, a second circuit in a third region of the plurality of active regions, and a second power circuit in a fourth region of one of the plurality of active regions; forming a plurality of connections over the plurality of active regions; forming a first interconnect structure and a second interconnect structure in a first metallization layer of a plurality of metallization layers over the plurality of connections and the plurality of active regions, wherein at least a portion of the plurality of transistors is electrically coupled to other transistors through the plurality of connections and the first and second interconnect structures; and forming at least one isolation structure in the first metallization layer to electrically isolate the first interconnect structure and the second interconnect structure, wherein the first power circuit selectively provides a first supply voltage to the first circuit through the first interconnect structure, and the second power circuit selectively provides a second supply voltage to the second circuit through the second interconnect structure. Simple Explanation of the Diagram

[0006] The embodiments disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In practice, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1A illustrates a top view of an example integrated circuit including a circuit having a single cell height according to some embodiments. Figure 1B illustrates a cross-sectional view of an example integrated circuit of Figure 1A according to some embodiments. Figure 2A illustrates a cross-sectional view of an example integrated circuit of Figure 1A, comprising four power domains, according to some embodiments. Figure 2B illustrates a cross-sectional view of an example integrated circuit of Figure 2A, comprising two power domains, according to some embodiments. Figure 3 illustrates a schematic diagram of an example integrated circuit of at least one of Figures 1A, 1B, 2A, and 2B, which includes a stack of circuits partitioned into four power domains, according to some embodiments. Figure 4 illustrates a schematic diagram of an example integrated circuit of at least one of Figures 1A, 1B, 2A, and 2B, which includes a stack of circuits partitioned into two power domains, according to some embodiments. Figure 5A illustrates a top view of an example integrated circuit including one or more circuits having multiple cell heights according to some embodiments. Figure 5B illustrates a cross-sectional view of an example integrated circuit of Figure 5A according to some embodiments. Figures 6A to 6B illustrate schematic diagrams of an example integrated circuit of at least one of Figures 5A to 5B, which includes a circuit partitioned into two power domains, according to some embodiments. Figures 7 and 8 illustrate schematic diagrams of an example integrated circuit of at least one of Figures 5A to 5B, which includes a circuit partitioned into four power domains, according to some embodiments. Figure 9 illustrates a schematic diagram of an example integrated circuit according to some embodiments, including a circuit partitioned into three power domains, as shown in Figures 5A to 5B. Figure 10 illustrates a schematic diagram of an example integrated circuit from at least one of Figures 1A to 1B or Figures 5A to 5B, according to some embodiments, including configuration variations of tiled units for adjusting the partitioning of the power domain. Figures 11A to 11B illustrate schematic diagrams of an example integrated circuit according to some embodiments, including one or more transistors for short-circuiting segmented power grids (e.g., combining power domains), at least one of Figures 1A to 1B or Figures 5A to 5B. Figure 12 illustrates a flowchart of an example method for forming an integrated circuit according to some embodiments. Figure 13 illustrates a flowchart of another example method for forming an integrated circuit according to some embodiments. Figure 14 illustrates a flowchart of yet another example of a method for forming an integrated circuit according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of some embodiments of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein may be interpreted similarly accordingly.

[0009] In integrated circuit (IC) designs, such as memory designs, headers can be used to supply power to various functions within the chip. Different functions can be achieved or executed through the operation of one or more circuits within the IC. Headers can operate as switches or power distribution networks to control or otherwise manage the power delivery to one or more circuits or devices within the IC, for example, ensuring that different parts / areas of the IC receive the necessary power to operate or execute individual functions. To optimize power delivery, headers can be segmented based on the functional division of an entire area. For example, power supply can be divided / partitioned into different (power) domains through one or more headers, such as non-active power (NAP) and switching rails. NAP can refer to areas of the IC that do not actively perform operations that may consume relatively minimal power. Switching rails can supply power to active areas that consume relatively more energy / power compared to at least non-active areas. Separating power supplies can facilitate power distribution to different domains or reduce power consumption within the IC.

[0010] In certain IC layouts, such as peripheral sub-block layouts, adjacent devices may operate at different supply voltages or power levels. Peripheral sub-block layouts may include peripheral circuitry, such as, but not limited to, at least one of input / output (I / O) buffers, decoders, or sense amplifiers. Peripheral circuitry facilitates communication between the IC's core logic and external interfaces, for example, for managing power distribution or signal integrity. For instance, one or more first devices may require a relatively large power supply to operate relative to other second devices. In certain areas associated with the first devices, this demand for a relatively large power supply may lead to competition for power resources. For example, when multiple devices simultaneously consume a relatively large amount of power, the power distribution network may be overloaded or strained, potentially causing voltage drops or power fluctuations. In this case, competition for power resources may affect device performance or reliability, potentially leading to operational problems such as slower operation, increased heat generation, or reduced overall efficiency.

[0011] To address these challenges, the technical solutions and methods discussed herein can segment, divide, or otherwise partition the power domains of a device chain (e.g., comprising multiple circuits or devices) to ensure that adjacent devices receive the power supply required for device operation. A power domain can refer to a group of devices, circuits, or components sharing the same power supply, which can be independently powered on or off. For example, these systems and methods can partition the power domains of a circuit chain into multiple power domains using at least one isolation structure (e.g., a back-end-of-line (BEOL) metal with dielectric material). For example, each power domain may include one or more circuits from the circuit chain. Segmenting power domains prevents potential conflicts between devices or components and ICs that simultaneously consume relatively large power supplies.

[0012] In further examples, these systems and methods can utilize power supplies from adjacent columns (or rows) within devices that do not operate within sub-blocks, or, in some cases, across sub-blocks. These devices can receive power supplies from adjacent columns or rows via one or more connections between power groups / domains. By using at least one isolation structure to segment power domains and / or allowing / enabling power supplies from adjacent columns or rows, these systems and methods can avoid adjusting the front end (FE) plan view, shorten or segment the power grid (through tiling configuration), and customize the power domain units within a custom IC for individual devices or groups of devices. Therefore, these systems and methods in the technical solutions can utilize the techniques or configurations discussed herein to provide flexible power systems, sub-cell-level power domain segmentation, and / or enhanced power domain adjustment flexibility.

[0013] Figures 1A and 1B illustrate an example IC 100 comprising a circuit having a single cell height according to some embodiments. Figure 1A illustrates a top view of the example IC 100 according to some embodiments. Figure 1B illustrates a cross-sectional view of the example IC 100 of Figure 1A according to some embodiments. For example, Figure 1B illustrates an example cross-sectional view of the IC 100 of Figure 1A cut along line A-A'. IC 100 may include a plurality of devices formed in an oxide diffusion (OD) region, zone, or layer. These devices may consist of one or more transistors, resistors, capacitors, or other components thereof. These devices may include, correspond to, or be referred to as circuits 102 (e.g., 102A-B). These devices may include power circuits 104 (e.g., 104A-C, sometimes generally referred to as circuit 104). Power circuits 104 may sometimes be referred to as headers, which are used as switches to control or manage the power distribution to one or more circuits 102.

[0014] The OD (Original Device) can be an area within the IC where one or more transistors are fabricated. The fabricated transistors can be part of circuits 102 and 104. For example, transistors can be interconnected to form one or more logic gates, amplifiers, memory cells, or other functional units. By controlling the flow of electrical signals, the transistors work together to perform calculations, store data, or regulate power within the IC, for example, to perform individual operations of circuits 102 and 104.

[0015] The OD can be formed along the main surface of the substrate (not shown). Circuits 102, 104 (or transistors) formed along the main surface of the substrate can occupy regions 101A-E and can be referred to as the front end (e.g., using a front-end of line (FEOL) process). For example, circuits 102A-B can be formed in regions 101B and 101D respectively, and power circuits 104A-C can be formed in regions 101A, 101C, and 101E respectively. As shown, power circuit 104B can be inserted laterally between circuits 102A-B. Regions 101A-E can be referred to as the first to fifth regions, respectively, or in other non-limiting configurations. Transistors can be manufactured or formed using any suitable deposition, etching, or masking(multiple) techniques and other non-limiting manufacturing techniques. Transistors can be composed of various materials, including but not limited to at least one of silicon, germanium, gallium arsenide, polycrystalline silicon, etc. It should be noted that the OD may include any number of transistors or circuits 102, 104 to perform the intended features or functionality of IC 100, not limited to those discussed herein.

[0016] Circuits 102 and 104 may be part of at least one unit in IC 100, such as a memory unit or other functional unit. Circuits 102 and 104 may be in a single unit height. IC may include interconnect structures 106, 108, and 110 (e.g., 106A-B, 108A-D, and 110A-C) that electrically connect devices within IC 100. As shown in Figures 1A to 1B, interconnect structures 106, 108, and 110 may be labeled as metal track 0 (MT0), metal track 1 (MT1), and metal track 2 (MT2), respectively. For the purpose of providing an example, MT0 may represent a metal track in layer 0 (e.g., a first metallization layer). MT1 may represent a metal track in layer 1 (e.g., a second metallization layer). MT2 may represent a metal track in layer 2 (e.g., a third metallization layer), and so on. The interconnection structures 106, 108, and 110 can extend in pre-configured directions, such as lateral, longitudinal, diagonal, and vertical directions.

[0017] The device can receive electrical signals or supply power through at least one of the interconnect structures 106, 108, and 110, for example, allowing the device to communicate and operate independently or in conjunction. The interconnect structures 106, 108, and 110 can be formed in multiple metallization layers. The metallization layers (and / or interconnect structures 106, 108, and 110) can be composed of metals such as aluminum, copper, gold, tungsten, or other suitable materials. Different interconnect structures 106, 108, and 110 can be composed of similar or different materials. The metallization layers can be formed using a back-end-of-line (BEOL) process. Multiple metallization layers can be formed above the FEOL or OD layer. Individual metallization layers can be stacked on top of each other; for example, a first metallization layer is formed above / on the OD layer, a second metallization layer is formed above the first metallization layer, and a third metallization layer is formed above the second metallization layer, etc. The first, second, third, or other metallization layers can be configured in different orders.

[0018] Interconnect structures 106, 108, and 110 in different metallization layers can be electrically coupled using via structures. For example, interconnect structure 106 can be electrically coupled to interconnect structure 108 using a first via structure (e.g., VIA1). In another example, interconnect structure 108 can be electrically coupled to interconnect structure 110 using a second via structure (e.g., VIA2).

[0019] Electrical paths can be created within IC 100 using multiple metallization layers. For illustrative purposes, the interconnect structures 106 in the first metallization layer can be supplied with power from a power source (e.g., VDD or VSS) (not shown). The power source can be an internal power source of IC 100 or an external power source of IC 100. Power supply to circuit 102 can be managed by one or more power circuits 104 (e.g., headers) or other components used to distribute power to different areas within IC 100.

[0020] For example, power circuit 104A may be electrically coupled to circuit 102A, and power circuit 104C may be electrically coupled to circuit 102B. In some cases, power circuit 104B may be electrically coupled to at least one of the circuits 102. Circuits 102 and power circuit 104 may be electrically coupled to at least interconnect structure 106. Power circuit 104 may operate, for example, as a switch to control the power supply from interconnect structure 106 for distribution to individual circuits 102, for example, these circuits may operate with the same or different supply voltages. As an illustrative example, regions 101B and 101D associated with circuits 102A-B may be presented in different sizes, wherein, for example, a smaller region represents relatively lower power consumption during the execution of circuit operation, and a larger region represents relatively higher power consumption during the execution of circuit operation. It should be noted that circuits 102 operating at different voltage or power levels may be presented in areas of similar size, or circuits operating at a lower power level compared to another circuit may be associated with a relatively small area in IC 100. For example, the area size does not need to reflect the power consumption level of circuit 102.

[0021] Circuits 102 and 104 may be electrically connected to at least interconnect structure 106 via a plurality of connections (e.g., composed of polysilicon or other suitable materials). For example, polysilicon may be used to form the gate structure of a transistor for electrical connections between components in IC 100. Other power circuits 104 may be electrically coupled to one or more circuits 102. IC 100 may include more or fewer power circuits 104 and / or circuits 102 (e.g., devices) to perform predetermined / pre-configured functions.

[0022] Circuit 102 may be a charging device. In some cases, circuit 102 may compete for power supply during operation, for example, when connected to the same power domain or power group. To prevent or avoid competition for power resources, an isolation structure 112 may be formed to separate the power domains (e.g., power_1 and power_2) via power circuit 104. For example, isolation structure 112 may include or correspond to a metal layer (e.g., CM0A). Isolation structure 112 may be formed during the BEOL process using a non-conductive material (such as any suitable dielectric material). Isolation structure 112 may be composed of other materials, not limited to those discussed herein. Isolation structure 112 may be formed between portions of interconnect structure 106 that supply power or voltage to circuits 102, 104. For example, after forming interconnect structure 106 (e.g., MTO), directional etching may be performed to cut MTO, thereby forming an opening. Next, the opening may be filled with a dielectric material (e.g., isolation structure 112) to electrically isolate the separated portions (e.g., 106A, 106B) in the interconnect structure 106. The isolation structure 112 may be disposed or formed above the power circuit 104B or region 101C.

[0023] For example, isolation structure 112 can electrically isolate a portion of interconnect structure 106 into interconnect structure 106A (e.g., a first interconnect structure labeled MT0A) and interconnect structure 106B (e.g., a second interconnect structure labeled MT0B). Isolation structure 112 can divide interconnect structure 106 to create different power domains that can be controlled independently, such as a first power domain associated with interconnect structure 106A and a second power domain associated with interconnect structure 106B. Interconnect structure 106A can be used to electrically couple power circuit 104A to circuit 102A. Interconnect structure 106B can be used to electrically couple power circuit 104C to circuit 102B. In some cases, at least one of interconnect structures 106B can be used to electrically couple power circuit 104B to at least one of circuits 102. Circuit 102 can be connected to its individual power domain via power circuit 104 (e.g., header) to ensure that each circuit 102 receives an individual operating supply voltage, such as a first supply voltage for circuit 102A and a second supply voltage for circuit 102B.

[0024] By using isolation structure 112 to partition the power domain, sub-cell-level power domain partitioning can be achieved without a new FE planar diagram, reducing interference between adjacent devices and competition for power resources. In various implementations, IC 100 may include additional isolation structures, interconnect structures, metallization layers, or other components thereof. It should also be noted that the designations "first," "second," and "third," etc., for any components discussed herein, such as circuits, power circuits, devices, interconnect structures, isolation structures, etc., are for illustrative purposes and do not limit the structure to any particular order. Therefore, this designation is interchangeable; for example, in some instances, the first component may sometimes be referred to as the second component, the third component, or other components.

[0025] For illustrative purposes, IC 100 may include vertical interconnect access (VIA) (e.g., sometimes referred to as via structures), such as VIA0 and VIA1, for connections between interconnect structures in different metallization layers. The metallization layers may be stacked vertically, horizontally, or diagonally. The partitioned interconnect structures 106A-B may be electrically coupled to each other using one or more of interconnect structures 108 and 110. For example, interconnect structure 106 may extend laterally in a first metallization layer above the OD or the main surface of the substrate. Multiple interconnect structures 108 may be formed in a second metallization layer above the first metallization layer, extending in another lateral direction perpendicular to interconnect structure 106. Multiple interconnect structures 108 may be electrically coupled to interconnect structure 106 using VIA1. Interconnect structure 110 may be formed in a third metallization layer above the second metallization layer, extending in a lateral direction perpendicular to interconnect structure 108. Interconnect structure 110 may extend in the same lateral direction as interconnect structure 106. Interconnect structure 110 can be electrically coupled to interconnect structure 108 via VIA2. As shown at least in Figure 1B, as an example, interconnect structure 106A and interconnect structure 106B can be electrically coupled to each other via at least interconnect structure 110. Interconnect structures 106, 108, and 110 facilitate efficient power and signal distribution on IC 100.

[0026] By using separate power domains, the individual circuits 102 within IC 100 can operate at their required (e.g., optimal) power levels. The power domains are isolated from each other to prevent power leakage and ensure that each region receives an appropriate power supply based on circuit operation. Thus, these systems and methods can improve the efficiency and performance of IC 100 by increasing the accuracy of power distribution control and reducing the risk of voltage drop. In various configurations, IC 100 may include more or fewer components discussed herein.

[0027] Figure 2A illustrates a cross-sectional view of example IC 100 of Figure 1A, which includes four power domains, according to some embodiments. Figure 2A provides example IC 200A, which includes one or more components, structures, or features similar to (or different from) IC 100 of Figure 1A. IC 200A may include different configurations, arrangements, or layouts compared to IC 100. In various configurations, the individual ICs discussed herein (e.g., Figures 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7 through 10, 11A, and 11B) may include similar and / or different components, layouts, arrangements, features, or functionalities related to each other, such as similar circuits / devices and their circuit operation, different layouts or arrangements of components, similar or different numbers of power domains, or similar numbers of power circuits, to illustrate various example configurations. The various ICs shown in this document are provided as non-limiting examples; for example, more or fewer components can be added, and different configurations, setups, or interconnections can be configured.

[0028] IC 200A may include circuits 102A-D (e.g., sometimes generally referred to as circuit 102). Circuit 102 may include or be composed of transistors. Individual circuits 102 can be used to perform individual operations at a predetermined supply voltage. For example, circuits 102A-D may operate at a first to a fourth supply voltage, respectively. In some cases, two or more circuits 102 may operate at the same supply voltage. Similar to circuit 102 in Figures 1A-1B, circuits 102 may be disposed or fabricated in OD, each electrically connected to interconnect structures 202A-D (e.g., sometimes referred to as interconnect structure 202, e.g., CM0A) through a plurality of connections (e.g., poly) vias.

[0029] As shown in Figure 2A, the interconnect structure 202 can be divided, partitioned, or divided into four parts, corresponding to four power domains (e.g., power_1, power_2, power_3, and power_4). The interconnect structures 202A-D can be electrically isolated from each other using isolation structures 112A-C. The individual isolation structures 112A-C can be composed of similar or different materials for electrically isolating the interconnect structure 202. Through the isolation interconnect structure 202, the power domains (or power groups) can be separated, for example, divided into four power domains or four parts within a power supply group.

[0030] Individual power circuit 104 may be electrically coupled to at least one of circuits 102 to control power distribution to circuit 102. For example, power circuit 104 may operate as a switch to distribute / supply supply voltage to individual(s) circuit(s) 102 or to prevent / disconnect supply voltage. Interconnection structure 202 may facilitate electrical connection between power circuit 104 and circuit 102. For example, interconnection structure 202A may be used to electrically couple power circuit 104A to circuit 102A. Interconnection structure 202B may be used to electrically couple power circuit 104B or 104C to circuit 102B. Interconnection structure 202C may be used to electrically couple power circuit 104B or 104C to circuit 102C. For example, interconnection structure 202D may be used to electrically couple power circuit 104C to circuit 102D. Other configurations of interconnection structure 202, power circuit 104, and electrical connections between circuits 102 may be configured, and are not limited to the examples herein.

[0031] Individual interconnect structure 202 can be electrically coupled to other interconnect structures 108, 110 using via structures (e.g., VIA0 and / or VIA1). Interconnect structure 110 can be electrically coupled to interconnect structure 108 using VIA1. Interconnect structure 108 can be coupled to interconnect structure 202 using VIA2. Interconnect structure 202 can extend in the same lateral direction as interconnect structure 110. Interconnect structure 108 can extend in a direction perpendicular to interconnect structures 202, 110. Interconnect structures 108, 110, 202 can be formed or configured to extend along other directions. Using these electrical connections, individual interconnect structures 108A-D can be electrically coupled to each other using at least interconnect structure 110.

[0032] Circuits 102A-D can send or receive electrical signals to each other through at least interconnect structure 110. By separating power domains, IC 200A can prevent circuits 102A-D from competing for power resources. In various cases, the partitioned power domains can be combined, short-circuited, or connected to each other through at least one interconnect structure, for example, by short-circuiting or coupling certain power circuits 104 or power supply lines between different power domains, such as by combining, but not limited to, those shown in Figure 2B.

[0033] Figure 2B illustrates a cross-sectional view of an example integrated circuit of Figure 2A, including two power domains, according to some embodiments. IC 200B of Figure 2B may include one or more components, features, or functionalities of IC 200A of Figure 2A and / or IC 100 of Figures 1A through 1B. In some cases, IC 200B may include additional or different components compared to the other ICs in at least one of Figures 1A through 2A.

[0034] Similar to IC 200A, IC 200B may include circuitry 102, power circuitry 104, and interconnect structure 202, which is divided into four power domains using isolation structure 112. In this illustrative example, pairs of power domains may be combined or grouped together to share a power supply. For example, at least a portion of interconnect structure 202A may be electrically coupled to at least a portion of interconnect structure 202C to share a power domain (e.g., power_1). Further, at least a portion of interconnect structure 202B may be electrically coupled to at least a portion of interconnect structure 202D to share another power domain (e.g., power_2). In such cases, the power supply group of interconnect structure 202 (e.g., MTO) may be divided into two parts or two power domains.

[0035] In Figure 2B, interconnect structures 204A-B (e.g., sometimes referred to as interconnect structures 204) may be formed in a third metallization layer above the second metallization layer (e.g., including interconnect structure 108). Interconnect structures 204 may be composed of materials similar to or different from interconnect structure 110. Interconnect structure 204A can be used to electrically couple interconnect structure 202A (associated with a first power domain) to interconnect structure 202C. Interconnect structure 204B can be used to electrically couple interconnect structure 202B (associated with a second power domain) to interconnect structure 202D.

[0036] Circuits 102A and 102C sharing the first power domain can be separated or inserted via circuit 102B (which shares the second power domain with circuit 102D). Similarly, circuits 102B and 102D sharing the second power domain can be separated or inserted via circuit 102C. The connection between interconnect structures 202 and 204 can be via at least interconnect structure 108 (or other intermediate interconnect structure). In some configurations, interconnect structure 202 can be directly connected to interconnect structure 204 using a via structure. Coupling between pairs or groups of interconnect structures 202A and 202C or interconnect structures 202B and 202D may include or involve shorting power lines to individual circuits 102, thereby allowing a shared power domain. Thus, the four power domains in Figure 2A can be combined into two power domains, as shown in Figure 2B.

[0037] Figure 3 illustrates a schematic diagram of an example integrated circuit of at least one of Figures 1A, 1B, 2A, and 2B, according to some embodiments, including a stack of circuits partitioned into four power domains. Figure 3 includes IC 300. IC 300 may be manufactured within a placement and routing boundary (PR boundary). A PR boundary may represent a designated area in a layout that allows the placement of transistors and routing connections, for example, an active area with certain design rules. IC 300 may include a stack of transistors or circuits (e.g., circuits _1 [0]~[3] to circuits _4 [0]~[3]) within the PR boundary. The circuitry in IC 300 may correspond to or include components, features, or functionalities incorporating, for example, at least one of, but not limited to, the circuit 102 described in Figures 1A, 1B, 2A, and 2B. IC 300 may include a plurality of headers (HDs). HD may correspond to or include, for example, at least one of Figures 1A, 1B, 2A and 2B, but is not limited to the components, features or functionalities in the power circuit 104 described in those figures.

[0038] The stack of transistors of IC 300 may include a plurality of layers 302A-D (e.g., sometimes referred to as layers 302). In some cases, each layer 302 in the stack of circuits may represent a single IC. The circuits in each layer 302 of the stack may have a single cell height. A single layer 302 may include various circuits (e.g., circuits 1 to 4), each of which is coupled to a separate header (or power circuit). HD can control or manage the power distribution to one or more circuits in the same or different power domains. Although four example circuits (or devices) and three example HDs are provided, more or fewer circuits or HDs may be fabricated or formed from the fabricated transistors. The interconnections or couplings between circuits and / or HDs may be described in conjunction with, but not limited to, at least one of Figures 1A, 1B, 2A, and 2B.

[0039] In some configurations, each layer 302 in the stack can reside in a separate power domain. For example, the MTO power supply group is divided into four parts (or layers 302). For instance, the circuitry (including HD) in layer 302A can be in (or associated with) a first power domain (e.g., power_1). The circuitry in layer 302B can be in a second power domain (e.g., power_2). The circuitry in layer 302C can be in a third power domain (e.g., power_3). The circuitry in layer 302D can be in a fourth power domain (e.g., power_4). Power supply lines (e.g., interconnect structures 106, 202) may be coupled to one or more transistors (e.g., p-type metal-oxide-semiconductor (PMOS), n-type metal-oxide-semiconductor (NMOS), or other types of metal-oxide-semiconductor field-effect transistors (MOSFETs)) of the HD to enable or disable power delivery to one or more circuits. For example, circuits within the same power domain may be connected to the same PMOS of at least one HD to receive supply voltage from the same power supply. In another example, the HD may include multiple transistors (e.g., multiple PMOS), each PMOS providing voltage from a separate power supply to operate different circuits or devices. In some cases, one or more circuits may communicate with other circuits in the same or different layers 302. In other cases, one or more circuits may be isolated from (e.g., not communicate with) other circuits in the same or different layers 302.

[0040] Figure 4 illustrates a schematic diagram of an example integrated circuit from at least one of Figures 1A, 1B, 2A, and 2B, according to some embodiments, comprising a stack of circuitry partitioned into two power domains. Figure 4 includes an IC 400 fabricated within the PR boundary. IC 400 may include one or more components similar to at least IC 300, as described in conjunction with at least Figure 3. IC 400 may include a stack of circuitry or devices divided into layers 402A-D (e.g., sometimes referred to as layer 402). IC 400 (or other ICs) may include more or fewer circuitry layers within the stack.

[0041] In various configurations, at least one connection (e.g., a power group connection) can be used to divide the circuitry within the stack into two power domains or power groups. A power group connection can represent, for example, interconnect structures, wires, or other coupling components used to electrically couple from one power domain to another at a power line, or to couple transistors supplying power in different power domains, for example, integrating power domains into a single power domain. In this case, a power group connection (e.g., one or more interconnect structures) can be formed, deposited, or established to couple power domains between layers 402A and 402C. Between layers 402A and 402C, IC 400 may include a first power domain (e.g., power_1). A power group connection can be used to couple power domains between layers 402B and 402D to share a power supply. Therefore, between layers 402B and 402D, IC 400 may include a second power domain (e.g., power_2). In some other configurations, power group connections can be coupled between different layers, such as layers 402A, 402D or layers 402B, 402C. By providing power group connections to combine power groups or power domains, the systems and methods in the technical solution can improve the flexibility of power domain adjustment in flexible power systems.

[0042] Figures 5A to 5B illustrate an example IC 500 comprising one or more circuits having multiple cell heights according to some embodiments. Figure 5A illustrates a top view of the example IC 500 according to some embodiments. Figure 5B illustrates a cross-sectional view of the example IC 500 of Figure 5A according to some embodiments, cut along line A-A' or line B-B'. A circuit having multiple cell heights may refer to a device or circuit in which at least a portion extends beyond a single cell height, as shown in Figures 5A to 5B. One or more components or functions in IC 500 may be similar to (or in some cases different from) other ICs discussed herein (e.g., at least one of IC 100, 200A, 200B, etc.).

[0043] As shown in the figures, Figures 5A to 5B include a plurality of transistors manufactured or formed in an OD on the main surface of a substrate (not shown). The transistors in the OD may include, correspond to, or be part of at least one of circuits / devices 502A-D (e.g., sometimes referred to as circuit 502) and / or power circuits 504A-F (e.g., sometimes referred to as power circuit 504). In the first unit height, power circuits 504A, 502A, 504B, 502B, and 504C may be manufactured in regions 501A-E, respectively. In the second unit height, power circuits 504D, 502C, 504E, 502D, and 504F may be manufactured in regions 501F-J.

[0044] IC 500 may include interconnect structures 506A-D, 508A-H, and 510A-B formed in a metallization layer. Interconnect structures 506A-D may sometimes be referred to as interconnect structures(s) 506. Interconnect structures 508A-H may sometimes be referred to as interconnect structures(s) 508. Interconnect structures 510A-B may sometimes be referred to as interconnect structures(s) 510. Interconnect structures 506, 508, and 510 may be composed of materials similar to or different from, but not limited to, those materials used in conjunction with at least one of the interconnect structures 106, 108, and 110 described in those figures.

[0045] Interconnect structures 506, 508, and 510 may be formed on the OD. For example, interconnect structure 506 (and other MTOA and MTOB structures) may be formed in a first metallization layer above the OD, extending in a first lateral direction. Interconnect structure 508 may be formed in a second metallization layer above the first metallization layer, extending in a second lateral direction perpendicular to the first lateral direction. Interconnect structure 510 may be formed in a third metallization layer above the second metallization layer, extending in the first lateral direction, for example, parallel to interconnect structure 506. One or more interconnect structures 506, 508, and 510 may be electrically coupled to each other using via structures (e.g., VIA0, VIA1, etc.).

[0046] Interconnect structure 506 can carry power supplies from one or more power sources for distribution to circuits 502, 504. To prevent competition for power resources, interconnect structure 506 can be segmented / divided / partitioned to divide circuits 502, 504 into different power domains. Interconnect structure 506 can be divided into multiple sections using one or more isolation structures 512A~B (e.g., sometimes referred to as isolation structure 512). For example, isolation structure 512A can divide interconnect structure 506 in a first cell height into interconnect structures 506A~B. Isolation structure 512B can divide interconnect structure 506 in a second cell height into interconnect structures 506C~D. Isolation structures 512 can be formed above areas 501C, 501H or power circuits 504B, 504E, respectively. In this configuration of the electrically isolated portion of interconnect structure 506, four power domains can be established in IC 500, for example, across the cell height. For example, circuits 502A~D can be associated with the first to fourth power groups or power domains, respectively.

[0047] Interconnect structure 510A can electrically couple interconnect structure 506A to interconnect structure 506B. Interconnect structure 510B can electrically couple interconnect structure 506C to interconnect structure 506D. Interconnect structure 508 can be inserted between interconnect structures 506 and 510. The power connection of (multiple) interconnect structures 508 (e.g., MT1) can be disconnected. In some implementations, disconnecting the power connection of (multiple) interconnect structures 508 may disconnect or prevent power supply to at least one of the interconnect structures 506 (e.g., MT0). Interconnect structures 508 (e.g., MT2 line) can be cross-patterned; for example, the connections between power supply lines can be alternated or intersecting. For example, cross-connections can prevent any overlap or crossing of power supply lines, ensuring that power domains remain separated or electrically isolated from each other. IC 500 may include more or fewer components, cells, electrical connections, etc. The components in IC 500 can be configured or laid out differently.

[0048] Figures 6A to 6B illustrate schematic diagrams of an example integrated circuit of at least one of Figures 5A to 5B, which includes a circuit partitioned into two power domains according to some embodiments. Figures 6A to 6B may each include ICs 600A to 600B, which contain one or more components or features similar to or different from at least IC 500, as described in conjunction with Figures 5A to 5B. ICs 600A to 600B may include devices / circuits, for example, a stack of devices in layers 602A to 602B (e.g., sometimes referred to as layers 602). The stack of circuits may include HDs to control power supply to one or more circuits. The circuits may operate in response to receiving individual predetermined supply voltages. One or more circuits may include multiple cell heights, such as circuit_3 [0] and circuit_3 [1] extending across layer 602. Transistors (as part of the circuits or HDs) may be fabricated within PR boundaries.

[0049] ICs 600A~B may include two power domains (e.g., power_1 and power_2). Different configurations or connections for establishing the two power domains may be provided between ICs 600A~B. For example, IC 600A may include a power group connection coupled between circuit_2 [1] (or corresponding HD) and circuit_3 [1] to share a power supply. The power group connection may be coupled to a transistor, such as a PMOS or other type of MOSFET, to control the power supply to individual circuits so that associated circuits share power resources within the same power domain. In this case, the first power domain may include circuit_1 [0], circuit_2 [0], and circuit_3 [0], and the second power domain may include circuit_1 [1], circuit_2 [1], and circuit_3 [1].

[0050] In another instance, IC 600B may include other power group connections (in addition to the power group connections in IC 600A), such as between circuit_1[0] and circuit_2[1] and between circuit_1[1] and circuit_2[0]. For example, by establishing connections, circuit_1[0] may be part of a second power domain and circuit_1[1] may be part of a first power domain. Other instances of connection configurations may be provided in the non-limiting examples herein.

[0051] Figures 7 and 8 illustrate schematic diagrams of example integrated circuits including at least one of Figures 5A to 5B, which are partitioned into four power domains, according to some embodiments. Figures 7 and 8 respectively include ICs 700 and 800, each comprising, but not limited to, at least one of, ICs 500, 600A-B, described in conjunction with Figures 5A, 5B, 6A, and 6B, in terms of components, features, or functionality. IC 700 may include a stack of circuits / devices formed within PR boundaries. In this case, IC 700 may include four layers 702A-C of circuitry (e.g., sometimes referred to as layers 702). IC 800 may include a stack (or multiple stacks) of circuitry formed within multiple PR boundaries. In this case, IC 800 may include eight layers 802A-H of circuitry (e.g., sometimes referred to as layers 802).

[0052] ICs 700 and 800 provide various layouts or configurations for interconnects between circuits or HDs to use power grouping connections to short-circuit or combine different power domains. Power grouping connections can be connected to circuits in different layers 702 and 802. In some cases, different parts of a circuit (e.g., circuits 3 and 5) may be in different power domains, for example, operating at different supply voltages.

[0053] For example, IC 700 may include four power domains. A first power domain (e.g., power_1) may include circuits_1 [2] and_2 [2] coupled to circuits_4 [2,3] and a portion of circuit_5. A second power domain (e.g., power_2) may include circuits_1 [3] and_2 [3] coupled to circuits_4 [0,1] and_6 [0]. A third power domain (e.g., power_3) may include circuits_1 [1] and_2 [1] coupled to a portion of circuit_3 and a portion of circuit_5. A fourth power domain may include circuits_1 [0] and_2 [0] coupled to a portion of circuit_3 and circuit_6 [1]. The power connection of MT1 may be disconnected. The power network may be connected in a cross-connect mode as described above.

[0054] IC 800 may include four power domains. For example, the interconnection in IC 800 between circuits in different layers 802 may be at least partially similar to the interconnection in IC 700 of Figure 7. In this case, IC 800 may include one or more power group connections to electrically couple circuits in different PR boundaries (e.g., connections between different circuit stacks). As an example of establishing a second power domain (e.g., power_2), the power group connection may connect circuit_1 [3] and circuit_2 [3] in the first stack (e.g., the first PR boundary, including layers 802A~D) to circuit_4 [0,1] and circuit_6 [0] in the second stack (e.g., the second PR boundary, including layers 802E~H). Other connections may be configured to combine power domains or connect certain circuits to a specific power domain.

[0055] Figure 9 illustrates a schematic diagram of an example integrated circuit according to some embodiments, including a circuit partitioned into three power domains, as shown in Figures 5A to 5B. Figure 9 includes IC 900. IC 900 may include, but is not limited to, one or more components, features, or functions of ICs 500, 600, 700, and 800 as shown in Figures 5A, 5B, 6A and 6B, 7 and 8. IC 900 may include a stack of circuits in layers 902A-D. IC 900 may include circuits having multiple cell heights, such as circuit_3 and circuit_5. IC 900 may partition the power domains into three power domains (e.g., power_1, power_2, and power_3). IC 900 may include an example layout of circuitry and connections used to establish the three power domains.

[0056] For example, a first power domain may include circuit _3 (and associated HD). A second power domain may include circuits _1 [0]~[3] and circuits _2 [0]~[3]. Interconnections between these circuits may be described in conjunction with, for example, at least Figures 5A to 5B. For example, the circuits may be electrically coupled through one or more interconnect structures or wiring. In this example, a third power domain may include circuits _4 [0,1,2,3], circuits _5 and _6 [0]~[1]. Power group connections may be used to electrically couple circuit _4 [0,1] to circuit _4 [2,3]. Power group connections may extend across (or above) circuit _3. In various implementations, (multiple) power group connections may extend across other circuits or interconnect structures discussed herein, for example, above or below certain components or structures.

[0057] Figure 10 illustrates a schematic diagram of an example integrated circuit from at least one of Figures 1A to 1B or Figures 5A to 5B, according to some embodiments, showing configuration variations of tiled units including adjustments to the partitioning of power domains. As shown, by attaching different tiled units for adjustment, various configuration variations of the connections between circuits in layout 1000 can be provided. Tiled units can be used to adjust the partitioning of power domains and manage connections between different circuits. The configuration of the tiled units can be varied to provide flexibility in the combination or partitioning of power domains and the connections of circuits within the layout. The use of tiled units to adjust the partitioning of power domains in an integrated circuit can be shown in or described in conjunction with Figure 10.

[0058] For example, in configuration 1002 (e.g., tile_cell_A), the four power domains including circuits in layout 1000 (e.g., circuits_1 [0]~[3] and circuits_2 [0]~[3]) can be combined into two power domains. In the first power domain of configuration 1002, the power group is connected to the power supply group associated with circuits_1 [0], [2], and circuits_2 [1], [3]. In the second power domain of configuration 1002, the power group is connected to the power supply group associated with circuits_1 [1], [3], and circuits_2 [0], [2].

[0059] Configurations 1004 and 1008 (e.g., tile_cell_B and tile_cell_C, respectively) can provide instance connections between circuits for dividing a power supply group (e.g., a power domain) into four parts. In configurations 1004 and 1008, one or more circuits can be coupled to other circuits in different layers of the circuit stack. For example, a power group connection can couple circuit_1 [0] to circuit_2 [1], circuit_1 [1] to circuit_2 [2], and circuit_1 [2] to circuit_2 [3]. In configuration 1004, the power group connection can be kept within the PR boundary such that circuit_1 [3] can be used to couple to circuit_2 [0], for example, as described in conjunction with at least Figure 7. In configuration 1008, the power group connection can extend beyond the PR boundary to the circuit, such that circuit _1 [3] can be coupled to circuit _3 [0] and circuit _2 [0] can be coupled to circuit _0 [3], for example, as described at least in conjunction with Figure 8.

[0060] Figures 11A to 11B illustrate schematic diagrams of an example integrated circuit according to some embodiments, including one or more transistors 1102A-C or 1104A-C for short-circuiting segmented power grids (e.g., combining power domains). Figures 11A to 11B include IC 1100. IC 1100 may include one or more components similar to or different from other ICs described in conjunction with at least one of Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7 through 10. For the purpose of providing an example, IC 1100 may include circuitry, power group connections, and other components similar to IC 400 of Figure 4.

[0061] In some configurations, IC 1100 may include or add transistors 1102A-C or 1104A-C to short-circuit divide the power grid, for example, to combine power domains between layers in a stacked circuit. Transistors 1102A-C are sometimes referred to as transistor 1102. Transistors 1104A-C are sometimes referred to as transistor 1104. Transistors 1102 and 1104 may be PMOS, NMOS, or other types of MOSFETs. For example, a PMOS transistor may be added or implemented herein to short-circuit divide the power grid.

[0062] For example, in Figure 11A, IC 1100 may include transistors 1102 coupled between adjacent layers in a stack of circuits. When powered on, transistor 1102A may be coupled to the HD associated with circuits _1 [0]~[3] and / or circuits _2 [0]~[3]. When powered on, transistor 1102B may be coupled to the HD associated with circuits _3 [0]~[3]. When powered on, transistor 1102C may be coupled to the HD associated with circuits _4 [0]~[3]. In this case, transistors 1102A~C (for PMOS) may be disabled by sending a high signal (e.g., '1' or a predetermined voltage) and powered on by sending a low signal (e.g., '0' or no voltage).

[0063] In response to the activation of individual transistors 1102, the power grid or power line between circuits or HDs can be short-circuited, thereby allowing the corresponding circuits (as described above) to receive supply voltage from the same power supply. When transistor 1102 is deactivated, the power domains can be separated to prevent competition for power resources. As shown, signals from Short_en 0, Short_en1, and Short_en2 can be used to control transistors 1102A~C, respectively.

[0064] The same operation of transistor 1102 can be applied to transistor 1104. Signals from Short_en0, Short_en1, and Short_en2 can be used to control transistors 1104A to C, respectively. For example, activating transistor 1104A can short-circuit the power supply to circuits _1 [0] to [3] and circuits _2 [0] to [3], thereby allowing these circuits to operate in a single power domain. Similarly, activating transistor 1104C can short-circuit the power supply to circuits _4 [0] to [3], thereby allowing these circuits to operate in a single power domain. When transistor 1104B is activated, the power supply to circuits _3 [1] to [2] can be short-circuited, thereby allowing these circuits to operate in the same power domain (e.g., operating in one or a combination of the first power domain and / or the second power domain). Circuits _3 [0] and _3 [3] can operate in their respective power domains. Thus, by adding transistors 1102 and 1104, the systems and methods in the technical solution can allow for configurable combination or separation of the power domain by dynamically short-circuiting the power grid. The placement of the transistors can be flexible and vary depending on the IC design or configuration, for example, for designs that minimize gate delay or manage IR drop. For instance, strategically placing transistors can help reduce signal propagation time and maintain a stable supply voltage, thereby improving the overall performance and reliability of the integrated circuit.

[0065] Figure 12 illustrates a flowchart of an example method 1200 for forming an integrated circuit (e.g., IC 100, 200A-B, 300, 400, 500, etc.) according to some embodiments. For example, method 1200 may include operations, features, or components for manufacturing or forming an integrated circuit(s), as described with reference to at least one, but not limited to, Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7-10, 11A, and 11B. Thus, the following embodiments of method 1200 will be described in conjunction with Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7-10, 11A, and 11B. The embodiments shown in Method 1200 are merely examples. Therefore, it should be understood that any of the various operations of Method 1200 may be omitted, rearranged, and / or added, while still remaining within the scope of some embodiments disclosed herein.

[0066] Method 1200 begins with operation 1202, forming a first circuit and a first power circuit. For example, method 1200 may include forming the first circuit (e.g., 102A) in a first region (e.g., 101B) along the main surface of a substrate. The main surface may refer to the top layer of the substrate. The first circuit can be used to operate at a first supply voltage (e.g., a first predetermined power level consumed from a power supply).

[0067] Method 1200 may include forming a first power circuit (e.g., 104A, such as in a header) in a second region (e.g., 101A) along the main surface. The first power circuit may be used to selectively provide a first supply voltage to a first circuit. For example, the first power circuit (or other power circuits herein) may be used to control the power supply from a power source (e.g., internal or external to the IC) to at least the first circuit. In some configurations, the first power circuit (or other power circuits) may control the power supply from a power source to multiple circuits.

[0068] Next, method 1200 proceeds to operation 1204, forming a second circuit and a second power circuit. Method 1200 may include forming the second circuit (e.g., 102B) in a third region (e.g., 101D) along the main surface. The second circuit can be used to operate at a second supply voltage (e.g., a second predetermined power level). The first circuit and the second circuit may have different power consumption levels. Other circuits may have similar or different power consumption levels relative to the first circuit and / or the second circuit.

[0069] Method 1200 may include forming a second power circuit (e.g., 104C) in a fourth region (e.g., 101E) along the main surface. The second power circuit may be used to selectively provide a second supply voltage to the second circuit. The first and third regions may be adjacent to each other in a lateral direction. In the lateral direction, the second region may be positioned relative to the first and third regions, and the fourth region may be positioned relative to the third region and the first region.

[0070] In some configurations, a third power circuit (e.g., 104B) may be formed, inserted laterally between the first and second circuits. The third power circuit may also be formed in a fifth region (e.g., 101C) between the first and third regions. In some cases, the third power circuit may be provided for design purposes, for example, disconnected from the first and second circuits. In some cases, the third power circuit may be electrically coupled to at least one of the first, second, or other circuits to selectively provide individual supply voltages.

[0071] Method 1200 continues to operation 1206, which forms at least one interconnect structure (e.g., interconnect structure 106, 202, or 506). For example, method 1200 may include forming an interconnect structure (e.g., 106) in a first of a plurality of metallization layers above the main surface. The IC may include metallization layers formed above the main surface, wherein each of the metallization layers includes a metal structure forming for providing connections between components or to external components. In this case, the interconnect structure may represent a metal track or power line carrying a power supply from a power source.

[0072] Subsequently, method 1200 proceeds to operation 1208, electrically isolating the interconnect structure into a first interconnect structure (e.g., interconnect structure 106A) and a second interconnect structure (e.g., interconnect structure 106B). For example, method 1200 may include electrically isolating the interconnect structure into the first interconnect structure (e.g., 106A) and the second interconnect structure (e.g., 106B) using at least one isolation structure (e.g., 112). The isolation structure may be formed by performing directional etching to cut the interconnect structure (e.g., MTO) to form an opening. The opening may be filled with a dielectric material to electrically isolate the separated portions (e.g., 106A, 106B) within the interconnect structure (e.g., 106). At least one isolation structure may be disposed above a third power circuit. At least one isolation structure may be formed in a first metallization layer between the first and second interconnect structures. By electrically isolating the interconnect structure into two portions, separate power domains can be provided to prevent competition for power resources between the two circuits.

[0073] A first interconnect structure can be used to electrically couple a first power circuit to a first circuit. A second interconnect structure can be used to electrically couple a second power circuit to a second circuit. The circuit and the power circuit can be electrically coupled to the first and second interconnect structures through a plurality of connections (e.g., polysilicon or other materials). Both the first and second interconnect structures can extend in a lateral direction.

[0074] Method 1200 may include forming a third interconnect structure (e.g., 110, MT2) in a second of a plurality of metallization layers above a first metallization layer. Method 1200 may include electrically coupling a first interconnect structure to a second interconnect structure using at least a third interconnect structure. The first to third interconnect structures may all extend along the same lateral direction.

[0075] The coupling between the first and second interconnect structures and the third interconnect structure can be inserted by one or more other interconnect structures. For example, method 1200 may include forming a fourth interconnect structure (e.g., 108A or 108B, such as MT1) in a third of a plurality of metallization layers between the first and second metallization layers. In this case, the third metallization layer may refer to the layer above the first metallization layer and below the second metallization layer. The fourth interconnect structure may be electrically coupled to the first and third interconnect structures. Method 1200 may include a fifth interconnect structure (e.g., 108C or 108D, such as another MT1) formed in the third metallization layer. The fifth interconnect structure may be electrically coupled to the second and third interconnect structures. The coupling between the interconnect structures may be via at least one via structure (e.g., VIA0, VIA1, etc.). The fourth and fifth interconnect structures may extend along another lateral direction perpendicular to the first to third interconnect structures (e.g., a second lateral direction or a longitudinal direction).

[0076] In some configurations, method 1200 may include forming a third circuit (e.g., 102C) in a sixth region along the main surface. Method 1200 may include forming a fourth circuit (e.g., 102D) in a seventh region along the main surface. Method 1200 may include forming a sixth interconnect structure (e.g., 202C) in a first metallization layer. The sixth interconnect structure may be used to electrically couple the third circuit to one of a first power circuit, a second power circuit, or another power circuit different from the first and second power circuits. Method 1200 may include a seventh interconnect structure (e.g., 202D) formed in the first metallization layer. The seventh interconnect structure may be used to electrically couple the fourth circuit to one of a first power circuit, a second power circuit, or another power circuit different from the first and second power circuits. In some implementations, for example, the first power circuit and / or the second power circuit may be used to selectively provide multiple supply power to multiple circuits. The first, second, sixth, and seventh interconnect structures may be electrically isolated from each other using a plurality of isolation structures (e.g., 112A~C). In such cases, electrical isolation can be used to provide four power domains to further prevent competition for power resources between the four circuits.

[0077] In some cases, the third circuit can be used to operate with a third supply voltage, and the fourth circuit can be used to operate with a fourth supply voltage. The third and fourth supply voltages may be different from each other, and may also be different from the first and second supply voltages. In such cases, the first, second, sixth, and seventh interconnection structures may be electrically coupled to each other using at least a third interconnection structure (e.g., 110), for example, for communication between the first to fourth circuits / devices.

[0078] In some other cases, method 1200 may include forming an eighth interconnect structure (e.g., 204B) in a second metallization layer. For example, similar to the first circuit, a third circuit may be used to operate with a first supply voltage. A fourth circuit may be used to operate with a second supply voltage, similar to the second circuit. In such cases, method 1200 may configure connections to divide a power supply group into two parts (e.g., for two power domains). The first interconnect structure (e.g., 202A) and the sixth interconnect structure (e.g., 202C) are electrically coupled to each other using at least a third interconnect structure (e.g., 204A). The second interconnect structure (e.g., 202B) and the seventh interconnect structure (e.g., 202D) may be electrically coupled to each other using at least an eighth interconnect structure (e.g., 204B). The seventh and eighth interconnect structures may be used to short-circuit or combine transistors or power lines associated with power circuits that selectively provide supply power to individual circuits, such that the first and third circuits can receive the first supply voltage, and the second and fourth circuits can receive the second supply voltage. Other layouts or interconnections between components may be implemented, and are not limited to those discussed herein.

[0079] Figure 13 illustrates a flowchart of an example method 1300 for forming an integrated circuit (e.g., IC 100, 200A-B, 300, 400, 500, etc.) according to some embodiments. For example, method 1300 may include operations, features, or components for manufacturing or forming an integrated circuit(s), as discussed with respect to at least one, but not limited to, Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7-10, 11A, and 11B. Therefore, the following embodiments of method 1300 will be described in conjunction with Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7-10, 11A, and 11B. The illustrated embodiment of method 1300 is merely an example. Therefore, it should be understood that any of the various operations of method 1300 may be omitted, reordered, and / or added, while still remaining within the scope of some embodiments disclosed herein. In some configurations, the operations in method 1300 may include one or more operations similar to (or in some cases different from) method 1200, as described in conjunction with at least Figure 12.

[0080] Method 1300 begins with operation 1302 by providing (or forming) a substrate comprising a main surface. The substrate may be composed of any suitable material, such as, but not limited to, at least one of silicon, gallium nitride, gallium arsenide, or germanium. The main surface of the substrate may refer to a surface of the substrate (e.g., a top surface or a bottom surface), for example, the surface may be parallel to a wafer plane.

[0081] Next, method 1300 proceeds to operation 1304, forming a plurality of transistors in an active region along the main surface of the substrate. An active region may refer to a portion of an integrated device or circuit where at least a portion of electrical operations (such as current conduction, amplification, switching, etc.) occur. The plurality of transistors formed in the active region may be electrically coupled to each other or configured to form one or more circuits. For example, the plurality of transistors may form a first circuit (e.g., 102A) in a first region (e.g., 101B), a first power circuit (e.g., 104A) in a second region (e.g., 101A), a second circuit (e.g., 102B) in a third region (e.g., 101D), and a second power circuit (e.g., 104C) in a fourth region (e.g., 101E).

[0082] Regions one through four can be positioned laterally. Laterally, region two can be positioned relative to regions one and three, and region four can be positioned relative to regions three and one. Multiple transistors can form other circuits (or fewer circuits), not limited to the first and second circuits, and the first and second power circuits. In some cases, multiple transistors formed in the active region can be electrically coupled to one or more other transistors, not limited to those discussed herein.

[0083] Method 1300 continues to operation 1306, forming a plurality of connections above the active region. The connections can be made of any suitable material, such as polysilicon. These connections can be used to form the gate structure of the transistor for electrical connection between components. These connections can be used to electrically couple the transistors (associated with (multiple) circuits) to each other. In some cases, these connections can be used to electrically couple the transistors to other non-limiting transistors, devices, components, or structures.

[0084] Method 1300 continues to operation 1308, forming an interconnect structure (e.g., interconnect structure 106, 202, or 506) in a first of a plurality of metallization layers (e.g., a first metallization layer or MTO) above the plurality of connections and active regions. The IC may include metallization layers formed on a main surface, wherein each of the metallization layers includes a metal structure formed to provide connections between components or to external components. At least a portion of the plurality of transistors may be electrically coupled to other transistors through the plurality of connections and interconnect structures. The interconnect structure may represent a metal track or power line carrying a power supply from a power source.

[0085] Next, method 1300 continues to operation 1310, forming at least one isolation structure in the first metallization layer to electrically isolate the interconnect structure into at least two portions, for example, a first interconnect structure and a second interconnect structure. To form the isolation structure, method 1300 may involve etching at least a portion of the interconnect structure, thereby dividing the interconnect structure into at least two portions. In this case, the first portion may be referred to as the first interconnect structure, and the second portion as the second interconnect structure. Any suitable etching technique may be used. Once the portion (or opening) is formed, method 1300 may involve depositing the isolation structure into the etched portion to electrically isolate the first interconnect structure from the second interconnect structure. Any suitable deposition technique may be used. The isolation structure may be composed of any suitable non-conductive material.

[0086] Power circuits can be used to selectively supply voltage to individual circuits via interconnect structures. For example, a first circuit can be used to operate at a first supply voltage (e.g., a first predetermined power level consumed from a power supply). A first power circuit can be used to selectively supply a first supply voltage to a first circuit. A second circuit can be used to operate at a second supply voltage (e.g., a second predetermined power level). A second power circuit can be used to selectively supply a second supply voltage to a second circuit. Power circuits can be used to control the power supply from a power source (e.g., internal or external to an IC) to at least one circuit. Power (or voltage) from the first power circuit can be supplied to the first circuit via individual connections and a first interconnect structure. Power from the second power circuit can be supplied to the second circuit via individual connections and a second interconnect structure.

[0087] In various configurations, method 1300 may include forming a plurality of via structures (e.g., VIA1 or VIA2) over a first metallization layer. Method 1300 may include forming a third interconnect structure (e.g., 110, MT2) in a second of the plurality of metallization layers (e.g., a second metallization layer) over the first metallization layer and the via structures. The first interconnect structure may be electrically coupled to the second interconnect structure via one or more of the via structures and the third interconnect structure. It should be noted that other structures, components, or materials may be formed in the IC, not limited to those discussed herein.

[0088] Figure 14 illustrates a flowchart of an example method 1400 for forming an integrated circuit (e.g., IC 100, 200A-B, 300, 400, 500, etc.) according to some embodiments. For example, method 1400 may include operations, features, or components for manufacturing or forming an integrated circuit(s), as discussed with respect to at least one, but not limited to, Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7 through 10, 11A, and 11B. Therefore, the following embodiments of method 1400 will be described in conjunction with Figures 1A, 1B, 2A, 2B, 3, 4, 5A, 5B, 6A, 6B, 7 through 10, 11A, and 11B. The illustrated embodiment of method 1400 is merely an example. Therefore, it should be understood that any of the various operations of method 1400 may be omitted, reordered, and / or added, while still remaining within the scope of some embodiments disclosed herein. In some configurations, the operations in method 1400 may include one or more operations similar to (or in some cases different from) methods 1200 and / or 1300, as described at least in conjunction with Figures 12 and / or 13.

[0089] Method 1400 begins with operation 1402 by providing (or forming) a substrate including a main surface. The substrate may be composed of any suitable material, such as, but not limited to, at least one of silicon, gallium nitride, gallium arsenide, or germanium. The main surface of the substrate may refer to a surface of the substrate (e.g., a top surface or a bottom surface), for example, the surface may be parallel to the wafer plane.

[0090] Next, method 1400 proceeds to operation 1404, forming a plurality of transistors in an active region along the main surface of the substrate. An active region may refer to a portion of an integrated device or circuit where at least a portion of electrical operations (such as current conduction, amplification, switching, etc.) occur. The plurality of transistors formed in the active region may be electrically coupled to each other or configured to form one or more circuits. For example, the plurality of transistors may form a first circuit (e.g., 102A) in a first region (e.g., 101B), a first power circuit (e.g., 104A) in a second region (e.g., 101A), a second circuit (e.g., 102B) in a third region (e.g., 101D), and a second power circuit (e.g., 104C) in a first region (e.g., 101E).

[0091] Regions one through four can be positioned laterally. Laterally, region two can be positioned relative to regions one and three, and region four can be positioned relative to regions three and one. Multiple transistors can form other circuits (or fewer circuits), not limited to the first and second circuits, and the first and second power circuits. In some cases, multiple transistors formed in the active region can be electrically coupled to one or more other transistors, not limited to those discussed herein.

[0092] Method 1400 continues to operation 1406, forming a plurality of connections above the active region. These connections can be made of any suitable material, such as polysilicon. These connections can be used to form the gate structure of the transistor for electrical connection between components. These connections can be used to electrically couple the transistors (associated with (multiple) circuits) to each other. In some cases, these connections can be used to electrically couple the transistors to other non-limiting transistors, devices, components, or structures.

[0093] Method 1400 continues to operation 1408, forming a first interconnect structure (e.g., 106A, 202A, or 506A) and a second interconnect structure (e.g., 106B, 202B, or 506B) in a first of a plurality of metallization layers (e.g., a first metallization layer or MTO) over a plurality of connections and active regions. The IC may include metallization layers formed on a main surface, wherein each of the metallization layers includes a metal structure formed to provide connections between components or to external components. At least a portion of the plurality of transistors may be electrically coupled to other transistors through the plurality of connections and interconnect structures. The interconnect structure may represent a metal track or power line carrying power from a power source. The first interconnect structure may be formed over a first and second region of the active region, for example, over a first circuit and a first power circuit. The second interconnect structure may be formed over a third and fourth region of the active region, for example, over a second circuit and a second power circuit.

[0094] Next, method 1400 continues to operation 1410, forming at least one isolation structure in the first metallization layer to electrically isolate the first interconnect structure from the second interconnect structure. For example, the first interconnect structure and the second interconnect structure may be formed in different regions or portions of the first metallization layer, wherein the first and second interconnect structures may be separated by gaps or openings. To form the isolation structure, method 1300 may include depositing the isolation structure into the opening to electrically isolate the first interconnect structure from the second interconnect structure. Any suitable deposition technique may be used. The isolation structure may be composed of any suitable non-conductive material.

[0095] Power circuitry can be used to selectively supply supply voltages to individual circuits via first and / or second interconnect structures (and other interconnect structures). For example, a first circuit can be used to operate at a first supply voltage (e.g., a first predetermined power level consumed from the power supply). The first power circuit can be used to selectively supply the first supply voltage to the first circuit. A second circuit can be used to operate at a second supply voltage (e.g., a second predetermined power level). The second power circuit can be used to selectively supply the second supply voltage to the second circuit. Power circuitry can be used to control the power supply from a power source (e.g., internal or external to an IC) to at least one circuit. Power (or voltage) from the first power circuit can be supplied to the first circuit via individual connections and the first interconnect structure. Power from the second power circuit can be supplied to the second circuit via individual connections and the second interconnect structure.

[0096] In various configurations, method 1300 may include forming a plurality of via structures (e.g., VIA1 or VIA2) over a first metallization layer. Method 1300 may include forming a third interconnect structure (e.g., 110, MT2) in a second of the plurality of metallization layers (e.g., a second metallization layer) over the first metallization layer and the via structures. The first interconnect structure may be electrically coupled to the second interconnect structure via one or more of the via structures and the third interconnect structure. It should be noted that other structures, components, or materials may be formed in the IC, not limited to those discussed herein.

[0097] In one embodiment disclosed herein, an integrated circuit includes a first circuit for operating at a first supply voltage, wherein the first circuit is formed in a first region along a main surface of a substrate. The integrated circuit includes a first power circuit for selectively providing the first supply voltage to the first circuit, wherein the first power circuit is formed in a second region along the main surface. The integrated circuit includes a second circuit for operating at a second supply voltage, wherein the second circuit is formed in a third region along the main surface. The integrated circuit includes a second power circuit for selectively providing a second supply voltage to the second circuit, wherein the second power circuit is formed in a fourth region along the main surface. The integrated circuit includes a first interconnect structure formed in a first of a plurality of metallization layers above the main surface, wherein the first interconnect structure is used to electrically couple the first power circuit to the first circuit. The integrated circuit includes a second interconnect structure formed in the first metallization layer, wherein the second interconnect structure is used to electrically couple the second power circuit to the second circuit. The first interconnect structure and the second interconnect structure are electrically isolated from each other by at least one isolation structure.

[0098] In some embodiments, at least one isolation structure is formed in the first metallization layer.

[0099] In some embodiments, along a lateral direction, the first region and the third region are positioned adjacent to each other, the second region is positioned relative to the first region and the third region, and the fourth region is positioned relative to the third region and the first region.

[0100] In some embodiments, the integrated circuit further includes a third power circuit, which is inserted between the first circuit and the second circuit in a lateral direction.

[0101] In some embodiments, at least one isolation structure is disposed above the third power circuit.

[0102] In some embodiments, both the first interconnect structure and the second interconnect structure extend in the lateral direction.

[0103] In some embodiments, the integrated circuit further includes a third interconnect structure. The third interconnect structure is formed in one of a plurality of metallization layers, a second metallization layer, above the first metallization layer. The first interconnect structure and the second interconnect structure are electrically coupled to each other by at least the third interconnect structure.

[0104] In some embodiments, the first to third interconnect structures all extend along the same lateral direction.

[0105] In some embodiments, the integrated circuit further includes a fourth interconnect structure and a fifth interconnect structure. The fourth interconnect structure is formed in a third metallization layer among a plurality of metallization layers between a first metallization layer and a second metallization layer. The fourth interconnect structure is electrically coupled to the first interconnect structure and the third interconnect structure. The fifth interconnect structure is formed in the third metallization layer. The fifth interconnect structure is electrically coupled to the second interconnect structure and the third interconnect structure. The fourth and fifth interconnect structures extend along a direction perpendicular to the first to third interconnect structures.

[0106] In some embodiments, the first circuit and the second circuit have different power consumption levels.

[0107] In some embodiments, the integrated circuit further includes a third circuit, a fourth circuit, a sixth interconnect structure, and a seventh interconnect structure. The third circuit is formed in a sixth region along the main surface. The fourth circuit is formed in a seventh region along the main surface. The sixth interconnect structure is formed in a first metallization layer. The sixth interconnect structure electrically couples the third circuit to a first power circuit, a second power circuit, or another power circuit different from the first and second power circuits. The seventh interconnect structure is formed in the first metallization layer. The seventh interconnect structure electrically couples the fourth circuit to the first power circuit, the second power circuit, or another power circuit different from the first and second power circuits. The first, second, sixth, and seventh interconnect structures are electrically isolated from each other by a plurality of isolation structures.

[0108] In some embodiments, the third circuit operates with a third supply voltage. The fourth circuit operates with a fourth supply voltage. The first, second, sixth, and seventh interconnect structures are electrically coupled to each other using at least a third interconnect structure.

[0109] In some embodiments, the integrated circuit further includes an eighth interconnect structure. The eighth interconnect structure is formed in a second metallization layer. The third circuit operates with a first supply voltage. The fourth circuit operates with a second supply voltage. The first interconnect structure and the sixth interconnect structure are electrically coupled to each other using at least a third interconnect structure. The second interconnect structure and the seventh interconnect structure are electrically coupled to each other using at least an eighth interconnect structure.

[0110] In another embodiment of some of the embodiments disclosed herein, an integrated circuit is provided. The integrated circuit includes a plurality of circuits, each circuit being operable at at least one of a first supply voltage or a second supply voltage, wherein the plurality of circuits are formed along a main surface of a substrate. The integrated circuit includes a plurality of power circuits, each power circuit being selectively provided with at least one of the first supply voltage or the second supply voltage up to one of the plurality of circuits, wherein the plurality of supply voltages are formed along the main surface. The integrated circuit includes a plurality of interconnect structures in a first metallization layer of a plurality of metallization layers formed above the main surface, each of the plurality of interconnect structures being used to electrically couple one of the plurality of power circuits to at least one of the plurality of circuits. The plurality of interconnect structures are electrically isolated from each other by at least one isolation structure.

[0111] In some embodiments, the plurality of circuits includes a first circuit and a second circuit. The plurality of power circuits includes a first power circuit and a second power circuit. The plurality of interconnect structures include a first interconnect structure and a second interconnect structure electrically isolated from each other by a first isolation structure. The first interconnect structure electrically couples the first power circuit to the first circuit. The second interconnect structure electrically couples the second power circuit to the second circuit.

[0112] In some embodiments, the plurality of circuits further include a third circuit and a fourth circuit. The plurality of power circuits further include a third power circuit. The plurality of interconnect structures further include a third interconnect structure and a fourth interconnect structure. The plurality of interconnect structures are electrically isolated from each other by a second isolation structure and electrically isolated from the first and second interconnect structures by a third isolation structure. The third interconnect structure electrically couples one of the first to third power circuits to the third circuit, and the fourth interconnect structure electrically couples one of the first to third power circuits to the fourth circuit.

[0113] In some embodiments, the integrated circuit further includes a fifth interconnect structure and a sixth interconnect structure. The fifth interconnect structure and the sixth interconnect structure are formed in a second metallization layer, one of a plurality of metallization layers above the first metallization layer, wherein the first to fourth interconnect structures are electrically coupled to each other by at least the fifth interconnect structure, or the first and third interconnect structures are electrically coupled to each other by at least the fifth interconnect structure, and the second and fourth interconnect structures are electrically coupled to each other by at least the sixth interconnect structure.

[0114] In another embodiment of some embodiments disclosed herein, a method for forming an integrated circuit is provided. The method includes providing a substrate including a main surface. The method includes forming a plurality of transistors in an active region along the main surface of the substrate, wherein the plurality of transistors form a first circuit in a first region of the active region, a first power circuit in a second region of the active region, a second circuit in a third region of the active region, and a second power circuit in a fourth region of the active region. The method includes forming a plurality of connections over the active region. The method includes forming a first interconnect structure and a second interconnect structure in a first of a plurality of metallization layers over the multiple connections and the active region, wherein at least a portion of the plurality of transistors is electrically coupled to other transistors through the multiple connections and the first and second interconnect structures. The method includes forming at least one isolation structure in the first metallization layer to electrically isolate the first interconnect structure and the second interconnect structure, wherein the first power circuit is used to selectively provide a first supply voltage to the first circuit through the first interconnect structure, and wherein the second power circuit is used to selectively provide a second supply voltage to the second circuit through the second interconnect structure.

[0115] In some embodiments, the step of forming the at least one isolation structure includes the following steps: depositing the at least one isolation structure between a first interconnect structure and a second interconnect structure to electrically isolate the first interconnect structure and the second interconnect structure.

[0116] In some embodiments, the method further includes the steps of: forming a plurality of via structures over a first metallization layer; and forming a third interconnect structure in one of the plurality of metallization layers over the first metallization layer and the plurality of via structures, wherein the first interconnect structure and the second interconnect structure are electrically coupled to each other via at least one or more of the plurality of via structures and the third interconnect structure.

[0117] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of some embodiments disclosed herein. Those skilled in the art should understand that some embodiments of this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of some embodiments of this disclosure.

[0118] 100:IC 101A: District 101B: District 101C: District 101D: District 101E: District 102A: Circuit 102B: Circuit 102C: Circuit 102D: Circuit 104A: Power Circuit 104B: Power Circuit 104C: Power Circuit 106: Interconnection Structure 106A: Interconnection Structure 106B: Interconnection Structure 108: Interconnection Structure 108A~108B: Interconnection Structure 108C~108D: Interconnection Structure 110: Interconnection Structure 110A~110C: Interconnection Structure 112: Isolation Structure 112A~112C: Isolation Structure 200A~200B:IC 202A: Interconnection Structure 202B: Interconnection Structure 202C: Interconnection Structure 202D: Interconnection Structure 204A: Interconnection Structure 204B: Interconnection Structure 300:IC 302A~302D: Layers 400:IC 402A~402D: Layers 500:IC 501A~501J: Area 502A~502D: Circuits 504A~504F: Power Circuits 506A~506D: Interconnection Structure 508: Interconnection Structure 508A~508H: Interconnection Structure 510A~510B: Interconnection Structure 512: Isolation Structure 512A~512B: Isolation Structure 600A~600B:IC 602A~602B: Layers 700:IC 702A~702D: Layers 800:IC 802A~802H: Layer 900:IC 902A~902D: Layers 1000: Layout 1002: Configuration 1004: Configuration 1008: Configuration 1100:IC 1102A~1102C: Transistors 1104A~1104C: Transistors 1200: Method 1202~1208: Operation 1300: Method 1302~1310: Operation 1400: Method 1402~1410: Operation A-A':line B-B': line CM0A: Metal layer HD: Header MT0A: Interconnection Structure MT0B: Interconnection Structure MT1: Metal Rail MT2: Metal Rail OD: Oxide diffusion PR: Placement and Routing

[0119] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit comprising: a first circuit for operating at a first supply voltage, wherein the first circuit is formed in a first region along a main surface of a substrate; a first power circuit for selectively providing the first supply voltage to the first circuit, wherein the first power circuit is formed in a second region along the main surface; a second circuit for operating at a second supply voltage, wherein the second circuit is formed in a third region along the main surface; a second power circuit for selectively providing the second supply voltage to the second circuit, wherein the second power circuit is formed in a fourth region along the main surface; a first interconnect structure formed in one of a plurality of metallization layers above the main surface, wherein the first interconnect structure is used to electrically couple the first power circuit to the first circuit; and a second interconnect structure formed in the first metallization layer, wherein the second interconnect structure is used to electrically couple the second power circuit to the second circuit. The first interconnect structure and the second interconnect structure are electrically isolated from each other by at least one isolation structure.

2. The integrated circuit as claimed in claim 1, wherein the first region and the third region are positioned adjacent to each other along a lateral direction, wherein the second region is positioned relative to the first region and the third region, and wherein the fourth region is positioned relative to the third region and the first region.

3. The integrated circuit as claimed in claim 1, further comprising: a third interconnect structure formed in one of the second metallization layers above the first metallization layer; wherein the first interconnect structure and the second interconnect structure are electrically coupled to each other by at least the third interconnect structure, wherein the first to third interconnect structures all extend along the same lateral direction.

4. The integrated circuit as claimed in claim 3, further comprising: a fourth interconnect structure formed in a third metallization layer among the metallization layers between the first and second metallization layers, wherein the fourth interconnect structure is electrically coupled to the first and third interconnect structures; and a fifth interconnect structure formed in the third metallization layer, wherein the fifth interconnect structure is electrically coupled to the second and third interconnect structures, wherein the fourth and fifth interconnect structures extend along a direction perpendicular to the other side of the first to third interconnect structures.

5. The integrated circuit as claimed in claim 1, further comprising: a third circuit formed in a sixth region along the main surface; a fourth circuit formed in a seventh region along the main surface; a sixth interconnect structure formed in the first metallization layer, wherein the sixth interconnect structure is used to electrically couple the third circuit to one of the first power circuit, the second power circuit, or another power circuit different from the first and second power circuits; and a seventh interconnect structure formed in the first metallization layer, wherein the seventh interconnect structure is used to electrically couple the fourth circuit to one of the first power circuit, the second power circuit, or another power circuit different from the first and second power circuits, wherein the first, second, sixth, and seventh interconnect structures are electrically isolated from each other by a plurality of isolation structures.

6. An integrated circuit comprising: a plurality of circuits, each of the circuits being operable at at least one of a first supply voltage or a second supply voltage, wherein the circuits are formed along a main surface of a substrate; a plurality of power circuits, each of the power circuits being selectively supplied with at least one of the first supply voltage or the second supply voltage to one of the circuits, wherein the power circuits are formed along the main surface; and a plurality of interconnect structures formed in a first metallization layer of a plurality of metallization layers above the main surface, each of the interconnect structures being electrically coupled to one of the power circuits to at least one of the circuits, wherein the interconnect structures are electrically isolated from each other by at least one isolation structure.

7. The integrated circuit as described in claim 6, wherein: The circuits include a first circuit and a second circuit. The power circuits include a first power circuit and a second power circuit. The interconnect structures include a first interconnect structure and a second interconnect structure electrically isolated from each other by a first isolation structure. The first interconnect structure is used to electrically couple the first power circuit to the first circuit, and the second interconnect structure is used to electrically couple the second power circuit to the second circuit. The circuits further include a third circuit and a fourth circuit. The power circuits further include a third power circuit, and the interconnect structures further include a third interconnect structure and a fourth interconnect structure. The interconnect structures are electrically isolated from each other by a second isolation structure and electrically isolated from the first and second interconnect structures by a third isolation structure. The third interconnect structure is used to electrically couple one of the first to third power circuits to the third circuit, and the fourth interconnect structure is used to electrically couple one of the first to third power circuits to the fourth circuit.

8. The integrated circuit as claimed in claim 6, further comprising: a fifth interconnect structure and a sixth interconnect structure formed in a second metallization layer among a plurality of metallization layers above the first metallization layer, wherein the first to fourth interconnect structures are electrically coupled to each other by at least the fifth interconnect structure, or the first and third interconnect structures are electrically coupled to each other by at least the fifth interconnect structure, and the second and fourth interconnect structures are electrically coupled to each other by at least the sixth interconnect structure.

9. A method of forming an integrated circuit, the method comprising the steps of: providing a substrate including a main surface; forming a plurality of transistors in a plurality of active regions along the main surface of the substrate, wherein the transistors form a first circuit in a first region of one of the active regions, a first power circuit in a second region of one of the active regions, a second circuit in a third region of one of the active regions, and a second power circuit in a fourth region of one of the active regions; and forming a plurality of connections over the active regions; A first interconnect structure and a second interconnect structure are formed in one of a plurality of metallization layers above the connections and the active regions, wherein at least a portion of the transistors are electrically coupled to other transistors through the connections and the first and second interconnect structures; and at least one isolation structure is formed in the first metallization layer to electrically isolate the first interconnect structure and the second interconnect structure, wherein the first power circuit is used to selectively provide a first supply voltage to the first circuit through the first interconnect structure, and wherein the second power circuit is used to selectively provide a second supply voltage to the second circuit through the second interconnect structure.

10. The method of claim 9, further comprising the steps of: forming a plurality of via structures over the first metallization layer; and forming a third interconnect structure in one of the metallization layers over the first metallization layer and the via structures, wherein the first interconnect structure and the second interconnect structure are electrically coupled to each other via at least one or more of the via structures and the third interconnect structure.

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