Memory device having planarized fins

Abstract

This application discloses a memory element and a method for manufacturing a memory element. The memory element includes: a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first flat top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins among the plurality of fins, wherein the first word line includes an oxide layer conforming to the surface of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer; and an isolation structure extending into the semiconductor substrate and surrounding the active region.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113129939, filed August 9, 2024, which claims priority and benefits over U.S. Official Application No. 18 / 665,837, filed May 16, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a memory element and a method for manufacturing the same, and more specifically, to a memory element having planarized fins on a substrate and a method for manufacturing the same. Prior Technology

[0003] Dynamic random access memory (DRAM) is a semiconductor configuration used to store bits of data in individual capacitors within an integrated circuit (IC). DRAM is typically formed as trench capacitor DRAM cells. Advanced methods for fabricating buried gate electrodes involve constructing the transistor's gate electrode and word lines in trenches within the active area (AA) of a shallow trench isolation (STI) structure.

[0004] Over the past few decades, with continuous improvements in semiconductor manufacturing technology, the size of electronic devices has shrunk accordingly. As the size of unit transistors shrinks to a few nanometers in length, the size of the contact between the unit transistor and the active region can become a problem. A smaller contact area between the unit transistor and the active region can lead to a significant decrease in the performance of the unit transistor. Therefore, improvements are needed to address these manufacturing challenges.

[0005] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a memory element. This memory element includes: a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first flat top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins among the plurality of fins, wherein the first word line includes an oxide layer conforming to the surfaces of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second flat top surface. The active region comprises: a second flat top surface substantially coplanar with the first flat top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitor plug disposed in a second insulating layer and on the conductive plug, and configured to protrude from the second insulating layer; and a contact pad disposed on the second insulating layer and on the capacitor plug.

[0007] Another aspect of this disclosure provides a memory element. This memory element includes: a semiconductor substrate defining an active region; a plurality of fins disposed in and protruding from the active region of the semiconductor substrate, wherein each of the plurality of fins has a first flat top surface; a word line structure including a first word line extending into the semiconductor substrate and between a pair of adjacent fins among the plurality of fins, wherein the first word line includes an oxide layer conforming to the surfaces of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second flat top surface, wherein the second flat top surface is adjacent to the plurality of fins. The first flat top surface of each of the fins is substantially coplanar; an isolation structure extends into the semiconductor substrate and surrounds the active region; a second character line is disposed within the isolation structure and separated from the first character line by the plurality of fins; a conductive plug is disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitor plug is disposed in a second insulating layer and on the conductive plug, and protrudes from the second insulating layer; a contact pad is disposed on the second insulating layer and on the capacitor plug; a patterned mask is disposed on the second insulating layer and surrounds the contact pad; and a metal plug is disposed on the contact pad.

[0008] Another aspect of this disclosure provides a method for manufacturing a memory element. This method includes: providing a first semiconductor structure, wherein the first semiconductor structure includes: a semiconductor substrate defining a plurality of active regions; an isolation structure surrounding each of the plurality of active regions; a plurality of first recesses and a plurality of second recesses located in the semiconductor substrate; a plurality of fins protruding from the semiconductor substrate, wherein each of the plurality of fins has a flat surface; a first dielectric layer conforming to each of the plurality of first recesses and surrounding the plurality of fins, wherein after the first dielectric layer is formed, the plurality of... Each fin has a first top surface; a first conductive member located within each of the plurality of first recesses and surrounded by the first dielectric layer; a second dielectric layer disposed on the first conductive member and surrounded by the first dielectric layer; and a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure, the conductive plug extends through the first insulating layer, and each of the plurality of fins has a flat top surface. The method further includes: forming an insulating layer on the first semiconductor structure; forming a capacitor plug in the insulating layer; forming a barrier layer on and attached to the sidewalls of the capacitor plug; and forming a contact pad on the second insulating layer and on the capacitor plug.

[0009] In summary, because the top portion of each fin protruding from the substrate is planarized before contact is formed between the cell capacitor and one of the fins, the contact area between the cell capacitor and the fin is increased, and the curved surface of the top portion becomes a flat surface. Therefore, the overall performance of the memory device and the manufacturing process of the memory device are improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the embodiments and the claims. This disclosure should also be understood in conjunction with the component symbols in the drawings, which represent similar components throughout the specification. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. Figure 1 is a perspective view illustrating memory elements of some embodiments disclosed herein. Figure 2 is a top view illustrating the array area of ​​memory elements in Figure 1. Figures 3A, 3B, and 3C are cross-sectional views illustrating a portion of a memory element taken along section line A-A' in Figure 2, according to some embodiments of this disclosure. 4 is a flowchart illustrating a method for manufacturing a memory element according to some embodiments of this disclosure. Figures 5 to 29 are cross-sectional views illustrating intermediate stages in the formation process of memory elements according to some embodiments of the present disclosure. Implementation

[0012] The embodiments or examples of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described in this document, should be considered as would normally be conceived by one of ordinary skill in the art to which this disclosure pertains.

[0013] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0014] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context otherwise requires. It should be understood that the terms "comprising" and "including," when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.

[0015] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used in this document to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagram, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0016] Figure 1 is a perspective view illustrating a memory element 100 according to some embodiments of the present disclosure. In some embodiments, the memory element 100 includes a plurality of unit cells arranged in rows and columns.

[0017] Referring to Figure 1, the memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a host semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped single-crystal silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

[0018] In some embodiments, the semiconductor substrate 101 includes a peripheral region 101a and an array region 101b that is at least partially surrounded by the peripheral region 101a. In some embodiments, the peripheral region 101a is adjacent to the periphery of the semiconductor substrate 101, and the array region 101b is adjacent to the central region of the semiconductor substrate 101. In some embodiments, the array region 101b can be used to fabricate transistors, capacitors, or other similar components.

[0019] In some embodiments, the semiconductor substrate 101 includes a first surface 101c and a second surface 101d opposite to the first surface 101c. In some embodiments, the first surface 101c is the front side of the semiconductor substrate 101, wherein electronic devices or components are subsequently formed on the first surface 101c and electrically connected to an external circuit. In some embodiments, the second surface 101d is the back side of the semiconductor substrate 101, wherein no electronic devices or components are present.

[0020] Figure 2 is a top view illustrating the array region 101b of the semiconductor substrate 101 of Figure 1. Referring to Figure 2, the semiconductor substrate 101 includes a plurality of active areas 102. In some embodiments, the active areas 102 are doped regions in the semiconductor substrate 101. In some embodiments, the active areas 102 extend horizontally above or below a first surface 101c of the semiconductor substrate 101. In some embodiments, each active area 102 includes the same type of dopant. In some embodiments, each active area 102 includes a dopant type different from the dopant types included in other active areas 102. In some embodiments, each active area 102 has the same conductivity type. In some embodiments, the active areas 102 include n-type dopant.

[0021] In some embodiments, the memory element 100 includes an isolation structure 103 extending into a semiconductor substrate 101 and surrounding an active region 102. In some embodiments, the isolation structure 103 extends from a first surface 101c toward a second surface 101d of the semiconductor substrate 101. In some embodiments, the isolation structure 103 is a shallow trench isolation (STI) structure. In some embodiments, the isolation structure 103 defines the boundary of each active region 102. In some embodiments, the isolation structure 103 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0022] Figure 3A is a cross-sectional view illustrating a portion of a memory element 100 taken along section line A-A' in Figure 2, according to some embodiments of this disclosure. Referring to Figures 2 and 3A, a plurality of recesses 104 are formed in an array region 101b of a semiconductor substrate 101, spanning an active region 102 and an isolation structure 103. In some embodiments, the recesses 104 include a first recess 104a extending into the semiconductor substrate 101 and a second recess 104b extending into the isolation structure 103. In some embodiments, the first recess 104a extends across more than one active region 102. In some embodiments, the first recess 104a and the second recess 104b have the same depth. In some embodiments, the first recess 104a is shallower than the second recess 104b.

[0023] Referring to FIG. 3A, a plurality of fins 101e are formed in a semiconductor substrate 101. In some embodiments, the top surface of the fins is coplanar with the first surface 101c of the semiconductor substrate 101. In some embodiments, the fins 101e are alternately disposed with the first groove 104a. In some embodiments, the top of the fins 101e is the active region 102 of the semiconductor substrate 101. In some embodiments, each fin 101e has a first top surface 101f, as shown in FIG. 3A. In some embodiments, the first top surface 101f of the fin 101e is planar or flat.

[0024] In some embodiments, the memory 100 includes a first word line 105 located within a first recess 104a, as shown in FIG3A. The first word line 105 extends into the semiconductor substrate 101. In some embodiments, the first word line 105 is disposed between an adjacent pair of fins 101e. In some embodiments, at least a portion of the first word line 105 is surrounded by an active region 102.

[0025] In some embodiments, the first character line 105 includes a second dielectric layer 105a, a first conductive member 105b, and a third dielectric layer 105c. In some embodiments, the second dielectric layer 105a is disposed conforming to the sidewall of the first recess 104a. In some embodiments, the second dielectric layer 105a is disposed conforming to the surfaces of two adjacent fins 101e. In some embodiments, the second dielectric layer 105a contacts the entire sidewall of the first recess 104a. In some embodiments, the second dielectric layer 105a is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof. In some embodiments, the second dielectric layer 105a comprises a dielectric material having a low dielectric constant (low k).

[0026] In some embodiments, a first conductive member 105b is disposed within a first groove 104a and surrounded by a second dielectric layer 105a. In some embodiments, the first conductive member 105b is separated from the fin 101e by the second dielectric layer 105a. In some embodiments, the first conductive member 105b comprises a conductive material, such as tungsten (W).

[0027] In some embodiments, a third dielectric layer 105c is disposed within the first groove 104a and above the first conductive member 105b, and is surrounded by the second dielectric layer 105a. In some embodiments, the third dielectric layer 105c is formed of an insulating material, such as silicon nitride, silicon oxynitride, other similar materials, or combinations thereof. In some embodiments, the third dielectric layer 105c has a second top surface 105d that is substantially coplanar with the first top surface 101f of the fin 101e. In some embodiments, the second top surface 105d of the third dielectric layer 105c is planar or flat.

[0028] In some embodiments, the second dielectric layer 105a has a third top surface 105e that is substantially coplanar with the first top surface 101f of the fin 101e and the second top surface 105d of the third dielectric layer 105c. In some embodiments, the third top surface 105e of the second dielectric layer 105a is planar or flat. In some embodiments, the third top surface 105e of the second dielectric layer 105a is coupled to the first top surface 101f of the fin 101e and the second top surface 105d of the third dielectric layer 105c.

[0029] In some embodiments, the isolation structure 103 has a fourth top surface 103a that is substantially coplanar with the first top surface 101f of the fin 101e, the second top surface 105d of the third dielectric layer 105c, and the third top surface 105e of the second dielectric layer 105a. In some embodiments, the fourth top surface 103a is planar or flat.

[0030] In some embodiments, memory 100 includes a second character line 106 located within a second recess 104b, as shown in FIG3A. In some embodiments, the second character line 106 is surrounded by an isolation structure 103. In some embodiments, the second character line 106 is separated from the first character line 105 by a fin 101e. In some embodiments, the height H1 of the first character line 105 is substantially the same as the height H2 of the second character line 106. In some embodiments, the height H1 of the first character line 105 is substantially less than the height H2 of the second character line 106.

[0031] In some embodiments, the second character line 106 includes a second conductive member 106a located within a second groove 104b, and a fourth dielectric layer 106b located above the second conductive member 106a and within the second groove 104b. In some embodiments, the second conductive member 106a includes a conductive material, such as tungsten (W). In some embodiments, the fourth dielectric layer 106b is formed of an insulating material, such as silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0032] In some embodiments, the fourth dielectric layer 106b has a fifth top surface 106c that is substantially coplanar with the first top surface 101f of the fin 101e, the second top surface 105d of the third dielectric layer 105c, the third top surface 105e of the second dielectric layer 105a, and the fourth top surface 103a of the isolation structure 103. In some embodiments, the fifth top surface 106c of the fourth dielectric layer 106b is a planar or flat surface. In some embodiments, the fifth top surface 106c of the fourth dielectric layer 106b is coupled to the fourth top surface 103a of the isolation structure 103.

[0033] Referring to FIG3A, the memory 100 further includes a first insulating layer 107 located on the semiconductor substrate 101 and the isolation structure 103, and a conductive plug 108 extending through the first insulating layer 107. In some embodiments, the first insulating layer 107 covers the isolation structure 103, the second word line 106, the first word line 105, and at least a portion of the fins 101e. In some embodiments, the first insulating layer 107 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0034] In some embodiments, the conductive plug 108 contacts the first top surface 101f of the fin 101e. In some embodiments, the interface 108a between the conductive plug 108 and the fin 101e is a planar interface. In some embodiments, the interface 108a is disposed between the conductive plug 108 and the first top surface 101f of the fin 101e. In some embodiments, the conductive plug 108 is formed of a conductive material, such as copper, silver, or other similar materials. In some embodiments, the conductive plug 108 is configured to be electrically connected to a capacitor disposed on the first insulating layer 107.

[0035] Figure 3B is a cross-sectional view illustrating a portion of a memory element 100 taken along section line A-A' in Figure 2 according to some embodiments of the present disclosure. As shown in Figure 3B, the memory 100 may also include a contact pad 810 disposed on a conductive plug 108.

[0036] Referring to Figure 3B, a second insulating layer 807 is formed over the first insulating layer 107, and a capacitor plug 411 is formed in the second insulating layer 807. The second insulating layer 807 may be made of the same material used to form the first insulating layer 107, but is not limited thereto. The second insulating layer 807 is formed by the same process used to form the first insulating layer 107. The capacitor plug 411 is formed by the following process, which includes: performing a photolithography process to define the location of the capacitor plug 411; performing an etching process, such as anisotropic dry etching, to form a capacitor plug opening (not shown) extending through the second insulating layer 807; depositing a conductive material over the second insulating layer 807 and in the capacitor plug opening; performing a metallization process in the capacitor plug opening to form the capacitor plug 411 over the conductive plug 108; and performing a planarization process, such as chemical mechanical polishing, to remove excess deposited material and provide a substantially flat surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering. In some embodiments, a barrier layer 412 is provided between the capacitor plug 411 and the second insulating layer 807. The barrier layer 412 is disposed on and attached to the sidewalls S1 and S2 of the capacitor plug 411. The barrier layer 412 is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0037] Referring to Figure 3B, the protruding portion 411A of the capacitor plug 411 and the top portion 412A of the barrier layer 412 can protrude from the second insulating layer 807. In some embodiments, an etch-back process is performed to remove the top portion of the second insulating layer 807, thereby exposing the protruding portion 411A of the capacitor plug 411 and the top portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, the top surface of the capacitor plug 411 is higher than the top surface 807TS of the second insulating layer 807, and the sidewalls of the top portion 412A of the barrier layer 412 are exposed.

[0038] Referring to Figure 3B, firstly, a deposition process is performed to form a liner (not shown) covering the top surface 807TS of the second insulating layer 807, the top surface of the protrusion 411A, and the sidewalls S3 and S4 of the top portion 412A. In some embodiments, the liner is a silicon-containing layer, such as a polycrystalline silicon layer. Next, a heating process is performed to form a contact pad 810 on the second insulating layer 807. In some embodiments, a silicide process (heating process) is performed to form the contact pad 810 on the second insulating layer 807, wherein the contact pad 810 includes the protrusion 411A of the capacitor plug 411, the top portion 412A of the barrier layer 412, a first silicide layer (metallic silicide) 808A located on the protrusion 411A, and a second silicide layer (metallic silicide) 808B located on the sidewall of the protrusion 411A. In some embodiments, the heating process transforms a portion of the protrusion 411A and the liner into a first silicate layer 808A. In some embodiments, the heating process transforms the top portion 412A of the barrier layer 412 and the liner 808 into a second silicate layer 808B. In other words, the first silicate layer 808A and the second silicate layer 808B are made of different materials. The contact pad 810 is formed without using lithography, i.e., the contact pad 810 is self-aligned with the capacitor plug 411. In some embodiments, the thickness and shape of the protrusion 411A and the top portion 412A can be varied (not shown in the figures).

[0039] Furthermore, etching processes, such as anisotropic dry etching, can be performed to remove portions of the substrate that have not been transformed into metallic silicides by the heating process. In some embodiments, the silicide process between the top portion 412A and the substrate is performed faster than the silicide process between the protrusion 411A and the substrate, and the top of the second silicide layer 808B is higher than the top of the first silicide layer 808A. In other words, since the height H4 of the second silicide layer 808B is greater than the height H3 of the first silicide layer 808A, a stepped structure is formed between the first silicide layer 808A and the second silicide layer 808B. In some embodiments, the second silicide layer 808B surrounds the first silicide layer 808A, and the width W4 of the second silicide layer 808B is greater than the width W3 of the first silicide layer 808A.

[0040] Figure 3C is a cross-sectional view illustrating a portion of a memory element 100 taken along section line A-A' in Figure 2, according to some embodiments of this disclosure. Compared to Figure 3B, the memory element 100 in Figure 3C may also include a metal plug 163 disposed on a contact pad 810.

[0041] Referring to Figure 3C, a patterned mask 133 is disposed on the second insulating layer 807, a fifth dielectric layer 151 is disposed on the patterned mask 133, and a metal plug 163 is disposed in the fifth dielectric layer 151. In some embodiments, the metal plug 163 directly contacts the first silicate layer 808A and the second silicate layer 808B. It should be noted that, according to some embodiments, the second silicate layer 808B partially covers the sidewalls 163S of the metal plug 163. In some embodiments, the metal plug 163 is electrically connected to the capacitor plug 411 through the first silicate layer 808A and the second silicate layer 808B. In some embodiments, the metal plug 163 is made of a conductive material, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable metallic materials. The formation of the metal plug 163 may include a deposition process and a planarization process. Deposition processes can include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), sputtering, electroplating, or other suitable processes. Planarization processes can include chemical mechanical polishing (CMP).

[0042] Figure 4 is a flowchart illustrating a method S200 for manufacturing a memory element according to some embodiments of the present disclosure, and Figures 5 to 29 are cross-sectional views illustrating intermediate stages in the formation process of a memory element 100 according to some embodiments of the present disclosure.

[0043] The stages illustrated in Figures 5 through 29 are also schematically shown in the flowchart of Figure 4. The manufacturing stages illustrated in Figures 5 through 29 describe the process steps shown in Figure 4. Method S200 includes multiple operations, and the description and explanation should not be regarded as a limitation on the order of these operations. Method S200 includes multiple steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210).

[0044] In some embodiments, method S200 includes providing a semiconductor substrate having a plurality of active regions and including an isolation structure surrounding each of the plurality of active regions (step S201); forming and patterning a first dielectric layer on the semiconductor substrate and the isolation structure (step S202); removing portions of the semiconductor substrate exposed via the first dielectric layer to form a plurality of first grooves extending into the semiconductor substrate, and forming a plurality of fins protruding from the semiconductor substrate (step S203); forming a second dielectric layer conforming to each of the plurality of first grooves and surrounding the plurality of fins, wherein after forming the second dielectric layer, each of the plurality of fins has a first top surface, the first top surface being a rounded surface (step S204); forming a first conductive member within each of the plurality of first grooves and surrounded by the second dielectric layer (step S205); forming on the first conductive member... A third dielectric layer is formed and surrounded by a second dielectric layer (step S206); a portion of the first dielectric layer, the second dielectric layer, and the first top surface of the plurality of fins are removed to form a second top surface of each of the plurality of fins, wherein the second top surface is a planar surface (step S207); a first insulating layer is formed on the semiconductor substrate, and a conductive plug is formed in the first insulating layer (step S208); a second insulating layer is formed on the first insulating layer, a capacitor plug is formed in the second insulating layer and protrudes from the second insulating layer, a barrier layer is formed on the sidewall of the capacitor plug and attached to the sidewall of the capacitor plug, and a contact pad is formed on the second insulating layer and disposed on the capacitor plug (step S209); a patterned mask is formed on the second insulating layer, a fifth dielectric layer is formed on the patterned mask, and a metal plug is formed in the fifth dielectric layer and on the capacitor plug (step S210).

[0045] Referring to FIG. 5, a semiconductor substrate 101 is provided according to step S201 in FIG. 4. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate.

[0046] In some embodiments, the semiconductor substrate 101 includes a peripheral region 101a and an array region 101b that is at least partially surrounded by the peripheral region 101a. In some embodiments, the peripheral region 101a is adjacent to the periphery of the semiconductor substrate 101, and the array region 101b is adjacent to the central region of the semiconductor substrate 101. In some embodiments, the array region 101b can be used to fabricate transistors, capacitors, or other similar components.

[0047] Figure 6 is a top view of the semiconductor substrate 101 of Figure 5. In some embodiments, the peripheral region 101a is covered by a peripheral photoresist 109, as shown in Figure 6. In some embodiments, the peripheral photoresist 109 is used to protect components located in the peripheral region 101a. In some embodiments, the array region 101b is exposed via the peripheral photoresist 109, as shown in Figure 6.

[0048] Figure 7 is a cross-sectional view illustrating a portion of the array region 101b taken along section line B-B' in Figure 6, according to some embodiments of this disclosure. In some embodiments, the semiconductor substrate 101 includes a plurality of active regions 102. In some embodiments, the active regions 102 are doped regions in the semiconductor substrate 101. In some embodiments, each active region 102 includes the same type of dopant. In some embodiments, each active region 102 includes a dopant type different from the dopant types included in other active regions 102. In some embodiments, each active region 102 has the same conductivity type.

[0049] In some embodiments, the isolation structure 103 extends into the semiconductor substrate 101 and surrounds the active region 102. In some embodiments, the isolation structure 103 is a shallow trench isolation (STI) structure. In some embodiments, the isolation structure 103 defines the boundary of one of the active regions 102. In some embodiments, the isolation structure 103 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0050] In some embodiments, according to step S202 in FIG4, a first dielectric layer 122 is formed on the semiconductor substrate 101 and the isolation structure 103. In some embodiments, the first dielectric layer 122 is formed by deposition, chemical vapor deposition (CVD), or any other suitable process. Next, in some embodiments, the first dielectric layer 122 is covered by a plurality of mask layers, as shown in FIG7. In some embodiments, the mask layers include a second mask layer 121 located on the first dielectric layer 122 and a first mask layer 120 located on the second mask layer 121. In some embodiments, the first mask layer 120 includes an insulating material, such as an oxide or other similar material. In some embodiments, the first mask layer 120 includes silicon dioxide. In some embodiments, the first mask layer 120 includes a plurality of first trenches 120a that cut through the first mask layer 120 and extend over the semiconductor substrate 101 and the isolation structure 103. In some embodiments, in some embodiments, the second mask layer 121 is at least partially exposed through the first mask layer 120. In some embodiments, the second cover layer 121 comprises carbon or other similar materials.

[0051] Next, as shown in Figures 8 and 9, the first dielectric layer 122 is patterned. In some embodiments, portions of the first dielectric layer 122 exposed via the first masking layer 120 and portions of the second masking layer 121 exposed via the first masking layer 120 are removed to form a plurality of second trenches 122a, as shown in Figures 8 and 9. Figure 8 is a top view illustrating the peripheral region 101a and the array region 101b after the formation of the second trenches 122a, and Figure 9 is a cross-sectional view drawn along line C-C' in Figure 8. In some embodiments, the isolation structure 103 and the active region 102 are at least partially exposed via the second trenches 122a. After the formation of the second trenches 122a, the first masking layer 120 is removed, as shown in Figure 10.

[0052] Referring to FIG11, according to step S203 in FIG4, a portion of the semiconductor substrate 101 exposed via the first dielectric layer 122 and the second masking layer 121 is removed to form a plurality of first grooves 104a. In some embodiments, the portion of the semiconductor substrate 101 is removed by dry etching or any other suitable process. In some embodiments, the first grooves 104a extend into the semiconductor substrate 101 to form a plurality of fins 101e protruding from the semiconductor substrate 101. In some embodiments, the fins 101e and the first grooves 104a are alternately arranged.

[0053] In some embodiments, portions of the isolation structure 103 exposed via the first dielectric layer 122 and the second masking layer 121 are removed to form a plurality of second grooves 104b, as shown in FIG11. In some embodiments, the second grooves 104b extend into the isolation structure 103. In some embodiments, portions of the isolation structure 103 are removed by dry etching or any other suitable process. In some embodiments, the first grooves 104a and the second grooves 104b are alternately arranged. In some embodiments, the height H1 of the first groove 104a is substantially the same as the height H2 of the second groove 104b. In some embodiments, the height H1 of the first groove 104a is substantially less than the height H2 of the second groove 104b. In some embodiments, the first grooves 104a and the second grooves 104b are formed simultaneously or sequentially.

[0054] In some embodiments, after forming the first groove 104a, the second masking layer 121 is removed, as shown in FIG12. In some embodiments, after forming the second groove 104b, the second masking layer 121 is removed. In some embodiments, the second masking layer 121 is removed by etching or any other suitable process.

[0055] Referring to FIG. 13, a second dielectric layer 105a is formed according to step S204 in FIG. 4. In some embodiments, the second dielectric layer 105a conforms to the first groove 104a and surrounds the fin 101e. In some embodiments, the second dielectric layer 105a is formed on the bottom and sidewalls of the first groove 104a. In some embodiments, the second dielectric layer 105a is formed by thermal oxidation or any other suitable process. In some embodiments, the formation of the second dielectric layer 105a includes consuming the surface of the fin 101e exposed via the first groove 104a. In some embodiments, the width W1 of the fin 101e (as shown in FIG. 12) is reduced after the formation of the second dielectric layer 105a. In some embodiments, the second dielectric layer 105a is an oxide layer. In some embodiments, the second dielectric layer 105a is a silicon dioxide layer.

[0056] In some embodiments, after forming the second dielectric layer 105a, a rounded top surface 101g of the fin 101e is formed, as shown in FIG14. FIG14 is an enlarged view illustrating the portion surrounded by the dashed line in FIG13. In some embodiments, the rounded top surface 101g is a convex surface. In some embodiments, a portion of the second dielectric layer 105a is disposed between the first dielectric layer 122 and the rounded top surface 101g of the fin 101e. In some embodiments, the second dielectric layer 105a contacts a portion of the fin 101e exposed via the first groove 104a. In some embodiments, a portion of the rounded top surface 101g contacting the first dielectric layer 122 has a width W2, which is substantially smaller than the width W1 of the fin 101e.

[0057] Referring to Figures 15 and 16, a first conductive member 105b is formed according to step S205 in Figure 4. In some embodiments, the first conductive member 105b is surrounded by a second dielectric layer 105a. In some embodiments, the formation of the first conductive member 105b includes depositing a conductive material 105b' in a first groove 104a and over the first dielectric layer 122 and the second dielectric layer 105a, as shown in Figure 15, followed by removing a portion of the conductive material 105b' located over the first dielectric layer 122 and in the first groove 104a, as shown in Figure 16. In some embodiments, after removing a portion of the conductive material 105b', at least a small amount of the second dielectric layer 105a is exposed above the conductive material 105b'. In some embodiments, after removing a portion of the conductive material 105b', at least a small amount of the conductive material 105b' is surrounded by an active region 102. In some embodiments, the conductive material 105b' includes tungsten or other similar materials. In some embodiments, the conductive material 105b' is deposited by deposition or any other suitable process. In some embodiments, portions of the conductive material 105b' are removed by etch-back or any other suitable process.

[0058] In some embodiments, a second conductive member 106a is formed, as shown in FIG16. In some embodiments, the second conductive member 106a is formed within a second groove 104b and surrounded by an isolation structure 103. In some embodiments, the formation of the second conductive member 106a includes depositing a conductive material 105b' within the second groove 104b and on the first dielectric layer 122, as shown in FIG15, followed by removing portions of the conductive material 105b' on the first dielectric layer 122 and portions of the conductive material 105b' within the first groove 104a, as shown in FIG16. In some embodiments, the first conductive member 105b and the second conductive member 106a are formed simultaneously or separately.

[0059] Referring to Figures 17 and 18, according to step S206 in Figure 4, a third dielectric layer 105c is formed on the first conductive member 105b, and the third dielectric layer 105c is surrounded by the second dielectric layer 105a. In some embodiments, the third dielectric layer 105c is formed on the first conductive member 105b and at least partially formed within the first groove 104a. In some embodiments, the third dielectric layer 105c is a nitride layer. In some embodiments, the formation of the third dielectric layer 105c includes depositing dielectric material 105c' within the first groove 104a and on the first dielectric layer 122 and the first conductive member 105b, as shown in Figure 17, and then removing a portion of the dielectric material 105c' located outside the first groove 104a, as shown in Figure 18. In some embodiments, the dielectric material 105c' is deposited by deposition or any other suitable process. In some embodiments, a portion of the dielectric material 105c' is removed by planarization, chemical mechanical polishing (CMP), or any other suitable process.

[0060] In some embodiments, a fourth dielectric layer 106b is formed on the second conductive member 106a and at least partially within the second groove 104b. In some embodiments, the fourth dielectric layer 106b is a nitride layer. In some embodiments, the formation of the fourth dielectric layer 106b includes depositing a dielectric material 105c' within the second groove 104b and on the first dielectric layer 122 and the second conductive member 106a, as shown in FIG17, and then removing a portion of the dielectric material 105c' located outside the second groove 104b, as shown in FIG18. In some embodiments, the third dielectric layer 105c and the fourth dielectric layer 106b are formed simultaneously.

[0061] Referring to Figures 18 and 19, according to step S207 in Figure 4, a portion of the rounded top surface 101g of the second dielectric layer 105a, the first dielectric layer 122, and the fin 101e is removed. In some embodiments, after removing the rounded top surface 101g of the fin, a flat first top surface 101f of the fin 101e is formed, as shown in Figure 19. In some embodiments, the flat first top surface 101f of the fin 101e is substantially lower than the rounded top surface 101g of the fin 101e. In some embodiments, after removing the rounded top surface 101g of the fin 101e, the height H1 of the fin 101e is reduced. In some embodiments, the length of the rounded top surface 101g is greater than the length of the flat first top surface 101f.

[0062] In some embodiments, the rounded top surface 101g and a portion of the dielectric material 105c' (as shown in FIG. 17) are removed simultaneously, such that a flat first top surface 101f and a third dielectric layer 105c are formed simultaneously. In some embodiments, the removal of a portion of the first dielectric layer 122, the second dielectric layer 105a, and the rounded top surface 101g of the fin 101e includes planarization or CMP.

[0063] In some embodiments, a second top surface 105d is also formed after the third dielectric layer 105c is formed. In some embodiments, the second top surface 105d is planar and substantially coplanar with the flat first top surface 101f of the fin 101e. In some embodiments, a third top surface 105e is formed after a portion of the second dielectric layer 105a is removed. In some embodiments, the third top surface 105e is planar and substantially coplanar with the flat first top surface 101f and the second top surface 105d of the fin 101e.

[0064] In some embodiments, a portion of the isolation structure 103 is also removed to form a fourth top surface 103a, as shown in FIG18. In some embodiments, the removal of a portion of the isolation structure 103 and the removal of the rounded top surface 101g are performed simultaneously. In some embodiments, the fourth top surface 103a is planar and substantially coplanar with the flat first top surface 101f, second top surface 105d, and third top surface 105e of the fin 101e.

[0065] In some embodiments, a fifth top surface 106c is formed after the fourth dielectric layer 106b is formed. In some embodiments, the removal of a portion of the isolation structure 103 and the formation of the fourth dielectric layer 106b are performed simultaneously. In some embodiments, the fifth top surface 106c is planar and substantially coplanar with the flat first top surface 101f, second top surface 105d, third top surface 105e, and fourth top surface 103a of the fin 101e. In some embodiments, the first interface 105f between the first conductive member 105b and the third dielectric layer 105c is substantially coplanar with the second interface 106d between the second conductive member 106a and the fourth dielectric layer 106b.

[0066] Referring to Figures 20, 21, and 22, according to step S208 in Figure 4, after forming a flat first top surface 101f, a first insulating layer 107 is formed on the semiconductor substrate 101, and a conductive plug 108 is formed in the first insulating layer 107. In some embodiments, the conductive plug 108 extends through the first insulating layer 107. In some embodiments, the first insulating layer 107 is formed by disposing an insulating material 107' on the fin 101e, the isolation structure 103, the second dielectric layer 105a, the third dielectric layer 105c, and the fourth dielectric layer 106b, as shown in Figure 20. A portion of the insulating material 107' is then removed to form a plurality of third grooves 107a extending through the first insulating layer 107, as shown in Figure 21. In some embodiments, at least a portion of the flat first top surface 101f of the fin 101e is exposed via the first insulating layer 107. In some embodiments, the insulating material 107' includes insulating materials, such as oxides, nitrides, or other similar materials.

[0067] Referring to FIG22, after the formation of the first insulating layer 107, a conductive plug 108 is formed. In some embodiments, the conductive plug 108 extends through the first insulating layer 107 and contacts the flat first top surface 101f of the fin 101e. In some embodiments, the conductive plug 108 is formed by depositing a conductive material into a third recess 107a. In some embodiments, the conductive material includes copper, silver, or other similar materials. In some embodiments, the conductive material is deposited by deposition, electroplating, or any other suitable process. In some embodiments, a flat interface 108a is formed between the conductive plug 108 and the flat first top surface 101f of the fin 101e. In this way, as shown in FIG1, a memory element 100 including an array region 101b can be formed, as shown in FIG3A. In some embodiments, a cell capacitor is disposed above and electrically connected to the conductive plug 108.

[0068] Referring to Figures 4 and 23 to 26, according to some embodiments of this disclosure, in step S209, the formation of memory 100 may further include forming a second insulating layer 807, a capacitor plug 411, a barrier layer 412, and a contact pad 810. In this way, a memory element 100 including an array region 101b can be formed, as shown in Figure 3A. In some embodiments, the cell capacitor is disposed above and electrically connected to the contact pad 810.

[0069] Referring to FIG23, a second insulating layer 807 is formed on the first insulating layer 107. In some embodiments, the second insulating layer 807 may be made of the same material used to form the first insulating layer 107, but is not limited thereto. In some embodiments, the second insulating layer 807 is formed by the same process used to form the first insulating layer 107.

[0070] Referring to Figure 23, a capacitor plug 411 is formed in the second insulating layer 807 and over the conductive plug 108. In some embodiments, the capacitor plug 411 is formed by a process including: performing a photolithography process to define the location of the capacitor plug 411; performing an etching process, such as anisotropic dry etching, to form a capacitor plug opening (not shown) extending through the second insulating layer 807; depositing a conductive material over the second insulating layer 807 and in the capacitor plug opening; performing a metallization process in the capacitor plug opening to form the capacitor plug 411 over the conductive plug 108; and performing a planarization process, such as chemical mechanical polishing, to remove excess deposited material and provide a substantially flat surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering.

[0071] Referring to Figure 23, a barrier layer 412 is disposed between the capacitor plug 411 and the second insulating layer 807. The barrier layer 412 is disposed on and attached to the sidewalls S1 and S2 of the capacitor plug 411. In some embodiments, the barrier layer 412 is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0072] Referring to Figure 24, an etching process is performed to remove a portion of the second insulating layer 807, thereby exposing the protruding portion 411A of the capacitor plug 411. In some embodiments, an etch-back process is performed to remove the top portion of the second insulating layer 807, thereby exposing the protruding portion 411A of the capacitor plug 411 and the top portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, the top surface of the capacitor plug 411 is higher than the top surface of the second insulating layer 807, and the sidewalls of the top portion 412A are exposed.

[0073] Referring to Figure 25, a deposition process is performed to form a liner 808 covering the top surface 807TS of the second insulating layer 807, the top surface of the protrusion 411A, and the sidewalls S3 and S4 of the top portion 412A. In some embodiments, the liner 808 is a silicon-containing layer, such as a polycrystalline silicon layer.

[0074] Referring to Figure 26, a heating process is performed to form a contact pad 810 on the second insulating layer 807. In some embodiments, a silanization process (heating process) is performed to form the contact pad 810 on the second insulating layer 807, wherein the contact pad 810 includes a protrusion 411A of a capacitor plug 411, a top portion 412A of a barrier layer 412, a first silicide layer (metallic silicide) 808A located on the protrusion 411A, and a second silicide layer (metallic silicide) 808B located on the sidewall of the protrusion 411A. In some embodiments, the heating process transforms a portion of the protrusion 411A and the liner 808 into the first silicide layer 808A. In some embodiments, the heating process transforms the top portion 412A of the barrier layer 412 and the liner 808 into the second silicide layer 808B. In other words, the contact pad 810 is formed without using lithography, that is, the contact pad 810 is self-aligned with the capacitor plug 411. In some embodiments, the thickness and shape of the protrusion 411A and the top portion 412A can be changed (not shown in the figure).

[0075] Furthermore, an etching process, such as an anisotropic dry etching process, is performed to remove portion P2 of the substrate 808 that was not transformed into metallized silicide by the heating process. In some embodiments, the silicide process between the top portion 412A and the substrate 808 is performed faster than the silicide process between the protruding portion 411A and the substrate 808, and the top of the second silicide layer 808B is higher than the top of the first silicide layer 808A. In other words, since the height H4 of the second silicide layer 808B is greater than the height H3 of the first silicide layer 808A, a stepped structure is formed between the first silicide layer 808A and the second silicide layer 808B. In some embodiments, the second silicide layer 808B surrounds the first silicide layer 808A, and the width W4 of the second silicide layer 808B is greater than the width W3 of the first silicide layer 808A.

[0076] Referring to Figures 4 and 27 to 29, according to some embodiments of this disclosure, in step S210, the formation of the memory 100 may further include forming a patterned mask 133 on the second insulating layer 807, forming a fifth dielectric layer 151 on the patterned mask 133, and forming a metal plug 163 in the fifth dielectric layer 151 and on the capacitor plug 411. In this way, a memory element 100 including the array region 101b can be formed, as shown in Figure 3C. In some embodiments, the cell capacitor is disposed above and electrically connected to the metal plug 163.

[0077] Referring to Figure 27, a patterned mask 133 is disposed on the second insulating layer 807, and contact pads 810 are disposed within the patterned mask 133. In some embodiments, a planarization process, such as chemical mechanical polishing or etching, is performed to remove portions of the patterned mask 133, thereby providing a substantially flat surface for subsequent process steps. The planarization process is performed until the second silicate layer 808B is exposed. In some embodiments, the top surface 810TS of the contact pads 810 (or the top surface of the second silicate layer 808B) is substantially coplanar with the top surface 133TS of the patterned mask 133.

[0078] Referring to FIG28, a fifth dielectric layer 151 is formed on a patterned mask 133, and another patterned mask 153 is formed on the fifth dielectric layer 151. In some embodiments, the fifth dielectric layer 151 is etched using the patterned mask 153 as a mask to form an opening 160 through the fifth dielectric layer 151.

[0079] In some embodiments, a portion of the patterned mask 133 over the first silicate layer 808A is removed, exposing the top surface 183TS of the first silicate layer 808A through the opening 160. Furthermore, during the etching process used to form the opening 160, the second silicate layer 808B can be lightly etched. The opening 160 can be formed by a wet etching process, a dry etching process, or a combination thereof. After the opening 160 is formed, the patterned mask 153 can be removed.

[0080] Referring to Figure 29, a metal plug 163 is formed in the opening 160 (see Figure 28) to directly contact the second silicate layer 808B and the first silicate layer 808A. In some embodiments, the metal plug 163 is made of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable metallic materials. The formation of the metal plug 163 may include a deposition process and a planarization process. The deposition process may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, metal-organic chemical vapor deposition, sputtering, electroplating, or other suitable processes. The planarization process may include a chemical mechanical polishing process.

[0081] One aspect of this disclosure provides a memory element. This memory element includes: a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first flat top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins among the plurality of fins, wherein the first word line includes an oxide layer conforming to the surfaces of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second flat top surface. The active region comprises: a second flat top surface substantially coplanar with the first flat top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitor plug disposed in a second insulating layer and on the conductive plug, and configured to protrude from the second insulating layer; and a contact pad disposed on the second insulating layer and on the capacitor plug.

[0082] Another aspect of this disclosure provides a memory element. This memory element includes: a semiconductor substrate defining an active region; a plurality of fins disposed in and protruding from the active region of the semiconductor substrate, wherein each of the plurality of fins has a first flat top surface; a word line structure including a first word line extending into the semiconductor substrate and between a pair of adjacent fins among the plurality of fins, wherein the first word line includes an oxide layer conforming to the surfaces of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second flat top surface, wherein the second flat top surface is adjacent to the plurality of fins. The first flat top surface of each fin is substantially coplanar; an isolation structure extends into the semiconductor substrate and surrounds the active region; a second character line is disposed within the isolation structure and separated from the first character line by the plurality of fins; a conductive plug is disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitor plug is disposed in a second insulating layer and on the conductive plug, and is configured to protrude from the second insulating layer; a contact pad is disposed on the second insulating layer and on the capacitor plug; a patterned mask is disposed on the second insulating layer and surrounds the contact pad; and a metal plug is disposed on the contact pad.

[0083] Another aspect of this disclosure provides a method for manufacturing a memory element. This method includes: providing a first semiconductor structure, wherein the first semiconductor structure includes: a semiconductor substrate defining a plurality of active regions; an isolation structure surrounding each of the plurality of active regions; a plurality of first recesses and a plurality of second recesses located in the semiconductor substrate; a plurality of fins protruding from the semiconductor substrate, wherein each of the plurality of fins has a flat surface; a first dielectric layer conforming to each of the plurality of first recesses and surrounding the plurality of fins, wherein after the formation of the first dielectric layer, each of the plurality of fins has a first top surface; and a first conductive member located within each of the plurality of first recesses and surrounded by the first... The first conductive member is surrounded by a dielectric layer; a second dielectric layer is disposed on and surrounded by the first dielectric layer; and a conductive plug is disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure, the conductive plug extends through the first insulating layer, and each of the plurality of fins has a flat top surface; an insulating layer is formed on the first semiconductor structure; a capacitor plug is formed in the insulating layer; a barrier layer is formed on the sidewalls of the capacitor plug and attached to the sidewalls of the capacitor plug; and a contact pad is formed on the second insulating layer and on the capacitor plug.

[0084] In summary, because the top portion of each fin protruding from the substrate is planarized before contact is formed between the cell capacitor and one of the fins, the contact area between the cell capacitor and the fin is increased by the planarization of the top portion, thereby transforming the curved surface of the top portion into a flat surface. Therefore, the overall performance of the memory device and the manufacturing process of the memory device are improved.

[0085] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0086] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0087] 100: Memory Components 101: Semiconductor substrate 101a: Surrounding Area 101b: Array area 101c: First surface 101d: Second surface 101e: Fins 101f: First top surface 101g: Top surface 102: Active Zone 103: Isolation Structure 103a: Fourth top surface 104: Groove 104a: First groove 104b: Second groove 105: First character line 105a: Second dielectric layer 105b: First conductive component 105b': Conductive material 105c: Third dielectric layer 105c': Dielectric material 105d: Second top surface 105e: Third top surface 105f: First Interface 106: Second character line 106a: Second conductive component 106b: Fourth dielectric layer 106c: Fifth top surface 106d: Second Interface 107: First insulating layer 107': Insulating material 107a: Third groove 108: Conductive plug 108a: Interface 109: Peripheral light resistance 120: First curtain layer 120a: First trench 121: Second drape layer 122a: Second trench 122: First dielectric layer 133: Patterned veil 133TS: Top Surface 151: Fifth dielectric layer 153: Patterned veil 160: Opening 163: Metal plug 163S: Sidewall 183TS: Top Surface 411: Capacitor plug 411A: Protruding part 412: Barrier Layer 412A: Top section 807: Second Insulation Layer 807TS: Top Surface 808: Lining 808A: First silicon layer 808B: Second silicon layer 810: Contact pad 810TS: Top Surface H1: Height H2: Height H3: Height H4: Height P2: Part S1: Sidewall S2: Sidewall S3: Sidewall S4: Sidewall W1: Width W2: Width W3: Width W4: Width S200: Method S201: Steps S202: Steps S203: Steps S204: Steps S205: Steps S206: Steps S207: Steps S208: Steps S209: Steps S210: Steps

Claims

1. A memory element, comprising: A semiconductor substrate is defined with an active region; A plurality of fins are disposed in the active region of the semiconductor substrate and protrude from the semiconductor substrate, wherein each of the plurality of fins has a first flat top surface; A word line structure includes: a first word line extending into the semiconductor substrate and between a pair of adjacent fins among a plurality of fins, wherein the first word line includes an oxide layer conforming to the surface of the pair of adjacent fins among the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second flat top surface, wherein the second flat top surface is substantially coplanar with the first flat top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; and a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; and a capacitor plug disposed in a second insulating layer and on the conductive plug, and protruding from the second insulating layer. A contact pad is disposed on the second insulating layer and on the capacitor plug; a patterned mask is disposed on the second insulating layer and surrounds the contact pad; and a metal plug is disposed on the contact pad.

2. The memory element as claimed in claim 1, wherein the oxide layer has a third flat top surface, wherein the third flat top surface is substantially coplanar with the first flat top surface of each of the plurality of fins and the second flat top surface of the first nitride layer.

3. The memory element as claimed in claim 2, wherein the third flat top surface of the oxide layer is coupled to the first flat top surface of one of the plurality of fins and the second flat top surface of the first nitride layer.

4. The memory element as claimed in claim 3, wherein the isolation structure has a fourth flat top surface, wherein the fourth flat top surface is substantially coplanar with the first flat top surface of each of the plurality of fins.

5. The memory element as claimed in claim 1, wherein the conductive component comprises tungsten.

6. The memory element as described in claim 1, wherein a height of the second word line is substantially greater than a height of the first word line.

7. The memory element as claimed in claim 1, wherein the conductive plug extends through the first insulating layer.

8. The memory element as claimed in claim 7, wherein the conductive plug is formed of copper, silver or other similar material.

9. The memory element as claimed in claim 8, wherein the conductive plug is configured to be electrically connected to the capacitor plug, wherein the capacitor plug is disposed above the first insulating layer.

10. The memory element as claimed in claim 9, wherein the first insulating layer is formed of silicon oxide, silicon nitride, silicon oxynitride, other similar materials or combinations thereof.

11. The memory element as claimed in claim 1, wherein the capacitor plug includes a protrusion that protrudes from the second insulating layer.

12. The memory element as claimed in claim 11, wherein the capacitor plug is made of aluminum, copper, tungsten, cobalt or other suitable metal or metal alloy.

13. The memory element as claimed in claim 12, wherein the second insulating layer is formed of a material identical to that of the first insulating layer.

14. The memory element as claimed in claim 13 further includes a barrier layer disposed between the capacitor plug and the second insulating layer, and disposed on and attached to the sidewall of the capacitor plug.

15. The memory element as claimed in claim 14, wherein the barrier layer is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

16. The memory element as claimed in claim 15, wherein the barrier layer includes a top portion that protrudes from the second insulating layer and wherein the top portion has a sidewall that protrudes from a top surface of the second insulating layer.

17. The memory element as claimed in claim 16, wherein the contact pad includes the protrusion of the capacitor plug, the top portion of the barrier layer, a first silicate layer on the protrusion, and a second silicate layer on the sidewall of the top portion of the barrier layer, wherein the second silicate layer directly contacts the sidewall of the top portion of the barrier layer and the top surface of the second insulating layer.

18. The memory element as described in claim 17, wherein a heating process is performed to form the contact pad.

19. The memory element as claimed in claim 18, wherein the first silicon layer and the second silicon layer are made of different materials.

20. The memory element as claimed in claim 19, wherein the patterned mask is disposed on the second insulating layer.

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