Memory device

Abstract

According to one embodiment, a memory device includes: first and second memory regions, each including a conductive layer stacked in a first direction; a connection portion located between the first and second memory regions in a second direction, the connection portion including a platform; and interconnects, corresponding to the platforms, provided above the connection portion. First to fourth sub-steps of the connection portion are arranged in the order of the first sub-step, the second sub-step, the third sub-step, and the fourth sub-step in a direction from the first memory region to one of the second memory regions, and the first to fourth sub-steps are arranged in the order of the first sub-step, the second sub-step, the fourth sub-step, and the third sub-step in a direction from the interconnects to one of the platforms.

Description

Technical Field

[0001] The embodiments described herein are generally related to a memory device. Prior Technology

[0002] It is well known that NAND flash memory can store data in a non-volatile manner. Summary of the Invention

[0003] Generally, according to one embodiment, a memory device includes: first and second memory regions, each comprising a plurality of conductive layers stacked in a first direction and disposed in a second direction perpendicular to the first direction; a bridging portion provided in the second direction between the first memory region and the second memory region, the bridging portion coupling the plurality of conductive layers of the first memory region to each other; a connecting portion provided in the second direction between the first memory region and the second memory region, the connecting portion including a plurality of platforms coupled to the plurality of conductive layers via the bridging portion; and a plurality of interconnects connected to the plurality of platforms. Correspondingly provided above the connection portion; and a plurality of contacts that electrically couple the plurality of platforms to each other, wherein the connection portion includes a first sub-step, a second sub-step, a third sub-step, and a fourth sub-step, each including one of the plurality of platforms, the first to fourth sub-steps being arranged in the order of the first sub-step, the second sub-step, the third sub-step, and the fourth sub-step in a direction from one side of the first memory region to one side of the second memory region, and the first to fourth sub-steps being arranged in the order of the first sub-step, the second sub-step, the fourth sub-step, and the third sub-step in a direction from one side of the plurality of interconnects to one side of the plurality of platforms.

[0004] The memory device described in this embodiment helps to reduce the cost of memory devices. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram illustrating one example of the overall configuration of a memory device according to one of the first embodiments.

[0006] Figure 2 is a circuit diagram illustrating one example of a circuit configuration of a memory cell array, one of the memory devices in the first embodiment.

[0007] Figure 3 is a plan view showing one example of a planar layout of the memory cell array of the memory device according to the first embodiment.

[0008] Figure 4 is a plan view of an example of the planar layout of one memory region in the memory cell array of the memory device of the first embodiment.

[0009] Figure 5 is a cross-sectional view of an example of a cross-sectional structure of the memory region of the memory cell array of the memory device of the first embodiment.

[0010] Figure 6 is a cross-sectional view of one example of the cross-sectional structure of the memory support of the memory device of the first embodiment.

[0011] Figure 7 is a plan view of an example of a planar layout of a connecting portion of the memory cell array of the memory device according to the first embodiment.

[0012] Figure 8 is a cross-sectional view of an example of a cross-sectional structure of the connection portion of the memory cell array of the memory device according to the first embodiment.

[0013] Figure 9 is a cross-sectional view of an example of a cross-sectional structure of the connection portion of the memory device according to the first embodiment.

[0014] Figures 10, 11, and 12 are schematic diagrams illustrating one example of a cross-sectional structure of the connection portion of the memory device according to the first embodiment.

[0015] Figure 13 is a cross-sectional view illustrating one step of a method for manufacturing a memory device according to the first embodiment.

[0016] Figure 14 shows a cross-sectional view of area XIV in Figure 13.

[0017] Figures 15 and 16 are cross-sectional views illustrating one step of the method for manufacturing the memory device of the first embodiment.

[0018] Figure 17 shows a cross-sectional view of area XVII in Figure 16.

[0019] Figures 18 and 19 are cross-sectional views illustrating one step of the method for manufacturing the memory device of the first embodiment.

[0020] Figure 20 shows a cross-sectional view of area XX in Figure 19.

[0021] Figures 21 and 22 are cross-sectional views illustrating one step of the method for manufacturing the memory device of the first embodiment.

[0022] Figure 23 shows a cross-sectional view of area XXIII in Figure 22.

[0023] Figure 24 is a cross-sectional view illustrating one step of the method for manufacturing the memory device of the first embodiment.

[0024] Figure 25 shows a cross-sectional view of an example of a cross-sectional structure of a memory cell array, a memory device, and a connecting portion of a second embodiment.

[0025] Figure 26 is a schematic cross-sectional view of area XXVI of Figure 25.

[0026] Figures 27, 28, 29 and 30 are cross-sectional views illustrating one step of the method for manufacturing the memory device of the second embodiment.

[0027] Figure 31 shows a cross-sectional view of area XXXI in Figure 30. Implementation

[0028] [Example] In the following description, embodiments will be illustrated with reference to the accompanying drawings. The drawings are schematic or conceptual. The dimensions and scale of the drawings may not be identical to those of the actual product. In the following description, structural elements with the same function and configuration will be identified by the same reference symbols. The digits following the letters of the reference symbols are referenced by reference symbols containing the same letters and are used to distinguish elements with similar configurations. When elements identified by reference symbols containing the same symbols do not need to be distinguished from each other, they will be identified by reference symbols containing only letters. (1) First embodiment

[0029] One of the first embodiments of the memory device will be described with reference to Figures 1 to 24. [a] Configuration example [a-1] Configuration of memory device 1

[0030] Figure 1 is a block diagram illustrating an example of the overall configuration of a memory device 1 according to one embodiment. The memory device 1 can be controlled by an external memory controller 2. The memory device 1 is a semiconductor memory; for example, it is a NAND flash memory capable of storing data in a non-volatile manner. When the memory device 1 is a NAND flash memory, the memory device 1 communicates with the memory controller 2 by exchanging various control signals and performing data transmission based on the NAND flash memory interface standard.

[0031] As shown in Figure 1, the memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a decoder module 15, and a sense amplifier module 16.

[0032] The memory cell array 10 comprises a plurality of blocks BLK0 to BLKn (n being 1 or a larger integer). Each block BLK contains an aggregate of a plurality of memory cells capable of storing data in a non-volatile manner. In NAND flash memory, the block BLK serves as, for example, a data erasure unit. The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. For example, each memory cell is associated with one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0033] Command register 11 holds a command CMD received by memory device 1 from memory controller 2. Command CMD contains, for example, an instruction for causing sequencer 13 to perform a read operation, a write operation, an erase operation, etc.

[0034] Address register 12 holds address information ADD received by memory device 1 from memory controller 2. Address information ADD includes, for example, a block address BA, a page address PA, and a row address CA. For example, the block address BA, page address PA, and row address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0035] The sequencer 13 controls the overall operation of the memory device 1. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, the sense amplifier module 16, etc. to perform a read operation, a write operation, an erase operation, etc., based on the command CMD held in the command register 11.

[0036] Driver module 14 generates voltages for read, write, erase, and other operations. Driver module 14 applies the generated voltages to interconnects corresponding to a selected word line, for example, based on the page address PA held in address register 12.

[0037] The column decoder module 15 selects one of the blocks BLK in the memory cell array 10 based on the block address BA held in the address register 12. The column decoder module 15 transmits, for example, the voltage applied to the interconnect corresponding to the selected word line to the selected word line in the selected block BLK.

[0038] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line based on the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line (or the presence / absence of a current flowing through the bit line) and transmits a determination result to the memory controller 2 as the read data DAT.

[0039] The aforementioned memory device 1 and memory controller 2 can be combined to form a device (or a system). Examples of such a device include a memory card (e.g., an SDTM card), a USB (Universal Serial Bus) memory, a UFS (Universal Flash Storage) device, and an SSD (Solid State Drive). [a-2] Circuit configuration of memory cell array 10

[0040] Figure 2 is a circuit diagram illustrating one example of the circuit configuration of the memory cell array 10 included in the memory device 1 of this embodiment. Figure 2 shows one of the plurality of blocks BLK included in the memory cell array 10. As shown in Figure 2, the block BLK includes, for example, five serial units SU0 to SU4.

[0041] Each string cell SU contains a plurality of NAND strings NS associated with bit lines BL0 to BLm-1 (m being 1 or a larger integer). Each NAND string NS contains, for example, memory cell transistors (hereinafter also referred to as memory cells) MT0 to MTn-1 and select transistors STD and STS. Each memory cell transistor MT contains a control gate and a charge storage layer. Each memory cell transistor MT can store data in a substantially non-volatile manner. Each of the select transistors STD and STS is used to select a string cell SU during various operations.

[0042] In each NAND string NS, memory cell transistors MT0 to MTn-1 are series-coupled. The drain of transistor STD is coupled to one of the associated bit lines BL among the multiple bit lines BL0 to BLm-1. The source of transistor STD is coupled to one end of the series-coupled memory cell transistors MT0 to MTn-1. The drain of transistor STS is coupled to the other end of the series-coupled memory cell transistors MT0 to MTn-1. The source of transistor STS is coupled to the source line SL.

[0043] Each of the control gates of the memory cell transistors MT0 to MTn-1 is coupled to one of the associated word lines WL among the plurality of word lines WL0 to WLn-1.

[0044] The gates of multiple select transistors STS are coupled to select gate line SGS.

[0045] The gates of the plurality of select transistors STD in series unit SU0 are coupled to the select gate line SGD0. The gates of the plurality of select transistors STD in series unit SU1 are coupled to the select gate line SGD1. The gates of the plurality of select transistors STD in series unit SU2 are coupled to the select gate line SGD2. The gates of the plurality of select transistors STD in series unit SU3 are coupled to the select gate line SGD3. The gates of the plurality of select transistors STD in series unit SU4 are coupled to the select gate line SGD4.

[0046] Different row addresses are assigned to bit lines BL0 to BLm-1. Each bit line BL is shared by NAND strings NS that are assigned the same row address in multiple blocks BLK. Select gate lines SGD0 to SGD4 and SGS, and word lines WL0 to WLn-1 are provided to each block BLK. Source lines SL are shared, for example, by multiple blocks BLK.

[0047] A set of memory cell transistors MT coupled to a common word line WL in a string cell SU is called, for example, a cell CU. For example, the storage capacity of a cell CU containing a memory cell transistor MT for storing 1 bit of data is defined as "1 page". Depending on the number of data bits stored in the memory cell transistor MT, the cell CU may have a storage capacity of two pages or more.

[0048] The circuit configuration of the memory cell array 10 of the memory device 1 in the embodiment is not limited to the above configuration. The number of string cells SU contained in each block BLK and the number of memory cell transistors MT, select transistors STD and STS contained in each NAND string NS can be appropriately changed according to the circuit configuration of the memory cell array 10. [a-3] Structure of memory cell array 10

[0049] One example of the structure of the memory cell array 10 of the memory device 1 in this embodiment will be described. In the figures referred to below, the X direction corresponds to the direction of extension of the word line WL, the Y direction corresponds to the direction of extension of the bit line BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate 20 used to form the memory device 1. In the plan view, shading is added as appropriate to facilitate viewing. The shading added to the plan view is not necessarily related to the material or characteristics of the shading component. In the cross-sectional view, a set of configurations (components) is omitted as appropriate to facilitate viewing. The configurations in each figure are shown in a simplified manner as appropriate. <Memory Cell Array 10: Planar Layout>

[0050] Figure 3 is a plan view illustrating an example of the planar layout of the memory cell array 10 of the memory device 1 in this embodiment. Figure 3 shows the regions corresponding to the eight blocks BLK0 to BLK7.

[0051] As shown in Figure 3, for example, the planar layout of the memory cell array 10 is divided in the X direction into two memory regions MA1 and MA2 and a connection region HA. Each of the memory regions MA1 and MA2 is used for storing data. Each of the memory regions MA1 and MA2 contains a plurality of NAND strings NS. The connection region HA is located between the memory regions MA1 and MA2 arranged in the X direction. The connection region HA is one of the areas that provides contacts or the like for interconnecting the stack of memory cell array 10.

[0052] The memory cell array 10 includes a plurality of slits SLT and a plurality of slits SHE.

[0053] Each of the plurality of slot SLTs has a portion extending in the X direction. The plurality of slot SLTs are configured in the Y direction. Each of the plurality of slot SLTs traverses memory regions MA1 and MA2 and connection region HA in the X direction. Each slot SLT has a structure in which, for example, one insulator and / or a plate-shaped contact is embedded internally (in a recess in the interconnect stack). Each slot SLT divides a plurality of adjacent interconnects (e.g., word lines WL0 to WLn-1, select gate lines SGD and SGS), in which the slot SLTs are inserted. In this example, each region partitioned by the plurality of slot SLTs corresponds to a block BLK. In the description given below, among the plurality of slot SLTs configured in the Y direction, the slot SLT configured at odd-numbered positions will be referred to as "SLTo", and the slot SLT configured at even-numbered positions will be referred to as "SLTe".

[0054] A plurality of slit SHEs are configured in memory regions MA1 and MA2. Each of the plurality of slit SHEs corresponding to memory region MA1 is provided across memory region MA1. In memory region MA1, the plurality of slit SHEs are configured in the Y direction. Each of the plurality of slit SHEs corresponding to memory region MA2 is provided across memory region MA2. In memory region MA2, the plurality of slit SHEs are configured in the Y direction. In this example, four slit SHEs are configured between adjacent slits SLT. Each slit SHE has a structure in which an insulator is embedded internally (in a recess in the interconnect stack). The slit SHEs divide adjacent interconnects in which the slit SHEs are inserted. The slit SHEs divide only the select gate line SGD. In this example, each region partitioned by slits SLT and slit SHEs (or by two slit SHEs) corresponds to a string cell SU.

[0055] The connection area HA contains multiple connection parts HP and multiple bridging parts BRG.

[0056] The connecting portion HP comprises a plurality of contacts (also referred to as contact portions) interconnected with a plurality of word lines WL, etc. The connecting portion HP is a structure comprising a plurality of sub-steps (and a plurality of ball-shaped step segments) as described later (hereinafter referred to as a step structure). The connecting portion HP is configured for every two blocks BLK. In other words, the connecting portion HP is configured between adjacent slits SLTo. Each connecting portion HP is divided by a slit SLTe. In the description given below, among the plurality of connecting portions HP configured in the Y direction, the connecting portion HP located at odd-numbered positions will be referred to as "HPo", and the connecting portion HP located at even-numbered positions will be referred to as "HPe".

[0057] The bridging portion BRG is electrically coupled to memory regions MA1 and MA2 and the connection portion HP via the interconnect stack of memory cell array 10. The bridging portion BRG is a structure continuous with the interconnect stack of the two memory regions MA1 and MA2. Each of the plurality of conductive layers of the bridging portion BRG (which may also be called a bridging layer for distinction) is electrically coupled to the corresponding conductive layer in the first memory region MA1 and the second memory region MA2. The bridging portion BRG is configured for each block. Each bridging portion BRG is configured between adjacent slits SLTo and SLTe. Between slits SLTo and SLTe, the bridging portion BRG is adjacent to the connection portion HP in the Y direction. For example, the bridging portion BRG is provided between slit SLTo and the connection portion HP. Bridging portions BRGs that are adjacent to each other in the Y direction and have slits SLTo between them are separated and insulated by slits SLTo.

[0058] In this manner, the conductive layers (and insulating layers) in the interconnect stack of the memory cell array 10 extend from memory regions MA1 and MA2 to the bridging portion BRG, and further extend from the bridging portion BRG to the connection portion HP. The two memory regions MA1 and MA2, configured in the X direction, are electrically coupled via the bridging portion BRG extending in the X direction. Each conductive layer in the portion continuous with the memory region MA in the connection portion HP may have a region where each conductive layer is directly coupled to the memory region MA without requiring the bridging portion BRG.

[0059] The connection region HA may further include a contact region (not shown). A plurality of contact regions are configured, for example, for each block BLK. The contact region includes a plurality of contacts (not shown). A plurality of contacts of the connection portion HP are coupled to contacts in the contact region. Contacts in the contact region couple the contacts of the connection portion HP and the interconnects above the memory cell array 10 to the interconnects below the memory cell array 10. The contact region may be provided in the X direction between the connection portion HP and the memory region MA, or it may be provided along a slit SLTe in the connection portion HP.

[0060] In the memory cell array 10, the layout shown in FIG3 is repeatedly arranged in the Y direction. The memory cell array 10 of the memory device 1 in this embodiment may have a planar layout that is structurally different from the planar layout shown in FIG3. The number of slits SHE disposed between adjacent slits SLT can be designed to be any number. The number of string cells SU formed between adjacent slits SLT can be changed based on the number of slits SHE disposed between adjacent slits SLT. <Structure of Memory Region MA in Memory Cell Array 10> (Planar layout of memory region MA in memory cell array 10)

[0061] Figure 4 is a plan view illustrating an example of a planar layout of a memory region MA in the memory cell array 10 of the memory device 1 of this embodiment. Figure 4 shows a block BLK. As shown in Figure 4, in the memory region MA, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Each slit SLT includes a contact LI and a spacer SP.

[0062] Each memory pillar (MP) serves as, for example, a NAND string (NS). In the region between two adjacent slits (SLT), a plurality of memory pillars (MP) are arranged in, for example, 24 columns and an interleaved pattern. Slits (SHE) overlap with the memory pillars (MP) at a predetermined interval (spacing). The memory pillars (MP) overlapping with the slits (SHE) are in contact with two different select gate lines (SGD).

[0063] A plurality of bit lines BL are configured in the X direction. Each of the plurality of bit lines BL has a portion extending in the Y direction. Each bit line BL is configured such that it overlaps with at least one memory pillar MP in the Z direction within each string cell SU. In this example, two bit lines BL are configured to overlap with one memory pillar MP. One of the two bit lines BL overlapping the memory pillar MP is electrically coupled to the memory pillar MP via a contact CV.

[0064] For example, the contact CV between the memory pillar MP and the bit line BL that are in contact with the slit SHE is omitted. Therefore, the memory pillar MP and the bit line BL that are in contact with the slit SHE are electrically disconnected.

[0065] The number and configuration of components such as memory struts (MP) and slits (SHE) between adjacent slits (SLT) are not limited to the configuration described with reference to Figure 4, but can be changed as needed. The number of bit lines (BL) overlapping each memory strut (MP) can be designed to be any number.

[0066] Contact LI has a conductor extending in the X direction. Spacer SP is an insulator provided on the side of contact LI. Contact LI is sandwiched by spacer SP. Contact LI is separated and insulated from conductors adjacent to contact LI in the Y direction (e.g., word lines WL0 to WLn-1 and select gate lines SGD and SGS) by spacer SP. (Cross-sectional structure of memory region MA in memory cell array 10)

[0067] Figure 5 is a cross-sectional view taken along line VV of Figure 4, showing an example of a cross-sectional structure of the memory region MA of the memory cell array 10 of the memory device 1 of this embodiment. As shown in Figure 5, the memory cell array 10 further includes a semiconductor substrate (hereinafter simply referred to as a substrate) 20, conductive layers 21, 22 and 25, and insulating layers 32a, 32, 34 and 38. The memory cell array 10 has a structure (interconnect stack 300) in which a plurality of conductive layers 22 (22a, 22b, 22c) are stacked in the Z direction.

[0068] An insulating layer 38 is provided on the upper surface of the semiconductor substrate 20. The insulating layer 38 covers circuitry (not shown) corresponding to, for example, a column decoder module 15 and / or a sense amplifier module 16 on the semiconductor substrate 20.

[0069] A conductive layer 21 is provided on the surface above the insulating layer 38. The conductive layer 21 is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 21 serves as the source line SL. The conductive layer 21 contains, for example, silicon doped with phosphorus.

[0070] An insulating layer 32a is provided on the surface above the conductive layer 21. A conductive layer 22a is provided on the surface above the insulating layer 32a. The conductive layer 22a is, for example, a plate-shaped layer extending in an XY plane. The conductive layer 22a serves as a selected gate line (SGS). The conductive layer 22a contains, for example, tungsten.

[0071] Insulating layer 32 and conductive layer 22b are alternately stacked on the upper surface of conductive layer 22a in the Z direction. Each conductive layer 22b is, for example, a plate-shaped layer extending in an XY plane. A plurality of stacked conductive layers 22b are sequentially used as word lines WL0 to WLn-1 from the side of semiconductor substrate 20. Conductive layer 22b contains, for example, tungsten.

[0072] A conductive layer 22c is provided above the uppermost conductive layer 22b, wherein an insulating layer 32 is inserted. The conductive layer 22c is, for example, a plate-like layer extending along the XY plane. The conductive layer 22c serves as a selected gate line (SGD). The conductive layer 22c contains, for example, tungsten.

[0073] An insulating layer 34 is provided on the surface above the conductive layer 22c. The insulating layer 34 may consist of a plurality of layers. A conductive layer 25 is provided on the surface above the insulating layer 34. The conductive layer 25 is, for example, a linear layer extending in the Y direction. The conductive layer 25 serves as a bit line BL. In an area not shown, a plurality of conductive layers 25 are arranged in the X direction. The conductive layer 25 contains, for example, copper.

[0074] Each memory pillar (MP) is provided to extend in the Z direction within the interconnect stack 300, penetrating the insulating layer 32 and the conductive layer 22. The bottom of each memory pillar (MP) contacts the conductive layer 21. The intersection between the memory pillar (MP) and the conductive layer 22a serves as a select transistor (STS). The intersection between the memory pillar (MP) and each conductive layer 22b serves as a memory cell transistor (MT). The intersection between the memory pillar (MP) and the conductive layer 22c serves as a select transistor (STD).

[0075] Each memory pillar MP includes, for example, a core component 40, a semiconductor layer 41, and a stacked film 42. The core component 40 is provided to extend in the Z direction. For example, the upper end of the core component 40 is contained in a layer above the conductive layer 22c, and the lower end of the core component 40 reaches the conductive layer 21. The semiconductor layer 41 covers the periphery of the core component 40. At the bottom of the memory pillar MP, a portion of the semiconductor layer 41 contacts the conductive layer 21. Except for the portions where the semiconductor layer 41 and the interconnect layer 21 contact each other, the stacked film 42 covers the sides and bottom of the semiconductor layer 41. The core component 40 includes an insulator, for example, silicon oxide. The semiconductor layer 41 includes, for example, silicon.

[0076] A columnar contact CV is provided on the surface above the semiconductor layer 41 in the memory pillar MP. In the illustrated area, two contact CVs corresponding to two of the six memory pillar MPs are depicted. In the memory region MA, a contact CV is coupled to a memory pillar MP that does not overlap with the slit SHE and is not coupled to a contact CV in an area not shown (e.g., an area in the depth direction or forward direction of the drawing).

[0077] A conductive layer 25 (i.e., a bit line BL) contacts the upper surface of a contact CV. A contact CV is coupled to one of the conductive layers 25 in the spaces partitioned by slits SLT and SHE. That is, memory pillars MP provided between adjacent slits SLT and SHE and memory pillars MP provided between two adjacent slits SHE are electrically coupled to the conductive layers 25.

[0078] The slit SLT has a portion provided, for example, along the XZ plane and dividing the conductive layer 22. A contact LI is provided along the slit SLT. The upper portion of the contact LI contacts the insulating layer 34. The lower portion of the contact LI contacts the conductive layer 21. The contact LI serves as, for example, a portion of the source line SL. A spacer SP is provided at least between the contact LI and the conductive layers 22a, 22b, and 22c. The contact LI and the conductive layers 22a, 22b, and 22c are separated and insulated by the spacer SP.

[0079] The slit SHE has a portion provided, for example, along the XZ plane and dividing at least a conductive layer 22c. The upper end of the slit SHE contacts an insulating layer 34. The lower end of the slit SHE contacts an insulating layer 32 between the uppermost conductive layer 22b and the conductive layer 22c. The slit SHE contains an insulator, for example, silicon oxide. The upper ends of the slit SHE and the slit SLT may be aligned or misaligned. The upper ends of the slit SHE and the memory pillar MP may be aligned or misaligned.

[0080] Figure 6 is a cross-sectional view taken along line VI-VI of Figure 5, showing one example of the cross-sectional structure of the memory pillar MP in the memory device 1 of this embodiment. Figure 6 shows the cross-sectional structure of the memory pillar MP in a layer including the conductive layer 22, which is parallel to the surface of the semiconductor substrate 20.

[0081] As shown in Figure 6, the stacked membrane 42 includes, for example, a tunneling insulating membrane 43, a charge trapping membrane 44, and a block insulating membrane 45.

[0082] In the cross-section containing the conductive layer 22, a core component 40 is provided in the central portion of the memory backbone MP. A semiconductor layer 41 surrounds the sides of the core component 40. A tunneling insulating film 43 surrounds the sides of the semiconductor layer 41. A charge trapping film 44 surrounds the sides of the tunneling insulating film 43. A block insulating film 45 surrounds the sides of the charge trapping film 44. The conductive layer 22 surrounds the sides of the block insulating film 45. The tunneling insulating film 43 contains, for example, silicon oxide. The charge trapping film 44 contains, for example, silicon nitride. The block insulating film 45 contains, for example, silicon oxide or aluminum oxide.

[0083] In each of the aforementioned memory pillars MP, the semiconductor layer 41 serves as the channel region (current path) for the memory cell transistors MT0 to MTn-1 and the select transistors STD and STS. The charge trapping film 44 serves as a charge storage layer for one of the memory cell transistors MT. The memory device 1 allows a current to flow through the memory pillars MP between the bit line B1 and the contact LI (source line SL) by turning on the memory cell transistors MT0 to MTn-1 and the select transistors STD and STS. <Structure of the connecting part HP of memory cell array 10>

[0084] The structure of the connection portion HP in the memory device 1 of this embodiment will be described with reference to Figures 7 to 12.

[0085] Figure 7 is a plan view showing an example of the planar layout of the connection portion HP of the memory cell array 10 in the memory device 1 of this embodiment. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the connection portion HP of the memory cell array 10 in the memory device 1 of this embodiment. For clarity, some components of the connection portion HP are not shown in Figure 8 or are shown in a simplified manner.

[0086] As shown in Figures 7 and 8, each connecting portion HP includes a plurality of steps forming portions (hereinafter referred to as sub-steps) 311 and 312. The plurality of sub-steps 311 and 312 are provided in each connecting portion HP such that, when viewed in the Z direction, they are alternately arranged in the X direction. When viewed in the Y direction, the plurality of sub-steps 311 and 312 are provided at different locations (height, layered areas) in the Z direction. For example, in the connecting portion HP, the plurality of sub-steps 311 and 312 are arranged such that their arrangement gradually decreases from the end of the memory region MA towards the center of the connecting portion HP.

[0087] Each sub-step 311, 312 includes a plurality of conductive layers 22 and a plurality of insulating layers 32. Each of the conductive layers 22 and insulating layers 32 extends from the interconnect stack 300 of the memory region MA via the bridging portion BRG or extends directly from the memory region MA. Each sub-step 311, 312 includes k conductive layers 22. In each sub-step 311, 312, one conductive layer 22 and one insulating layer 32 form a step 80. Each sub-step 311, 312 includes a plurality of steps 80 (e.g., k steps) arranged in the Z direction. It is expected that "k" is a value represented by a power of 2 (e.g., 2, 4, 8, and 16...).

[0088] In each sub-step 311, 312, each of the plurality of conductive layers 22 comprises a plurality of portions 700 (hereinafter referred to as platforms or platform portions) that do not overlap with the upper layers (conductive layer 22 and insulating layer 32) in the Z direction. In each sub-step 311, 312, each of the plurality of platforms (e.g., k platforms) 700 is provided on each of the plurality of steps 80 contained in the sub-steps 311 and 312. Because of the formation of the platform 700, a step is formed between the plurality of steps 80 of the sub-steps 311 and 312. In the description given below, the side of each sub-step 311, 312 on which the platform 700 is formed (the side having the step) will be referred to as a step forming surface (or a step forming surface, a step configuration area, or a platform configuration area). The surfaces of the sub-steps 311 and 312 on opposite sides of the step-forming surface in a direction parallel to the surface of the semiconductor substrate 20 will be referred to as the back side.

[0089] Each of the sub-staircases 311 descends in the direction from the first memory region MA1 to the second memory region MA2. In other words, each of the sub-staircases 311 ascends in the direction from the second memory region MA2 to the first memory region MA1. In each sub-staircase 311, a plurality of platforms 700 are provided on the side facing the second memory region MA2.

[0090] Each of the sub-staircases 312 ascends in the direction from the first memory region MA1 to the second memory region MA2. In other words, each of the sub-staircases 312 descends in the direction from the second memory region MA2 to the first memory region MA1. In each sub-staircase 312, a plurality of platforms 700 are provided on the side facing the first memory region MA1.

[0091] In the following description, for the purpose of distinction, sub-step 311 may be conveniently referred to as downward sub-step 311 and sub-step 312 may be conveniently referred to as upward sub-step 312.

[0092] In this embodiment, a sub-staircase 311 and a sub-staircase 312 form a court-shaped staircase segment SS (SS1, SS2, SS3, ..., SS7, SS8). A plurality of court-shaped staircase segments (which may be simply referred to as staircase segments or a main staircase and a court-like structure) SS are arranged in the X direction within each connecting portion HP. In the plurality of court-shaped staircase segments SS, the plurality of sub-staircases 311 and 312 are arranged such that, when viewed in the Z direction, the step-forming surface of sub-staircase 311 faces the step-forming surface of sub-staircase 312.

[0093] The connection area HP comprises a plurality of intermediate portion IPs (IP1, IP2, IP3, IP4). Each intermediate portion IP is provided in the area between adjacent sub-steps 311 and 312 in the X direction. In the following description, an intermediate portion IP may be referred to as a boundary portion (or a ramp portion, a cliff portion, or a boundary area).

[0094] Each of the plurality of intermediate portion IPs is formed by the side of a plurality of groups (a plurality of steps 80) each consisting of a conductive layer 22 and an insulating layer 32. Each intermediate portion IP has a surface that slopes from memory region MA1 to memory region MA2 or from memory region MA2 to memory region MA1 (hereinafter referred to as a sloped surface).

[0095] The intermediate IP portion is formed by an etching process performed on the connection portion HP during the manufacturing process of the memory device 1. A plurality of intermediate IP portions 1 indicate that they are processed together by the same manufacturing process. A plurality of intermediate IP portions 2 indicate that they are processed together by the same manufacturing process. A plurality of intermediate IP portions 3 indicate that they are processed together by the same manufacturing process.

[0096] Each intermediate IP1 is provided between sub-steps 311 and 312 in each court-shaped stepped section SS. Each intermediate IP2 is provided between court-shaped stepped sections SS. Each intermediate IP3 is provided between two groups GP that contain multiple court-shaped stepped sections SS. Intermediate IP4 is provided between the first zone R1 and the second zone R2 in the connecting section HP.

[0097] For example, in the connection portion HP shown in Figure 8, the plurality of conductive layers 22 of the plurality of sub-steps 311 and 312 in the first region R1 correspond to the upper semiconducting layer 22 (i.e., word lines WLi to WLn-1 and select gate line SGD) of the plurality of conductive layers 22 in the memory cell array 10. The plurality of conductive layers 22 of the plurality of sub-steps 311 and 312 in the second region R2 correspond to the lower semiconducting layer 22 (i.e., select gate line SGS and word lines WL0 to WLi-1) of the plurality of conductive layers 22 in the memory cell array 10.

[0098] The connection part HP contains a plurality of contacts (contact portions) CC.

[0099] Each of the plurality of contacts CC is provided on the upper surface of a corresponding platform 700 of the plurality of platforms 700 of each sub-step 311, 312. Each contact CC is electrically coupled to one of the plurality of conductive layers 22 in memory regions MA1 and MA2 via the platform 700 and the bridging layer (conductive layer 22) of the bridging portion BRG.

[0100] A plurality of interconnects (e.g., conductive layers containing metal) 26 are provided in the Z direction above the connection region HA. Each of the plurality of interconnects 26 is electrically coupled to a corresponding of a plurality of contacts CC. Thus, each interconnect 26 is electrically coupled to a corresponding conductive layer 22 (word line WL or select gate line SGS, SGD) via contact CC and platform 700. Each of the plurality of interconnects 26 is electrically coupled to, for example, a circuit of a column decoder module 15 via another contact (not shown) provided in a contact region (not shown).

[0101] Depending on the structure of the connecting portion HP and its manufacturing process, there may be a case where the platform 700 is provided on each of two or more sub-steps 311 and 312 in a specific layer of the connecting portion HP (a conductive layer 22 at a specific location in the Z direction). In this case, a platform that does not directly contact the contact element CC can be provided.

[0102] The memory device 1 of this embodiment does not include a beam-like structure extending in the Z direction on the sub-steps 311 and 312 (or the intermediate portion IP) of the connecting portion HP. The beam-like structure is a redundant component (dummy pattern) not used as a constituent element of the memory device 1. The beam-like structure includes a structure of one or more conductive layers (or insulating layers) and one or more insulating layers stacked in the Z direction. For example, this beam-like structure is generated during the manufacturing process to ensure a dimensional margin for alignment between the constituent elements of the memory device 1 and the mask layer.

[0103] The number of sub-steps 311 and 312 provided in the connection portion HP is appropriately designed based on the number of conductive layers 22 in the interconnect stack 300 and the number of conductive layers 22 assigned to each sub-step 311, 312. For example, if the number of conductive layers 22 is half the number shown in the example of FIG8, then the number of court-shaped step sections SS and sub-steps 311 and 312 provided in region R1 defines the connection portion HP. In this case, a plurality of sub-steps 311 and 312 (platform 700) of court-shaped step sections SS1 and SS2 in region R1 are associated with the upper semi-conductive layer 22 of the interconnect stack 300, and a plurality of sub-steps 311 and 312 of court-shaped step sections SS3 and SS4 in region R1 are associated with the lower semi-conductive layer 22 of the interconnect stack 300. (Structural examples of sub-steps 311 and 312)

[0104] A more specific description of the structure of the sub-steps 311 and 312 in the connecting portion HP of the memory device 1 in this embodiment will be given with reference to FIG9. FIG9 is a schematic cross-sectional view showing the structure of a plurality of court-shaped step sections SS and a plurality of sub-steps 311 and 312 in area R1 of the connecting portion HP of FIG8.

[0105] As shown in Figure 9, each sub-staircase 311 and 312 is provided in the court-shaped staircase section SS. In each court-shaped staircase section SS, the step-forming surfaces of the two sub-staircases 311 and 312 face the center side of the court-shaped staircase section SS. In each court-shaped staircase section SS, the position of one sub-staircase in the Z direction is above the position of the other sub-staircase in the Z direction.

[0106] As described above, each sub-step 311, 312 includes a platform 700 provided on the conductive layer 22 of each step 80. Therefore, a step 799 is formed between the steps 80 disposed in the Z direction.

[0107] In each court-shaped stepped section SS, an intermediate portion IP1 is provided between two sub-steps 311 and 312. The intermediate portion IP1 serves as a boundary portion between the two sub-steps 311 and 312 of the court-shaped stepped section SS.

[0108] More specifically, the various court-shaped stepped sections SS1, SS2, SS3, and SS4 shown in Figure 9 have the configurations described below.

[0109] The first ball-shaped stepped section SS1 includes a sub-step (downward sub-step) 311-1, a sub-step (upward sub-step) 312-1, and an intermediate portion IP1-1. Sub-step 311-1 is provided on the side of memory region MA1, and sub-step 312-1 is provided on the side of memory region MA2. The position H1 of sub-step 311-1 in the Z direction is higher than the position H2 of sub-step 312-1 in the Z direction. It should be noted that the position of the top of each sub-step 311, 312 in the Z direction is used as a reference for comparing the positions of sub-steps 311 and 312 in the Z direction. The position of the components (e.g., sub-steps 311 and 312) in the connecting portion HP in the Z direction is represented by the position measured from the surface of semiconductor substrate 20.

[0110] Viewed in the Z direction, the intermediate portion IP1-1 is provided in the X direction between sub-steps 311-1 and 312-1. Viewed in the Y direction, the intermediate portion IP1-1 has a step-forming surface facing the lower sub-step 312-1 in the X direction. Viewed in the Y direction, the intermediate portion IP1-1 is provided in the Z direction between the lowest step (bottom) of the upper sub-step 311-1 and the lowest step of the lower sub-step 312-1. The inclined surface of the intermediate portion IP1-1 extends from the lowest step of the upper sub-step 311-1 to the lowest step of the lower sub-step 312-1. The inclined surface of the intermediate portion IP1-1 may be a surface substantially perpendicular to the surface of the semiconductor substrate 20.

[0111] The middle part IP1 has a dimension D1 in the Z direction (see Figure 12).

[0112] When viewed in the Z direction, the second court-shaped stepped section SS2 is adjacent to the court-shaped stepped section SS1 in the X direction via the intermediate portion IP2-1. The position of the court-shaped stepped section SS2 in the Z direction is lower than that of the court-shaped stepped section SS1 in the Z direction.

[0113] The ball court-shaped stepped section SS2 includes a sub-step 311-2, a sub-step 312-2, and an intermediate portion IP1-2. Sub-step 311-2 is provided on the side of memory region MA1, and sub-step 312-2 is provided on the side of memory region MA2. When viewed in the Z direction, sub-step 311-2 is aligned with sub-step 312-1 in the X direction, with an intermediate portion IP2-1 between them. Sub-step 311-2 is positioned between sub-steps 312-1 and 312-2 in the X direction. The position H3 of sub-step 311-2 in the Z direction is lower than the position H4 of sub-step 312-2 in the Z direction.

[0114] In two adjacent court-shaped stepped sections SS1 and SS2 in the X direction, the relationship between the position of sub-step 311 in the Z direction and the position of sub-step 312 in the Z direction is different in each court-shaped stepped section SS.

[0115] The intermediate portion IP1-2 is provided in the X direction between sub-steps 311-2 and 312-2. The intermediate portion IP1-2 is provided in the Z direction below sub-step 312-2. The intermediate portion IP1-2 forms a surface facing the steps of sub-step 311-2 in the X direction. The inclined surface of the intermediate portion IP1-2 extends from the lowest step of sub-step 312-2 to the lowest step of sub-step 311-2. The intermediate portion IP1-2 has a dimension D1 in the Z direction.

[0116] The intermediate portion IP2-1 is disposed in a region (boundary zone) between the first court-shaped stepped section SS1 and the second court-shaped stepped section SS2. The intermediate portion IP2-1 is provided between the top step (top) of sub-step 312-1 and the top step of sub-step 311-2. The inclined surface of the intermediate portion IP2-1 extends from the top step of the upper sub-step 312-1 to the top step of the lower sub-step 311-2. The intermediate portion IP2-1 has a dimension D2 in the Z direction (see Figure 12). For example, the dimension D2 of the intermediate portion IP2-1 is larger than the dimension D1 of the intermediate portion IP1.

[0117] When viewed in the Z direction, the third court-shaped stepped section SS3 is adjacent to the second court-shaped stepped section SS2 in the X direction via the middle portion IP3. The position of the court-shaped stepped section SS3 in the Z direction is lower than the position of the court-shaped stepped section SS2 in the Z direction.

[0118] The court-shaped stepped section SS3 includes a sub-step 311-3, a sub-step 312-3, and an intermediate section IP1-3. In the court-shaped stepped section SS3, the configuration of sub-steps 311-3 and 312-3 is similar to the configuration of sub-steps 311-1 and 312-1 in the court-shaped stepped section SS1.

[0119] In the X-direction configuration of sub-steps 311-3 and 312-3, sub-step 311-3 is provided on the side of memory region MA1, and sub-step 312-3 is provided on the side of memory region MA2. The position H5 of sub-step 311-3 in the Z-direction is higher than the position H6 of sub-step 312-3 in the Z-direction. The positions H5 and H6 of sub-steps 311-3 and 312-3 in the Z-direction are lower than the position H3 of sub-step 311-2 in the Z-direction.

[0120] In the ball court-shaped stepped section SS3, the intermediate portion IP1-3 is provided between sub-steps 311-3 and 312-3. The intermediate portion IP1-3 is provided below sub-step 311-3 in the Z direction. The inclined surface of the intermediate portion IP1-3 faces the step-forming surface of sub-step 312-3 in the X direction. The intermediate portion IP1-3 has a dimension D1 in the Z direction.

[0121] The intermediate portion IP3 is disposed in a zone (boundary zone) between the second court-shaped step section SS2 and the third court-shaped step section SS3. The intermediate portion IP3 is provided between the top rung of sub-step 312-2 and the top rung of sub-step 311-3. The inclined surface of the intermediate portion IP3 extends from the top of sub-step 312-2 to the top of sub-step 311-3. The intermediate portion IP3 has a dimension D3 in the Z direction (see Figure 12). For example, the dimension D3 of the intermediate portion IP3 is larger than the dimension D2 of the intermediate portion IP2.

[0122] The fourth court-shaped stepped section SS4 is adjacent to the third court-shaped stepped section SS3 in the X direction, with a middle section IP2-2 positioned between them. The aforementioned court-shaped stepped section SS3 is positioned between court-shaped stepped sections SS2 and SS4 in the X direction. Court-shaped stepped section SS4 is positioned higher than court-shaped stepped section SS3 in the Z direction.

[0123] The court-shaped stepped section SS4 includes a sub-step 311-4, a sub-step 312-4, and an intermediate section IP1-4. In the court-shaped stepped section SS4, the configuration of sub-steps 311-4 and 312-4 is similar to the configuration of sub-steps 311-2 and 312-2 in the court-shaped stepped section SS2.

[0124] In the X-direction configuration of sub-steps 311-4 and 312-4, sub-step 311-4 is provided on the side of memory region MA1, and sub-step 312-4 is provided on the side of memory region MA2. The position H7 of sub-step 311-4 in the Z-direction is lower than the position H8 of sub-step 312-4 in the Z-direction. The positions H7 and H8 of sub-steps 311-4 and 312-4 in the Z-direction are lower than the position H3 of sub-step 311-2 in the Z-direction. The positions H7 and H8 of sub-steps 311-4 and 312-4 in the Z-direction are higher than the position H5 of sub-step 311-3 in the Z-direction.

[0125] In the ball court-shaped stepped section SS4, the intermediate portion IP1-4 is provided between sub-steps 311-4 and 312-4. The intermediate portion IP1-4 is provided below sub-step 312-4 in the Z direction. The inclined surface of the intermediate portion IP1-4 faces the step-forming surface of sub-step 311-4 in the X direction. The intermediate portion IP1-4 has a dimension D1 in the Z direction.

[0126] As described above, each contact CC is provided on the platform 700 of the conductive layer 22 of each of the sub-steps 311 and 312. Each contact CC is coupled to an upper-layer interconnect 26.

[0127] As described above, in each ball-shaped stepped section SS, sub-steps 311 and 312 are inclined to each other and adjacent to each other in the X and Z directions.

[0128] In the following description, a group GP consisting of four sub-steps 311 and 312 of two adjacent court-shaped stepped sections SS in the X direction (with an intermediate portion IP2 between them) will be referred to as a stepped group GP (GP1, GP2, ...). When the four sub-steps 311 and 312 forming the stepped group GP are described in the unit of the court-shaped stepped section SS, the two court-shaped stepped sections SS arranged in the X direction (with an intermediate portion IP2 between them) will be referred to as a court group SX (SX1, SX2, ...). (Layout of sub-stairs 311 and 312 of stair group GP)

[0129] Referring to Figure 10, a more specific description will be given of how each of the stair groups GP1 and GP2 of the connecting portion HP is constructed in the memory device 1 of this embodiment (i.e., the arrangement pattern of the plurality of sub-stairs 311 and 312 in the X direction and their positions in the Z direction).

[0130] Figure 10(a) is a schematic cross-sectional view showing the arrangement of multiple sub-steps 311 and 312 of step group GP1 (court group SX1). Figure 10(b) is a schematic cross-sectional view showing the arrangement of multiple sub-steps 311 and 312 of step group GP2 (court group SX2).

[0131] In the examples shown in Figures 10(a) and (b), the orientation of the plurality of sub-steps 311 and 312 of each stair group GP1, GP2 is from the first memory region MA1 to the second memory region MA2 (from the right side of the drawing to the left side), and this direction is considered to be the reference direction for describing this embodiment. In this configuration direction, the sub-steps (downward sub-steps) 311 and the sub-steps (upward sub-steps) 312 are alternately arranged in each stair group GP.

[0132] As described above, when the plurality of sub-steps 311 and 312 are provided at different heights, the plurality of step-forming surfaces of the plurality of sub-steps 311 and 312 are not arranged at the same height (layer) in the X direction. That is, the plurality of platforms 700 do not exist on the same straight line (same height) in the X direction.

[0133] As shown in Figure 10(a), among the four sub-steps 311-1, 312-1, 311-2, and 312-2 belonging to step group GP1, the position H1 of the top of sub-step 311-1 in the Z-direction is higher than any of the positions H2, H3, and H4 of the top of sub-steps 312-1, 311-2, and 312-2 in the Z-direction. The position H3 of the top of sub-step 311-2 in the Z-direction is lower than any of the positions H1, H2, and H4 of the top of sub-steps 311-1, 312-1, and 312-2 in the Z-direction.

[0134] The position H2 of the top of sub-staircase 312-1 in the Z direction is lower than the position H1 of the top of sub-staircase 311-1 in the Z direction but higher than the position H4 of the top of sub-staircase 312-2 in the Z direction. The position H4 of the top of sub-staircase 312-2 in the Z direction is lower than the position H2 of the top of sub-staircase 312-1 in the Z direction but higher than the position H3 of the top of sub-staircase 311-2 in the Z direction.

[0135] As described above, in this embodiment, in the stair group GP1 composed of two adjacent ball-shaped stair sections SS1 and SS2, the four sub-stairs 311-1, 312-1, 311-2 and 312-2 are arranged in the X direction (for example, in one of the directions from the first memory region MA1 to the second memory region MA2) in the order of sub-stairs 311-1, sub-stairs 312-1, sub-stairs 311-2 and sub-stairs 312-2.

[0136] In addition, these four sub-steps 311-1, 312-1, 311-2, and 312-2 are arranged in the Z direction in the order of sub-steps 311-1, 312-2, 312-2, and 311-2 (that is, in descending order of the height of sub-steps 311 and 312 in the Z direction).

[0137] As shown in Figure 10(b), among the four sub-steps 311-3, 312-3, 311-4, and 312-4 belonging to step group GP2, the position H8 of the top of sub-step 312-4 in the Z-direction is higher than any of the positions H5, H6, and H7 of the top of sub-steps 311-3, 312-3, and 311-4 in the Z-direction. The position H6 of the top of sub-step 312-3 in the Z-direction is lower than any of the positions H5, H7, and H8 of the top of sub-steps 311-3, 311-4, and 312-4 in the Z-direction.

[0138] The position H7 of the top of sub-step 311-4 in the Z direction is lower than the position H8 of the top of sub-step 312-4 in the Z direction and higher than the position H5 of the top of sub-step 311-3 in the Z direction.

[0139] The position H5 of the top of sub-step 311-3 in the Z direction is lower than the position H7 of the top of sub-step 311-4 in the Z direction and higher than the position H6 of the top of sub-step 312-3 in the Z direction.

[0140] As described above, in this embodiment, in the stair group GP2 composed of two adjacent ball-shaped stair sections SS3 and SS4 in the X direction, four sub-stairs 311-3, 312-3, 311-4 and 312-4 are arranged from the first memory region MA1 to the second memory region MA2 in the X direction in the order of sub-stairs 311-3, sub-stairs 312-3, sub-stairs 311-4 and sub-stairs 312-4.

[0141] These four sub-steps 311-3, 312-3, 311-4 and 312-4 are arranged in the Z direction in the order of sub-steps 312-4, 311-4, 311-3 and 312-3 (that is, in descending order of the height of sub-steps 311 and 312 in the Z direction).

[0142] In the plurality of sub-steps 311-1, 312-1, 311-2 and 312-2 of the step group GP1, the third sub-step 311-2, counted from the first memory region MA1 to the second memory region MA2, exists at the lowest position in the Z direction.

[0143] On the other hand, among the plurality of sub-steps 311-3, 312-3, 311-4 and 312-4 of the step group GP2, the second sub-step 312-3, counted from the first memory region MA1 to the second memory region MA2, exists at the lowest position in the Z direction.

[0144] When the heights of the plurality of sub-steps 311-3, 312-3, 311-4 and 312-4 are counted in order from the second memory region MA2 to the first memory region MA1, the sub-step 312-3 with height H6 is the third sub-step counted from the side of the second memory region MA2.

[0145] When the arrangement of the step-forming surfaces of the plurality of sub-steps 311-3, 312-3, 311-4 and 312-4 relative to the stair group GP2 is oriented in the direction from the side of the second memory region MA2 to the side of the first memory region MA1, the sub-steps 311-3 and 311-4 can be regarded as upward sub-steps and the sub-steps 312-3 and 312-4 can be regarded as downward sub-steps.

[0146] As can be seen from the above, the structures of the sub-steps 311-3, 312-3, 311-4 and 312-4 of step group GP2 are symmetrical with the structures of the sub-steps 311-1, 312-1, 311-2 and 312-2 of step group GP1.

[0147] That is, in this embodiment, the height distribution of the plurality of sub-steps 311-3, 312-3, 311-4 and 312-4 of the step group GP2 (court group SX2) has a mirror relationship with the height distribution of the plurality of sub-steps 311-1, 312-1, 311-2 and 312-2 of the step group GP1 (court group SX1) (symmetric about the X direction), wherein the middle part IP3 serves as a boundary (axis of symmetry).

[0148] In step group GP1, the height distribution of sub-steps 311-2 and 312-2 of the second court-shaped step section SS2 is a mirror image of the height distribution of steps 311-1 and 312-1 of the first court-shaped step section SS1, with the middle part IP2-1 serving as a boundary. Similarly, in step group GP2, the height distribution of sub-steps 311-4 and 312-4 of the fourth court-shaped step section SS4 is a mirror image of the height distribution of sub-steps 311-3 and 312-3 of the court-shaped step section SS3, with the middle part IP2-2 serving as a boundary.

[0149] In this embodiment, the symmetry axis system of the two structures having a mirror relationship intersects the inclined surface of each intermediate part IP along an axis in the Z direction (this axis may be referred to as the Z axis below).

[0150] In the connecting section HP, the height distribution of the plurality of sub-steps 311 and 312 in zone R2 is a mirror image of the height distribution of the plurality of sub-steps 311 and 312 in zone R1, with the Z-axis intersecting the intermediate section IP4 serving as an axis of symmetry. However, the plurality of sub-steps 311 and 312 in zone R2 are provided in a zone (layer) that is lower in the Z direction than the plurality of sub-steps 311 and 312 in zone R1. (The structure of sub-steps 311 and 312 belonging to different step groups GP)

[0151] Referring to Figure 11, one description of the structure of multiple sub-steps 311 and 312 belonging to different step groups GP will be given (configuration pattern in the X direction and position in the Z direction).

[0152] Figure 11 is a schematic cross-sectional view of one of the structures of a plurality of sub-steps 311 and 312, wherein two ball court-shaped step sections SS2 and SS3, which are arranged in the X direction via the middle part IP3, are extracted from the connection part HP of the memory device 1 in this embodiment.

[0153] As shown in Figure 11, in the two ball-shaped stepped sections SS2 and SS3 with the middle part IP3 between them, a plurality of sub-steps 311-2, 312-2, 311-3 and 312-3 are arranged from the side of the first memory region MA1 to the side of the second memory region MA2 in the order of sub-steps 311-2, sub-steps 312-2, sub-steps 311-3 and sub-steps 312-3.

[0154] As described above, sub-staircase 311-2 has a height H3 in the Z direction, and sub-staircase 312-2 has a height H4 in the Z direction. Sub-staircase 311-3 has a height H5 in the Z direction, and sub-staircase 311-4 has a height H6 in the Z direction.

[0155] The position H3 of sub-step 311-2 in the Z direction is lower than the position H4 of sub-step 312-2 in the Z direction and higher than the position H5 of sub-step 311-3 in the Z direction.

[0156] The position H5 of sub-step 311-3 in the Z direction is lower than the position H3 of sub-step 311-2 in the Z direction and higher than the position H6 of sub-step 312-3 in the Z direction.

[0157] These four sub-steps 311-2, 312-2, 311-3, and 312-3 are arranged in the Z direction in the order of sub-steps 312-2, 311-2, 311-3, and 312-3 (i.e., in descending order of the height of the tops of sub-steps 311 and 312 in the Z direction).

[0158] It can be seen that, among the multiple sub-steps 311-2, 312-2, 311-3 and 312-3 in the ball court-shaped stepped sections SS2 and SS3, the height power of sub-steps 311-2, 312-2, 311-3 and 312-3 in the Z direction is different from the arrangement order of sub-steps 311-2, 312-2, 311-3 and 312-3 in the X direction.

[0159] In addition, the height distribution of sub-steps 311-2 and 312-2 in the court-shaped staircase section SS2 is a mirror image of the height distribution of sub-steps 311-3 and 312-3 in the court-shaped staircase section SS3, with the middle part IP3 serving as a boundary. (Structure of the SS section, shaped like a sports field)

[0160] As shown in Figures 8 to 11, the four court-shaped stepped sections SS1, SS2, SS3 and SS4 in area R1 are arranged along the X direction in the order of court-shaped stepped section SS1, court-shaped stepped section SS2, court-shaped stepped section SS3 and court-shaped stepped section SS4 in one of the directions from memory area MA1 to memory area MA2.

[0161] When comparing the positions (coordinates) of the court-shaped stepped sections SS1, SS2, SS3 and SS4 in the Z direction within the unit of the court-shaped stepped section SS, the power of height reduction in the Z direction is the order of court-shaped stepped sections SS1, SS2, SS4 and SS3.

[0162] The position of the court-shaped stepped section SS in the Z direction is considered to be the top of the higher sub-step in the Z direction, which is one of the two sub-steps 311 and 312 contained in each court-shaped stepped section SS.

[0163] This will be described in detail.

[0164] The court-shaped stepped section SS1 is provided above the court-shaped stepped sections SS2, SS3 and SS4 in the Z direction.

[0165] The court-shaped stepped section SS2 is provided in the Z direction below the court-shaped stepped section SS1 and above the court-shaped stepped section SS4.

[0166] The court-shaped stepped section SS4 is provided in the Z direction below the court-shaped stepped section SS2 and above the court-shaped stepped section SS3.

[0167] The court-shaped stepped section SS3 is provided in the Z direction below the court-shaped stepped sections SS1, SS2 and SS4.

[0168] When the positions of the court-shaped stepped sections SS5, SS6, SS7, and SS8 in zone R2 are compared in the Z direction as the positions of the court-shaped stepped sections SS1, SS2, SS3, and SS4 in zone R1, the power of the height of the court-shaped stepped sections SS5, SS6, SS7, and SS8 in the Z direction is the order of court-shaped stepped section SS8, court-shaped stepped section SS7, court-shaped stepped section SS5, and court-shaped stepped section SS6.

[0169] However, as described above, the positions of court-shaped stepped sections SS5, SS6, SS7, and SS8 in the Z-direction are lower than the position of court-shaped stepped section SS3 in the Z-direction. For example, court-shaped stepped section SS5 is provided in the Z-direction below court-shaped stepped section SS3 and above court-shaped stepped section SS6 in zone R1. Court-shaped stepped sections SS7 and SS8 are provided in the Z-direction below court-shaped stepped section SS3 and above court-shaped stepped section SS5 in zone R1.

[0170] As described above, the distribution of the height positions of the multiple ball-shaped stepped sections SS has a configuration similar to that of the height position distribution of sub-steps 311 and 312. (Structure of the middle IP portion)

[0171] Referring to Figure 12, one description of the structure of the plurality of intermediate portions IP in the connection portion HP of the memory device 1 in this embodiment will be given.

[0172] Figure 12 is a schematic cross-sectional view illustrating one of the structures of the plurality of intermediate portions (boundary portions, inclined portions, cliff portions) IP in the connection portion HP of the memory device 1 in this embodiment.

[0173] As described above, a plurality of intermediate portions IP1 (IP1-1, IP1-2, IP1-3, and IP1-4), IP2 (IP2-1, IP2-2), IP3, and IP4 are provided in the connection portion HP. Each intermediate portion IP includes a plurality of conductive layers 22 and a plurality of insulating layers 32. Unlike the sub-steps 311 and 312, the intermediate portion IP does not have a platform 700. Therefore, a contact CC is not provided on the intermediate portion IP. However, it should be noted that a contact CC may contact the uppermost conductive layer 22 of the intermediate portion IP.

[0174] The intermediate portion IP1-1 is provided in the ball court-shaped stepped section SS1. The intermediate portion IP1-1 has an inclined surface F1-1 facing one of the second memory regions MA2. The inclined surface F1-1 is inclined from the side of the first memory region MA1 to the side of the second memory region MA2.

[0175] The intermediate portion IP1-2 is provided in the ball court-shaped stepped section SS2. The intermediate portion IP1-2 has an inclined surface F1-2 facing one of the first memory regions MA1. The inclined surface F1-2 is inclined from the side of the second memory region MA2 toward the side of the first memory region MA1.

[0176] The intermediate portion IP1-3 is provided in the ball court-shaped stepped section SS3. The intermediate portion IP1-3 has an inclined surface F1-3 facing one of the second memory regions MA2. The inclined surface F1-3 is inclined from the side of the first memory region MA1 to the side of the second memory region MA2.

[0177] The intermediate portion IP1-4 is provided in the ball court-shaped stepped section SS4. The intermediate portion IP1-4 has an inclined surface F1-4 facing one of the first memory regions MA1. The inclined surface F1-4 is inclined from the side of the second memory region MA2 toward the side of the first memory region MA1.

[0178] Intermediate portion IP2-1 is provided in the boundary region between the court-shaped stepped section SS1 and the court-shaped stepped section SS2. Intermediate portion IP2-1 is provided in the X direction at a position between intermediate portions IP1-1 and intermediate portions IP1-2. Intermediate portion IP2-1 has an inclined surface F2-1 facing one of the second memory regions MA2. Inclined surface F2-1 is inclined from the side of the first memory region MA1 to the side of the second memory region MA2.

[0179] Intermediate portion IP2-2 is provided in the boundary region between the court-shaped stepped section SS3 and the court-shaped stepped section SS4. Intermediate portion IP2-2 is provided in the X direction at a position between intermediate portions IP1-3 and intermediate portions IP1-4. Intermediate portion IP2-2 has an inclined surface F2-2 facing one of the first memory regions MA1. Inclined surface F2-2 is inclined from the side of the second memory region MA2 toward the side of the first memory region MA1.

[0180] The intermediate portion IP3 is provided in the boundary area between the court-shaped stepped section SS2 and the court-shaped stepped section SS3. The intermediate portion IP3 is provided in the X direction at a position between the intermediate portions IP1-2 and the intermediate portions IP1-3. The intermediate portion IP3 has an inclined surface F3 facing one of the second memory regions MA2. The inclined surface F3 is inclined from the side of the first memory region MA1 to the side of the second memory region MA2.

[0181] For example, the tilt angles of the tilted surface F1 of the intermediate portion IP1, the tilt angles of the tilted surface F2 of the intermediate portion IP2, and the tilt angles of the tilted surface F3 of the intermediate portion IP3 are substantially equal. However, it should be noted that the tilt angles of the intermediate portions IP1, IP2, and IP3 may vary depending on the processing conditions. The tilt angle of the intermediate portion IP is an angle formed by the X direction (the upper surface of the substrate 20 or platform 700) and the tilted surface.

[0182] The inclined surfaces F1, F2, and F3 are not limited to flat surfaces, but can be irregular. Due to their irregularity, steps can be generated on the inclined surfaces F1, F2, and F3. The size of the platform on the inclined surfaces F1, F2, and F3 that can generate steps is much smaller than the size of the platform 700 of the sub-steps 311 and 312.

[0183] Each intermediate IP portion has a dimension in the Z direction, as described below.

[0184] For example, the dimension of the intermediate portion IP in the Z direction (the height of the intermediate portion IP) is the distance in the Z direction from the platform surface connected to the upper end (top) of the intermediate portion IP to the platform surface connected to the lower end (bottom) of the intermediate portion IP. The upper end of the intermediate portion IP is one end of the intermediate portion IP on the side of the interconnect 26, and the lower end of the intermediate portion IP is one end of the intermediate portion IP on the side of the substrate 20.

[0185] Each intermediate portion IP1 has a dimension D1 in the Z direction. Dimension D1 is substantially equal to, for example, the dimension D0 of sub-step 311 (or sub-step 312) in the Z direction. However, it should be noted that dimension D1 may differ from dimension D0 and may, for example, be one step larger than dimension D0. Each intermediate portion IP2 has a dimension D2 in the Z direction. Dimension D2 is larger than dimension D1. For example, dimension D2 is about 1.5 to 2 times the dimension D1. Intermediate portion IP3 has a dimension D3 in the Z direction. Dimension D3 is larger than dimension D2 and is, for example, about 1.5 to 2 times the dimension D2.

[0186] For example, regarding the Z-direction coordinates of the middle part IP, the position Ha of the upper end of the middle part IP1-1 in the Z-direction is above the position Hb1 of the upper end of the middle part IP2-1 in the Z-direction. The position Hb1 of the upper end of the middle part IP2-1 in the Z-direction is the same as the position H2 of the platform 700 on the top step (top) of the sub-staircase 312-1 in the Z-direction.

[0187] The upper part of the middle section IP1-2 is at a position Hc in the Z direction lower than the upper part of the middle section IP2-1 is at a position Hb1 in the Z direction but higher than the lower part of the middle section IP2-1 is at a position Hb2 in the Z direction. The lower part of the middle section IP2-1 is at a position Hb2 in the Z direction, which is the same as the uppermost platform 700 of the sub-step 311-2 is at a position H3 in the Z direction.

[0188] The position Hd of the upper end of the middle part IP1-3 in the Z direction is higher than the position Hb3 of the lower end of the middle part IP2-2 in the Z direction and lower than the position Hb4 of the upper end of the middle part IP2-2 in the Z direction. The position Hb3 of the lower end of the middle part IP2-2 in the Z direction is the same as the position H6 of the uppermost platform 700 of the sub-step 312-3 in the Z direction.

[0189] The position He of the upper end of the middle part IP1-4 in the Z direction is higher than the position Hb4 of the upper end of the middle part IP2-2 in the Z direction. The position Hb4 of the upper end of the middle part IP2-2 in the Z direction is the same as the position H7 of the uppermost platform 700 of the sub-step 311-4 in the Z direction.

[0190] The upper part of the middle IP3, in the Z direction, is positioned Hf, which is lower than the upper part of the middle IP1-1, in the Z direction, and higher than the upper part of the middle IP1-2, in the Z direction, Hc. The lower part of the middle IP3, in the Z direction, is positioned Hg, which is lower than the upper part of the middle IP1-4, in the Z direction, He, and higher than the upper part of the middle IP1-3, in the Z direction, Hd.

[0191] The upper ends of each intermediate IP1 are continuously connected to the lower platform 700 of the corresponding sub-steps 311 and 312. The position of the upper end of each intermediate IP1 in the Z direction is substantially the same as the position of the lower platform 700 connected to the upper end of the intermediate IP1. The upper ends of each intermediate IP2 are continuously connected to the upper platform 700 of the corresponding sub-steps 311 and 312. The position of the upper end of each intermediate IP2 in the Z direction is substantially the same as the position of the upper platform 700 connected to the upper end of the intermediate IP2. The upper end of each intermediate IP3 is continuously connected to the upper platform 700 of the sub-step 312. The position of the upper end of each intermediate IP3 in the Z direction is substantially the same as the position of the upper platform 700 connected to the upper end of the intermediate IP3.

[0192] Therefore, the position of the upper part of the middle IP in the Z direction is essentially the same as the position of the bottom of the contact CC connected to the upper platform 700 in the Z direction.

[0193] In the two stair groups GP1 and GP2 configured in the X direction, similar to the height distribution of the sub-stairs 311 and 312 (and the ball court-shaped stair section SS) belonging to the two stair groups GP1 and GP2, the height distribution of the plurality of intermediate parts IP1-1, IP1-2 and IP2-1 belonging to stair group GP1 has a mirror relationship with the height distribution of the plurality of intermediate parts IP1-3, IP1-4 and IP2-2 belonging to stair group GP2, wherein the intermediate part IP3 serves as a boundary.

[0194] The plurality of sub-steps 311 and 312, the plurality of ball-shaped step sections SS, and the plurality of intermediate IPs in area R2 of the connecting portion HP shown in Figure 8 have a structure in which the configuration shown in Figures 9 to 12 is horizontally flipped, and are configured from the second memory area MA2 to the first memory area MA1. The height distribution of the plurality of intermediate IPs in area R2 is a mirror image of the height distribution of the plurality of intermediate IPs shown in Figure 12, wherein intermediate IP4 serves as a boundary portion.

[0195] The middle section IP4 is adjacent to the ball court-shaped stepped section SS4 in the X direction.

[0196] The intermediate portion IP4 has an inclined surface F4 facing one of the second memory regions MA2. The inclined surface F4 is inclined from the side of the first memory region MA1 towards the side of the second memory region MA2. The upper end of the intermediate portion IP4 is positioned in the Z direction higher than the upper end position He of the intermediate portions IP1-4 and lower than the upper end position Hc of the intermediate portions IP1-2. For example, the upper end position of the intermediate portion IP4 in the Z direction is the same as the position H8 of the uppermost platform 700 of the sub-step 312-4. The intermediate portion IP4 has a dimension D4 in the Z direction. Dimension D4 is larger than dimension D3 and is, for example, about 1.5 to 2 times the size of dimension D3.

[0197] In this embodiment, the sub-steps 311 and 312 and the ball court-shaped step section SS in the connection portion HP of the memory device 1 are formed by the manufacturing process described later so as to have the aforementioned periodic structure.

[0198] Therefore, in the memory device 1 of this embodiment, the adjacent structures (sub-steps, ball-shaped step sections, step groups, etc.) (where the intermediate portions IP1, IP2, IP3 and IP4, generated by batch etching multiple layers in the manufacturing process, serve as boundaries) have a mirror relationship with each other.

[0199] In Figures 7 to 12, the positions (coordinates) of sub-steps 311 and 312 in the Z-direction are shown as the positions of the top (uppermost part) of sub-steps 311 and 312 in the Z-direction. However, it should be noted that the positions of sub-steps 311 and 312 in the Z-direction can be indicated by a portion other than the top of sub-steps 311 and 312. For example, the positions of sub-steps 311 and 312 in the Z-direction can be indicated by the positions of the bottom (lowermost part) of sub-steps 311 and 312 or by the center position between the top and bottom of sub-steps 311 and 312. In Figures 7 to 12, the positions of sub-steps 311 and 312 in the X-direction are the positions of the ends of sub-steps 311 and 312 on the side of the first memory region M1. However, it should be noted that the positions of sub-steps 311 and 312 in the X direction can be indicated by the portion other than the ends of sub-steps 311 and 312 on the side of the first memory region M1. For example, the positions of sub-steps 311 and 312 in the X direction can be indicated by the positions of the ends of sub-steps 311 and 312 on the side of the second memory region MA2 or by the center position between the two ends of the sub-steps in the X direction.

[0200] Even if the reference positions of sub-steps 311 and 312 change, the plurality of sub-steps 311 and 312 still maintain the same positional relationship in both the X and Z directions as described in Figures 7 to 12.

[0201] Furthermore, a structure other than the semiconductor substrate 20 can be used to refer to "up" and "top" with respect to the Z direction. For example, in the case where a wafer bonding structure of the semiconductor substrate 20 is removed, the direction in which the platform 700 is oriented to provide a contact CC thereon can be associated with "up" and "top". [b] Manufacturing method

[0202] A method for manufacturing a memory device according to the first embodiment will be described with reference to Figures 13 to 24. Figures 13, 15, 16, 18, 19, 21, 22, and 24 are cross-sectional views illustrating one step of the method for manufacturing the memory device 1 of the embodiment. Figures 14, 17, 20, and 23 are cross-sectional views illustrating one step of the method for manufacturing the memory device of the embodiment, with a portion of the connecting part HP extracted.

[0203] As shown in Figure 13, for example, a circuit (not shown) including a column decoder module 15 is formed on a semiconductor substrate 20 by CVD (chemical vapor deposition), and then an insulating layer 38 is formed on the semiconductor substrate 20. The circuit on the semiconductor substrate 20 is covered by the insulating layer 38. A conductive layer 21 is formed on the insulating layer 38, for example, by CVD. The conductive layer 21 is a layer used for the source lines SL in the memory cell array 10.

[0204] An insulating layer 32a is formed on the conductive layer 21, for example, by CVD. A plurality of insulating layers 32 and a plurality of insulating layers 39 are formed alternately on the insulating layer 32a, for example, by CVD.

[0205] Therefore, in a memory region MA and a connection region HA, a stack 300X is formed in the Z direction above the semiconductor substrate 20. The lowest layer of the stack 300X in the Z direction is an insulating layer 32a, and this lowest insulating layer 32a is formed on the upper surface of the conductive layer 21. An insulating layer 39 is formed on the upper surface of the insulating layer 32a.

[0206] The plurality of insulating layers 39 are layers that are replaced by conductive layers 22 (e.g., select gate lines SGS and SGD and word lines WL) in the steps described later. In the following description, insulating layer 39 will be referred to as a sacrificial layer 39. The number of sacrificial layers 39 in the layer stack 300X may vary depending on the number of conductive layers 22 formed in the memory cell array 10.

[0207] A mask layer 90 is formed in the Z direction above the layer stack 300X by performing a photolithography process. A plurality of openings OP0 are provided in the mask layer 90.

[0208] The openings OP0 are provided such that they correspond to the positions in which the court-shaped stepped sections will be formed in the connecting region HA. The number of openings OP0 disposed in the connecting region HA in the X direction can be varied according to the number of conductive layers 22 provided in the memory cell array 10. In the example shown in Figure 13, the masking layer 90 includes eight openings OP0 above the connecting region HA of a block BLK.

[0209] By repeatedly etching the layer stack 300X and repeatedly slimming the mask layer 90, a mountain-shaped structure (hereinafter referred to as a mountain) 301 is formed in the layer stack 300X when viewed in the Y direction. The mountain 301 is a structure containing a plurality of platforms 700. The mountain (also referred to as a double-sided staircase) 301 contains a plurality of platforms 700 on the side of the first memory region MA1 and the side of the second memory region MA2.

[0210] The portion between two adjacent mountain sections 301 in the X direction (the area between the side edges of the mountain) is called a valley section 302.

[0211] More specifically, the plurality of mountain sections 301 and the plurality of valley sections 302 are formed by performing multiple etching and slimming processes, as described below.

[0212] A first anisotropic etching is performed based on the pattern of mask layer 90, with layer stacking 300X to remove one step of 80X etch amount through opening OP0. Therefore, a sacrificial layer 39 and an insulating layer 32 are removed from the region corresponding to opening OP0. Subsequently, mask layer 90 is selectively shrunk (slimmed down) by isotropic etching in a slimming process. Therefore, opening OP0 isotropically widens.

[0213] A second anisotropic etching process (performed after the first slimming process) is performed using mask layer 90, with layer stack 300X etched through opening OP0 by an etching amount of one step 80X. At this time, upper platform 700 acts as a mask for one of the lower layers 32 and 39 of layer stack 300X. Therefore, a step 799 is formed between the two stacked sacrificial layers 39 (two steps 80X), and a stepped structure is formed in layer stack 300X. A second slimming process (isotropic etching) is performed on mask layer 90. This further isotropically widens opening OP0.

[0214] Subsequently, multiple etching processes (e.g., k etching processes) and multiple slimming processes (e.g., k-1 slimming processes) are performed until a plurality of hills 301 containing a predetermined number (k) of platforms 700 are formed.

[0215] Figure 14 is one example of the configuration of area XIV shown in Figure 13.

[0216] For example, as shown in Figure 14, a plurality of hills 301 are formed in a layer stack 300X. Each hill 301 includes two platforms 700 on each side of the hill 301. In each step 80X of the hill 301, the upper surface of the sacrificial layer 39 is exposed and the upper surface of the insulating layer 32 is covered by the upper sacrificial layer 39.

[0217] The dimension (width) W1 of the platform 700 formed in the first position of one of the steps 80X in the Z direction is substantially equal in both the X and Y directions. The dimension W2 of the platform 700 formed in the second position of one of the steps 80X in the Z direction is substantially equal in both the X and Y directions. Preferably, the widths of the platforms 700 in the steps 80X are substantially the same, but their equality may differ.

[0218] Since platform 700 is formed, the processed shape of the ends of memory regions MA1 and MA2 on the side of the connecting portion HP is like a staircase. Therefore, in the connecting portion HP, sub-staircases 311x and 312x containing a plurality of stacked sacrificial layers 39 are formed at the terminal portions of memory regions MA1 and MA2.

[0219] After the mountain section 301 is formed, the masking layer 90 is removed. Therefore, in the connection region HA, the layer stack 300X has a ladder 80X, each containing an insulating layer 39 and an insulating layer 32.

[0220] As shown in Figure 15, a mask layer 91 is formed in the Z direction above the layer stack 300X using a lithography process. A plurality of openings OP1 are provided in the mask layer 91. The plurality of openings OP1 formed in the mask layer 91 cause the mountain portions 301 (301a, 301b) disposed in each connecting portion HP in the X direction to be alternately exposed. Therefore, in the connecting portion HP, the mountain portion 301a exposed in the openings OP1 and the mountain portion 301b covered by the mask layer 91 are alternately disposed in the X direction.

[0221] The mask layer 91 is patterned by a photolithography process so that the edge Eg1 of the opening OP1 (also called the opening edge or mask edge) is located in the region (valley) 302 between the side edges of the two hills 301a and 301b arranged in the X direction.

[0222] In this step, regarding the misalignment of the masking layer 91, the position of the edge Eg1 of the opening OP1 of the masking layer 91 in the X direction can be designed to ensure a margin in the size of the platform width of the platform 700 that will be formed at the lowest step of each of the hills 301a and 301b based on the masking layer 91 by an etching process.

[0223] The number of openings OP1 disposed in each connection portion HP in the X direction can be varied according to the number of conductive layers 22 provided in the memory cell array 10. In the example shown in FIG15, the masking layer 91 includes four openings OP1 disposed in the X direction and located above the connection portion HP. When the number of openings OP1 is 4, the number of masking edges Eg1 of the masking layer 91 appearing in the cross section along the X direction is 8.

[0224] As shown in Figure 16, the layer stack 300X is etched by anisotropic etching based on the pattern of the mask layer 91. In this etching, the patterns of the platform 700 and step 799 of the mountain 301a are transferred to the underlying sacrificial layer 39 and insulating layer 32. Therefore, a mountain 301c is formed in the region (location) below the mountain 301b (301a) in the Z direction. The mountain 301c has a structure substantially the same as that of the mountain 301a.

[0225] Figure 17 is one example of the configuration of area XVII shown in Figure 16.

[0226] As shown in Figure 17, for example, in the connecting portion HP, layer stack 300X is etched through opening OP1 with an etch amount corresponding to the height of the mountain 301 of a plurality of layers 32 and 39. The uppermost step of the formed mountain 301c is positioned one step lower than the lowermost step of the mountain 301a.

[0227] By etching the mountain portion 301a and the valley portion 302, a plurality of intermediate portions (cliff portions) IP1 are formed below the mountain portion 301b, making them continuous with the bottom (lowest platform 700) of the mountain portion 301b. The intermediate portions IP1 are adjacent to the mountain portion 301c in the X direction. For example, each intermediate portion IP1 includes a taper and has a specific tilt angle in the Z direction. The tilted surface of each intermediate portion IP1 faces the mountain portion 301c. The dimension of the intermediate portion IP1 in the Z direction is larger than the dimension of the mountain portion 301c in the Z direction.

[0228] In the following description, the process of processing multiple steps 80X in the stack 300X by means of a single anisotropic etching (e.g., the etching performed on the hill 301 in this step) will be referred to as a multi-stage etching process (or a multi-stage etching step).

[0229] After the mountain part 301c and the middle part IP1 are formed by a multi-level etching process, the mask layer 91 is removed.

[0230] As shown in Figure 18, a mask layer 92 is formed in the Z direction above the layer stack 300X by a lithography process. A plurality of openings OP2 are provided in the mask layer 92. The mask edge Eg2 of each opening OP2 is disposed on the top TPa of the hill 301c (the upper end of the hill 301c in the Z direction). When the number of openings OP2 is 2, the number of mask edges Eg2 of the mask layer 92 appearing in the cross section along the X direction is 4.

[0231] A plurality of openings OP2 are exposed in a region between the tops TPa of two hills 301c in the X direction, with hills 301b (or 301d) interposed between them. Therefore, the step-forming surface on one side of one of the hills 301c in the X direction is exposed in the openings OP2. Additionally, the hill 301d, positioned between two exposed step-forming surfaces in the X direction, is also exposed in the openings OP2.

[0232] On the other hand, the mountain 301b between the stepped surfaces covered by the masking layer 92 is covered by the masking layer 92.

[0233] As described above, in this step, the position of the edge Eg2 of the opening OP2 of the mask layer 92 in the X direction is different from the position of the edge Eg1 of the opening of the mask layer 91 in the steps shown in Figures 15 to 17.

[0234] In this step, regarding the misalignment between the masking layer 92 and the top TPa of the mountain 301c, the position of the edge Eg2 of the opening OP2 can be designed with a margin in mind, based on the platform width (the dimension of the platform in the X direction) of the top of the mountain 301c.

[0235] As shown in Figure 19, the 300X stack is etched by anisotropic etching based on the pattern of the mask layer 92.

[0236] Figure 20 is one example of the configuration of area XX shown in Figure 19.

[0237] In this step, the layer stack 300X is etched to a height corresponding to the height of the plurality of layers 32 and 39 (plural steps 80X) contained in the mountain 301d and the middle part IP1.

[0238] In this etching, the patterns of the platform 700 and steps 799 of the exposed mountain 301d are transferred to the lower sacrificial layer 39 and insulating layer 32.

[0239] Therefore, a mountain portion 301e and an intermediate portion IP1 are formed in the area below which the mountain portion 301d is located. The mountain portion 301e has a structure substantially identical to that of the mountain portion 301d.

[0240] By etching the mountain portion 301c, the stepped surface (a plurality of platforms and steps) and valleys on the exposed side of the mountain portion 301c are etched, with the masking edge Eg2 serving as a boundary, and a plurality of intermediate portions IP2 are formed. The pattern of the stepped surface on the etched side of the mountain portion 301c is transferred to a plurality of insulating layers 32 and a plurality of sacrificial layers 39 below the intermediate portions IP2. Therefore, a sub-step 311x or a sub-step 312x is formed below the intermediate portions IP2. Furthermore, the portion of the mountain portion 301c covered by the masking layer 92 is not etched and is left as sub-steps 311x and 312x. In this way, a plurality of sub-steps 311x and 312x are formed from one mountain portion 301c. The intermediate portions IP1 face the formed plurality of sub-steps 311x and 312x in the X direction, respectively.

[0241] For example, the upper part of the mountain 301e is located in the Z direction below the bottom surface of the middle part IP1 covered by the masking layer 92.

[0242] After the multi-level etching process in this step is completed, remove the mask layer 92.

[0243] As shown in Figure 21, a mask layer 93 is formed in the Z direction above the layer stack 300X using a lithography process. An opening OP3 is provided in the mask layer 93. The mask edge Eg3 of the opening OP3 of the mask layer 93 is located in the X direction on the top TPb of the respective hill 301e (the upper end of the hill 301e in the Z direction). The number of mask edges Eg3 of the mask layer 93 appearing in the cross section along the X direction is 2.

[0244] The opening OP3 partially exposes the mountain section 301e in the connecting portion HP, with the top TPb of the mountain section 301e serving as a boundary. The opening OP3 exposes the area between the top TPb of the two mountain sections 301e in the X direction. Therefore, in addition to the portion of the mountain section 301e, the mountain section 301b above the intermediate portion IP2 and the sub-steps 311x and 312x with their respective tops TPa are also exposed through the opening OP3.

[0245] As described above, in this step, the position of the edge Eg3 of the opening OP3 of the masking layer 93 in the X direction differs from the position of the edge Eg2 of the opening OP2 of the masking layer 92 in the steps shown in Figures 18 to 20. In this step, regarding the misalignment between the masking layer 93 and the top TPb of the mountain 301e, the position of the edge Eg3 of the opening OP3 can be designed with a margin in mind, considering the platform width (the dimension of the platform in the X direction) of the top TPb of the mountain 301e.

[0246] As shown in Figure 22, the 300X stack is etched by anisotropic etching based on the pattern of the mask layer 93.

[0247] Figure 23 is one example of the configuration of area XXIII shown in Figure 22.

[0248] As shown in Figure 23, in this step, the layer stack 300X is etched to a certain height corresponding to the plurality of layers 32 and 39 (plural steps 80X) contained in the mountain 301b (301f) and the intermediate portions IP1 and IP2. In the etching performed through the opening OP3, the pattern of the mountain 301b and sub-steps 311x and 312x shown in Figure 21 is transferred to the underlying sacrificial layer 39 and insulating layer 32.

[0249] Therefore, a mountain section 301f, sub-steps 311x and 312x, and intermediate portions IP1 and IP2 are formed in the area below the component covered by the shielding layer 93. The mountain section 301f has a structure substantially identical to that of the mountain section 301b. For example, the upper end of the mountain section 301f is located in the Z direction below one step of the lowest platform 700 covered by the shielding layer 93.

[0250] Through this etching, intermediate IP3 portions are formed on the back side of sub-steps 311x and 312x that are configured with mask edges Eg3. Each intermediate IP3 portion extends from the top TPb to the upper end of the sub-steps 311x and 312x below the top TPb.

[0251] After the multi-level etching process in this step is completed, remove the mask layer 93.

[0252] As shown in Figure 24, a mask layer 94 is formed in the Z direction above the layer stack 300X using a lithography process. An opening OP4 is provided in the mask layer 94. The opening edge Eg4 of the opening OP4 of the mask layer 94 is located on the top TPc of the hill 301f in the X direction. The opening OP4 exposes the upper side region R2 of the second memory region MA2 from the top TPc of the hill 301f in the connecting portion HP. A mask layer 94 covers the region R1 of the connecting portion HP of the first memory region MA1, which is closer to the top TPc of the hill 301f. The number of mask edges Eg4 of the mask layer 94 appearing in the cross section along the X direction is 2.

[0253] As described above, in this step, the position of the edge Eg4 of the opening OP4 of the masking layer 94 in the X direction is different from the position of the edge Eg2 of the opening OP2 of the masking layer 92 in the steps shown in Figures 18 to 20, and different from the position of the edge Eg3 of the opening OP3 of the masking layer 93 in the steps shown in Figures 21 to 23. In this step, regarding the misalignment between the masking layer 94 and the top TPc of the mountain 301f, the position of the edge Eg4 of the opening OP4 can be designed with a margin in mind, considering the platform width (the dimension of platform 700 in the X direction) of the top TPc of the mountain 301f.

[0254] That is, in this embodiment, the portion of the mask edges Eg (Eg1, Eg2, Eg3, Eg4) that are continuously disposed in multiple multi-stage etching steps does not exist in the connecting portion HP. Therefore, the beam-like structure extending in the Z direction is not formed in the connecting portion HP.

[0255] Subsequently, the layer stack 300X is etched by anisotropic etching based on the pattern of the mask layer 94. In this step, the layer stack 300X is etched in an amount corresponding to the height of a plurality of steps 80 from the top of the layer stack 300X to the bottom surface of the middle portion IP1 of the bottom layer.

[0256] Therefore, as shown in Figure 8 above, within region R2, the pattern of each exposed component is transferred to the plurality of sacrificial layers 39 and the plurality of insulating layers 32 located below. Furthermore, in this step, the surface above the sacrificial layer 39, which is the bottommost layer of the layer stack 300X, is exposed. An intermediate portion IP4 is formed below the mask edge Eg4 in the boundary region between region R1 and region R2.

[0257] After the multi-stage etching process is completed, remove the mask layer 94.

[0258] Through a manufacturing process comprising the aforementioned multi-level etching procedures, a pattern of one of several sub-steps 311 and 312 and a pattern of one of several ball-shaped step segments SS are formed, which are mirror images of each other and have an intermediate portion IP between them. According to the aforementioned manufacturing process, no beam-shaped structure is formed in the connecting portion HP.

[0259] After the stepped structure (including a plurality of sub-steps 311 and 312) is formed in the connecting portion HP, the memory strut MP is formed in the memory cell array 10 (see Figures 5 and 6). The procedure for forming the memory strut MP is summarized below.

[0260] First, a mask layer with a plurality of openings is formed on the layer stack 300X. In this step, the openings of the mask layer are formed in regions corresponding to the locations where a plurality of memory pillars MP are formed. By using this mask layer for anisotropic etching, a plurality of memory retention regions are formed in memory regions MA1 and MA2 of the layer stack 300X. The block insulating film 45, charge trapping film 44, and tunneling insulating film 43 are sequentially formed on the side and bottom surfaces of the plurality of memory retention regions. A portion of the block insulating film 45, charge trapping film 44, and tunneling insulating film 43 provided at the bottom of the memory retention regions is removed. Subsequently, a semiconductor layer 41 and a core component 40 are formed in the memory retention regions. A portion of the core component 40 provided in the region above the memory retention regions is removed. A semiconductor layer 41 is formed in the void created by the removal.

[0261] Subsequently, an insulating layer 34 is formed on the memory cell array 10. At this point, the insulating layer 34 is embedded in the connection region HA, and the bridging portion BRG and the connection portion HP are covered by the insulating layer 34.

[0262] After the insulating layer 34 is formed, a slot SLT is formed in a predetermined region of the layer stack 300X. Subsequently, a replacement procedure for the sacrificial layer 39 is performed. Thus, an interconnect stack 300 is formed. Specifically, a plurality of sacrificial layers 39 are selectively removed via the slot SLT by wet etching using hot phosphoric acid or the like. Therefore, air gaps are created in the regions where the sacrificial layers 39 of the layer stack 300X are removed. The structure from which the plurality of sacrificial layers 39 are removed is maintained by a plurality of memory pillars (MP), support pillars (not shown), etc. Conductors are embedded in the air gaps within the layer stack 300X via the slot SLT. For example, in this step, a CVD method is used to form a conductor.

[0263] The conductors formed inside the slit SLT are removed by an etch-back process. Therefore, the conductors formed in adjacent interconnect layers are separated. Thus, a conductive layer 22a serving as the select gate line SGS, a plurality of conductive layers 22b serving as word lines WL0 to WLn-1, and a conductive layer 22c serving as the select gate line SGD are formed.

[0264] The conductive layer 22 extends to the memory regions MA1 and MA2, the bridging portion BRG in the connection region HA, and the connection portion HP. The conductive layer 22 is exposed above the sub-steps 311 and 312 of the connection portion HP. Therefore, the exposed portion of the conductive layer 22 is formed as a platform 700 in the sub-steps 311 and 312.

[0265] The conductive layer 22 formed in this step may include a barrier metal. In this case, during the conductor formation process performed after the removal of the sacrificial member 39, titanium nitride is deposited as a barrier metal and then tungsten is formed on the titanium nitride.

[0266] After the conductive layer 22 is formed, an embedding process is performed on the slit SLT. Specifically, an insulating layer (spacer SP) is formed in a manner that covers the sides and bottom of the slit SLT. Next, a portion of the spacer SP provided at the bottom of the slit SLT is removed. Subsequently, a contact LI is formed in the slit SLT.

[0267] A slit SHE is formed to facilitate the segmentation of the conductive layer 22c in the Y direction.

[0268] A plurality of contacts CC are formed on the steps 311 and 312 of the connecting portion HP by a contact forming step. Each of the plurality of contacts CC is coupled to the corresponding platform 700 of the plurality of sub-steps (downward sub-steps) 311 and the plurality of sub-steps (upward sub-steps) 312 in the connecting portion HP.

[0269] In an interconnect formation step, a plurality of interconnects 26 are formed over an insulating layer 34 covering the memory region MA and the connection region HA. Each of the plurality of interconnects 26 is coupled to a corresponding contact CC in the connection portion HP.

[0270] As described above, the manufacturing process of the memory device 1 in this embodiment forms a stepped structure for coupling contacts to an interconnect stack 300 in the memory cell array 10.

[0271] The manufacturing method (manufacturing process) of the connection portion HP of the memory device 1 in this embodiment is not limited to the examples shown in Figures 13 to 24 (e.g., the number of layers in the hill 301, the number of layers in the sub-steps 311 and 312, the number of openings in each masking layer and / or the number of times a multi-level etching process is performed), but can be appropriately changed depending on the number of conductive layers 22 in the memory cell array 10. [c] Conclusion

[0272] In the process of manufacturing a stepped structure in a connection area of ​​a specific memory device, an extra component (hereinafter referred to as a beam-like structure) extending in the Z direction may be generated in the connection area to provide a margin for misalignment between the connection area and the masking layer.

[0273] Beam-shaped structures increase the size of the connection area and can cause defects in the event of collapse.

[0274] Furthermore, if one of the masking edges (one edge of the opening OP) of the masking layer is disposed on the beam structure or on the intermediate portion IP produced by a multi-stage etching process, a slit extending to one of the multiple steps of the sub-step may be formed in the layer stack due to the displacement of the masking edge. If a conductor remains in this slit during the replacement of a conductor from a sacrificial layer, a short circuit occurs between the interconnects.

[0275] If a large margin is ensured at the masking edge of the masking layer to avoid such defects, the area of ​​the connecting region tends to increase.

[0276] The memory device 1 of this embodiment has the configuration shown in Figures 10 to 12 regarding the X and Z directions of the plurality of sub-steps 311 and 312 in the connection portion HP.

[0277] According to this embodiment, as described with reference to Figures 13 to 24 above, when forming the connection portion HP having the configuration shown in Figures 10 to 12, the positions of the edges of the openings OP1, OP2, OP3, and OP4 of the layer stack 300X etched in each of the mask layers 91, 92, 93, and 94 in the connection portion HP are not repeatedly arranged at specific positions in the connection portion HP. In the memory device 1 of this embodiment formed by this manufacturing process, the connection portion HP does not include a beam-shaped structure.

[0278] Therefore, in this embodiment, the alignment margin between the connection region HA and the masking layers 91, 92, 93, and 94 does not need to be designed under harsh conditions. Thus, the space required to ensure the margin is reduced.

[0279] Therefore, the memory device 1 of this embodiment can reduce the area of ​​the connection region HA. Therefore, the memory device 1 of this embodiment can reduce the chip size.

[0280] Furthermore, according to this embodiment, the aforementioned beam-like structure, which is generated to ensure a certain alignment margin, is not formed in the connection region HA.

[0281] Therefore, the memory device 1 of this embodiment can suppress defects that may occur in the connection part due to the beam-shaped structure.

[0282] As described above, the memory device and its manufacturing method in this embodiment help to reduce the cost of the memory device. (2) Second embodiment

[0283] The memory device and its manufacturing method according to the second embodiment will be described with reference to Figures 25 to 31. [a] Configuration

[0284] The configuration of memory device 1 in this embodiment will be described with reference to Figures 25 and 26.

[0285] Figure 25 is a schematic cross-sectional view illustrating a structural example of a connection portion of the memory cell array 10 of the memory device 1 in this embodiment. As shown in Figure 25, in this embodiment, each of the step group GP (two ball court-shaped step sections SS) comprising four sub-steps 311z and 312z has the structure (configuration pattern) shown in Figure 10(a) or (b), as in the first embodiment. These step groups GP are configured in the connection portion HP such that the two structures adjacent to the intermediate portions IP2 and IP3, which serve as boundaries, have a mirror relationship.

[0286] In this embodiment, the plurality of sub-steps 311z and 312z and the plurality of intermediate portions IP may have the structures described in Figures 11 and 12.

[0287] In this embodiment, the structure of the plurality of sub-steps 311z and 312z in region R2 is a mirror image of the structure of the plurality of sub-steps 311z and 312z in region R1, and there is no intermediate part serving as a boundary between the two regions R1 and R2. In this respect, this embodiment differs from the first embodiment.

[0288] Furthermore, the internal configuration of sub-steps 311z and 312z in this embodiment differs from the internal configuration of sub-steps 311 and 312 described in conjunction with the first embodiment.

[0289] Therefore, in this embodiment, the correspondence between the platform 700 (700a, 700b) in each of regions R1 and R2 and the conductive layer 22 in memory regions MA1 and MA2 is different from the correspondence between the platform 700 and the conductive layer 22 in the first embodiment.

[0290] For example, each of the sub-steps 311z and 312z in region R1 includes a platform 700a contained in one of the even-numbered conductive layers (e.g., word lines WL0, WL2, ...) among the plurality of conductive layers 22. Each of the sub-steps 311z and 312z in region R2 includes a platform 700b contained in one of the odd-numbered conductive layers (e.g., select gate line SGS, word lines WL1, WL3, ...) among the plurality of conductive layers 22.

[0291] The configuration of the sub-steps 311z and 312z in the connection portion HP of the memory device 1 provided in this embodiment will be described with reference to FIG26.

[0292] Figure 26 is a schematic cross-sectional view of area XXVI of Figure 25.

[0293] As shown in Figure 26, a plurality of sub-steps (downward sub-steps) 311z (311z-3, 311z-4, 311z-5 and 311z-6) and a plurality of sub-steps (upward sub-steps) 312z (312z-3, 312z-4, 312z-5 and 312z-6) are alternately arranged in the X direction, as in the first embodiment. A pair of sub-steps 311z and 312z form a ball-shaped staircase section SS.

[0294] In each of the sub-steps 311z and 312z, a platform 700 (700a, 700b) is provided to one of a pair (hereinafter referred to as a step pair) containing two steps 80 99.

[0295] One of a plurality of contacts CC (CCa, CCb) is provided on the surface above platform 700 of step 99.

[0296] In this embodiment, in the boundary region between regions R1 and R2, two sub-steps 311z-5 and 312z-4 are adjacent to each other in the X direction, such that the back surfaces of sub-steps 311z-5 and 312z-4 are in contact with each other. The conductive layer 22 and insulating layer 32 of each step 80 are continuous between the two sub-steps 311z-5 and 312z-4. The two sub-steps 311z-5 and 312z-4 share a plurality of conductive layers 22 and a plurality of insulating layers 32.

[0297] The positions of sub-steps 311z and 312z in zone R2 in the Z direction are shifted down by one step 80 from the positions of sub-steps 311z and 312z in zone R1 in the Z direction.

[0298] For example, when comparing sub-staircase 311z-5 and sub-staircase 312z-4, the top of sub-staircase 311z-5 is positioned in the Z direction one step lower than the top of sub-staircase 312z-4 in the Z direction. When the platform 700a of sub-staircase 312z-4 is provided with an even number of steps in the step 80 series of step pairs 99, the platform 700b of sub-staircase 311z-5 is provided with an odd number of steps in the step pairs 99.

[0299] Therefore, each of the sub-steps 311z and 312z in region R1 has a platform 700a corresponding to one of the plurality of even-numbered conductive layers 22. Platform 700a is coupled to contact CCa. Each of the sub-steps 311z and 312z in region R2 has a platform 700b corresponding to one of the plurality of odd-numbered conductive layers 22. Platform 700b is coupled to contact CCb.

[0300] As described above, in this embodiment, a plurality of conductive layers 22 in the memory region MA are coupled to, for example, a circuit of a decoder module 15 via a bridging portion BRG and a connecting portion HP. [b] Manufacturing method

[0301] The manufacturing method of the memory device 1 in this embodiment will be described with reference to Figures 27 to 30.

[0302] Figures 27 and 30 are schematic cross-sectional views illustrating one step of a method for manufacturing the memory device 1 of this embodiment.

[0303] As shown in Figure 27, the etching process based on the pattern of the mask layer 90 and the slimming process of the mask layer 90 are repeated to form a plurality of hills 309 in the layer stack 300X, as shown in Figures 13 and 14 of the first embodiment.

[0304] In this embodiment, the layers are stacked 300X to etch one of the two insulating layers 32 and the two sacrificial layers 39 by an etching process.

[0305] Therefore, a group comprising two insulating layers 32 and two sacrificial layers 39 (a step pair 99x comprising two steps 80x) is formed into a step 799x by an etching step. In each step pair 99x, the upper surface of the sacrificial layer 39 above the step pair 99x is exposed, and each of the upper surfaces of the two insulating layers 32 and one sacrificial layer 39 below the upper sacrificial layer 39 is covered by an upper layer (insulating layer 32 or sacrificial layer 39).

[0306] As described above, a plurality of steps 799x are formed in a layer stack 300X by an etching process, wherein four layers, including two insulating layers 32 and two sacrificial layers 39, are processed as a unit.

[0307] As shown in Figure 28, a mask layer 91 is formed in the Z direction above the layer stack 300X by a photolithography process. A plurality of openings OP1 are provided in the mask layer 91. As in the first embodiment, the openings OP1 are formed to alternately expose the hills 309 (309a, 309b) disposed in the connecting portions HP in the X direction.

[0308] The layer stack 300X is etched with an etching amount corresponding to one step number of the mountain 309. The pattern of the steps 799x of the mountain 309 corresponding to the opening OP1 is transferred in the Z direction to the plurality of sacrificial layers 39 and insulating layers 32 below. Thus, a mountain 309a is formed at a position on the side of the mountain 309b covered by the masking layer 91 that is recessed towards the semiconductor substrate 20. At this time, an intermediate portion (cliff portion) IP1 is formed below the mountain 309b. The intermediate portion IP1 faces the step formation surface of the mountain 309a.

[0309] After removing the masking layer 91, the layer stack 300X is etched based on the pattern of the masking layer having a masking edge on the mountain 309a in a manner substantially identical to the steps shown in Figures 18 to 20 above. Thus, the pattern of the step-forming surface of the mountain 309a and the pattern of the mountain 309b are transferred to the lower layer of the layer stack 300X, forming an intermediate portion IP2.

[0310] As shown in Figure 29, after a multi-stage etching process to form the intermediate portion IP2, a mask layer 93 is formed in the Z direction above the layer stack 300X by a lithography process. An opening OP3 is provided in the mask layer 93.

[0311] In this step, in a manner substantially similar to that shown in Figures 21 to 23 above, the masking edge Eg3 of the opening OP3 is located on the top TPb of the mountain 309b, which is juxtaposed with the middle portion IP2 in the X direction.

[0312] A multi-stage etching process based on the pattern of mask layer 93 is used to transfer the patterns of the mountain 309, sub-steps 311y and 312y, and intermediate portions IP1 and IP2 exposed in the opening OP3 to multiple insulating layers 32 and sacrificial layers 39 in the lower layer. An intermediate portion IP3 is formed below the mask edge Eg3.

[0313] Therefore, in this step, a symmetrical structure comprising a plurality of sub-steps 311y and 312y and a plurality of intermediate portions IP1, IP2 and IP3 is formed in the connecting portion HP, wherein the mountain portion 309x serves as a center.

[0314] As shown in Figure 30, a mask layer 95 is formed in the Z direction above the layer stack 300X using a lithography process. An opening OP5 is provided in the mask layer 95.

[0315] An opening OP5 is formed in the masking layer 95, exposing half of the connection portion HP on the side of the second memory region MA2. The other half of the connection portion HP on the side of the first memory region MA1 is covered by the masking layer 95. One of the masking edges of the masking layer 95 is located on the top of the hill 309x.

[0316] In this step, the layer stack is etched at 300X etch amount to etch one step 80. One sacrificial layer 39 and one insulating layer 32 contained in one step 80 are removed.

[0317] Figure 31 is a cross-sectional view of one example of the configuration of area XXXI shown in Figure 30.

[0318] As shown in Figure 31, the position of each of the sub-steps 311y and 312y in region R2 in the Z direction is recessed by one step from the position of each of the sub-steps 311y and 312y in region R1 in the Z direction toward the semiconductor substrate 20.

[0319] In region R1, each of the platforms 700a corresponding to the even-numbered conductive layers 39 is preserved. In region R2, each of the platforms 700b corresponding to the odd-numbered conductive layers 39 is exposed.

[0320] Subsequently, the steps of forming the memory pillar MP, forming the slit SLT, the replacement procedure (forming the conductive layer 22), forming the contact CC, and forming the interconnect 26 are performed sequentially in a manner substantially similar to the manufacturing process described in conjunction with the first embodiment.

[0321] By performing the above steps, the memory device 1 of this embodiment is formed.

[0322] In this embodiment, the number of ladders 80 removed from layer stack 300X during interconnect stack formation (the amount of etching in layer stack 300X) is substantially the same as the number of ladders 80 removed from layer stack 300X in the first embodiment. However, in this embodiment, anisotropic etching based on the pattern of mask layer 95 does not correspond to a multi-stage etching process, and the number of times a multi-stage etching process is performed is one less than the number of times a multi-stage etching process is performed in the first embodiment. In this embodiment, the size of each intermediate portion IP (IP1, IP2, and IP3) (e.g., the size of the intermediate portion IP in the X direction) is substantially the same as the size of each intermediate portion IP1, IP2, and IP3 in the first embodiment.

[0323] The memory device of this embodiment can achieve the same advantages as the memory device of the first embodiment. (3) Other

[0324] In the above embodiments, a NAND flash memory is described as an example of a memory device. However, the memory device of the embodiments may be another type of memory device, as long as it is a device having an interconnect stack.

[0325] In this embodiment, the memory cell array 10 may have a structure in which a plurality of memory pillars MP and a plurality of interconnect stacks 300 are stacked in the Z direction. In this case, the plurality of interconnect portions HP are stacked in the Z direction. Each interconnect portion HP is coupled to a memory region MA provided at the same height via a bridging portion BRG or directly.

[0326] While specific embodiments have been described, these embodiments are illustrative only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of the invention. Cross-reference to related applications

[0327] This application is based on and asserts priority to Japanese Patent Application No. 2021-136962, filed on August 25, 2021, the entire contents of which are incorporated herein by reference.

[0328] 1: Memory device 2: Memory controller 10: Memory Cell Array 11: Command Register 12: Address Register 13: Sequencer 14: Driver Module 15: Column Decoder Module 16: Sensing Amplifier Module 20: Semiconductor substrate 21: Conductive layer 22: Conductive layer 22a: Conductive layer 22b: Conductive layer 22c: Conductive layer 25: Conductive layer 26: Interconnectors 32: Insulation layer 32a: Insulation layer 34: Insulation layer 38: Insulation layer 39: Insulation layer 40: Core component 41: Semiconductor layer 42: Stacked membranes 43: Tunneling insulating film 44: Charge trapping membrane 45: Block insulation film 80: Steps 80x: Step 90: Mask layer 91: Masking layer 92: Masking layer 93: Masking layer 94: Masking layer 95: Masking layer 99: Ladder pair 99x: Ladder pair 300: Interconnect Stack 300X: Layer stacking 301: Yamabe 301a: Yamabe 301b: Yamabe 301c: Yamabe 301d: Yamabe 301e: Yamabe 301f:Yamabe 302:Tanibe 309: Yamabe 309a: Yamabe 309b: Yamabe 309x:Yamabe 311: Substaircase 311x: Sub-staircase 311y: Substrate 311z: Substrate 311-1: Sub-staircase 311-2: Sub-staircase 311-3: Sub-staircase 311-4: Sub-staircase 311z-3: Substrate 311z-4: Substrate 311z-5: Substrate 311z-6: Substrate 312: Substrate 312x: Sub-staircase 312y: Substrate 312z: Substrate 312z-3: Substrate 312z-4: Sub-staircase 312z-5: Substrate 312z-6: Substrate 312-1: Sub-staircase 312-2: Sub-staircase 312-3: Sub-staircase 312-4: Sub-staircase 700: Platform 700a: Platform 700b: Platform 799: Steps 799x: Steps ADD: Address Information BA: Block Address BL: Bitline BL0 to BLm-1: Bit lines BLK: Block BLK0 to BLKn: Blocks BRG: Bridging section CA: Row Address CC: Contact CCa: Contact element CCb: Contact element CMD: command CU: Cellular Unit CV: Contact D0: Dimensions D1: Dimensions D2: Dimensions D3: Dimensions D4: Dimensions DAT: Write Data Eg1: Mask edge Eg2: Mask edge Eg3: Mask edge Eg4: Mask edge F1-1: Inclined surface F1-2: Inclined surface F1-3: Inclined Surface F1-4: Inclined Surface F2-1: Inclined Surface F2-2: Inclined Surface F3: Inclined surface F4: Inclined Surface GP: Ladder Group GP1: Ladder Group GP2: Ladder Group GP3: Ladder Group GP4: Ladder Group H1: Position H2: Location H3: Location H4: Location H5: Location H6: Location H7: Location H8: Location Ha: Location HA: Connectivity Area Hb1: Location Hb2: Location Hb3: Location Hb4: Location Hc: Position Hd: Location He: Location Hf: Position Hg: Location HP: Connection Part HPe: Connection part HPo: Connection part IP1: Middle section IP1-1: Middle section IP1-2: Middle section IP1-3: Middle Section IP1-4: Middle Section IP2: Middle section IP2-1: Middle section IP2-2: Middle section IP3: Middle section IP4: Middle section LI: Contact MA: Memory area MA1: Memory area MA2: Memory area MP: Memory Pillar MT: Memory Cell Transistor MT0 to MTn-1: Memory Cell Transistors NS: NAND string OP0: Opening OP1: Opening OP2: Opening OP3: Opening OP4: Opening OP5: Opening PA: Page address R1: Zone 1 R2: Second Zone SGD: Select Gate Line SGD0 to SGD4: Select gate line SGS: Select Gate Line SHE: Narrow Slit SL: Source Line SLT: Slit SLTe: Slit SLTo: Slit SP: Spacer SS: Stadium-shaped stepped section SS1: Stadium-shaped stepped section SS2: Stadium-shaped stepped section SS3: Stadium-shaped stepped section SS4: Stadium-shaped stepped section SS5: Stadium-shaped stepped section SS6: Stadium-shaped stepped section SS7: Stadium-shaped stepped section SS8: Stadium-shaped stepped section STD: Select Transistor STS: Select Transistor SU: Serial unit SU0 to SU4: Serial Units SX: Stadium Group SX1: Stadium Group SX2: Stadium Group TPa: Top TPb: Top TPc: Top W1: Size W2: Size WL: Word Line WL0 to WLn-1: Word lines

Claims

1. A memory device comprising: A plurality of conductive layers are stacked in a first direction. Each conductive layer includes first and second memory regions, a bridge area, and a hookup area. The first and second memory regions are disposed in a second direction perpendicular to the first direction. The bridge area is provided in the second direction between the first and second memory regions. The conductive layers of the bridge area couple the conductive layers of the first and second memory regions to each other. The hookup area is provided in the second direction between the first and second memory regions. The hookup area includes a plurality of stepped portions, each stepped portion including a plurality of terraces. The terraces are coupled to the conductive layers of the first and second memory regions via the conductive layers of the bridge area. The hookup area also includes a plurality of non-terraces provided between the stepped portions. The plurality of stepped portions include: a first stepped portion, a second stepped portion, a third stepped portion, a fourth stepped portion, a fifth stepped portion, and a sixth stepped portion arranged sequentially from one side of the first memory region to one side of the second memory region; the plurality of non-platform portions include: a first non-platform portion provided in the second direction between the second and third stepped portions, a second non-platform portion provided in the second direction between the third and fourth stepped portions, a third non-platform portion provided in the second direction between the fourth and fifth stepped portions, and a fourth non-platform portion provided in the second direction between the fifth and sixth stepped portions; the fourth stepped portion is positioned in the first direction lower than the second stepped portion and higher than the third stepped portion in the first direction, and the fifth stepped portion is positioned in the first direction lower than the third stepped portion and higher than the sixth stepped portion in the first direction.

2. The memory device of claim 1, wherein each of the plurality of non-platform portions has an inclined surface between adjacent stepped portions.

3. The memory device of claim 1, wherein the top of the fourth step portion in the first direction is lower than the top of the second step portion in the first direction and higher than the top of the third step portion in the first direction, and the top of the fifth step portion in the first direction is lower than the top of the third step portion in the first direction and higher than the top of the sixth step portion in the first direction.

4. The memory device of claim 1, wherein each of the first, third and fifth staircase portions is a downward staircase comprising the plurality of platforms descending from the side of the first memory region toward the side of the second memory region, and each of the second, fourth and sixth staircase portions is an upward staircase comprising the plurality of platforms ascending from the side of the first memory region toward the side of the second memory region.

5. The memory device of claim 1, wherein the third non-platform portion has an inclined surface, and the dimension of the third non-platform portion in the first direction is greater than the dimension of the second non-platform portion in the first direction.

6. The memory device of claim 1, wherein each of the second and third non-platform portions has an inclined surface, and the dimension of the third non-platform portion in the first direction is greater than the dimension of the second non-platform portion in the first direction.

7. The memory device of claim 1, wherein each of the third and fourth non-platform portions has an inclined surface, and the dimension of the third non-platform portion in the first direction is greater than the dimension of the fourth non-platform portion in the first direction.

8. The memory device of claim 1, wherein the first to sixth step portions are: arranged in series in the second direction without the arrangement of other step portions of the plurality of step portions and without the arrangement of other memory regions.

9. The memory device of claim 1, wherein the plurality of stepped portions further comprises a seventh stepped portion, an eighth stepped portion, and a ninth stepped portion, wherein the seventh, eighth, and ninth stepped portions are provided in the second direction between the sixth stepped portion and the second memory region, wherein the positions of the seventh, eighth, and ninth stepped portions in the first direction are lower than the positions of the sixth stepped portion in the first direction, wherein the seventh, eighth, and ninth stepped portions are sequentially arranged from the side of the second memory region toward the side of the first memory region, and wherein the position of the seventh stepped portion in the first direction is lower than the position of the eighth stepped portion in the first direction and higher than the position of the ninth stepped portion in the first direction.

10. The memory device of claim 9, wherein the top of the seventh step portion in the first direction is lower than the top of the eighth step portion in the first direction and higher than the top of the ninth step portion in the first direction.

11. The memory device of claim 9, wherein the eighth step portion is: a downward step comprising the plurality of platforms descending from the side of the first memory region toward the side of the second memory region, and each of the seventh and ninth step portions is: an upward step comprising the plurality of platforms ascending from the side of the first memory region toward the side of the second memory region.

12. The memory device of claim 9, wherein the plurality of non-platform portions further comprises: a fifth non-platform portion provided in the second direction between the seventh and eighth step portions, and a sixth non-platform portion provided in the second direction between the eighth and ninth step portions, the sixth non-platform portion having an inclined surface, and the size of the sixth non-platform portion in the first direction being greater than the size of the fifth non-platform portion in the first direction.

13. The memory device of claim 9, wherein the plurality of non-platform portions further comprises: a fifth non-platform portion provided in the second direction between the seventh and eighth step portions, and a sixth non-platform portion provided in the second direction between the eighth and ninth step portions, each of the second and sixth non-platform portions having an inclined surface, and the dimension of the sixth non-platform portion in the first direction being greater than the dimension of the second non-platform portion in the first direction.

14. The memory device of claim 9, wherein the seventh to ninth step portions are: arranged in series in the second direction without the arrangement of other step portions of the plurality of step portions.

15. The memory device of claim 9, wherein the position profile of the seventh to ninth steps in the first direction is a mirror image of the position profile of the third to fifth steps in the first direction.

16. The memory device of claim 1, wherein the plurality of conductive layers comprises: a plurality of word lines connected to a plurality of memory cells in a memory string; and a plurality of select gate lines connected to a plurality of select gate transistors on the drain side of the memory string.

17. The memory device of claim 16, wherein the number of the plurality of select gate lines in the first memory region is five.

18. The memory device of claim 1, further comprising: A plurality of interconnects, corresponding to the plurality of platforms of each of the first to sixth step portions, are provided above the connection area; and a plurality of contacts, which electrically couple the plurality of platforms to the plurality of interconnects.

19. The memory device as claimed in claim 1, wherein the memory device includes NAND flash memory.

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