Display panel and display apparatus

Abstract

A display panel and a display device thereof. The display panel includes a plurality of gate lines, a plurality of main source lines, a plurality of secondary source lines, and a pixel array. The secondary source lines are individually coupled to one of the main source lines. The pixel array includes a plurality of pixel circuits. Each pixel circuit has a plurality of first pixel circuit groups coupled to the main source lines and a plurality of second pixel circuit groups coupled to the secondary source lines, and the gate lines have a plurality of first gate lines and a plurality of second gate lines arranged in an alternating manner. In each of the first pixel circuit groups, at least one pixel circuit is coupled to a first gate line, and at least one other pixel circuit is coupled to a second gate line.

Description

Technical Field

[0001] This invention relates to a display technology, and more particularly to a display panel and a display device thereof. Prior Technology

[0002] A flat-panel display (FPD) is a general term for image display devices with a thin, flat screen (and casing). Compared to the older cathode ray tube (CRT) displays, it has advantages such as saving space, providing realistic images, and being easy to scale up. Currently, besides televisions, it is widely used in various essential electronic products such as smartphones, computers, and tablets. Currently, flat-panel displays are broadly classified into liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and light-emitting diode (LED) displays.

[0003] Compared to the gate driver used to activate the pixel circuits, the source driver used to charge the pixel circuits requires greater driving power, meaning the source driver has a higher hardware cost. Therefore, display devices employing Half Source Driving (HSD) technology have been proposed, reducing the overall hardware cost of the display device by decreasing the number of source channels in the source driver. However, because Half Source Driving (HSD) technology causes the pixel circuits in the same column to be activated sequentially during two horizontal scanning periods, the charging time of the pixel circuits in the same column is inconsistent. Therefore, when displaying a specific pattern, uneven brightness and darkness (MURA) may occur due to insufficient charging of some pixel circuits. Summary of the Invention

[0004] The present invention provides a display panel and a display device thereof, which can reduce / suppress the problem of uneven brightness and darkness (MURA) when displaying a specific pattern.

[0005] The display panel of the present invention includes a plurality of gate lines, a plurality of main source lines, a plurality of secondary source lines, and a pixel array. The gate lines receive a plurality of gate signals and each extends along a first direction. The main source lines receive a plurality of source signals and extend along a second direction perpendicular to the first direction. The secondary source lines are each individually coupled to one of the main source lines and extend along the second direction. The pixel array includes a plurality of pixel circuits arranged in an array. Each pixel circuit has a plurality of first pixel circuit groups coupled to the main source lines and a plurality of second pixel circuit groups coupled to the secondary source lines, and the gate lines have a plurality of first gate lines and a plurality of second gate lines arranged in an interleaved manner. In each of the first and second pixel circuit groups, at least one of the pixel circuits is coupled to at least one of the first gate lines, and at least another pixel circuit is coupled to at least one of the second gate lines.

[0006] The display device of the present invention includes a gate driver, a source driver, and a display panel as described above. The gate driver provides a plurality of gate signals. The source driver provides a plurality of source signals.

[0007] Based on the above, in each of the first pixel circuit group and the second pixel circuit group, at least one pixel circuit is coupled to one of the first gate lines and / or at least one other pixel circuit is coupled to one of the second gate lines that are interleaved with the first gate lines, so that the pixel circuits with bright spots are distributed. This can alleviate / suppress the problem of uneven brightness and darkness (MURA) when displaying a specific pattern.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0009] Figure 1A is a system schematic diagram of a display device according to an embodiment of the present invention. Figures 1B to 1G are schematic diagrams of a system according to an embodiment of the present invention, showing the pixel circuit group coupled to the gate line. Figure 2A is a schematic diagram of the driving waveforms of the gate signal and source signal for driving the display panel to display a dot-shaped inspection screen according to an embodiment of the present invention. Figure 2B is a schematic diagram of a dot-shaped inspection screen displayed on a display panel according to an embodiment of the present invention. Figure 3A is a schematic diagram of the driving waveforms of the gate signal and source signal for driving the display panel to display a horizontal stripe image according to an embodiment of the present invention. Figure 3B is a schematic diagram of a display panel displaying a horizontal stripe image according to an embodiment of the present invention. Figure 4A is a schematic diagram of the driving waveforms of the gate signal and source signal for driving the display panel to display a cyan image according to an embodiment of the present invention. Figure 4B is a schematic diagram of a display panel displaying a cyan image according to an embodiment of the present invention. Implementation

[0010] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0011] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0012] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “or” signifies “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0013] Figure 1A is a system schematic diagram of a display device according to an embodiment of the present invention. Referring to Figure 1A, in this embodiment, the display device 100 includes a gate driver 110, a source driver 120, and a display panel 130. The gate driver 110 is coupled to the display panel 130 to provide a plurality of gate signals (such as SG1~SG8). The source driver 120 is coupled to the display panel 130 to provide a plurality of source signals (such as SS1~SSn), where n is a lead number.

[0014] The display panel 130 includes a plurality of gate lines (e.g., LG1~LG8), a plurality of main source lines (e.g., LS1a~LSna), a plurality of secondary source lines (e.g., LS1b~LSnb), and a pixel array 131. The gate lines (e.g., LG1~LG8) are coupled to gate drivers 110 to receive gate signals (e.g., SG1~SG8), and each extends along a first direction D1. The main source lines (e.g., LS1a~LSna) are coupled to source drivers 120 to receive source signals (e.g., SS1~SSn), and extend along a second direction D2 perpendicular to the first direction D1. The secondary source lines (e.g., LS1b~LSnb) are each coupled to a corresponding main source line (e.g., LS1a~LSna) via a trace extending along the first direction D1, and extend along the second direction D2.

[0015] The pixel array 131 includes multiple pixel circuits PX arranged in an array. The pixel circuits PX have (or are divided into) multiple first pixel circuit groups (such as GPX11 to GPX1x) coupled to the main source lines (such as LS1a to LSna) and multiple second pixel circuit groups (such as GPX21 to GPX2x) coupled to the secondary source lines (such as LS1b to LSnb), where x is a derivation number.

[0016] In each of the first pixel circuit group (GPX11~GPX1x) and the second pixel circuit group (e.g. GPX21~GPX2x), each column of pixel circuits PX is alternately coupled to one of a plurality of odd-numbered gate lines (e.g. LG1, GL3, LG5, LG7, corresponding to the first gate line) and one of a plurality of even-numbered gate lines (e.g. LG2, GL4, LG6, LG8, corresponding to the second gate line).

[0017] For example, in the first pixel circuit group GPX11, the odd-numbered pixel circuits PX in the first column are coupled to gate line LG1, and the even-numbered pixel circuits PX in the first column are coupled to gate line LG2; the odd-numbered pixel circuits PX in the second column are coupled to gate line LG4, and then the even-numbered pixel circuits PX in the second column are coupled to gate line LG3; the odd-numbered pixel circuits PX in the third column are coupled to gate line LG6, and then the even-numbered pixel circuits PX in the third column are coupled to gate line LG5; the odd-numbered pixel circuits PX in the fourth column are coupled to gate line LG7, and the even-numbered pixel circuits PX in the fourth column are coupled to gate line LG8, and so on. These will not be elaborated further here.

[0018] In the other direction, in the second pixel circuit group GPX21, the odd-numbered pixel circuits PX in the first column are coupled to gate line LG2, and the even-numbered pixel circuits PX in the first column are coupled to gate line LG1; the odd-numbered pixel circuits PX in the second column are coupled to gate line LG3, and then the even-numbered pixel circuits PX in the second column are coupled to gate line LG4; the odd-numbered pixel circuits PX in the third column are coupled to gate line LG5, and then the even-numbered pixel circuits PX in the third column are coupled to gate line LG6; the odd-numbered pixel circuits PX in the fourth column are coupled to gate line LG8, and the even-numbered pixel circuits PX in the fourth column are coupled to gate line LG7, and so on.

[0019] Based on the above, according to the circuit layout of the pixel array 131, when the gate signals SG1~SG8 are sequentially enabled, the pixel circuit PX coupled to even-numbered gate lines (such as LG2, GL4, LG6, LG8) typically has a higher charge than the pixel circuit PX coupled to odd-numbered gate lines (such as LG1, GL3, LG5, LG7). That is, the display brightness of the pixel circuit PX with even-numbered gate lines (such as LG2, GL4, LG6, LG8) may be higher. However, by alternately coupling each column of pixel circuit PX to staggered odd-numbered gate lines (such as LG1, GL3, LG5, LG7) and even-numbered gate lines (such as LG2, GL4, LG6, LG8), the brighter pixel circuit PXs are evenly distributed. This reduces / suppresses the problem of uneven brightness and darkness (MURA) when displaying a specific pattern.

[0020] In this embodiment, along the first direction, the circuit pattern of the pixel circuit PX in the first column of the first pixel circuit group GPX11 is symmetrical (or mirrored) to the circuit pattern of the pixel circuit PX in the second column of the first pixel circuit group GPX11. The circuit pattern of the pixel circuit PX in the second column of the first pixel circuit group GPX11 is identical to the circuit pattern of the pixel circuit PX in the third column of the first pixel circuit group GPX11. The circuit pattern of the pixel circuit PX in the third column of the first pixel circuit group GPX11 is symmetrical (or mirrored) to the circuit pattern of the pixel circuit PX in the fourth column of the first pixel circuit group GPX11, and so on. The rest can be deduced similarly and will not be elaborated further here. Furthermore, the second pixel circuit group (such as GPX21~GPX2x) also has the specific circuit layout described above.

[0021] In other words, when two adjacent pixel circuits PX coupled to the same main source line (such as LS1a~LSna) or the same primary source line (such as LS1b~LSnb) are respectively coupled to one of the odd-numbered gate lines (such as LG1, GL3, LG5, LG7), two pixel circuits PX on the same main source line (such as LS1a~LSna) or the same primary source line (such as LS1b~LSnb) that are adjacent to the above two adjacent pixel circuits PX are respectively coupled to one of the even-numbered gate lines (such as LG2, GL4, LG6, LG8). Furthermore, when two adjacent pixel circuits PX coupled to the same main source line (such as LS1a~LSna) or the same primary source line (such as LS1b~LSnb) are respectively coupled to one of the even-numbered gate lines (such as LG2, GL4, LG6, LG8), two pixel circuits PX adjacent to the above two adjacent pixel circuits PX on the same main source line (such as LS1a~LSna) or the same primary source line (such as LS1b~LSnb) are respectively coupled to one of the odd-numbered gate lines (such as LG1, GL3, LG5, LG7).

[0022] In this embodiment, the number of main source lines (e.g., LS1a~LSna) corresponding to the first pixel circuit group (e.g., GPX11~GPX1x) and the number of secondary source lines (e.g., LS1b~LSnb) corresponding to each second pixel circuit group (e.g., GPX21~GPX2x) are 6, for example. However, in other embodiments, the number of main source lines (e.g., LS1a~LSna) corresponding to the first pixel circuit group (e.g., GPX11~GPX1x) and the number of secondary source lines (e.g., LS1b~LSnb) corresponding to each second pixel circuit group (e.g., GPX21~GPX2x) can be a multiple of 3. That is, each of the first pixel circuit group (e.g., GPX11~GPX1x) and the second pixel circuit group (GPX21~GPX2x) includes pixel circuits PX in multiples of 3 rows.

[0023] In this embodiment, in each column of pixel circuits PX, every three consecutive pixel circuits PX can be regarded as a pixel circuit group UDSP, which determines the brightness and color of an image point in the image. The pixel circuits PX in the pixel circuit group UDSP are, for example, red pixel circuit, green pixel circuit and blue pixel circuit, but the embodiments of the present invention are not limited thereto.

[0024] In this embodiment, each primary source line (e.g., LS1a~LSna) shares the same source signal (e.g., SS1~SSn) with its corresponding (or coupled to) secondary source lines (e.g., LS1b~LSnb). Therefore, among these pixel circuits PX in the same column, when a pixel circuit PX coupled to one of the primary source lines (e.g., LS1a~LSna) is coupled to one of the odd-numbered gate lines (e.g., LG1, GL3, LG5, LG7) and the even-numbered gate lines (e.g., LG2, GL4, LG6, LG8), then the pixel circuit PX coupled to the secondary source line (LS1b~LSnb) coupled to one of the primary source lines (e.g., LS1a~LSna) is coupled to the other of the odd-numbered gate lines (e.g., LG1, GL3, LG5, LG7) and the even-numbered gate lines (e.g., LG2, GL4, LG6, LG8). For example, in the pixel circuit PX of the first column, the pixel circuit PX coupled to the main source line LS1a is coupled to the gate line LG1, but the pixel circuit PX coupled to the secondary source line LS1b is coupled to the gate line LG2, and so on.

[0025] In this embodiment, the first pixel circuit group (such as GPX11~GPX1x) and the second pixel circuit group (such as GPX21~GPX2x) can be staggered along the first direction D1.

[0026] In this embodiment, the gate driver 110 is disposed outside the display panel 130. However, in this embodiment of the invention, the gate driver 110 is disposed on the display panel 130. This is determined by the circuit design and is not limited to this embodiment of the invention.

[0027] Figures 1B to 1G are schematic diagrams of a system according to an embodiment of the present invention, showing the pixel circuit group coupled to the gate line. Referring to Figures 1A to 1G, in this embodiment, the same or similar elements are used. In Figure 1A, taking the pixel circuit group UDSP shown in the first pixel circuit group GPX11 as an example, the pixel circuits PX in the first column of the pixel circuit group UDSP are alternately coupled to the gate lines LG1 and LG2, and the pixel circuits PX in the second column of the pixel circuit group UDSP are alternately coupled to the gate lines LG4 and LG3. That is, the coupling method (or coupling pattern) of the first column of the pixel circuit group UDSP with the adjacent gate lines (i.e., LG1 and LG2) is opposite to the coupling method (or coupling pattern) of the second column of the pixel circuit group UDSP with the adjacent gate lines (i.e., LG3 and LG4).

[0028] Furthermore, in the first pixel circuit group GPX11, the coupling method (or coupling pattern) between the second column pixel circuit group UDSP and the adjacent gate lines (i.e., LG3 and LG4) is the same as the coupling method (or coupling pattern) between the third column pixel circuit group UDSP and the adjacent gate lines (i.e., LG5 and LG6). The rest can be referred to the diagram, and will not be described again here.

[0029] Further, Figures 1B to 1F show pixel circuit groups UDSPa to UDSPf with different coupling patterns. In pixel circuit group UDSPa, the three pixel circuits PX are coupled to gate line LGa, but not to gate line LGb. Gate line LGa can be one of the odd-numbered gate lines (such as LG1, GL3, LG5, LG7), and gate line LGb can be one of the even-numbered gate lines (such as LG2, GL4, LG6, LG8).

[0030] Similarly, in pixel circuit group UDSPb, the first and second pixel circuits PX are coupled to the gate line LGa, and the third pixel circuit PX is coupled to the gate line LGb; in pixel circuit group UDSPc, the first pixel circuit PX is coupled to the gate line LGa, and the second and third pixel circuits PX are coupled to the gate line LGb; in pixel circuit group UDSPd, the first pixel circuit PX is coupled to the gate line LGb, and the second and third pixel circuits PX are coupled to the gate line LGa; in pixel circuit group UDSPe, the first and second pixel circuits PX are coupled to the gate line LGb, and the third pixel circuit PX is coupled to the gate line LGa; in pixel circuit group UDSPf, all three pixel circuits PX are coupled to the gate line LGb, and there is no coupled gate line LGa.

[0031] In this embodiment of the invention, in each first pixel circuit group (GPX11~GPX1x), the pixel circuit group UDSP can be replaced by any one of the pixel circuit groups UDSPa~UDSPf, and the pixel circuit group UDSP of the second pixel circuit group (GPX21~GPX2x) is inversely complementary to the pixel circuit group UDSP of the first pixel circuit group (GPX11~GPX1x) (that is, the coupling relationship between the upper and lower parts is completely opposite).

[0032] Furthermore, in each of the first pixel circuit group (GPX11~GPX1x) and the second pixel circuit group (e.g., GPX21~GPX2x), each pixel circuit group UDSP may have the same or different coupling patterns as the vertically adjacent and / or horizontally adjacent pixel circuit group UDSPs. However, the coupling pattern of at least one pixel circuit group UDSP is still different from that of the other pixel circuit group UDSPs. Thus, the pixel circuits PX in the first pixel circuit group (GPX11~GPX1x) or the second pixel circuit group (e.g., GPX21~GPX2x) are partially coupled to odd-numbered gate lines (e.g., LG1, GL3, LG5, LG7) and the other parts are coupled to even-numbered gate lines (e.g., LG2, GL4, LG6, LG8). The above can be determined according to the circuit design, and the embodiments of the present invention are not limited thereto.

[0033] In detail, in each of the first pixel circuit group (GPX11~GPX1x) and the second pixel circuit group (such as GPX21~GPX2x), at least one of the pixel circuits PX is coupled to one of the odd-numbered gate lines (such as LG1, GL3, LG5, LG7), and at least one of the pixel circuits PX is coupled to one of the even-numbered gate lines (such as LG2, GL4, LG6, LG8).

[0034] Figure 2A is a schematic diagram of the driving waveforms of the gate signal and source signal for driving the display panel to display a dot-matrix inspection screen according to an embodiment of the present invention. Figure 2B is a schematic diagram of the display panel displaying a dot-matrix inspection screen according to an embodiment of the present invention. Referring to Figures 1A, 2A and 2B, in this embodiment, a portion of the display panel 130 (or pixel array 131) is shown, and it is assumed that a dot-matrix inspection screen (or SubChecker) is used to inspect and display the display panel 130 (or pixel array 131), wherein the pixel circuit PX of the pixel array 131 can be a liquid crystal pixel circuit.

[0035] In this embodiment, each column of pixel circuits PX alternates between red pixel circuits (such as R11~R14, R21~R24, R31~R34, R41~R44), green pixel circuits (such as G11~G14, G21~G24, G31~G34, G41~G44), and blue pixel circuits (such as B11~B14, B21~B24, B31~B34, B41~B44). For example, as shown in Figure 2B, the pixel circuits PX in the first column are, in order: red pixel circuit R11, green pixel circuit G11, blue pixel circuit B11, red pixel circuit R12, green pixel circuit G12, blue pixel circuit B12, red pixel circuit R13, green pixel circuit G13, blue pixel circuit B13, red pixel circuit R14, green pixel circuit G14, and blue pixel circuit B14. The rest can be seen in Figure 2B, and will not be described again here.

[0036] As shown in Figure 2A, in order to write the dot-matrix inspection screen, when the gate signals SG1 and SG2 are enabled, the odd-numbered source signals SS1, SS3, SS5, etc. provide the corresponding voltage levels, but the even-numbered source signals SS2, SS4, SS6, etc. remain at the reference level (e.g., the ground level); when the gate signals SG3 and SG4 are enabled, the even-numbered source signals SS2, SS4, SS6, etc. provide the corresponding voltage levels, but the odd-numbered source signals SS1, SS3, SS5, etc. remain at the reference level (e.g., the ground level), and so on. Furthermore, the red pixel circuits R11, R13, R22, R24, R31, R33, R42, R44, the green pixel circuits G12, G14, G21, G23, G32, G34, G41, G43, and the blue pixel circuits B11, B13, B22, B24, B31, B33, B42, B44 will be driven to display brightness, while the remaining pixel circuits PX will not display brightness.

[0037] As shown in Figure 2A, the amount of charge written when gate signals SG1 and SG3 are enabled is relatively low, while the amount of charge written when gate signals SG2 and SG4 are enabled is relatively high. This results in higher brightness for the red pixel circuits R13, R24, R31, and R42, the green pixel circuits G14, G23, G32, and G41, and the blue pixel circuits B13, B24, B31, and B42. In other words, areas A01 and A04 have lower brightness, while areas A02 and A03 have higher brightness. Although some pixel circuits PX are not fully activated, leading to insufficient charging of some PX, the circuit architecture of pixel array 131 evenly distributes the bright and dark areas, preventing vertical lines from appearing.

[0038] In this embodiment, red pixel circuits R11~R14, R21~R24, R31~R34, R41~R44, green pixel circuits G11~G14, G21~G24, G31~G34, G41~G44, and blue pixel circuits B11~B 14, B21~B24, B31~B34, and B41~B44 are driven, for example, by row inversion, but embodiments of the present invention may be driven by other inversions (e.g., point inversion, column inversion, screen inversion, etc.), which are dependent on the circuit design and are not limited to the embodiments of the present invention.

[0039] 3A is a schematic diagram of the driving waveforms of the gate signal and the source signal of the drive display panel displaying a horizontal stripe screen in accordance with an embodiment of the present invention. 3B is a display schematic of a display panel displaying a horizontal stripe screen according to an embodiment of the present invention. Refer to Figure 1A , Figure 2A , Figure 2B , Figure 3A , and Figure 3B , where identical or similar components use the same or similar labeling. In this embodiment, the display display panel 130 (or pixel array 131) is examined with a horizontal stripe screen.

[0040] As shown in Figure 3A , in order to write to the horizontal stripe screen, the source signals SS1~SS6 and others provide the corresponding voltage calibration when the gate signals SG1 and SG2 are energized. Further, red pixel circuits R11~R14, R31~R34, green pixel circuits G11~G14, G31~G34 and blue pixel circuits B11~B14, B31~B34 will be driven to display brightness, while the rest of the pixel circuit PX will not display brightness.

[0041] At this time, the red pixel circuits R12, R13, R31, R34, the green pixel circuits G11, G14, G32, G33 and the blue pixel circuits B12, B13, B31, and B34 will show higher brightness, which means there are brighter pixel circuit PX and darker pixel circuit PX in area A01~A04. Although, because some pixel circuit PX is not fully open, resulting in some pixel circuit PX undercharging, the circuit architecture of pixel array 131 distributes the bright and dark areas evenly (i.e., the bright and dark spots will be staggered), so that vertical fringes do not appear.

[0042] Figure 4A is a schematic diagram of the driving waveforms of the gate signal and source signal for driving the display panel to display a cyan image according to an embodiment of the present invention. Figure 4B is a schematic diagram of the display panel displaying a cyan image according to an embodiment of the present invention. Please refer to Figures 1A, 2A, 2B, 4A, and 4B, wherein the same or similar elements are referred to by the same or similar reference numerals. In this embodiment, the display panel 130 (or pixel array 131) is checked using a cyan image.

[0043] As shown in Figure 3A, to write a cyan image, when the gate signals (such as SG1~SG4) are enabled, the source signals SS2, SS3, SS5, and SS6 provide corresponding voltage levels, while source signals SS1 and SS4 remain at the reference level (e.g., the ground level). The rest follow the same principle, which will not be elaborated further here. In other words, the green pixel circuits G11~G14, G21~G24, G31~G34, G41~G44 and the blue pixel circuits B11~B14, B21~B24, B31~B34, B41~B44 are driven to display brightness, while the red pixel circuits R11~R14, R21~R24, R31~R34, and R41~R44 do not display brightness. At this time, since the same source signals (SS2, SS3, SS5, SS6) maintain the same voltage level, there is no issue of different brightness levels.

[0044] In summary, the display panel and display device of the present invention, by alternately coupling each column of pixel circuits to one of the odd-numbered gate lines (i.e., the first gate lines) and one of the even-numbered gate lines (i.e., the second gate lines) that are interleaved with the odd-numbered gate lines, ensures that the pixel circuits with bright spots are evenly distributed. This mitigates / suppresses the problem of uneven brightness and darkness (MURA) when displaying a specific pattern. Furthermore, in the first and second pixel circuit groups, at least one pixel circuit group has a different coupling pattern than the others, such that the pixel circuits in the first or second pixel circuit group are partially coupled to odd-numbered gate lines and the rest are coupled to even-numbered gate lines. This disperses the pixel circuits with bright spots, similarly mitigating / suppressing the problem of uneven brightness and darkness when displaying a specific pattern.

[0045] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0046] 100: Display device 110: Gate driver 120: Source Driver 130: Display panel 131:Pixel array A01~A04: Area B11~B14, B21~B24, B31~B34, B41~B44: Blue pixel circuit D1: First Direction D2: Second Direction UDSP, UDSPa~UDSPf: Pixel Circuit Group G11~G14, G21~G24, G31~G34, G41~G44: Green pixel circuit GPX11, GPX1x: First pixel circuit group GPX21, GPX2x: Second Pixel Circuit Group LG1~LG8, LGa, LGb: Gate wires LS1a~LSna: Main source poles LS1b~LSnb: Subsource pole lines PX: Pixel Circuit R11~R14, R21~R24, R31~R34, R41~R44: Red pixel circuit SG1~SG8: Gate signals SS1~SSn: Source signals

Claims

1. A display panel, comprising: Multiple gate lines receive multiple gate signals, and some of them extend along a first direction; A plurality of main source lines receiving a plurality of source signals and extending along a second direction perpendicular to the first direction; a plurality of secondary source lines, individually coupled to one of the main source lines and extending along the second direction, wherein each of the main source lines and a corresponding one of the secondary source lines jointly receive one of the source signals; and a pixel array including a plurality of pixel circuits arranged in an array, wherein the pixel circuits have a plurality of first pixel circuit groups coupled to the main source lines and a plurality of second pixel circuit groups coupled to the secondary source lines, and the gate lines have a plurality of first gate lines and a plurality of second gate lines arranged in an interleaved manner, wherein in each of the first pixel circuit groups and the second pixel circuit groups, at least one of the pixel circuits is coupled to at least one of the first gate lines, and at least one of the pixel circuits is coupled to at least one of the second gate lines.

2. The display panel as claimed in claim 1, wherein in each of the first pixel circuit groups and the second pixel circuit groups, each column of the pixel circuits is alternately coupled to one of the first gate lines and one of the second gate lines.

3. The display panel as claimed in claim 2, wherein when two adjacent pixel circuits coupled to the same main source line or the same primary source line are respectively coupled to one of the first gate lines, two pixel circuits on the same main source line or the same primary source line adjacent to the two adjacent pixel circuits are respectively coupled to one of the second gate lines; and when two adjacent pixel circuits coupled to the same main source line or the same primary source line are respectively coupled to one of the second gate lines, two pixel circuits on the same main source line or the same primary source line adjacent to the two adjacent pixel circuits are respectively coupled to one of the first gate lines.

4. The display panel as claimed in claim 1, wherein in the pixel circuits in the same column, the pixel circuit coupled to one of the main source lines is coupled to one of the first gate line and the second gate line, and the pixel circuit coupled to the secondary source line coupled to the one of the main source lines is coupled to the other of the first gate line and the second gate line.

5. The display panel as claimed in claim 1, wherein the first pixel circuit groups and the second pixel circuit groups are staggered along the first direction.

6. The display panel as claimed in claim 1, wherein the first pixel circuit groups and the second pixel circuit groups each comprise the pixel circuits in multiples of 3 rows.

7. The display panel as claimed in claim 1, wherein the pixel circuitry includes a plurality of liquid crystal pixel circuits.

8. The display panel as described in claim 7, wherein the pixel circuits are driven in a row-to-row inverted manner.

9. The display panel as claimed in claim 1, wherein the pixel circuits in each column are alternately a red pixel circuit, a green pixel circuit, or a blue pixel circuit.

10. A display device, comprising: A single gate driver provides multiple gate signals; A single source driver provides multiple source signals; And a display panel, including: a plurality of gate lines coupled to the gate driver to receive the gate signals, and each extending along a first direction; A plurality of primary source lines, coupled to the source driver to receive the source signals, and extending along a second direction perpendicular to the first direction; a plurality of secondary source lines, individually coupled to one of the primary source lines, and extending along the second direction, wherein each of the primary source lines and a corresponding one of the secondary source lines jointly receive one of the source signals; and a pixel array comprising a plurality of pixel circuits arranged in an array, wherein the pixel circuits have a plurality of first pixel circuit groups coupled to the primary source lines and a plurality of second pixel circuit groups coupled to the secondary source lines, and the gate lines have a plurality of first gate lines and a plurality of second gate lines arranged in an interleaved manner, wherein in each of the first pixel circuit groups and the second pixel circuit groups, at least one of the pixel circuits is coupled to at least one of the first gate lines, and at least one of the pixel circuits is coupled to at least one of the second gate lines.

11. The display device of claim 10, wherein in each of the first pixel circuit groups and the second pixel circuit groups, each column of the pixel circuits is alternately coupled to one of the first gate lines and one of the second gate lines.

12. The display device of claim 11, wherein when two adjacent pixel circuits coupled to the same main source line or the same primary source line are respectively coupled to one of the first gate lines, two pixel circuits on the same main source line or the same primary source line adjacent to the two adjacent pixel circuits are respectively coupled to one of the second gate lines; and when two adjacent pixel circuits coupled to the same main source line or the same primary source line are respectively coupled to one of the second gate lines, two pixel circuits on the same main source line or the same primary source line adjacent to the two adjacent pixel circuits are respectively coupled to one of the first gate lines.

13. The display device of claim 10, wherein in the pixel circuits in the same column, the pixel circuit coupled to one of the main source lines is coupled to one of the first gate line and the second gate line, and the pixel circuit coupled to the secondary source line coupled to the one of the main source lines is coupled to the other of the first gate line and the second gate line.

14. The display device of claim 10, wherein the first pixel circuit groups and the second pixel circuit groups are staggered along the first direction.

15. The display device as claimed in claim 10, wherein the first pixel circuit groups and the second pixel circuit groups each comprise the pixel circuits in multiples of 3 rows.

16. The display device as claimed in claim 10, wherein the pixel circuitry includes a plurality of liquid crystal pixel circuits.

17. The display device as claimed in claim 16, wherein the pixel circuits are driven in a row-to-row inverted manner.

18. The display device as claimed in claim 10, wherein the pixel circuits in each column are alternately a red pixel circuit, a green pixel circuit, or a blue pixel circuit.

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