A delay-locked loop circuit for high frequency clocks and a method for resisting signal interference

Abstract

This invention provides a delay-locked loop (LLO) circuit suitable for high-frequency clocks and a method for resisting signal interference. The LLO circuit includes a phase frequency detection circuit, an automatic correction circuit, a charge pump, and a voltage-controlled delay circuit. The automatic correction circuit adjusts the clock frequency of a first rising signal and a first falling signal output by the phase frequency detection circuit, and generates a second rising signal and a second falling signal to reduce the operating frequency of the charge pump and the voltage-controlled delay circuit, thereby reducing the frequency and time of phase error adjustment in the LLO circuit. Therefore, this invention avoids non-ideal effects in the LLO circuit, giving it better jitter performance and making it suitable for high-frequency clock environments.

Description

Technical Field

[0001] This invention relates to a delay-locked loop circuit, and more particularly to a delay-locked loop circuit suitable for high-frequency clocks and a method for resisting signal interference. Prior Technology

[0002] A delay-locked loop (DLL) is a circuit that controls the frequency and phase of a clock signal based on a feedback signal. Its main purpose is to generate a precise clock signal, and it is widely used in circuits that require clock operation, such as synchronous dynamic memory (SDRAM), analog-to-digital converters (ADCs), and digital signal processors (DSPs).

[0003] Generally, a delay-locked loop (LDL) uses a phase-frequency detection circuit to determine the phase error between the output clock signal and a reference clock signal for each clock cycle. Based on this phase error, it adjusts the frequency and / or phase of the output clock signal to accurately generate the desired clock signal. However, as the frequency of the output clock signal increases, non-ideal effects such as clock feedthrough appear, affecting the jitter performance of the LDL. Furthermore, the increased frequency of the output clock signal means an increase in the number of phase error adjustments the LDL needs to perform, further impacting its jitter performance. In particular, when the output clock signal frequency reaches the gigahertz (GHz) level, the frequency of phase error adjustments increases while the available time for these adjustments decreases. Since LDLs have operating speed limits, it becomes difficult to perform phase error adjustments for every gigahertz-level output clock signal using a LDL.

[0004] Therefore, proposing a delay-locked loop circuit suitable for high-frequency clocks is one of the problems that needs to be solved in this field. Summary of the Invention

[0005] In view of the problems existing in the prior art, the main objective of the present invention is to provide a delay-locked loop circuit and a signal interference suppression method suitable for high-frequency clocks. By reducing the frequency and time of phase error adjustment, the non-ideal effect is avoided, thereby enabling the delay-locked loop circuit to have better jitter performance.

[0006] A key technical means to achieve the above objective is to make the aforementioned delay-locked loop circuit include: A phase frequency detection circuit outputs a first rising signal and a first falling signal; An automatic correction circuit, electrically connected to the phase frequency detection circuit, is used to receive the first rising signal and the first falling signal, and output a second rising signal and a second falling signal based on the first rising signal and the first falling signal; wherein, the clock frequency of a portion of the second rising signal and the second falling signal is lower than the clock frequency of the first rising signal and the first falling signal; A charge pump, electrically connected to the automatic correction circuit, is used to output a voltage control signal; and A voltage-controlled delay circuit is electrically connected to the charge pump and the phase-frequency detection circuit. Based on the voltage control signal, it outputs a clock signal as a feedback signal.

[0007] Another key technical means adopted to achieve the above objectives is to make the aforementioned anti-signal interference methods include: Based on a first phase control signal, a first rising signal and a first falling signal are divided by a frequency division factor to generate a second rising signal and a second falling signal; and When the phase difference between a reference frequency signal and a feedback frequency signal is equal to or greater than a phase difference threshold, the first rising signal and the first falling signal are adjusted based on a second phase control signal to generate the second rising signal and the second falling signal.

[0008] Based on the above, the delay-locked loop circuit and anti-signal interference method of the present invention can adjust the frequency and / or phase of the second rising signal and the second falling signal through an automatic correction circuit, so that the clock frequency of a portion of the second rising signal and the second falling signal is less than the clock frequency of the first rising signal and the first falling signal, thereby reducing the frequency and time of phase error adjustment, avoiding the occurrence of non-ideal effects, and thus enabling the delay-locked loop circuit to have better jitter performance and be applicable to environments suitable for high-frequency clocks, thereby improving the convenience of application of the delay-locked loop circuit. Simple Explanation of the Diagram

[0009] Figure 1 is a schematic diagram of an embodiment of the delay-locked loop circuit according to an embodiment of the present invention; Figure 2 is a schematic diagram of an embodiment of the automatic correction circuit according to an embodiment of the present invention; Figure 3 is a schematic diagram of an embodiment of the automatic phase adjustment circuit and anti-interference circuit according to an embodiment of the present invention; Figure 4 is a schematic diagram of a signal embodiment of the automatic correction circuit according to an embodiment of the present invention; Figure 5 is a schematic diagram of another embodiment of the automatic phase adjustment circuit according to an embodiment of the present invention; Figure 6 is a schematic diagram of another embodiment of the anti-interference circuit according to an embodiment of the present invention; Figure 7 is a schematic diagram of another signal embodiment of the automatic correction circuit according to an embodiment of the present invention; Figure 8 is a schematic diagram of another signal embodiment of the automatic correction circuit according to an embodiment of the present invention; Figure 9 is a schematic diagram of another signal embodiment of the automatic correction circuit according to an embodiment of the present invention; Figure 10 is a schematic diagram of another embodiment of the automatic correction circuit according to an embodiment of the present invention; and Figure 11 is a schematic flowchart of an embodiment of the anti-signal interference method according to an embodiment of the present invention. Implementation

[0010] Regarding the delay-locked loop circuit of an embodiment of the present invention, please refer to FIG1, which includes a phase frequency detection circuit 100, an automatic correction circuit 200, a charge pump 300, a low-pass filter 400, and a voltage-controlled delay loop 500.

[0011] The phase frequency detection circuit 100 is electrically connected to the automatic correction circuit 200 and the voltage-controlled delay circuit 500. The phase frequency detection circuit 100 receives a feedback frequency signal FB and a reference frequency signal FREF, and outputs a first rising signal UP1 and a first falling signal DN1 to the automatic correction circuit 200 based on the feedback frequency signal FB and the reference frequency signal FREF. The feedback frequency signal FB is a clock signal output by the voltage-controlled delay circuit 500. The reference frequency signal FREF is a frequency signal from an external circuit. The external circuit is, for example, a system-on-a-chip (SoC), but this invention is not limited thereto. The phase frequency detection circuit 100 compares the phase error and frequency error between the feedback frequency signal FB and the reference frequency signal FREF, and generates the first rising signal UP1 and the first falling signal DN1 based on the phase error and frequency error. The phase frequency detection circuit 100 is, for example, a phase frequency detector.

[0012] The automatic correction circuit 200 is electrically connected to the phase frequency detection circuit 100 and the charge pump 300. The automatic correction circuit 200 is used to receive the first rising signal UP1 and the first falling signal DN1, and to adjust the phase error of the first rising signal UP1 and the first falling signal DN1 to generate a second rising signal UP2 and a second falling signal DN2, and to transmit the second rising signal UP2 and the second falling signal DN2 to the charge pump 300, wherein at least a portion of the clock frequency of the second rising signal UP2 and the second falling signal DN2 is less than the clock frequency of the first rising signal UP1 and the first falling signal DN1.

[0013] The charge pump 300 is electrically connected to the automatic correction circuit 200, the low-pass filter 400, and the voltage control delay circuit 500. The charge pump 300 receives the second rising signal UP2 and the second falling signal DN2, and generates and outputs a voltage control signal VCTRL based on the second rising signal UP2 and the second falling signal DN2. The voltage control signal VCTRL is transmitted to the voltage control delay circuit 500. The low-pass filter 400 is electrically connected to the charge pump 300 and the voltage control delay circuit 500. The low-pass filter 400 filters the voltage control signal VCTRL to eliminate unwanted noise. The low-pass filter 400 may be, for example, a low-pass filter circuit implemented with resistors and capacitors, and the invention is not limited thereto.

[0014] The voltage-controlled delay circuit 500 is electrically connected to the charge pump 300, the low-pass filter 400, and the phase-frequency detection circuit 100. The voltage-controlled delay circuit 500 receives the voltage control signal VCTRL and generates and outputs the clock signal based on the voltage control signal VCTRL. The voltage-controlled delay circuit 500 is, for example, a voltage-controlled delay line (VCDL), but the invention is not limited thereto.

[0015] As described above, since the delay-locked loop circuit of the present invention can adjust the phase error of the first rising signal UP1 and the first falling signal DN1 through the automatic correction circuit 200, and generate a second rising signal UP2 and a second falling signal DN2 whose clock frequency is lower than that of the first rising signal UP1 and the first falling signal DN1, the operating frequency of the charge pump 300 and the voltage-controlled delay circuit 500 can be reduced accordingly to the clock frequency of the second rising signal UP2 and the second falling signal DN2. The frequency at which the clock signal Clock is adjusted is also reduced, meaning that the overall phase error adjustment frequency and the required time of the delay-locked loop circuit are reduced. Therefore, when the delay-locked loop circuit is applied in a high-frequency clock environment, non-ideal effects can be avoided in the delay-locked loop circuit, thereby giving the delay-locked loop circuit better jitter performance and accurately outputting the desired clock signal Clock, thus improving the convenience of the delay-locked loop circuit application.

[0016] Please refer to Figure 2, which is a schematic diagram of an embodiment of the automatic correction circuit 200 of the present invention. The automatic correction circuit 200 includes an automatic phase adjustment circuit 210 and an anti-interference circuit 220. The automatic phase adjustment circuit 210 is electrically connected to the anti-interference circuit 220. The automatic phase adjustment circuit 210 is used to receive the feedback frequency signal FB and the reference frequency signal FREF, and output a phase control signal (a phase control signal DeEN or a phase control signal Dis_d) based on the feedback frequency signal FB and the reference frequency signal FREF. The anti-interference circuit 220 is electrically connected to the automatic phase adjustment circuit 210, the phase frequency detection circuit 100, and the charge pump 300. The anti-interference circuit 220 is used to receive the phase control signal, the first rising signal UP1, and the first falling signal DN1. The anti-interference circuit 220 generates and outputs the second rising signal UP2 and the second falling signal DN2 based on the phase control signal, the first rising signal UP1 and the first falling signal DN1.

[0017] Please refer to Figures 2 and 3 simultaneously. Figure 3 is a schematic diagram of an embodiment of the automatic phase adjustment circuit 210 and the anti-interference circuit 220 of the present invention. In this embodiment, an automatic phase adjustment circuit 210a includes a first inverter 211, a first flip-flop 212, a second flip-flop 213, a first delay circuit 214, and a gate unit 215.

[0018] The first inverter 211 has an input terminal and an output terminal. The input terminal receives the reference frequency signal FREF, and the output terminal is electrically connected to the first flip-flop 212. The first inverter 211 can be implemented using a NOT gate.

[0019] The first flip-flop 212 has a clock input terminal Clk, a reset terminal Reset, a data input terminal D, and a first data output terminal. and a second data output terminal The clock input terminal Clk of the first flip-flop 212 is electrically connected to the output terminal of the first inverter 211. The reset terminal Reset of the first flip-flop 212 receives the synchronization signal EN. The data input terminal D of the first flip-flop 212 is connected to the second data output terminal of the first flip-flop 212. Electrical connection. The first data output terminal of the first flip-flop 212. This is used to output a first output signal q1. The enable signal EN can be a control signal from the external circuit. The first flip-flop 212 is, for example, a D-type flip-flop.

[0020] The second flip-flop 213 has a clock input terminal Clk, a reset terminal Reset, a data input terminal D, and a first data output terminal. and a second data output terminal The clock input terminal Clk of the second flip-flop 213 is connected to the first data output terminal of the first flip-flop 212. Electrically connected to receive the first output signal q1. The reset terminal of the second flip-flop 213 receives the enable signal EN. The data input terminal D of the second flip-flop 213 is connected to the second data output terminal of the second flip-flop 213. Electrical connection. The first data output terminal of the second flip-flop 213. Used to output a second output signal q2. The second flip-flop 213 is, for example, a D-type flip-flop.

[0021] The first delay circuit 214 has an input terminal and an output terminal. The input terminal of the first delay circuit 214 is connected to the first data output terminal of the first flip-flop 212. An electrical connection is made to receive a first output signal q1. In one embodiment, the first delay circuit 214 includes a plurality of inverting units 2141 connected in series. The number of inverting units 2141 is, for example, four, and the invention is not limited thereto. The inverting unit 2141 may be implemented by a reverse gate.

[0022] The gate unit 215 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the gate unit 215 is connected to the first data output terminal of the second flip-flop 213. Electrical connection. The second input terminal of the gate unit 215 is electrically connected to the output terminal of the first delay circuit 214. The output terminal of the gate unit 215 is electrically connected to the anti-interference circuit 220 to output the first phase control signal DeEN. The gate unit 215 can be implemented by an AND gate.

[0023] Furthermore, the anti-interference circuit 220 includes a first gate unit 221, a second gate unit 222, and an OR gate unit 223, which are electrically connected to each other. In this embodiment, the anti-interference circuit 220 is used to receive the first phase control signal DeEN, and to divide the first rising signal UP1 and the first falling signal DN1 by a frequency division factor through the first phase control signal DeEN to generate the second rising signal UP2 and the second falling signal DN2.

[0024] The OR gate unit 223 has a first input terminal, a second input terminal, and an output terminal. At least one of the first input terminal and the second input terminal of the OR gate unit 223 receives the phase control signal, and the output terminal of the OR gate unit outputs the phase control signal. In this embodiment, the first input terminal of the OR gate unit 223 is electrically connected to the output terminal of the OR gate unit 215 and receives the first phase control signal DeEN. In one embodiment, the second input terminal of the OR gate unit 223 receives the second phase control signal Dis_d. In this embodiment, the voltage level of the second input terminal of the OR gate unit 223 is maintained at a low voltage level by the second phase control signal Dis_d, and the output terminal of the OR gate unit 223 outputs the first phase control signal DeEN.

[0025] The first gate unit 221 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first gate unit 221 receives the first rising signal UP1. The second input terminal of the first gate unit 221 is electrically connected to the output terminal of the gate unit 223 and receives the first phase control signal DeEN. The output terminal of the first gate unit 221 is electrically connected to the charge pump 300 and outputs the second rising signal UP2.

[0026] The second gate unit 222 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second gate unit 222 receives the first falling signal DN1. The second input terminal of the second gate unit 222 is electrically connected to the OR gate unit 223 and the first gate unit 221 and receives the first phase control signal DeEN. The output terminal of the second gate unit 222 is electrically connected to the charge pump 300 and outputs the second falling signal DN2.

[0027] Please refer to Figures 3 and 4 simultaneously. Figure 4 is a schematic diagram of the signal embodiment of the automatic correction circuit 200. Figure 4 includes the reference frequency signal FREF, the first rising signal UP1, the first falling signal DN1, the first phase control signal DeEN, the second rising signal UP2, and the second falling signal DN2. In Figure 4, the horizontal axis represents time, and the vertical axis represents voltage level. The reference frequency signal FREF is a frequency signal with a fixed clock frequency. The first rising signal UP1 and the first falling signal DN1 are control signals with fixed clock frequencies corresponding to the reference frequency signal FREF. The first phase control signal DeEN is a control signal with a fixed clock frequency, wherein the clock frequency of the first phase control signal DeEN is less than the clock frequency of the first rising signal UP1 and the first falling signal DN1. The second rising signal UP2 and the second falling signal DN2 are control signals with fixed clock frequencies, wherein the clock frequencies of the second rising signal UP2 and the second falling signal DN2 are less than the clock frequencies of the first rising signal UP1 and the first falling signal DN1. As shown in Figure 4, when the first phase control signal DeEN is an enabling voltage level (e.g., a high voltage level), the first phase control signal DeEN, the first rising signal UP1, and the first falling signal DN1 undergo logical operations through the first gate unit 221 and the second gate unit 222, causing the second rising signal UP2 and the second falling signal DN2 to correspond to the enabling voltage level of the first phase control signal DeEN. When the first phase control signal DeEN is a disabling voltage level (e.g., a low voltage level), the second rising signal UP2 and the second falling signal DN2 correspond to the disabling voltage level of the first phase control signal DeEN. The anti-interference circuit 220 uses the first phase control signal DeEN and the first falling signal DN1 to divide the frequency of the first rising signal UP1 and the first falling signal DN1 based on the division factor to generate the second rising signal UP2 and the second falling signal DN2. The division factor is a positive integer greater than 0. In this embodiment, the division factor is, for example, 4, meaning that the clock frequencies of the second rising signal UP2 and the second falling signal DN2 are one-quarter of the clock frequencies of the first rising signal UP1 and the first falling signal DN1, but this is not a limitation of the invention. In other words, the anti-interference circuit 220 can decide whether to block the first rising signal UP1 and the first falling signal DN1 based on the received first phase control signal DeEN. Therefore, by controlling the duration for which the first phase control signal DeEN is maintained at the disabled voltage level, the clock frequencies of the second rising signal UP2 and the second falling signal DN2 can be adjusted (reduced).

[0028] Please refer to Figures 2 and 5 simultaneously. Figure 5 is a schematic diagram of another embodiment of the automatic phase adjustment circuit 210 of the present invention. In this embodiment, an automatic phase adjustment circuit 210b includes a second delay circuit 216 and a third flip-flop 217. The second delay circuit 216 is electrically connected to the third flip-flop 217.

[0029] The second delay circuit 216 has an input terminal and an output terminal. The input terminal of the second delay circuit 216 is used to receive the reference frequency signal FREF. The output terminal of the second delay circuit 216 outputs a delayed frequency signal FREF_D. In one embodiment, the second delay circuit 216 includes a plurality of inverting units 2161 connected in series. The number of inverting units 2161 is, for example, four, and the invention is not limited thereto. The inverting units 2161 can be implemented by reverse gates.

[0030] The third flip-flop 217 is electrically connected to the output terminal of the second delay circuit 216. The third flip-flop 217 has a clock input terminal Clk, a data input terminal D, and a first data output terminal. The data input terminal D of the third flip-flop 217 is electrically connected to the output terminal of the second delay circuit 216 and receives the delayed frequency signal FREF_D. The clock input terminal Clk of the third flip-flop 217 is used to receive the feedback frequency signal FB. The first data output terminal of the third flip-flop 217... It is electrically connected to the anti-interference circuit 220 and outputs the second phase control signal Dis_d to the anti-interference circuit 220. The third flip-flop 217 is, for example, a D-type flip-flop.

[0031] Please refer to Figure 6, which is a schematic diagram of another embodiment of the anti-interference circuit 220 of the present invention. The difference between Figure 6 and Figure 3 is that, in this embodiment, the voltage level of the first input terminal of the OR gate unit 223 is maintained at a low voltage level by the first phase control signal DeEN, and the second input terminal of the OR gate unit 223 and the first data output terminal of the third flip-flop 217 are... The electrical connection is used to receive the second phase control signal Dis_d, and the output terminal of the OR gate unit 223 outputs the second phase control signal Dis_d. The second input terminals of the first OR gate unit 221 and the second OR gate unit 222 receive the second phase control signal Dis_d.

[0032] Please refer to Figures 7, 8, and 9. Figure 7 is a schematic diagram of another signal embodiment of the automatic correction circuit 200, Figure 8 is a schematic diagram of yet another signal embodiment of the automatic correction circuit 200, and Figure 9 is a schematic diagram of yet another signal embodiment of the automatic correction circuit 200. Figures 7 and 8 include the reference frequency signal FREF, the delayed frequency signal FREF_D, the feedback frequency signal FB, and the second phase control signal Dis_d. Figure 9 includes the first rising signal UP1, the first falling signal DN1, the second phase control signal Dis_d, the second rising signal UP2, and the second falling signal DN2. In Figures 7 to 9, the horizontal axis represents time, and the vertical axis represents voltage level. In Figure 7, during a detection period DR, when there is no phase difference between the reference frequency signal FREF and the feedback frequency signal FB, the second phase control signal Dis_d remains at the disabled voltage level. In other words, the clock signal Clock output by the voltage control delay circuit 500 is the desired clock signal, and this clock signal Clock does not require phase error adjustment. In Figure 8, during the detection period DR, a phase difference is generated between the reference frequency signal FREF and the feedback frequency signal FB. When this phase difference is equal to or greater than a phase difference threshold, the second phase control signal Dis_d changes from the disabled voltage level to the enabled voltage level. That is, the clock signal Clock output by the voltage control delay circuit 500 is an undesired clock signal, and this clock signal Clock requires phase error adjustment. Therefore, through the second delay circuit 216 and the third flip-flop 217, the second phase control signal Dis_d is changed from the disabled voltage level to the enabled voltage level, so that the automatic correction circuit 200 automatically performs phase error adjustment.

[0033] In Figure 9, when the second phase control signal Dis_d is the enable voltage level, the second phase control signal Dis_d, the first rising signal UP1, and the first falling signal DN1 undergo logical operations through the first gate unit 221 and the second gate unit 222, causing the second rising signal UP2 and the second falling signal DN2 to be at the enable voltage level corresponding to the second phase control signal Dis_d. When the second phase control signal Dis_d is the disable voltage level, the second rising signal UP2 and the second falling signal DN2 are at the disable voltage level corresponding to the second phase control signal Dis_d. That is, the anti-interference circuit 220 can determine whether to block the first rising signal UP1 and the first falling signal DN1 based on the received second phase control signal Dis_d. Therefore, the automatic correction circuit 200 can control the second phase control signal Dis_d based on the phase difference between the reference frequency signal FREF and the feedback frequency signal FB, so as to enable the second rising signal UP2 and the second falling signal DN2 in real time according to the change of the phase difference to adjust the phase and / or frequency of the clock signal Clock. That is, the automatic correction circuit 200 can enable the second rising signal UP2 and the second falling signal DN2 again when needed (when the phase difference is equal to or greater than a phase difference threshold value) to adjust the clock signal Clock, thereby adjusting (reducing) the clock frequency of the second rising signal UP2 and the second falling signal DN2.

[0034] Therefore, the automatic correction circuit 200 of the present invention can generate a second rising signal UP2 and a second falling signal DN2 whose clock frequencies are lower than those of the first rising signal UP1 and the first falling signal DN1. The operating frequency of the voltage control signal VCTRL can be reduced accordingly to the clock frequencies of the second rising signal UP2 and the second falling signal DN2, and the frequency at which the clock signal Clock is adjusted is also reduced. That is, when the delay-locked loop circuit is applied in a high-frequency clock environment, the frequency and time of its overall phase error adjustment are reduced, which can avoid non-ideal effects from occurring in the delay-locked loop circuit, thereby giving the delay-locked loop circuit better jitter performance and accurately outputting the desired clock signal Clock, thus improving the convenience of the delay-locked loop circuit application.

[0035] In another embodiment, the automatic phase adjustment circuit 210 can be implemented simultaneously by the embodiments of FIG3 and FIG5. Referring to FIG10, in this embodiment, the second input terminals of the first gate unit 221 and the second gate unit 222 of the anti-interference circuit 220 can receive the first phase control signal DeEN or the second phase control signal Dis_d from the output terminal of the OR gate unit 223. Referring again to FIG9, FIG9 may include the first phase control signal DeEN. In this embodiment, the automatic correction circuit 200 generates the second rising signal UP2 and the second falling signal DN2 with a fixed clock frequency through the first phase control signal DeEN, so that the automatic correction circuit 200 performs phase error adjustment based on the fixed clock frequency. When the phase difference between the reference frequency signal FREF and the feedback frequency signal FB is equal to or greater than the phase difference threshold, the automatic correction circuit 200 can further enable the second rising signal UP2 and the second falling signal DN2 in real time through the second phase control signal Dis_d, so as to adjust the clock signal Clock in real time. In this way, while minimizing the frequency and time of overall phase error adjustment, the voltage-controlled delay circuit 500 can accurately output the desired clock signal Clock, making the delay-locked loop circuit suitable for high-frequency clock environments and improving the ease of use of the delay-locked loop circuit.

[0036] Please refer to Figure 11. Based on the above embodiments and specific applications, the present invention further summarizes a signal interference suppression method for a delay-locked loop circuit. This method mainly involves the automatic phase adjustment circuit 210 (210a, 210b) and the interference suppression circuit 220 performing the following steps: The automatic phase adjustment circuit 210 and the anti-interference circuit 220 are activated (S110); Divide a first rising signal UP1 and a first falling signal DN1 by a division factor to generate a second rising signal UP2 and a second falling signal DN2 (S120); The automatic phase adjustment circuit 210 determines whether the phase difference between a reference frequency signal FREF and a feedback frequency signal FB is equal to or greater than a phase difference threshold value (S130). If the result is negative, return to step S120; When the determination is yes, a second phase control signal Dis_d is released to the anti-interference circuit 220 (S140); and Adjust the first rising signal UP1 and the first falling signal DN1 to generate the second rising signal UP2 and the second falling signal DN2 (S150).

[0037] In step S110, the automatic phase adjustment circuit 210a outputs a first phase control signal DeEN to the anti-interference circuit 220 based on the feedback frequency signal FB and the reference frequency signal FREF. The anti-interference circuit 220 receives the first rising signal UP1 and the first falling signal DN1 from the phase frequency detection circuit 100. In step S120, the anti-interference circuit 220 uses the first phase control signal DeEN to divide the first rising signal UP1 and the first falling signal DN1 by the division factor to generate the second rising signal UP2 and the second falling signal DN2. The division factor is a positive integer greater than 0. The clock frequencies of the second rising signal UP2 and the second falling signal DN2 are less than the clock frequencies of the first rising signal UP1 and the first falling signal DN1 based on the division factor. In step S130, the automatic correction circuit 200 determines whether the phase difference between the reference frequency signal FREF and the feedback frequency signal FB is equal to or greater than the phase difference threshold. When the phase difference between the reference frequency signal FREF and the feedback frequency signal FB is equal to or greater than the phase difference threshold, in step S140, the automatic phase adjustment circuit 210b outputs the second phase control signal Dis_d to the anti-interference circuit 220 based on the feedback frequency signal FB and the reference frequency signal FREF. In step S150, the anti-interference circuit 220 adjusts the first rising signal UP1 and the first falling signal DN1 based on the second phase control signal Dis_d to generate the second rising signal UP2 and the second falling signal DN2. In one embodiment, the clock frequencies of the second rising signal UP2 and the second falling signal DN2 in step S150 can be equal to or less than the clock frequencies of the first rising signal UP1 and the first falling signal DN1. After completing step S150, return to step S130.

[0038] In summary, the features of the delay-locked loop circuit and anti-signal interference method of the present invention are as follows: The present invention adjusts the frequency and / or phase of the second rising signal and the second falling signal by providing an automatic correction circuit between the phase frequency detection circuit and the charge pump, so that the clock frequency of a portion of the second rising signal and the second falling signal is lower than the clock frequency of the first rising signal and the first falling signal. Therefore, the present invention can reduce the frequency and time of phase error adjustment, thereby reducing signal glitch in traditional DLL circuit architectures, avoiding the occurrence of non-ideal effects, reducing signal noise and jitter, and thus enabling the delay-locked loop circuit to have better jitter performance. It is also suitable for environments with high-frequency clocks, thereby improving the convenience of delay-locked loop circuit applications.

[0039] The above embodiments are merely illustrative of the invention and are not intended to limit the invention. Any person skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention should be as set forth in the following claims.

[0040] 100: Phase and frequency detection circuit 200: Automatic calibration circuit 210, 210a, 210b: Automatic phase adjustment circuit 220: Anti-interference circuit 211: First Inverter 212: First flip-flop 213: Second flip-flop 214: First Delay Circuit 2141: Reverse Unit 215: Gate Unit 216: Second Delay Circuit 2161: Reverse Unit 217: Third flip-flop 221: First gate unit 222: Second gate unit 223: or gate unit 300: Charge Pump 400: Low-pass filter 500: Voltage Control Delay Loop Clock: time signal Clk: Clock input terminal D: Data Input Terminal DeEN: First phase control signal Dis_d: Second phase control signal DN1: First descent signal DN2: Second descent signal DR: Detection Period EN: Enable signal FB: Feedback Frequency Signal FREF: Reference Frequency Signal FREF_D: Delayed frequency signal First data output end Second data output terminal q1: First output signal q2: Second output signal Reset: Reset End UP1: First Ascent Signal UP2: Second Ascending Signal VCTRL: Voltage control signal S110~S150: Steps

Claims

1. A delay-locked loop circuit suitable for high-frequency clocks, comprising: A phase frequency detection circuit outputs a first rising signal and a first falling signal; an automatic correction circuit electrically connected to the phase frequency detection circuit receives the first rising signal and the first falling signal, and outputs a second rising signal and a second falling signal based on the first rising signal and the first falling signal; wherein the clock frequency of a portion of the second rising signal and the second falling signal is lower than the clock frequency of the first rising signal and the first falling signal; a charge pump electrically connected to the automatic correction circuit outputs a voltage control signal; and a voltage control delay circuit electrically connected to the charge pump and the phase frequency detection circuit outputs a clock signal based on the voltage control signal and serves as a feedback signal; wherein the automatic correction circuit is electrically connected between the phase frequency detection circuit and the charge pump.

2. The delay-locked loop circuit as described in claim 1, wherein, The phase frequency detection circuit receives a feedback frequency signal and a reference frequency signal, and outputs the first rising signal and the first falling signal based on the feedback frequency signal and the reference frequency signal; the charge pump receives the second rising signal and the second falling signal, and outputs the voltage control signal based on the second rising signal and the second falling signal; the voltage control delay circuit receives the voltage control signal and outputs the clock signal, which is then used as the feedback frequency signal and transmitted to the phase frequency detection circuit.

3. The delay-locked loop circuit as described in claim 2, wherein, The automatic correction circuit includes: an automatic phase adjustment circuit that receives the feedback frequency signal and the reference frequency signal, and outputs a phase control signal based on the feedback frequency signal and the reference frequency signal; and an anti-interference circuit that is electrically connected to the automatic phase adjustment circuit and the phase frequency detection circuit, for receiving the phase control signal, the first rising signal and the first falling signal, and outputting the second rising signal and the second falling signal based on the phase control signal, the first rising signal and the first falling signal.

4. The delay-locked loop circuit as described in claim 3, wherein, When the phase difference between the reference frequency signal and the feedback frequency signal is equal to or greater than a phase difference threshold, the phase control signal is a uniform energy voltage level.

5. The delay-locked loop circuit as described in claim 3, wherein, The anti-interference circuit is used to receive the phase control signal and divide the first rising signal and the first falling signal by a frequency division factor through the phase control signal to generate the second rising signal and the second falling signal.

6. The delay-locked loop circuit as described in claim 3, wherein, When the second rising signal and the second falling signal are at the same enable voltage level, the phase control signal is at the enable voltage level.

7. The delay-locked loop circuit as described in any one of claims 1 to 6, wherein, The second rising signal and the second falling signal have a fixed clock frequency.

8. A method for resisting signal interference, comprising: Based on a first phase control signal, a first rising signal and a first falling signal are divided by a division factor to generate a second rising signal and a second falling signal; and when the phase difference between a reference frequency signal and a feedback frequency signal is equal to or greater than a phase difference threshold, the first rising signal and the first falling signal are adjusted based on a second phase control signal to generate the second rising signal and the second falling signal; wherein the second rising signal and the second falling signal are used to generate a voltage control signal.

9. The anti-signal interference method as described in claim 8, comprising: When the phase difference between the reference frequency signal and the feedback frequency signal is less than the phase difference threshold, the first rising signal and the first falling signal are divided by the frequency division factor based on the first phase control signal to generate the second rising signal and the second falling signal.

10. The anti-signal interference method as described in claim 9, wherein, The clock frequencies of the second rising signal and the second falling signal are equal to or less than the clock frequencies of the first rising signal and the first falling signal.

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