LDMOS transistors and their manufacturing methods

Abstract

This invention provides an LDMOS transistor and its manufacturing method. The LDMOS transistor includes: a intrinsic region and a terminal region distributed along a first direction. The intrinsic region includes: a well region of a first doped type; a body region of a second doped type located in the well region; a drift region located in the well region, the drift region including at least one first implantation layer of the first doped type and at least one second implantation layer of the second doped type; a source region of the first doped type located in the body region; and a drain region of the first doped type located in the well region. The terminal region includes a third implantation region of the second doped type in contact with the second implantation layer. The direction from the source region to the drain region is set as a second direction, and the direction from the lower surface of the well region to the upper surface of the well region is set as a third direction. The first direction, the second direction, and the third direction are perpendicular to each other. The second implantation layer is set to be separated from the body region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an LDMOS transistor and a method for manufacturing an LDMOS transistor. Prior Technology

[0002] High voltage and high current place increasingly higher demands on laterally diffused metal oxide semiconductors (LDMOS): on the one hand, the wafer area of ​​high current application products depends on the successive reduction of the specific on-resistance Rsp, which puts forward higher requirements for the extreme optimization of breakdown voltage BV and specific on-resistance Rsp; on the other hand, it also puts forward higher requirements for the reliability of the device's high current short-circuit capability. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide an LDMOS transistor and a method for manufacturing the same, so as to solve the problems existing in the prior art.

[0004] According to a first aspect of the present invention, an LDMOS transistor is provided, comprising: a intrinsic region and a terminal region distributed along a first direction, the intrinsic region comprising: a well region of a first doped type; a body region of a second doped type extending from the upper surface of the well region into the interior of the well region; a drift region located in the well region, the drift region comprising at least one first implantation region of the first doped type and at least one second implantation region of the second doped type; a source region of the first doped type located in the body region; and a drain region of the first doped type located in the well region, the terminal region comprising a third implantation region of the second doped type in contact with the second implantation region, wherein the direction from the source region to the drain region is set as a second direction, the direction from the lower surface of the well region to the upper surface of the well region is set as a third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second implantation layer is set to be separate from the body region.

[0005] Preferably, each layer of the first implantation region includes a plurality of mutually separated first doped regions distributed along the second direction.

[0006] Preferably, each layer of the second implantation region includes a plurality of mutually separated second doped regions distributed along the second direction.

[0007] Preferably, the second injection region is located below the first injection region.

[0008] Preferably, one of the first injection zones is in contact with the upper surface of the well zone.

[0009] Preferably, the drain region is located in the first injection region.

[0010] Preferably, when the first injection region or the second injection region comprises at least two layers, the first injection region and the second injection region are alternately distributed in the third direction.

[0011] Preferably, the third implantation region includes a third doped region in contact with the second implantation region and a second well region in contact with the third doped region, the second well region being in contact with the bulk region of the intrinsic region.

[0012] Preferably, the third doped region is distributed at both ends of the second implantation region along the first direction, and the second well region is distributed at both ends of the body region along the first direction.

[0013] Preferably, the essential region further includes: an insulating structure located at least on the upper surface of the well region between the source region and the drain region, and a gate conductor extending from the source region at least over a portion of the drift region and located on the insulating structure, wherein the insulating structure includes a gate dielectric layer near the source region and a second insulating layer near the drain region.

[0014] Preferably, the drift region is located at least below the second insulating layer.

[0015] Preferably, the second insulating layer is configured as a thin dielectric layer, a withstand dielectric layer thicker than the gate dielectric layer, or a combination of one or two of the following: a shallow isolation trench.

[0016] According to a second aspect of the present invention, a method for manufacturing an LDMOS transistor is provided, comprising: forming an intrinsic region and a terminal region distributed along a first direction; the step of forming the intrinsic region comprising: forming a well region of a first doped type; forming a body region of a second doped type extending from the upper surface of the well region to the interior of the well region; forming a drift region located in the well region, the drift region comprising at least one first implantation region of the first doped type and at least one second implantation region of the second doped type; forming a source region of the first doped type located in the body region, and forming a drain region of the first doped type located in the well region; and the step of forming the terminal region comprising forming a third implantation region of the second doped type in contact with the second implantation region, wherein the direction from the source region to the drain region is set as a second direction, the direction from the lower surface of the well region to the upper surface of the well region is set as a third direction, the first direction, the second direction, and the third direction are perpendicular to each other, and the second implantation region is set to be separate from the body region.

[0017] Preferably, the step of forming a drift region located in the well region includes: forming a first mask template; forming at least one first implantation region of a first doping type based on the first mask template; and forming a second mask template; forming at least one second implantation region of a second doping type based on the second mask template.

[0018] Preferably, after forming the first injection region and before forming the second injection region, a second insulating layer is further formed above the drift region and on the surface of the well region.

[0019] Preferably, forming the third implantation region includes: forming a third doped region in contact with the second implantation region, and forming a second well region in contact with the third doped region, wherein the second well region is in contact with the bulk region of the intrinsic region.

[0020] Preferably, when the second implantation region is configured as a continuous single-layer structure, the first implantation region and the third doped region are formed simultaneously. Simple Explanation of the Diagram

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: [Figure 1] shows a cross-sectional view of a prior art LDMOS transistor; [Figure 2] shows a plan view of an LDMOS transistor according to a first embodiment of the present invention; [Figure 3] shows a cross-sectional view of the essential region of an LDMOS transistor according to a first embodiment of the present invention; [Figure 4] shows a cross-sectional view of the terminal region of an LDMOS transistor according to a first embodiment of the present invention; [Figure 5] shows a plan view of an LDMOS transistor according to a second embodiment of the present invention; [Figure 6] shows a cross-sectional view of the essential region of an LDMOS transistor according to a second embodiment of the present invention. Implementation

[0022] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0023] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0024] To describe a situation where A is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B". In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0025] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0026] Figure 1 shows a cross-sectional view of a prior art LDMOS transistor. The LDMOS transistor includes a substrate 101, a well region 102 on the substrate 101, a drift region 105 of a first doped type located in the well region 102, a body region 104 of a second doped type located in the well region, a drain region 108 located in the drift region 105, and a source region 107 and a body contact region 106 located in the body region 104. The LDMOS transistor also includes an implantation region 103 of a second doped type located below the drift region 105, the implantation region 103 extending below the source region 104 and contacting the source region 104. The injection region 103 can deplete itself with the drift region 105 to reduce the electric field on the transistor surface and greatly reduce the on-resistance of the transistor. However, when the large current minority carriers in the drain region flow through the surface channels of the drift region 105 and the body region 104 to the body contact region 106, they will trigger the parasitic npn (source / body / well, source / injection / drift) transistors to turn on, making the high current short-circuit capability of the LDMOS transistor very poor.

[0027] Figure 2 shows a plan view of an LDMOS transistor according to a first embodiment of the present invention. Figure 3 shows a cross-sectional view of the intrinsic region of the LDMOS transistor according to a first embodiment of the present invention. Specifically, Figure 3 is a cross-sectional view along the axis EF in Figure 2. Figure 4 shows a cross-sectional view of the terminal region of the LDMOS transistor according to a first embodiment of the present invention. Specifically, Figure 4 is a cross-sectional view along the axis AB in Figure 2. Referring to Figures 2, 3, and 4, as shown in Figure 2, the LDMOS transistor includes an intrinsic region 300 and a terminal region 400 distributed along a first direction F1. As shown in Figure 3, the intrinsic region includes: a well region 202 of a first doped type; a body region 204 of a second doped type extending from the upper surface of the well region to the interior of the well region; a drift region located in the well region 202, the drift region including at least one first implantation region 205 of the first doped type and at least one second implantation region 203 of the second doped type; a source region 207 of the first doped type located in the body region 204; and a drain region 208 of the first doped type located in the well region 202. The first injection region 205 is provided to increase the doping concentration in the well region, further reducing the specific on-resistance of the transistor. Additionally, the second injection region 203 is provided to mutually deplete the first injection region 205, thereby reducing the surface electric field between the transistor's gate and drain and increasing the transistor's breakdown voltage. Therefore, the shape, position, and number of the first injection region 205 and the second injection region 203 are not limited, as long as they can mutually deplete each other to optimize the breakdown voltage and specific on-resistance. The first doping type is set to either N-type or P-type, and the second doping type is set to the other of N-type and P-type.

[0028] As shown in Figure 4, the terminal region includes a third injection region of the second doping type that is in contact with the second injection region 203. Specifically, the third injection region includes a third doped region 220 that is in contact with the second injection region 203 and a second well region 221 that is in contact with the third doped region 220. The second well region 221 is in contact with the body region 204 in the intrinsic region 300.

[0029] Specifically, as shown in Figures 2 and 4, the third doped region 220 is distributed along the first direction at both ends of the second implantation region 203. Preferably, the third doped region 220 and the second implantation region 203 are synchronously formed in the same layer, and the second well region 221 is distributed along the first direction at both ends of the body region 204.

[0030] In this embodiment, the direction from the source region 207 to the drain region 208 is designated as the second direction F2, and the direction from the lower surface of the well region 202 to the upper surface of the well region 202 is designated as the third direction F3. The first direction F1, the second direction F2, and the third direction F3 are perpendicular to each other. In this embodiment, the first injection region 205 of the first doping type and the body region 204 of the second doping type are separated. At the same time, the second injection region 203 of the second doping type and the body region 204 of the second doping type are separated to reduce the flow of minority carriers from the drain region side through the second injection region 203 and the body region 204 of the essential region to the source region 207 and the body contact region 206, and to increase the flow of minority carriers from the drain region side through the terminal region 400 to the source region 207 and the body contact region 206.

[0031] Specifically, as shown in Figure 2, the LDMOS transistor further includes a body contact region 206 located in the body region 204 and adjacent to the source region 207; an insulating structure on the upper surface of the well region located at least between the source region 207 and the drain region 208, wherein the insulating structure includes a gate dielectric layer 211 near the source region and a second insulating layer 209 near the drain region; a gate conductor 210 is located at least on the gate dielectric layer 211, and further extends onto a portion of the second insulating layer 209. The gate conductor is made of polycrystalline silicon. The second insulating layer 209 is configured as a thin dielectric layer, a thick dielectric layer (silicon local oxide layer or nitride layer), or a combination of one or two of the following: a shallow isolation trench. Preferably, the thin dielectric layer may have the same thickness as the gate dielectric layer.

[0032] In this embodiment, the first injection region 205 is located at least below the second insulating layer 209. The first injection region 205 is positioned in contact with the upper surface of the well region 202, i.e., in contact with the second insulating layer 209. The drain region 208 is located within the first injection region 205. Positioning the first injection region 205 on the surface of the well region increases the doping concentration at the surface, making carriers flowing from the drain region to the source region more inclined to flow along the first injection region 205 on the surface, thus reducing the carrier flow resistance and path. In other embodiments, the first injection region 205 may not be in contact with the upper surface of the well region 202, i.e., the upper surface of the first injection region 205 is spaced a certain distance from the upper surface of the well region.

[0033] In this embodiment, the second injection region 203 is positioned below the first injection region 205, allowing the first injection region 205 and the second injection region 203 to better deplete each other. The distance between the first injection region 205 and the second injection region 203 is greater than or equal to 0. In other embodiments, the first injection region 205 and the second injection region 203 may also be positioned horizontally, or the second injection region 203 may surround the first injection region 205, etc. The positional relationship between the first injection region 205 and the second injection region 203 is not limited here.

[0034] In this embodiment, both the first injection region 205 and the second injection region 203 are set to one layer. In other embodiments, the first injection region 205 and the second injection region 203 may also be set to multiple layers. The first injection region 205 and the second injection region 203 are arranged alternately along a third direction, or multiple first injection regions 205 are arranged adjacent to each other, multiple second injection regions 203 are arranged adjacent to each other, and the multiple second injection regions 203 are disposed below the multiple first injection regions 205. The spacing between adjacent first injection regions 205 and second injection regions 203 is greater than or equal to 0.

[0035] Additionally, the LDMOS transistor further includes a substrate 201 of a second doping type, with the well region 202 located within the substrate 201, and the well region being of the first doping type. In other embodiments, a second doped epitaxial layer may also be included on the substrate 201, wherein the body region and the drift region are both located within the epitaxial layer, and the body region is in contact with the first implantation region, provided that the doping type of the well region surface (excluding the channel region) between the source region and the drain region is the same as the doping type of the source and drain regions. In other embodiments, a second doped epitaxial layer and a buried layer may also be included between the substrate 201 and the well region, which is not limited here.

[0036] In this embodiment, the terminal region further includes a shallow trench isolation structure 222, which is in contact with the second insulating layer 209 of the intrinsic region, and a conductor layer 223 located on a portion of the second well region 221 and a portion of the shallow trench isolation structure 222, which is in contact with the gate conductor of the intrinsic region.

[0037] This invention optimizes the breakdown voltage and specific on-resistance of LDMOS transistors by setting a first injection region 205 and a second injection region 203. Furthermore, the second injection region 203 is separated from the body region. A third injection region is provided in the terminal region so that minority carriers on the drain side (taking N-type doping as an example, the minority carriers are holes) flow through the second injection region 203 to the second doped region 220 and the second well region 221 in the terminal region, and finally to the source region and the body contact region 206. This configuration significantly reduces the base current of the parasitic NPN in the intrinsic region 300, suppresses the turn-on of the parasitic NPN, and greatly improves the reliability of high-current short-circuit operation.

[0038] Figure 5 shows a plan view of an LDMOS transistor according to a second embodiment of the present invention, and Figure 6 shows a cross-sectional view of the essential region of an LDMOS transistor according to a second embodiment of the present invention. The difference between the LDMOS transistor of this embodiment and the LDMOS transistor of the first embodiment is the different drift region structure; other structures are the same and will not be described in detail here.

[0039] The drift region includes at least one first implantation region 305 of a first doping type and at least one second implantation region 303 of a second doping type. Each first implantation region includes multiple separately arranged first doping regions 3051, and each second implantation region includes multiple separately arranged second doping regions 3031. Specifically, in this embodiment, both the first implantation region 305 and the second implantation region 303 are set as one layer. The multiple separately arranged first doping regions 3051 are arranged along a second direction, and the multiple separately arranged second doping regions 3031 are arranged along a second direction, with the second doping regions 3031 located below the first doping regions 3051. Preferably, one second doping region 3031 is disposed below each first doping region 3051. The spacing between adjacent first and second doping regions in the third direction is greater than or equal to 0.

[0040] In this embodiment, the spacing between adjacent first doped regions 3051 is the same, and the spacing between adjacent second doped regions 3031 is also the same. In other embodiments, the spacing between adjacent first doped regions 3051 and the width of each first doped region 3051 can be arbitrarily set according to requirements, as can the spacing between adjacent second doped regions 3031 and the width of each second doped region 3031, to maximize the optimization of breakdown voltage and specific on-resistance, reduce the base current of parasitic npn, and suppress npn turn-on. The structure in Figure 3 is a special case of the structure in Figure 6 when the spacing between the first doped region 3051 and the second doped region 3031 is zero. The structure in Figure 6 has greater freedom in balancing the required high-current short-circuit capability and specific on-resistance, especially when the spacing between the first doped regions 3051 is greater than the spacing between the second doped regions 3031, allowing the second implanted region to more completely deplete the first implanted region.

[0041] The present invention also provides a method for manufacturing an LDMOS transistor, which is applicable to, but not limited to, the LDMOS transistors of Figures 2 and 5. Specifically, the method includes: forming an intrinsic region 300 and a terminal region 400 distributed along a first direction. The step of forming the intrinsic region includes: forming a well region 202 of a first doped type; forming a body region 204 of a second doped type extending from the upper surface of the well region to the interior of the well region; forming a drift region located in the well region, the drift region including at least one first implantation region 205 / 305 of the first doped type and at least one second implantation region 203 / 303 of the second doped type; forming a source region 207 of the first doped type located in the body region 204; and forming a drain region 208 of the first doped type located in the well region 202. The step of forming the terminal region includes forming a third injection region of a second doped type that contacts the second injection region 203 / 303, wherein the direction from the source region 207 to the drain region 208 is set as a second direction, and the direction from the lower surface of the well region to the upper surface of the well region is set as a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other. The second injection region 203 / 303 is set to be separated from the body region 204 to reduce the flow of minority carriers from the drain region side through the second injection region and the body region of the intrinsic region to the body contact region, and to increase the flow of minority carriers from the drain region side through the terminal region to the body contact region.

[0042] The step of forming the drift region located in the well region includes: forming a mask template including an injection window; forming at least one first injection region of a first doped type based on the first mask template; and forming at least one second injection region of a second doped type based on the second mask template. The first and second injection regions at different depths can be formed by adjusting the injection energy and injection dose. The injection windows of the first and second masks may be the same or different.

[0043] When the first injection region 205 / 305 and the second injection region 203 / 303 are formed using two photomasks with different injection windows, after the formation of the first injection region 205 / 305 and before the formation of the second injection region 203 / 303, a second insulating layer 209 is further formed, located above the drift region and on the upper surface of the well region. In this embodiment, the second insulating layer 209 is configured as a locally grown silicon oxide layer, wherein the locally grown silicon oxide layer is a locally thermally grown silicon oxide layer. In other embodiments, the second insulating layer 209 may also be a deposited silicon oxide layer and / or a deposited silicon nitride layer.

[0044] The step of forming the third implantation region includes: forming a third doped region 220 in contact with the second implantation region 203 / 303, and forming a second well region 221 in contact with the third doped region 220, wherein the second well region 221 is in contact with the bulk region 204 of the intrinsic region. When the second implantation region 203 is configured as a continuous structure, preferably, the second implantation region 203 and the third doped region 220 are formed simultaneously.

[0045] The method further includes forming a gate dielectric layer 211 extending from the source region to the second insulating layer 209; and forming a gate conductor 210 located on the gate dielectric layer 211, wherein the gate conductor 210 extends from the source region 207 to at least a portion of the second insulating layer 209.

[0046] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only to the scope of the claims and their full scope and equivalents.

[0047] 101: Substrate 102: Well Area 103: Injection Zone 104: Body Area 105: Drift Zone 106: Body contact area 107: Source Region 108: Drainage Zone 201: Substrate 202: Well Area 203: Second Injection Zone 204: Body Area 205: First Injection Zone 206: Body contact area 207: Source Region 208: Duji Zone 209: Second insulating layer 210: Gate conductor 211: Gate dielectric layer 220: Second doped region 221: Second Well Area 222: Shallow trench isolation structure 223: Conductor layer 303: Second Injection Zone 3031: Second doped region 305: First Injection Zone 3051: First doped region

Claims

1. An LDMOS transistor, characterized in that it comprises: The intrinsic region and the terminal region are distributed along a first direction. The intrinsic region includes: a well region of a first doped type; a body region of a second doped type extending from the upper surface of the well region into the interior of the well region; a drift region located in the well region, the drift region including at least one first implantation region of the first doped type and at least one second implantation region of the second doped type; a source region of the first doped type located in the body region; and a drain region of the first doped type located in the well region. The terminal region includes a third implantation region of the second doped type that contacts the second implantation region. The direction from the source region to the drain region is set as a second direction, and the direction from the lower surface of the well region to the upper surface of the well region is set as a third direction. The first direction, the second direction, and the third direction are perpendicular to each other, and the second implantation layer is set to be separated from the body region.

2. The LDMOS transistor according to claim 1, wherein, Each layer of the first implantation region includes a plurality of mutually separated first doped regions distributed along the second direction.

3. The LDMOS transistor according to claim 1, wherein, Each layer of the second implantation region includes a plurality of mutually separated second doped regions distributed along the second direction.

4. The LDMOS transistor according to claim 1, wherein, The second injection area is located below the first injection area.

5. The LDMOS transistor according to claim 1, wherein, One of the first injection zones is in contact with the upper surface of the well zone.

6. The LDMOS transistor according to claim 5, wherein, The drain region is located in the first injection region.

7. The LDMOS transistor according to claim 1, wherein, When the first injection region or the second injection region comprises at least two layers, the first injection region and the second injection region are alternately distributed in the third direction.

8. The LDMOS transistor according to claim 1, wherein, The third implantation region includes a third doped region in contact with the second implantation region and a second well region in contact with the third doped region, the second well region being in contact with the bulk region of the intrinsic region.

9. The LDMOS transistor according to claim 8, wherein, The third doped region is distributed along the first direction at both ends of the second implantation region, and the second well region is distributed along the first direction at both ends of the body region.

10. The LDMOS transistor according to claim 1, wherein, The essential region further includes: an insulating structure located at least on the upper surface of the well region between the source region and the drain region, and a gate conductor extending from the source region at least over a portion of the drift region and located on the insulating structure, wherein the insulating structure includes a gate dielectric layer near the source region and a second insulating layer near the drain region.

11. The LDMOS transistor according to claim 10, wherein, The drift region is located at least below the second insulating layer.

12. The LDMOS transistor according to claim 10, wherein, The second insulating layer is configured as a thin dielectric layer, a withstand dielectric layer thicker than the gate dielectric layer, or a combination of one or two of the following: a shallow isolation trench.

13. A method for manufacturing an LDMOS transistor, characterized in that it comprises: The process of forming an essential region and a terminal region distributed along a first direction includes: forming a well region of a first doped type; forming a body region of a second doped type extending from the upper surface of the well region into the interior of the well region; forming a drift region located in the well region, the drift region including at least one first implantation region of the first doped type and at least one second implantation region of the second doped type; forming a source region of the first doped type located in the body region; and forming a drain region of the first doped type located in the well region. The process of forming the terminal region includes forming a third implantation region of the second doped type that contacts the second implantation region. The direction from the source region to the drain region is designated as a second direction, and the direction from the lower surface of the well region to the upper surface of the well region is designated as a third direction. The first direction, the second direction, and the third direction are perpendicular to each other, and the second implantation region is configured to be separate from the body region.

14. The method according to claim 13, wherein, The step of forming a drift region located in the well region includes: forming a first mask template; forming at least one first implantation region of a first doping type based on the first mask template; and forming a second mask template; forming at least one second implantation region of a second doping type based on the second mask template.

15. The method according to claim 14, wherein, After the formation of the first injection region and before the formation of the second injection region, a second insulating layer is formed above the drift region and on the surface of the well region.

16. The method according to claim 13, wherein, Forming the third implantation region includes: forming a third doped region in contact with the second implantation region, and forming a second well region in contact with the third doped region, wherein the second well region is in contact with the bulk region of the intrinsic region.

17. The method according to claim 16, wherein, When the second implantation region is configured as a continuous single-layer structure, the first implantation region and the third doped region are formed simultaneously.

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