Power converter

Abstract

This invention discloses a power converter, which is a low transformer turns ratio magnetically integrated current multiplier rectifier circuit. By adjusting the connection method of the synchronous rectifier transistor and the corresponding bridge arm, the effective duty cycle of the system can be increased while the circuit gain is reduced. Therefore, the power converter can reduce the transformer turns ratio for the same output voltage, thereby reducing transformer losses and costs.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a power converter. Prior Technology

[0002] To achieve higher system conversion efficiency, existing technologies often employ two-phase half-bridge current multiplier circuits and two-phase full-bridge current multiplier circuits for power conversion.

[0003] In a two-phase half-bridge current multiplier circuit, as shown in Figure 1(a), transistors Q1, Q2, Q3, and Q4 are all main switching transistors. When they are turned on, the transformer is energized; when they are turned off, the corresponding rectifier transistors SR1-SR4 are turned on to allow the energizing energy to be output for demagnetization. In this scheme, since transistors Q1 and Q2 belong to the same half-bridge circuit, transistors Q1 and Q2 cannot be turned on simultaneously, meaning the duty cycle range of the two-phase half-bridge circuit is 0-50%.

[0004] In a two-phase full-bridge current multiplier circuit, as shown in Figure 1(b), transistors Q1 and Q3 are the main switching transistors. When they are turned on, the transformer is energized. When they are turned off, the corresponding rectifier transistors SR1 and SR2 and the lower switching transistors (Q2, Q4) of the corresponding bridge arm are turned on to demagnetize. In this scheme, when the duty cycle is less than 50%, the output voltage is (D / N)*Vin, where D is the duty cycle and N is the turns ratio of the transformer. If the duty cycle is greater than 50%, there will be a mode in which the main switching transistors Q1 and Q3 are simultaneously turned on. At this time, the rectifier switches SR1 and SR2 are both turned off, so the magnetizing current will continue through the body diode, which will increase the loss and is not conducive to improving the system efficiency. Moreover, when the duty cycle is greater than 50%, the mode in which the main switching transistors Q1 and Q3 are simultaneously turned on and the mode in which the lower switching transistors Q2 and Q4 are simultaneously turned on are symmetrical. Therefore, when the duty cycle is greater than 50%, the output voltage of the circuit is [(1-D) / N]*Vin, and the voltage gain cannot be further adjusted. Summary of the Invention

[0005] In view of this, the present invention provides a power converter, which is a low transformer turns ratio magnetically integrated current-doubling rectifier circuit. This circuit, by adjusting the connection method of the synchronous rectifier transistors and the corresponding bridge arms, can both increase the effective duty cycle of the system and reduce the circuit gain. The power converter can reduce the transformer turns ratio while maintaining the same output voltage, thereby reducing transformer losses and lowering transformer costs.

[0006] This invention provides a power converter, comprising:

[0007] M transformer units, each transformer unit comprising a primary winding and a secondary winding, where M is an integer not less than 3; and

[0008] M bridge arms, each bridge arm is coupled between the two input terminals of the DC input voltage, and each bridge arm includes an upper switching transistor, a lower switching transistor, and a synchronous rectifier transistor connected in series;

[0009] In this configuration, the same-name terminal of each primary-side coil is connected to the common node of the upper switching transistor and the lower switching transistor in a corresponding bridge arm, and the different-name terminals of each primary-side coil are all connected to the same common node; and one end of each secondary-side coil is connected to the common node of the lower switching transistor and the synchronous rectifier transistor in different bridge arms, and the other end of each secondary-side coil is connected to one output terminal of the power converter.

[0010] Preferably, each of the bridge arms is coupled to the primary and secondary coils of different transformer units.

[0011] Preferably, the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and an i+1-th synchronous rectifier transistor connected in series. The corresponding terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the corresponding terminal of the i+1-th secondary winding is connected to the common node of the i+1-th synchronous rectifier transistor and the i-th lower switching transistor, where i is a natural number less than M.

[0012] Preferably, the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and a first synchronous rectifier transistor connected in series. The corresponding terminal of the i-th primary side coil is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the corresponding terminal of the first secondary side coil is connected to the common node of the first synchronous rectifier transistor and the i-th lower switching transistor, where i equals M.

[0013] Preferably, each of the upper switching transistors has the same conduction time and a phase difference of 360° / M. Each of the secondary rectifier transistors is complementary to the upper switching transistors with the same number. Each of the lower switching transistors is turned on when the upper switching transistors and synchronous rectifier transistors on its respective bridge arm are turned off.

[0014] Preferably, each of the bridge arms is coupled to the primary and secondary coils in the same transformer unit.

[0015] Preferably, the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and an i-th synchronous rectifier transistor connected in series. The same-name terminal of the i-th primary side coil is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the non-same-name terminal of the i-th secondary side coil is connected to the common node of the i-th lower switching transistor and the i-th synchronous rectifier transistor, where i is a natural number not less than M.

[0016] Preferably, each of the lower switching transistors has the same conduction time and a phase difference of 360° / M. Each of the secondary rectifier transistors is complementary to the lower switching transistor with the same number, and each of the upper switching transistors is complementary to the lower switching transistor with the same number.

[0017] Preferably, the upper or lower switching transistors in the M bridge arms have the same duty cycle, and the maximum is 1-1 / M.

[0018] Preferably, the voltage conversion ratio of the power converter is the ratio of the duty cycle to the sum of the turns ratio of the transformer unit and 1, the turns ratio of the transformer unit is the ratio of the number of turns of the primary coil to the number of turns of the secondary coil, wherein the M transformer units have the same turns ratio, and the duty cycle is the ratio of the conduction time of the upper switching transistor or the lower switching transistor to the switching period. Simple Explanation of the Diagram

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] [Figure 1] is a schematic diagram of a power converter in the prior art;

[0021] [Figure 2] is a schematic diagram of the power converter according to the first embodiment of the present invention;

[0022] [Figure 3] is a driving timing diagram of the power converter according to the first embodiment of the present invention;

[0023] [Figure 4] is a schematic diagram of the power converter according to the second embodiment of the present invention;

[0024] [Figure 5] Driving timing diagram of the power converter according to the second embodiment of the present invention;

[0025] [Figure 6] is a schematic diagram of the power converter according to the third embodiment of the present invention;

[0026] [Figure 7] is a schematic diagram of the power converter according to the fourth embodiment of the present invention. Implementation

[0027] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0028] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0029] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0030] Unless the context explicitly requires it, the words "including," "comprising," or similar terms used throughout the specification and the scope of the patent application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to."

[0031] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] Figure 2 is a schematic diagram of a power converter according to the first embodiment of the present invention. As shown in Figure 2, the power converter of this embodiment is described using a structure based on three transformer units as an example, which includes three transformer units and three bridge arms.

[0033] Specifically, each transformer unit includes a primary winding and a secondary winding, each bridge arm is coupled between the two input terminals of the DC input voltage Vin, and each bridge arm includes an upper switching transistor, a lower switching transistor and a synchronous rectifier transistor connected in series.

[0034] More specifically, the same-name terminal of each primary coil is connected to a common node of the corresponding upper and lower switching transistors, and the non-same-name terminals of each primary coil are all connected to the same common node; and the same-name terminal of each secondary coil is connected to a common node of different lower switching transistors and synchronous rectifier transistors, and the non-same-name terminals of each secondary coil are all connected to the same common node, which is connected to the ungrounded output terminal of the power converter, and generates an output voltage Vo at the output terminal.

[0035] In one embodiment, each bridge arm is coupled to the primary and secondary coils of a different transformer unit. In another embodiment, each bridge arm is coupled to the primary and secondary coils of the same transformer unit.

[0036] In this embodiment of the invention, transformer unit T1 includes a primary coil P1 and a secondary coil S1, transformer unit T2 includes a primary coil P2 and a secondary coil S2, and transformer unit T3 includes a primary coil P3 and a secondary coil S3. Each bridge arm is coupled to the primary and secondary coils in a different transformer unit. The first bridge arm includes an upper switching transistor Q1H, a lower switching transistor Q1L, and a synchronous rectifier transistor SR2 connected in series; the second bridge arm includes an upper switching transistor Q2H, a lower switching transistor Q2L, and a synchronous rectifier transistor SR3 connected in series; and the third bridge arm includes an upper switching transistor Q3H, a lower switching transistor Q3L, and a synchronous rectifier transistor SR1 connected in series.

[0037] It should be noted that the inductors Lm1, Lm2, and Lm3, which are connected in parallel with the secondary coils S1, S2, and S3 respectively, can be realized by the magnetizing inductance of the transformer unit or by externally connected independent inductors. In actual transformers, since the core and coils are not ideal, there are many parasitic parameters. First, the permeability of the core is not infinite, so the secondary coil of the transformer can be equivalent to an ideal secondary coil and a magnetizing inductance connected in parallel. Second, the primary and secondary coils of the transformer are not fully coupled, and there is some leakage inductance, but in this application, leakage inductance is temporarily ignored.

[0038] It should be understood that transformer unit T1, transformer unit T2, and transformer unit T3 can be three separate transformer modules, or they can be a single transformer module integrated together in a magnetic integration manner.

[0039] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the common node of the upper switching transistor Q1H and the lower switching transistor Q1L in the first bridge arm, and the corresponding terminal of the secondary winding S1 of transformer unit T1 is connected to the common node of the lower switching transistor Q3L and the synchronous rectifier transistor SR1 in the third bridge arm; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the common node of the upper switching transistor Q2H and the lower switching transistor Q2L in the second bridge arm, and the corresponding terminal of the secondary winding S2 of transformer unit T2 is connected to the common node of the lower switching transistor Q1L and the synchronous rectifier transistor SR2 in the first bridge arm; the corresponding terminal of the primary winding P3 of transformer unit T3 is connected to the common node of the upper switching transistor Q3H and the lower switching transistor Q3L in the third bridge arm, and the corresponding terminal of the secondary winding S3 of transformer unit T3 is connected to the common node of the lower switching transistor Q2L and the synchronous rectifier transistor SR3 in the second bridge arm. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor Co.

[0040] In the circuit structure shown in Figure 2, the control logic for the switching transistors is designed with the upper switching transistors Q1H, Q2H, and Q3H in each bridge arm as the main switching transistors. That is, during circuit operation, the ratio of the conduction time of the aforementioned upper switching transistors Q1H, Q2H, and Q3H to the switching cycle is denoted as the duty cycle D, and all upper switching transistors Q1H, Q2H, and Q3H have the same duty cycle D and conduction time. Specifically, the switching control signals of the upper switching transistors Q1H, Q2H, and Q3H have a sequential 120° phase difference.

[0041] Furthermore, the synchronous rectifier transistors SR1, SR2, and SR3 are complementaryly turned on with their corresponding main switching transistors Q1H, Q2H, and Q3H, respectively, i.e., Vg_SR1=! Vg_Q1H, Vg_SR2=! Vg_Q2H, and Vg_SR3=! Vg_Q3H. It should be noted that this complementary turning on is based on ideal operating conditions, where the related switching transistors do not turn on simultaneously, without considering the case of dead time. When dead time exists, the synchronous rectifier transistors SR1, SR2, and SR3 are non-overlappingly turned on with their corresponding main switching transistors Q1H, Q2H, and Q3H. Here, Vg_SRi, Vg_QiH, and Vg_QiL are the control signals for the corresponding synchronous rectifier transistor, the upper switching transistor, and the lower switching transistor, respectively.

[0042] Furthermore, the lower switching transistors Q1L, Q2L, and Q3L of each bridge arm are turned on when the other switching transistors on their respective bridge arms are turned off, i.e., satisfying "Vg_Q1L=!Vg_Q1H & !Vg_SR2", "Vg_Q2L=!Vg_Q2H & !Vg_SR3", and "Vg_Q3L =!Vg_Q3H ​​& !Vg_SR1", respectively. In other words, lower switching transistor Q1L is turned on when upper switching transistor Q1H and synchronous rectifier transistor SR2 are both turned off; lower switching transistor Q2L is turned on when upper switching transistor Q2H and synchronous rectifier transistor SR3 are both turned off; and lower switching transistor Q3L is turned on when upper switching transistor Q3H and synchronous rectifier transistor SR1 are both turned off.

[0043] Figure 3 shows the driving timing diagram of the power converter in the first embodiment. Figure 3(a) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is less than 1 / 3; Figure 3(b) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is greater than 1 / 3 and less than 2 / 3. It should be noted that, for the sake of brevity, only the first one-third of the working process of each working cycle T is analyzed here. Waveform IP is the current flowing through the primary coil in the transformer unit, waveform ISR is the current flowing through the synchronous rectifier transistor, and waveform VLm is the voltage on the inductor connected in parallel with the secondary coil. First, let's describe the operating condition when the duty cycle D is less than 1 / 3. Combining Figure 3(a) and Figure 2, during the time period 0~DT, the upper switching transistor Q1H is turned on, the upper switching transistors Q2H and Q3H are turned off, and the synchronous rectifier transistors SR2 and SR3 are turned on. The current conduction path is: primary coil P1 of upper switching transistor Q1H - primary coil P3 of T1 - output capacitor Co, therefore (the transformer's same-name terminal is defined as the positive terminal): Furthermore, the secondary coils S2 and S3 and the output capacitor Co are connected in parallel, therefore: Where VSi is the voltage on the i-th secondary coil. Define the turns ratio of a transformer as Np:Ns. According to the definition of a transformer, we have: Then it is sorted out as follows: Therefore, we can deduce that:

[0044] During the time period DT~T / 3, the upper switching transistors Q1H, Q2H, and Q3H are all off, while the synchronous rectifier transistors SR1, SR2, and SR3 are all on. Therefore: Therefore, we can conclude that: (The same applies to Lm2 and Lm3) Under steady state, based on the inductor volt-second balance and the above formula, we have: After sorting, we can get:

[0045] Next, let's discuss the operating condition where the duty cycle D is greater than 1 / 3 and less than 2 / 3. Referring to Figure 3(b) and Figure 2, during the time period 0~(D-1 / 3)T, the upper switching transistors Q1H and Q3H are on, the upper switching transistor Q2H is off, the lower switching transistor Q2L is on, and the synchronous rectifier transistor SR2 is on. Therefore, we have: The secondary coil S2 and the output capacitor CO are connected in parallel, therefore: According to the definition of a transformer, we have: Therefore, we can deduce that:

[0046] During the time period (D-1 / 3)T~T / 3, the upper switching transistor Q1H is turned on, while the upper switching transistors Q2H and Q3H are turned off, and the synchronous rectifier transistors SR2 and SR3 are turned on. The current conduction path is upper switching transistor Q1H - primary coil P1 of T1 - primary coil P3 of T3 - output capacitor Co, therefore: Therefore, we can conclude that: (The same applies to Lm2 and Lm3) Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:

[0047] Therefore, it can be seen that the power converter of this invention, through adjustment of the circuit structure, reduces the output voltage VO of the prior art to... Adjust the output voltage VO to Therefore, while achieving the same output voltage, the number of turns in the primary winding of the transformer can be reduced, thereby reducing transformer losses and costs.

[0048] Figure 4 is a schematic diagram of a power converter according to a second embodiment of the present invention. As shown in Figure 4, the power converter of this embodiment takes a structure based on three transformer units as an example, which includes three transformer units and three bridge arms. The difference between this embodiment and the first embodiment is that each bridge arm is coupled only to the primary and secondary coils of the same transformer unit.

[0049] In this embodiment of the invention, transformer unit T1 includes a primary coil P1 and a secondary coil S1, transformer unit T2 includes a primary coil P2 and a secondary coil S2, and transformer unit T3 includes a primary coil P3 and a secondary coil S3. Each bridge arm is coupled to the primary and secondary coils of the same transformer unit. The first bridge arm includes an upper switching transistor Q1H, a lower switching transistor Q1L, and a synchronous rectifier transistor SR1 connected in series; the second bridge arm includes an upper switching transistor Q2H, a lower switching transistor Q2L, and a synchronous rectifier transistor SR2 connected in series; and the third bridge arm includes an upper switching transistor Q3H, a lower switching transistor Q3L, and a synchronous rectifier transistor SR3 connected in series.

[0050] Furthermore, the same-name terminal of the primary coil P1 of transformer unit T1 is connected to the common node of the upper switching transistor Q1H and the lower switching transistor Q1L in the first bridge arm, and the non-same-name terminal of the secondary coil S1 of transformer unit T1 is connected to the common node of the lower switching transistor Q1L and the synchronous rectifier transistor SR1 in the first bridge arm; the same-name terminal of the primary coil P2 of transformer unit T2 is connected to the common node of the upper switching transistor Q2H and the lower switching transistor Q2L in the second bridge arm, and the non-same-name terminal of the secondary coil S2 of transformer unit T2 is connected to the common node of the lower switching transistor Q2L and the synchronous rectifier transistor SR2 in the second bridge arm; the same-name terminal of the primary coil P3 of transformer unit T3 is connected to the common node of the upper switching transistor Q3H and the lower switching transistor Q3L in the third bridge arm, and the non-same-name terminal of the secondary coil S3 of transformer unit T3 is connected to the common node of the lower switching transistor Q3L and the synchronous rectifier transistor SR3 in the third bridge arm. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor Co.

[0051] In the circuit structure shown in Figure 4, the control logic for the switching transistors is designed with the lower switching transistors Q1L, Q2L, and Q3L in each bridge arm as the main switching transistors. That is, during circuit operation, the ratio of the conduction time of these lower switching transistors Q1L, Q2L, and Q3L to the switching cycle is denoted as the duty cycle D, and all lower switching transistors Q1L, Q2L, and Q3L have the same duty cycle D and conduction time. Specifically, the switching control signals of the lower switching transistors Q1L, Q2L, and Q3L have a sequential 120° phase difference.

[0052] Furthermore, the synchronous rectifier transistors SR1, SR2, and SR3 are complementaryly turned on with their corresponding main switching transistors Q1L, Q2L, and Q3L, respectively, i.e., Vg_SR1=! Vg_Q1L, Vg_SR2=! Vg_Q2L, and Vg_SR3=! Vg_Q3L. It should be noted that this complementary turning on is based on ideal operating conditions, where the related switching transistors do not turn on simultaneously, and does not consider the case of dead time. When dead time exists, the synchronous rectifier transistors SR1, SR2, and SR3 are non-overlappingly turned on with their corresponding main switching transistors Q1L, Q2L, and Q3L.

[0053] Furthermore, the upper switching transistors Q1H, Q2H, and Q3H of each bridge arm are also complementary to their corresponding main switching transistors Q1L, Q2L, and Q3L, respectively. That is, they respectively satisfy Vg_Q1H=! Vg_Q1L, Vg_Q2H=! Vg_Q2L, and Vg_Q3H=! Vg_Q3L.

[0054] Thus, it can be seen that, on the one hand, in terms of circuit structure, the scheme of the first embodiment of the present invention involves the interlacing of the original secondary side structure of the transformer, and a single bridge arm needs to connect two different transformers; while in the scheme of the second embodiment of the present invention, a single transformer is only associated with one bridge arm, which is simpler in terms of circuit implementation; on the other hand, in terms of control method, in the scheme of the first embodiment of the present invention, the lower switching transistor of each bridge arm is turned on when all other switching transistors on the corresponding bridge arm are turned off, and the lower switching transistor of each bridge arm needs to adopt a relatively complex control method, and needs to make independent judgments and control independently; while in the scheme of the second embodiment of the present invention, the control logic of the upper switching transistor is the same as the control logic of the secondary side rectifier transistor SR, which reduces the logic judgment and the corresponding control signals, thus reducing the requirements for the control circuit.

[0055] Figure 5 shows the driving timing diagram of the power converter in the second embodiment. Figure 5(a) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is less than 1 / 3; Figure 5(b) mainly shows the operating waveform of transformer unit T1 when the duty cycle D is greater than 1 / 3 and less than 2 / 3. It should be noted that, for the sake of brevity, only the first one-third of the working process of each working cycle T is analyzed here. Waveform IP is the current flowing through the primary winding of the transformer unit, waveform ISR is the current flowing through the synchronous rectifier transistor, and waveform VLm is the voltage across the inductor connected in parallel with the secondary winding.

[0056] First, let's describe the operating condition when the duty cycle D is less than 1 / 3. Referring to Figure 5(a) and Figure 4, during the time period from 0 to DT, the lower switching transistor Q1L is turned on, and the lower switching transistors Q2L and Q3L are turned off. At this time, (the positive terminal of the transformer is defined as the positive terminal, and the positive terminal of the inductor is opposite to that of the transformer): Synchronous rectifier transistors SR2 and SR3 are turned on, and the secondary coils S2 and S3 and the output capacitor CO are connected in parallel. Therefore: According to the definition of a transformer, we have: Therefore, we can conclude that: During the time period DT~T / 3, synchronous rectifier transistors SR1, SR2, and SR3 are all turned on, therefore: Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:

[0057] Next, let's discuss the operating condition where the duty cycle D is greater than 1 / 3 and less than 2 / 3. Referring to Figure 5(b) and Figure 5, during the time period 0 to (D-1 / 3)T, the lower switching transistors Q1L and Q3L are turned on, the lower switching transistor Q2L is turned off, and the synchronous rectifier transistor SR2 is turned on. At this time, (the transformer's positive terminal is defined as the terminal with the same name, and the positive terminal of the inductor is opposite to that of the transformer): When synchronous rectifier transistor SR2 is turned on, the secondary coil S2 and output capacitor CO are connected in parallel, resulting in: According to the definition of a transformer, we have: Therefore, we can conclude that: Similarly, we have:

[0058] During the time period (D-1 / 3)T~T / 3, the lower switching transistor QIL is turned on, and the synchronous rectifier transistors SR2 and SR3 are turned on. The secondary coils S2 and S3 and the output capacitor CO are connected in parallel, so: Under steady state, based on the inductor volt-second balance and the above formula, we can obtain:

[0059] Therefore, it can be seen that the power converter of this invention, through adjustment of the circuit structure, reduces the output voltage VO of the prior art to... Adjust the output voltage VO to Therefore, while achieving the same output voltage, the number of turns in the primary winding of the transformer can be reduced, thereby reducing transformer losses and costs.

[0060] Figure 6 is a schematic diagram of a power converter according to the third embodiment of the present invention; the power converter of this embodiment takes a structure based on 4 transformer units as an example, which includes 4 transformer units and 4 bridge arms.

[0061] In this embodiment of the invention, transformer unit T1 includes a primary coil P1 and a secondary coil S1, transformer unit T2 includes a primary coil P2 and a secondary coil S2, and transformer unit T3 includes a primary coil P3 and a secondary coil S3. Each bridge arm is coupled to the primary and secondary coils in a different transformer unit. The first bridge arm includes an upper switching transistor Q1H, a lower switching transistor Q1L, and a synchronous rectifier transistor SR2 connected in series; the second bridge arm includes an upper switching transistor Q2H, a lower switching transistor Q2L, and a synchronous rectifier transistor SR3 connected in series; the third bridge arm includes an upper switching transistor Q3H, a lower switching transistor Q3L, and a synchronous rectifier transistor SR4 connected in series; and the fourth bridge arm includes an upper switching transistor Q4H, a lower switching transistor Q4L, and a synchronous rectifier transistor SR1 connected in series.

[0062] Furthermore, the corresponding terminal of the primary winding P1 of transformer unit T1 is connected to the common node of the upper switching transistor Q1H and the lower switching transistor Q1L in the first bridge arm, and the corresponding terminal of the secondary winding S1 of transformer unit T1 is connected to the common node of the lower switching transistor Q4L and the synchronous rectifier transistor SR1 in the fourth bridge arm; the corresponding terminal of the primary winding P2 of transformer unit T2 is connected to the common node of the upper switching transistor Q2H and the lower switching transistor Q2L in the second bridge arm, and the corresponding terminal of the secondary winding S2 of transformer unit T2 is connected to the common node of the lower switching transistor Q1L and the synchronous rectifier transistor SR2 in the first bridge arm. The primary winding P3 of transformer unit T3 is connected to the common node of the upper switching transistor Q3H and the lower switching transistor Q3L in the third bridge arm, and the secondary winding S3 of transformer unit T3 is connected to the common node of the lower switching transistor Q2L and the synchronous rectifier transistor SR3 in the second bridge arm. The primary winding P4 of transformer unit T4 is connected to the common node of the upper switching transistor Q4H and the lower switching transistor Q4L in the fourth bridge arm, and the secondary winding S4 of transformer unit T4 is connected to the common node of the lower switching transistor Q3L and the synchronous rectifier transistor SR4 in the third bridge arm. All non-same-name terminals of the primary windings are connected to the common node g1, and all non-same-name terminals of the secondary windings are connected to the output capacitor Co.

[0063] In the circuit structure shown in Figure 6, the control logic for the switching transistors is designed with the upper switching transistors Q1H, Q2H, Q3H, and Q4H in each bridge arm as the main switching transistors. That is, during circuit operation, the ratio of the conduction time of these upper switching transistors Q1H, Q2H, Q3H, and Q4H to the switching cycle is denoted as the duty cycle D, and all upper switching transistors Q1H, Q2H, Q3H, and Q4H have the same duty cycle D and conduction time. Specifically, the switching control signals of the upper switching transistors Q1H, Q2H, Q3H, and Q4H have a sequential 90° phase difference.

[0064] Furthermore, the synchronous rectifier transistors SR1, SR2, SR3, and SR4 are complementary to their corresponding main switching transistors Q1H, Q2H, Q3H, and Q4H, respectively, that is, they satisfy Vg_SR1=! Vg_Q1H, Vg_SR2=! Vg_Q2H, Vg_SR3=! Vg_Q3H, and Vg_SR4=! Vg_Q4H, respectively. Furthermore, the lower switching transistors Q1L, Q2L, Q3L, and Q4L of each bridge arm are turned on when the other switching transistors on their respective bridge arms are turned off, that is, they respectively satisfy "Vg_Q1L=!Vg_Q1H & !Vg_SR2", "Vg_Q2L=!Vg_Q2H & !Vg_SR3", "Vg_Q3L =!Vg_Q3H ​​& !Vg_SR4", and "Vg_Q4L=!Vg_Q4H & !Vg_SR1". That is, the lower switching transistor Q1L is turned on when the upper switching transistor Q1H and the synchronous rectifier transistor SR2 are both turned off; the lower switching transistor Q2L is turned on when the upper switching transistor Q2H and the synchronous rectifier transistor SR3 are both turned off; the lower switching transistor Q3L is turned on when the upper switching transistor Q3H and the synchronous rectifier transistor SR4 are both turned off; and the lower switching transistor Q4L is turned on when the upper switching transistor Q4H and the synchronous rectifier transistor SR1 are both turned off.

[0065] As can be seen from the first and third embodiments of the present invention, when extended to M transformer units, the i-th bridge arm includes the i-th upper switching transistor, the i-th lower switching transistor, and the i+1-th synchronous rectifier transistor connected in series. The same-name terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the same-name terminal of the i+1-th secondary winding is connected to the common node of the i-th synchronous rectifier transistor and the i-th lower switching transistor, where i is a natural number less than M.

[0066] The i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and a first synchronous rectifier transistor connected in series. The same-name terminal of the i-th primary side coil is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the same-name terminal of the first secondary side coil is connected to the common node of the first synchronous rectifier transistor and the i-th lower switching transistor, where i equals M.

[0067] Each upper switching transistor is a main switching transistor with the same conduction time and a phase difference of 360° / M. Each secondary rectifier transistor is complementary to the upper switching transistor with the same number. Each lower switching transistor is turned on when the upper switching transistor and the synchronous rectifier transistor on its respective bridge arm are turned off.

[0068] Figure 7 is a schematic diagram of a power converter according to the fourth embodiment of the present invention. This embodiment of the power converter uses a structure based on four transformer units as an example, comprising four transformer units and four bridge arms.

[0069] In this embodiment of the invention, transformer unit T1 includes a primary coil P1 and a secondary coil S1, transformer unit T2 includes a primary coil P2 and a secondary coil S2, and transformer unit T3 includes a primary coil P3 and a secondary coil S3. Each bridge arm is coupled to the primary and secondary coils in the corresponding transformer unit. The first bridge arm includes an upper switching transistor Q1H, a lower switching transistor Q1L, and a synchronous rectifier transistor SR1 connected in series; the second bridge arm includes an upper switching transistor Q2H, a lower switching transistor Q2L, and a synchronous rectifier transistor SR2 connected in series; the third bridge arm includes an upper switching transistor Q3H, a lower switching transistor Q3L, and a synchronous rectifier transistor SR3 connected in series; and the fourth bridge arm includes an upper switching transistor Q4H, a lower switching transistor Q4L, and a synchronous rectifier transistor SR4 connected in series.

[0070] Furthermore, the same-name terminal of the primary winding P1 of transformer unit T1 is connected to the common node of the upper switching transistor Q1H and the lower switching transistor Q1L in the first bridge arm, and the non-same-name terminal of the secondary winding S1 of transformer unit T1 is connected to the common node of the lower switching transistor Q1L and the synchronous rectifier transistor SR1 in the first bridge arm; the same-name terminal of the primary winding P2 of transformer unit T2 is connected to the common node of the upper switching transistor Q2H and the lower switching transistor Q2L in the second bridge arm, and the non-same-name terminal of the secondary winding S2 of transformer unit T2 is connected to the common node of the lower switching transistor Q2L and the synchronous rectifier transistor SR2 in the second bridge arm. The primary winding P3 of transformer unit T3 is connected to the common node of the upper switching transistor Q3H and the lower switching transistor Q3L in the third bridge arm. The secondary winding S3 of transformer unit T3 is connected to the common node of the lower switching transistor Q3L and the synchronous rectifier transistor SR3 in the third bridge arm. The primary winding P4 of transformer unit T4 is connected to the common node of the upper switching transistor Q4H and the lower switching transistor Q4L in the fourth bridge arm. The secondary winding S4 of transformer unit T4 is connected to the common node of the lower switching transistor Q4L and the synchronous rectifier transistor SR4 in the fourth bridge arm. All non-non ...

[0071] In the circuit structure shown in Figure 7, the control logic for the switching transistors is designed with the lower switching transistors Q1L, Q2L, Q3L, and Q4L in each bridge arm as the main switching transistors. That is, during circuit operation, the ratio of the conduction time of these lower switching transistors Q1L, Q2L, Q3L, and Q4L to the switching cycle is denoted as the duty cycle D, and all lower switching transistors Q1L, Q2L, Q3L, and Q4L have the same duty cycle D and conduction time. Specifically, the switching control signals of the lower switching transistors Q1L, Q2L, Q3L, and Q4L have a 90° phase difference sequentially.

[0072] Furthermore, the synchronous rectifier transistors SR1, SR2, SR3, and SR4 are complementary to their corresponding main switching transistors Q1L, Q2L, Q3L, and Q4L, respectively satisfying Vg_SR1=! Vg_Q1L, Vg_SR2=! Vg_Q2L, Vg_SR3=! Vg_Q3L, and Vg_SR4=! Vg_Q4L. Even further, the upper switching transistors Q1H, Q2H, Q3H, and Q4H of each bridge arm are also complementary to their corresponding main switching transistors Q1L, Q2L, Q3L, and Q4L, respectively satisfying Vg_Q1H=! Vg_Q1L, Vg_Q2H=! Vg_Q2L, Vg_Q3H=! Vg_Q3L, and Vg_Q4H=! Vg_Q4L.

[0073] Combining the second and fourth embodiments, it can be seen that when extended to M transformer units, the i-th bridge arm includes the i-th upper switching transistor, the i-th lower switching transistor, and the i-th synchronous rectifier transistor connected in series. The same-name terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the non-same-name terminal of the i-th secondary winding is connected to the common node of the i-th lower switching transistor and the i-th synchronous rectifier transistor, where i is a natural number not greater than M.

[0074] Each lower switching transistor serves as a main switching transistor, with the same conduction time and a phase difference of 360° / M. Each of the secondary-side rectifier transistors is complementary to the lower switching transistor with the same number, and each of the upper switching transistors is complementary to the lower switching transistor with the same number.

[0075] Therefore, the power converter of the present invention is a magnetically integrated current-doubling rectifier circuit with a low transformer turns ratio. By adjusting the connection method of the synchronous rectifier transistor and the corresponding bridge arm, the effective duty cycle of the system can be improved, while the circuit gain is reduced. The power converter of this application embodiment can reduce the transformer turns ratio under the same output voltage, thereby reducing transformer losses and lowering transformer costs.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

[0077] Q1, Q2, Q3, Q4: Switching transistors SR, SR1, SR2, SR3, SR4: Rectifying transistors Vin: Input voltage Vo: Output voltage T1, T2, T3, T4: Transformer Units P1, P2, P3, P4: Primary coils S1, S2, S3, S4: Secondary coils Q1H, Q2H, Q3H, Q4H: Upward switching transistors Q1L, Q2L, Q3L, Q4L: Down-switching transistors Lm1, Lm2, Lm3: Inductors g1: Public Node Co: Output capacitor

Claims

1. A power converter, comprising: There are M transformer units, each of which includes a primary winding and a secondary winding, where M is an integer not less than 3; The system comprises M bridge arms, each bridge arm being coupled between two input terminals of a DC input voltage, and each bridge arm including an upper switching transistor, a lower switching transistor, and a synchronous rectifier transistor connected in series; wherein, the same-name terminal of each primary-side coil is connected to a common node of the upper and lower switching transistors in a corresponding bridge arm, and the non-same-name terminals of each primary-side coil are all connected to the same common node; and one end of each secondary-side coil is connected to the common node of the lower switching transistor and the synchronous rectifier transistor in different bridge arms, and the other end of each secondary-side coil is connected to an output terminal of the power converter.

2. The power converter as claimed in claim 1, wherein each of the bridge arms is coupled to the primary and secondary coils in different of the transformer units.

3. The power converter as claimed in claim 2, wherein the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and an i+1-th synchronous rectifier transistor connected in series, the corresponding terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the corresponding terminal of the i+1-th secondary winding is connected to the common node of the i+1-th synchronous rectifier transistor and the i-th lower switching transistor, wherein... i is a natural number less than M.

4. The power converter as claimed in claim 2, wherein the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and a first synchronous rectifier transistor connected in series, the corresponding terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the corresponding terminal of the first secondary winding is connected to the common node of the first synchronous rectifier transistor and the i-th lower switching transistor, wherein, i equals M.

5. The power converter as described in claim 3 or 4, wherein each of the upper switching transistors has the same on-time and a phase difference of 360° / M, each of the secondary rectifier transistors is complementary to the upper switching transistors with the same number, and each of the lower switching transistors is turned on when the upper switching transistors and synchronous rectifier transistors on its respective bridge arm are turned off.

6. The power converter as claimed in claim 1, wherein each of the bridge arms is coupled to the primary and secondary coils in the same transformer unit.

7. The power converter as claimed in claim 6, wherein the i-th bridge arm includes an i-th upper switching transistor, an i-th lower switching transistor, and an i-th synchronous rectifier transistor connected in series, the same-name terminal of the i-th primary winding is connected to the common node of the i-th upper switching transistor and the i-th lower switching transistor, and the non-same-name terminal of the i-th secondary winding is connected to the common node of the i-th lower switching transistor and the i-th synchronous rectifier transistor, wherein, i is a natural number not less than M.

8. The power converter as claimed in claim 6, wherein each of the lower switching transistors has the same conduction time and a phase difference of 360° / M, each of the secondary rectifier transistors is complementary to the lower switching transistors with the same number, and each of the upper switching transistors is complementary to the lower switching transistors with the same number.

9. The power converter as claimed in claim 1, wherein the upper switching transistor or the lower switching transistor in the M bridge arms has the same duty cycle, and the maximum is 1-1 / M.

10. The power converter as claimed in claim 9, wherein the voltage conversion ratio of the power converter is the ratio of the duty cycle to the sum of the turns ratio of the transformer unit and 1, and the turns ratio of the transformer unit is the ratio of the number of turns of the primary winding to the number of turns of the secondary winding, wherein, The M transformer units have the same turns ratio, wherein the duty cycle is the ratio of the conduction time of the upper switching transistor or the lower switching transistor to the switching period.

Images