Semiconductor device and methods of formation

Abstract

The fluorine concentration in the gate dielectric layer can be balanced between gate-encapsulated p- and n-type field-effect transistors by including a capping layer around the gate dielectric layer. In some cases, combined with work function metal deposition and patterning, a portion of the capping layer can be removed from the surface of the gate dielectric layer in the p- and n-type field-effect transistor regions to ensure the removal of an equal or approximately equal portion of the underlying fluorine-containing gate dielectric layer in each region. Alternatively, the capping layer can be retained in the p- and n-type field-effect transistor regions to protect the underlying gate dielectric layer and act as a buffer layer to prevent removal of the gate dielectric layer during work function metal patterning. Therefore, balanced fluorine concentrations may occur between adjacent p- and n-type field-effect transistors, resulting in balanced device performance and reliability between adjacent p- and n-type field-effect transistors.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a method of forming a semiconductor device and a semiconductor device. Prior Technology

[0002] As semiconductor device manufacturing advances and technology node sizes shrink, transistors may become susceptible to short-channel effects (SCEs), such as hot carrier degradation, barrier layer reduction, and quantum confinement, among others. Furthermore, as transistor gate lengths shorten with smaller technology nodes, source / drain (S / D) electron tunneling increases, leading to increased off-state currents (the current flowing through the transistor's channels when it is in an off-state configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors (such as nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates for overcoming short-channel effects at smaller technology nodes. Compared to other types of transistors, nanostructure transistors are highly efficient structures that may experience reduced SCEs and enhanced carrier mobility. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor device. The method includes forming a plurality of first nanometer-structured channel layers, the first nanometer-structured channel layers being arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a plurality of second nanometer-structured channel layers, the second nanometer-structured channel layers being arranged in a direction substantially perpendicular to the semiconductor substrate. The method includes forming a gate dielectric layer around each of the first and second nanometer-structured channel layers. The method includes forming a capping layer around each of the first and second nanometer-structured channel layers, wherein the capping layer is formed on the gate dielectric layer. The method includes removing the capping layer from around each of the second nanometer-structured channel layers. The method includes forming a first work function metal layer around each of the second nanometer-structured channel layers and on the capping layer around each of the first nanometer-structured channel layers. The method includes removing the first work function metal layer and the capping layer from around each of the first nanometer-structured channel layers. The method includes forming a second work function metal layer around each of the first nanostructure channel layers and on a first work function metal layer around each of the first nanostructure channel layers.

[0004] As described in more detail above, some embodiments of this disclosure provide a method for forming a semiconductor device. The method includes forming a plurality of first nanostructure channel layers, the first nanostructure channel layers being arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a plurality of second nanostructure channel layers, the second nanostructure channel layers being arranged in a direction substantially perpendicular to the semiconductor substrate. The method includes forming a gate dielectric layer around each of the first and second nanostructure channel layers. The method includes forming a capping layer around each of the first and second nanostructure channel layers, wherein the capping layer is formed on the gate dielectric layer. The method includes forming a first work function metal layer on the capping layer around each of the first and second nanostructure channel layers. The method includes removing the first work function metal layer from the capping layer around each of the first nanostructure channel layers. The method includes forming a second work function metal layer on the capping layer around each of the first nanostructure channel layers and on the first work function metal layer around each of the second nanostructure channel layers.

[0005] As described in more detail above, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a plurality of first nanostructure channel layers arranged in a first direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a plurality of first dielectric layers disposed around each of the first nanostructure channel layers. The semiconductor device includes a plurality of second nanostructure channel layers arranged in the first direction, wherein the second nanostructure channel layers are adjacent to the first nanostructure channel layers in a second direction substantially perpendicular to the first direction. The semiconductor device includes a plurality of second dielectric layers disposed around each of the plurality of second nanostructure channel layers. The semiconductor device includes a first structure disposed around the first nanostructure channel layers and the first dielectric layers, the first structure including a first portion of a capping layer and a first portion of a first type metal layer on the first portion of the capping layer. The semiconductor device includes a second structure disposed around the second nanostructure channel layers and the second dielectric layers, the second structure including a second portion of a capping layer, a second type metal layer on the second portion of the capping layer, and a second portion of a first type metal layer on the second type metal layer. Simple Explanation of the Diagram

[0006] The appearance of some embodiments of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1A through 1C are schematic diagrams illustrating exemplary embodiments of the fin-defined process described in some embodiments of this disclosure. Figure 2 is a schematic diagram of the exemplary dummy gate structure formation process described in some embodiments of this disclosure. Figure 3 is a schematic diagram of an exemplary implementation of the source / drain groove formation process described in some embodiments of this disclosure. Figures 4A and 4B are schematic diagrams illustrating exemplary embodiments of the internal spacer formation process described in some embodiments of this disclosure. Figure 5 is a schematic diagram of an exemplary implementation of the source / drain region formation process described in some embodiments of this disclosure. Figure 6 is a schematic diagram of an exemplary implementation of an interlayer dielectric formation process described in some embodiments of this disclosure. Figures 7A through 7I are schematic diagrams illustrating exemplary implementations of the replacement gate process described in some embodiments of this disclosure. Figures 8A to 8E are schematic diagrams illustrating exemplary implementations of the replacement gate process described in some embodiments of this disclosure. Figure 9 is a schematic diagram of an exemplary process for incorporating fluorine into the gate dielectric layer, as described in some embodiments of this disclosure. Figure 10A is an exemplary embodiment, which includes a graph illustrating the fluorine distribution in an n-type transistor structure as described in some embodiments disclosed herein. Figure 10B is an exemplary embodiment, which includes a graph illustrating the fluorine distribution in a p-type transistor structure as described in some embodiments disclosed herein. Figure 11 is a flowchart of an exemplary process associated with the formation of a semiconductor device as described in some embodiments of this disclosure. Figure 12 is a flowchart of an exemplary process associated with the formation of a semiconductor device as described in some embodiments of this disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify some embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, some embodiments of this disclosure may repeat element symbols and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "upper part," and the like may be used in some embodiments of this disclosure to describe the relationship between one element or feature and another element or feature, as shown in the figures. The spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used in some embodiments of this disclosure may be interpreted accordingly.

[0009] Nanostructured transistors may include gate structures that enclose multiple nanostructured channels. Gate structures enclosing nanostructured channels increase control over the gate structure above the conductive channels within the nanostructured channels, increase the drive current of the nanostructured transistor, and / or reduce the SCE of the nanostructured transistor, among other examples. In some cases, semiconductor devices may include p-type metal-oxide-semiconductor (PMOS) and n-type metal-oxide-semiconductor (NMOS) nanostructured transistors. Integrating PMOS and NMOS nanostructured transistors into the same semiconductor device enables complementary metal-oxide-semiconductor (CMOS) integrated circuits to be implemented within the semiconductor device. However, nanostructured transistors face manufacturing challenges that can lead to performance issues, manufacturing yield problems, and / or device failures.

[0010] Incorporating fluorine (F) into the gate dielectric layer can improve its quality by passivating interface traps, potentially increasing device performance. However, due to different operations when forming the work function metal (WFM) for p-type field-effect transistors (PFETs) and n-type field-effect transistors (NFETs), the fluorine concentration can vary between GAA p-type PFETs and GAA n-type NFETs within the same semiconductor device. For example, non-uniform removal of the gate dielectric portion between the PFET and NFET regions during WFM patterning can lead to different fluorine concentrations between PFETs and NFETs. Variations in fluorine concentration can result in different electrical properties, performance, and reliability between GAA NFETs and PFETs. For example, the difference in fluorine concentration between PFET and NFET may lead to different bias temperature instability (BTI) and different time-dependent dielectric breakdown (TDDB) values ​​between PFET and NFET.

[0011] In some embodiments described in this disclosure, the fluorine concentration in the gate dielectric layer between GAA PFETs and NFETs can be balanced by including a capping layer on and around the gate dielectric layer during gate replacement processes. In some cases, combined with WFM deposition and patterning, portions of the capping layer can be removed from the surface of the gate dielectric layer in each of the PFET and NFET regions. Removing the capping layer from each region ensures the removal of an equal or approximately equal portion of the underlying fluorine-containing gate dielectric layer in each region. Therefore, due to the equal or approximately equal reduction in fluorine concentration in both the PFET and NFET regions, a balanced fluorine concentration may be achieved in adjacent PFETs and NFETs. Alternatively, the capping layer can be retained in the PFET and NFET regions to protect the underlying gate dielectric layer. In this case, WFM layers can be deposited on the remaining capping layers, which act as buffer layers to prevent the removal of portions of the gate dielectric layer during WFM patterning. Thus, the gate dielectric layer in each region remains intact, and the fluorine concentration in the PFET and NFET regions is minimally reduced. The same or approximately the same fluorine concentration in GAA PFETs and NFETs may result in balanced device performance and reliability between adjacent PFETs and NFETs.

[0012] Figures 1A through 1C are schematic diagrams of an exemplary embodiment 100 of the fin-defined fabrication process described in some embodiments of this disclosure. Exemplary embodiment 100 includes examples of forming fin structures and associated shallow trench isolation (STI) regions for a semiconductor device 105 as described in some embodiments of this disclosure. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-enclosed (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes examples of forming fin structures and associated STI regions for the transistors of the semiconductor device 105.

[0013] Figures 1A through 1C each illustrate a perspective view of the semiconductor device 105 and a cross-sectional view along the line (cross-section AA) in the perspective view. As illustrated in Figure 1A, the processing of the semiconductor device 105 is performed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0014] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., direction Z). For example, the layer stack 115 includes vertically alternating layers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 above the semiconductor substrate 110. The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in Figure 1A are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of some embodiments disclosed herein.

[0015] The sacrificial nanostructure layer 120 enables the definition of a vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 125 and serves as a reserved location layer for the subsequent formation of gate structures of transistors in the semiconductor device 105 formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first and second material compositions are the same material composition. In some embodiments, the first and second material compositions are different material compositions. As an example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This allows the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 to be selectively etched depending on the type of etchant used (e.g., allowing the sacrificial nanostructure layer 120 but not the nanostructure channel layer 125 to be etched, or allowing the nanostructure channel layer 125 but not the sacrificial nanostructure layer 120 to be etched).

[0016] One or more types of deposition tools can be used to deposit and / or grow alternating layers of layer stack 115 to include nanostructures (e.g., nanosheets) on semiconductor substrate 110. For example, the deposition tools can be used to grow sacrificial nanostructure layer 120 and / or nanostructure channel layer 125 by epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, sacrificial nanostructure layer 120 and / or nanostructure channel layer 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0017] One or more masking layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The masking layers may include a hard masking layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The masking layers may be used to perform fin patterning operations to form a fin structure in the semiconductor substrate 110.

[0018] As illustrated in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the Y direction within the semiconductor device 105 and may be aligned in the X direction within the semiconductor device 105. The fin structure 150 includes a portion of the layer stack 115 above and / or on the fin portion 160 above the semiconductor substrate 110. The fin structure 150 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on a pattern formed in one or more of the masking layers. The one or more masking layers may be patterned using photolithography techniques, including dual patterning or multiple patterning techniques. Etching tools may be used to etch the semiconductor substrate 110 based on a pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0019] As further illustrated in Figure 1B, some fin structures 150 may be formed with different widths for different types of nanostructured transistors. As an example, a first subset of fin structures 150a may be formed for p-type nanostructured transistors (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructured transistors), and a second subset of fin structures 150b may be formed for n-type nanostructured transistors (e.g., n-type metal-oxide-semiconductor (NMOS) nanostructured transistors). As another example, a first subset of fin structures 150a may be formed for nanostructured transistors used to operate at lower voltages, and a second subset of fin structures 150b may be formed for nanostructured transistors used to operate at higher voltages.

[0020] As illustrated in Figure 1C, the pad 165 and the STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The pad 165 and the STI region 170 may each comprise a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low dielectric constant dielectric material, and / or another suitable insulating material.

[0021] A deposition tool can be used to conformally deposit a liner (e.g., using ALD or another conformal deposition technique) and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the space between the fin structures 150 and extends above the top of the fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., chemical mechanical planarization, CMP) to planarize the dielectric layer such that the top surface of the dielectric layer is approximately coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a chemical mechanical polishing termination layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form an STI region 170 such that the top surface of the STI region 170 is approximately coplanar with or beneath the bottommost sacrificial nanostructure layer 120.

[0022] As indicated above, Figures 1A through 1C are provided as examples. Other examples may differ from those described with respect to Figures 1A through 1C.

[0023] Figure 2 is a schematic diagram of an exemplary embodiment 200 of the dummy gate formation process described in some embodiments of this disclosure. Exemplary embodiment 200 includes an example of forming a dummy gate structure 205 for a nanostructure transistor of a semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the processes described in conjunction with Figures 1A to 1C.

[0024] Figure 2 illustrates a perspective view of a semiconductor device 105, on which a dummy gate structure 205 is formed. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over a portion of the fin structure 150 and a portion of the STI region 170. The dummy gate structure 205 extends in the X direction and is aligned in the Y direction such that it is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent processing stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess, wherein the source / drain regions of the nanostructured transistor are formed in the fin structure 150.

[0025] The dummy gate structure 205 may include a gate electrode layer 210, a hard masking layer 215 on and / or above the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polysilicon (polysilicon or PO) or another material. The hard masking layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer, which may include silicon dioxide (SiO2) or another material) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer, which may include silicon nitride, such as Si3N4 or another material). The spacer layer 220 includes silicon carbide (SiOC), nitrogen-free SiOC, or another suitable material. The gate dielectric layer 225 may include silicon oxide (e.g., SiOx, such as SiO2), silicon nitride (e.g., SixNy, such as Si3N4), a high dielectric constant (high k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9) and / or another suitable material.

[0026] The layer of the dummy gate structure 205 can be formed using various semiconductor processing techniques, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor processing techniques.

[0027] Figure 2 further illustrates reference cross sections used in subsequent figures as described in some embodiments of this disclosure. Cross section AA, in the xz plane (referred to as the y-cut), spans the fin structure 150 in the source / drain region of the semiconductor device 105. Cross section BB, in the yz plane (referred to as the x-cut), is perpendicular to cross section AA and spans the dummy gate structure 205 and along the underlying fin structure 150. Cross section CC, in the xz plane, is parallel to cross section AA and perpendicular to cross section BB, and along the dummy gate structure 205. For clarity, subsequent figures refer to these reference cross sections. In some figures, for ease of depiction, some component symbols for parts or features shown may be omitted to avoid confusion with other parts or features.

[0028] As indicated above, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2.

[0029] Figure 3 is a schematic diagram of an exemplary embodiment 300 of the source / drain trench formation process described in some embodiments of this disclosure. Exemplary embodiment 300 includes an example of forming source / drain trenches 305 for the source / drain regions of a nanostructured transistor in a semiconductor device 105. Figure 3 is illustrated from a plurality of perspective views drawn in Figure 2, including a perspective view of cross-section AA, cross-section BB, and cross-section CC in Figure 2. In some embodiments, the operations described in connection with exemplary embodiment 300 are performed after the processes described in connection with Figures 1A through 2.

[0030] As illustrated in cross-sections AA and BB of Figure 3, the source / drain groove 305 is formed through a portion 155 of the fin structure 150 during the etching operation. The source / drain groove 305 is formed on opposite sides of the dummy gate structure 205. The etching operation can be performed using etching tools and may be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes the use of plasma etching technology, wet chemical etching technology, and / or another type of etching technology.

[0031] The source / drain grooves 305 also extend into a portion of the fin portion 160 of the fin structure 150. This results in the formation of a mesa region 310 in the fin structure 150. The sidewall of each portion of the source / drain groove 305 beneath the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as a base) represents a region of the fin portion 160 of the fin structure 150, on which a nanostructure channel is defined from the nanostructure channel layer 125. The nanostructure channel 315 extends between adjacent source / drain grooves 305 and is located beneath the dummy gate structure 205 between adjacent source / drain grooves 305.

[0032] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or nanowire, and other examples) that serves as a semiconducting channel for the nanostructure transistor of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may comprise silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is aligned in one direction (e.g., direction Z) that is substantially perpendicular to the semiconductor substrate 110. In other words, the nanostructure channel 315 is vertically aligned or stacked above the semiconductor substrate 110.

[0033] As indicated above, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3.

[0034] Figures 4A and 4B are schematic diagrams of an exemplary embodiment 400 of the internal spacer formation process described in some embodiments of this disclosure. Exemplary embodiment 400 includes an example of forming internal spacers between the ends of nanostructured channels 315 exposed in source / drain recesses 305. Figures 4A and 4B are each drawn from a plurality of perspective views shown in Figure 2, including a perspective view of cross-section AA, cross-section BB, and cross-section CC in Figure 2. In some embodiments, the operations described in connection with exemplary embodiment 400 are performed after the processes described in connection with Figures 1A through 3.

[0035] As illustrated in cross-section BB of Figure 4A, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain groove 305 are laterally etched during an etching operation (e.g., in a direction X approximately parallel to the length of the sacrificial nanostructure layer 120), thereby forming a cavity 405 between the ends of the sacrificial nanostructure layer 120 exposed in the source / drain groove 305. Specifically, the ends of the sacrificial nanostructure layer 120 below the dummy gate structure 205 can be laterally etched through the source / drain groove 305 using an etching tool to form a cavity 405 between the ends of the nanostructure channel 315. The cavity 405 can be formed in an approximately curved shape, approximately concave, approximately triangular, approximately square, or another shape.

[0036] As illustrated in cross sections AA and BB of Figure 4B, an inner spacer (InSP) 410 is formed within a cavity 405 in the source / drain recess 305 between the ends of perpendicularly adjacent nanostructure channels 315. The inner spacer 410 is included to reduce parasitic capacitance in the nanostructure transistors and to protect the source / drain regions (which are subsequently formed in the source / drain recess 305) from etching during nanosheet release operations to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The inner spacer 410 includes silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material.

[0037] To form the internal spacer 410, a deposition tool can be used to deposit a layer of dielectric material in the cavity 405 and along the sidewalls and bottom surface of the source / drain recess. CVD, PVD, and ALD techniques and / or another deposition technique can be used to deposit this dielectric material layer. An etching tool is used to subsequently remove excess material from the source / drain recess, such that the remaining portion corresponds to the internal spacer 410 in the cavity 405. In some embodiments, the etching operation may result in a curved or recessed surface of the internal spacer 410 facing the source / drain recess 305. In some embodiments, the surface of the internal spacer 410 facing the source / drain recess 305 is approximately flat, such that the surface of the internal spacer 410 and the surface of the end of the nanostructure channel 315 are approximately uniform and flush.

[0038] As indicated above, Figures 4A and 4B are provided as examples. Other examples may differ from those described with respect to Figures 4A and 4B.

[0039] Figure 5 is a schematic diagram of an exemplary embodiment 500 of the source / drain region formation process described in some embodiments of this disclosure. Exemplary embodiment 500 includes an example of forming the source / drain region of a nanostructured transistor of semiconductor device 105. Figure 5 is illustrated from a plurality of perspective views drawn in Figure 2, including a perspective view of cross-section AA, cross-section BB, and cross-section CC in Figure 2. In some embodiments, the operations described in connection with exemplary embodiment 500 are performed after the processes described in connection with Figures 1A through 4B.

[0040] As illustrated in cross sections AA and BB of Figure 5, the source / drain groove 305 is filled with one or more layers to form source / drain regions within the source / drain groove 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain groove 305, and the deposition tool can deposit source / drain regions 510 on the buffer region 505 in the source / drain groove 305. In some embodiments, the deposition tool is used to deposit a capping layer 515 on the source / drain regions 510 in the source / drain groove 305.

[0041] Buffer region 505 may include silicon (Si), boron-doped silicon (SiB), or another dopant, and / or another material. Buffer region 505 may be located between source / drain region 510 and adjacent mesa region 310 to reduce, minimize, and / or prevent dopant migration from source / drain region 510 to adjacent mesa region 310 and / or current leakage from source / drain region 510 to adjacent mesa region 310, which could otherwise lead to short-channel effects in semiconductor device 105. Therefore, buffer region 505 can increase the performance and / or yield of semiconductor device 105.

[0042] Source / drain regions 510 may individually or collectively represent a source or drain, depending on the context. Source / drain regions 510 may be included on opposite sides of a dummy gate structure 205, such that a nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge) and other examples), n-type materials (e.g., phosphorus (P) or arsenic (As) and other examples), and / or another type of dopant. Therefore, semiconductor device 105 may include p-type metal-oxide-semiconductor (PMOS) nanostructure transistors (which include p-type source / drain regions 510), n-type metal-oxide-semiconductor (NMOS) nanostructure transistors (which include n-type source / drain regions 510), and / or other types of nanostructure transistors.

[0043] One or more layers of the source / drain region 510 may be formed by epitaxial growth, deposition (e.g., using CVD, PVD, ALD), and / or by one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over an associated buffer region 505 (which may be referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or another dopant) and may be included as a shielding layer to reduce short-channel effects in the semiconductor device 105 and to reduce dopant extrusion or migration into the nanostructure channel 315. The second layer may include heavily doped silicon or heavily doped silicon-germanium. The second layer may be included to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0044] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or another material. The capping layer 515 may be included to reduce dopant diffusion and protect the underlying source / drain region 510 during semiconductor processing operations of the semiconductor device 105 prior to contact formation. Furthermore, the capping layer 515 may facilitate the formation of a metal-semiconductor (e.g., silicate) alloy.

[0045] As indicated above, Figure 5 is provided as an example. Other examples may differ from those described with respect to Figure 5.

[0046] Figure 6 is a schematic diagram of an exemplary embodiment 600 of the interlayer dielectric (ILD) formation process described in some embodiments of this disclosure. Figure 6 is drawn from a plurality of perspective views shown in Figure 2, including a perspective view of cross section AA, cross section BB, and cross section CC in Figure 2. In some embodiments, the operations described in connection with exemplary embodiment 500 are performed after the processes described in connection with Figures 1A through 5.

[0047] As illustrated in cross-sections AA and BB of Figure 6, a dielectric layer 605 is formed over the source / drain regions 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain regions 510 and / or to prevent damage to the source / drain regions 510 during the replacement gate process that replaces the dummy gate structures 205. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another type of ILD layer.

[0048] In some embodiments, a contact etch stop layer (CESL) is conformally deposited (e.g., by means of a deposition tool) over the source / drain region 510 prior to the formation of the dielectric layer 605. Alternatively, the capping layer 515 may be a CESL. The dielectric layer 605 is then formed on the CESL. The CESL may provide a mechanism to terminate the etching process when forming contacts or vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (SixNy), silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbide (SiCO), or combinations thereof, and other examples. The CESL may be deposited using deposition processes such as ALD, CVD, or another deposition technique.

[0049] As indicated above, Figure 6 is provided as an example. Other examples may differ from those described with respect to Figure 6.

[0050] Figures 7A through 7I are schematic diagrams of an exemplary embodiment 700 of a replacement gate (RPG) process described in some embodiments of this disclosure. Exemplary embodiment 700 includes an example of a replacement gate process for replacing a dummy gate structure 205 with a high-dielectric-constant / metal gate structure (e.g., a replacement gate structure) of a nanostructured transistor in semiconductor device 105. Figures 7A through 7I are each drawn from a perspective view of cross section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the operations described in conjunction with Figures 1A through 6.

[0051] As illustrated in cross sections BB and CC of Figure 7A, the gate replacement process includes a dummy gate removal operation. The dummy gate removal operation includes removing a dummy gate structure 205 from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or groove) between dielectric layers 605 and provides proximity to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 may be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or another type of etching technique.

[0052] The removal of the dummy gate structure 205 exposes the mesa region 310a (a region of the fin portion 160a, on which a nanostructure channel is defined by the nanostructure channel 315a) and the stack of nanostructure channels 315a arranged above the mesa region 310a in the Z direction of the semiconductor device 105. The removal of the dummy gate structure 205 also exposes the mesa region 310b (a region of the fin portion 160b, on which a nanostructure channel is defined by the nanostructure channel 315b) and the stack of nanostructure channels 315b arranged above the mesa region 310b in the Z direction of the semiconductor device 105. The nanostructure channels 315a and 315b extend in the Y direction of the semiconductor device 105. Nanostructured channels 315a and 315b can be arranged in the X direction in the semiconductor device 105, such that the nanostructured channels 315a and 315b are side by side or laterally adjacent in the semiconductor device 105.

[0053] Mesa region 310a and nanostructure channel 315a may be exposed to prepare for the formation of an n-type gate structure of an NMOS nanostructure transistor for semiconductor device 105 around nanostructure channel 315a. Mesa region 310b and nanostructure channel 315b may be exposed to prepare for the formation of a p-type gate structure of a PMOS nanostructure transistor for semiconductor device 105 around nanostructure channel 315b.

[0054] As further illustrated in Figure 7A, the gate replacement process includes a nanostructure release operation (e.g., a SiGe release operation). A nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This results in openings 705 (e.g., spaces) between nanostructure channels 315a (e.g., regions surrounding nanostructure channels 315a) and between nanostructure channels 315b (e.g., regions surrounding nanostructure channels 315b). The sacrificial nanostructure layer 120 can be removed by utilizing spaces previously occupied by the dummy gate structure 205. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on differences in etch selectivity between the material of the sacrificial nanostructure layer 120 and the materials of the nanostructure channels 315a and 315b, and between the material of the sacrificial nanostructure layer 120 and the material of the internal spacer 410. The internal spacer 410 can be used as an etch stop layer during the etching operation to protect the source / drain region 510 from being etched.

[0055] As illustrated in Figure 7B, the gate replacement operation continues, wherein a gate structure (e.g., a replacement gate structure) is formed in an opening 705 between the source / drain regions 510 of the nanostructured transistor of the semiconductor device 105. Specifically, an n-type gate structure 710a is formed in and around the nanostructured channels 315a of the NMOS nanostructured transistor of the semiconductor device 105. The n-type gate structure 710a occupies the region previously occupied by the sacrificial nanostructure layer 120 such that the n-type gate structure 710a encloses the nanostructured channel 315a and surrounds the nanostructured channel 315a on at least three sides. In some embodiments, the n-type gate structure 710a completely encloses the nanostructured channel 315a and surrounds the nanostructured channel 315a on all four sides.

[0056] A p-type gate structure 710b is formed in and around the nanostructure channels 315b of the PMOS nanostructure transistor in the semiconductor device 105. The p-type gate structure 710b occupies the area previously occupied by the sacrificial nanostructure layer 120, such that the p-type gate structure 710b encloses the nanostructure channel 315b and surrounds the nanostructure channel 315b on at least three sides. In some embodiments, the p-type gate structure 710b completely encloses the nanostructure channel 315b and surrounds the nanostructure channel 315b on all four sides.

[0057] Forming the n-type gate structure 710a and the p-type gate structure 710b may include forming a gate dielectric layer 715 around the nanostructure channels 315a and 315b, and on the mesa regions 310a and 310b. Deposition tools may be used to deposit the gate dielectric layer 715 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, the gate dielectric layer 715 is a high-dielectric-constant gate dielectric layer comprising one or more high-dielectric-constant materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2 – dielectric constant approximately 3.9). Examples include titanium oxide (TixOy, such as TiO2), lanthanum oxide (LaxOy, such as La2O3), hafnium oxide (HfOx, such as HfO2), yttrium oxide (YxOy, such as Y2O3), and tantalum oxide (TaxOy, such as...). Examples include Ta₂O₅, zirconium oxide (ZrOx, such as ZrO₂), and / or aluminum oxide (AlxOy, such as Al₂O₃), among others. Additionally and / or alternatively, silicon dioxide (SiO₂) and / or another dielectric material may be used instead of a high-dielectric-constant dielectric material. In some embodiments, the gate dielectric layer 715 may have a thickness ranging from about 0.5 nanometers to about 3 nanometers. However, other values ​​within this range are within the scope of some embodiments disclosed herein.

[0058] As further illustrated in Figure 7B, in some embodiments, the interface layer 720 may be formed around the nanostructure channels 315a and 315b and on the mesa regions 310a and 310b, such that the interface layer 720 is disposed between the gate dielectric layer 715 and the nanostructure channels 315a and 315b, and between the gate dielectric layer 715 and the mesa regions 310a and 310b. In this case, the gate dielectric layer 715 is formed around the interface layer 720 surrounding the nanostructure channels 315a and 315b. The interface layer 720 may include a thin layer of dielectric material, such as silicon oxide (SiOx). In some embodiments, the interface layer 720 is deposited using a deposition technique (such as ALD or CVD). In some embodiments, the interface layer 720 is formed by oxidation, wherein the surfaces of the nanostructure channels 315a and 315b and the mesa regions 310a and 310b are oxidized to form the interface layer 720.

[0059] As further illustrated in Figure 7B, fluorine is added to the gate dielectric layer 715 and / or the interface layer 720 via circular portions 725 representing fluorine atoms. In embodiments where the interface layer 720 may be omitted, fluorine is added to the gate dielectric layer 715. In embodiments where both the gate dielectric layer 715 and the interface layer 720 are present, fluorine may be added to both the gate dielectric layer 715 and / or the interface layer 720. As described in more detail in conjunction with Figure 9, the fluorine incorporation process may include deposition of a liner layer on the gate dielectric layer 715, deposition of a fluorine-containing source layer on the liner layer, an annealing process, and subsequent removal of the fluorine-containing source layer and the liner layer. Other methods for fluorine incorporation may include fluoride ion implantation processes, fluorine-containing gas plasma treatment operations, and / or fluorine-containing gas treatment operations.

[0060] As illustrated in Figures 7C and 7D, a capping layer 730 is formed on the gate dielectric layer 715, such that the capping layer 730 encapsulates the nanostructure channels 315a and 315b. The capping layer 730 is also formed on the mesa regions 310a and 310b.

[0061] The material of the capping layer 730 completely fills the openings 705 between and around the nanostructure channels 315a and 315b. In some embodiments, the material of the capping layer 730 may be a metal, such as titanium (Ti), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), hafnium (Hf), lanthanum (La), and cobalt (Co), as well as other metals, oxides, nitrides, and / or carbides of one or more metals. For example, the material of the capping layer 730 may be titanium nitride (TixNy), aluminum nitride (AlxNy), tungsten nitride (WxNy), molybdenum nitride (MoxNy), titanium oxide (TixOy), aluminum oxide (AlxOy), tungsten oxide (WxOy), molybdenum oxide (MoxOy), titanium carbide (TixCy), and / or aluminum carbide (AlxCy). Deposition tools can be used to deposit the capping layer 730 using PVD, ALD, CVD, oxidation, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. In some embodiments, the thickness of the capping layer 730 may range from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein. The thickness of the capping layer 730 may depend on the spacing (e.g., opening 705) between the nanostructure channels 315a and 315b. For example, the thickness of the capping layer 730 may be sufficient to completely fill the opening 705 between and around the nanostructure channels 315a and 315b. In other words, the capping layer 730 has sufficient thickness to merge between vertically adjacent nanostructure channels 315a and between vertically adjacent nanostructure channels 315b. For example, the thickness of the capping layer 730 may be greater than half the spacing between vertically adjacent nanostructure channels 315a and between vertically adjacent nanostructure channels 315b. The capping layer 730 may be completely merged between vertically adjacent nanostructure channels 315a and between vertically adjacent nanostructure channels 315b.

[0062] As illustrated in Figure 7D, during the process of removing the second portion of the capping layer 730 from the nanostructure channel 315b and the mesa region 310a, a masking layer 735 can be used to cover the first portion of the capping layer 730 on the nanostructure channel 315b and the mesa region 310a. The masking layer 735 protects the first portion of the capping layer 730 on the nanostructure channel 315a and the mesa region 310a, such that the first portion of the capping layer 730 remains on the nanostructure channel 315a and the mesa region 310a.

[0063] A deposition tool can be used to deposit a mask layer 735 on nanostructure channels 315a and 315b and mesa regions 310a and 310b. The mask layer 735 can then be patterned by removing a portion of the mask layer 735 from the nanostructure channels 315b and from the mesa regions 310b. An etching tool can be used to etch the mask layer 735 to pattern it.

[0064] Then, an etching tool can be used to remove a second portion of the capping layer 730 from the nanostructure channel 315b and the mesa region 310b, while the masking layer 735 protects the nanostructure channel 315a and the mesa region 310a. In some embodiments, wet etching techniques are used to remove the second portion of the capping layer 730 from the nanostructure channel 315b and the mesa region 310b. For example, wet etchants (such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), a mixture of ammonia (NH3) and hydrogen peroxide (H2O2) (APM), and / or hydrochloric acid (HCl), a mixture of hydrogen peroxide (H2O2) and water (HPM)) can be used to anisotropically etch the second portion of the capping layer 730 to remove the second portion of the capping layer 730 from the nanostructure channel 315b and the mesa region 310b.

[0065] Etching of the second portion of the capping layer 730 may result in the removal of a portion of the gate dielectric layer 715, which may lead to a decrease in the fluorine concentration on the side of the semiconductor device 105 (e.g., the PMOS side) where the p-type gate structure 710b will be formed. The decrease in fluorine concentration on the PMOS side is schematically illustrated by arrows and circular portions 725 (representing the removal of fluorine atoms) and differently patterned circular portions 740 (representing the vacancies where the removed fluorine atoms are located).

[0066] Subsequently, plasma ashing technology (e.g., using nitrogen (N2) plasma and hydrogen (H2) reactant gases) and / or another type of masking layer removal technology can be used to remove the masking layer 735 from the nanostructure channel 315a and from the mesa region 310a.

[0067] As illustrated in Figure 7E, a p-type work function metal layer 745 is formed on a first portion of the capping layer 730, wherein an n-type gate structure 710a will be formed (e.g., on the NMOS side) and on the gate dielectric layer 715 on the PMOS side. On the NMOS side, the p-type work function metal layer 745 is conformally deposited around each of the nanostructure channels 315a and around the mesa region 310a on the exposed surface of the first portion of the capping layer 730. On the PMOS side, the p-type work function metal layer 745 encloses the nanostructure channels 315b (e.g., on the four sides of the nanostructure channel 315b). The p-type work function metal layer 745 may also be formed on the mesa region 310b. In some embodiments, the p-type work function metal layer 745 enclosing the nanostructure channels 315b completely fills the openings 705 between and around the nanostructure channels 315b, such that the p-type work function metal layer 745 is merged between the nanostructure channels 315b.

[0068] Since the p-gate structure 710b is a metallic gate structure, a p-type work function metal layer 745 may be included in the p-gate structure 710b for work function tuning. The p-type work function metal layer 745 may include one or more p-type metals, such as tungsten (W), titanium (Ti), cobalt (Co), molybdenum (Mo), ruthenium (Ru), tungsten nitride (WxNy), titanium nitride (TixNy), tantalum nitride (TaxNy), molybdenum nitride (MoxNy), and / or another metal, metal oxide, metal nitride, and / or metal carbide having a work function greater than approximately 4.7 eV, and other examples. The p-type work function metal layer 745 may be included to tune the work function of the PMOS nanostructure transistor, such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 315b. This enables the PMOS nanostructure transistor to achieve a relatively low threshold voltage, while also enabling the PMOS nanostructure transistor to achieve relatively low current leakage.

[0069] Deposition tools can be used to deposit a p-type work function metal layer 745 using PVD, ALD, CVD, oxidation, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. The p-type work function metal layer 745 can be deposited in one or more deposition operations. In some embodiments, the p-type work function metal layer 745 is formed to a thickness ranging from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein. The thickness of the p-type work function metal layer 745 may depend on the spacing between the nanostructure channels 315b (e.g., openings 705). For example, the thickness of the p-type work function metal layer 745 may be sufficient to completely fill the openings 705 between and around the nanostructure channels 315b. In other words, the p-type work function metal layer 745 has sufficient thickness to merge between vertically adjacent nanostructure channels 315b. The p-type work function metal layer 745 can be completely merged between vertically adjacent nanostructure channels 315b.

[0070] As illustrated in Figure 7F, the first portion of the p-type work function metal layer 745 and the capping layer 730 is removed from the nanostructure channel 315a and the mesa region 310a. If the p-type work function metal layer 745 remains around the nanostructure channel 315a and the mesa region 310a, the p-type work function metal layer 745 may further cause the work function of the n-type gate structure 710a to be too far from the conductive band of the material of the nanostructure channel 315a.

[0071] A masking layer 750 may be formed on the nanostructure channel 315b and the mesa region 310b. During the process of removing the first portion of the p-type work function metal layer 745 and the first portion of the capping layer 730 from the nanostructure channel 315a and the mesa region 310a, the masking layer 750 may be used to cover a second portion of the p-type work function metal layer 745 on the nanostructure channel 315b and the mesa region 310b, such that the second portion of the p-type work function metal layer 745 remains on the nanostructure channel 315b and the mesa region 310b.

[0072] A deposition tool can be used to deposit a mask layer 750 on nanostructure channels 315a and 315b and mesa regions 310a and 310b. The mask layer 750 can then be patterned by removing a portion of the mask layer 750 from the nanostructure channels 315a and the mesa regions 310a. An etching tool can be used to etch the mask layer 750 to pattern it. The etching tool can then be used to remove a first portion of the p-type work function metal layer 745 and a first portion of the capping layer 730 from the nanostructure channels 315a and the mesa regions 310a, while the mask layer 750 protects the nanostructure channels 315b and the mesa regions 310b.

[0073] In some embodiments, wet etching techniques are used to remove a second portion of the p-type work function metal layer 745 from the nanostructure channel 315a and from the mesa region 310a. For example, solutions (such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), a mixture of ammonia (NH3) and hydrogen peroxide (H2O2) (APM), and / or a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2) and water (HPM)) can be used to etch the second portion of the p-type work function metal layer 745.

[0074] In some embodiments, the first portion of the capping layer 730 may be removed after the first portion of the p-type work function metal layer 745 has been removed from the nanostructure channel 315a and the mesa region 310a. For example, a first etching operation may be performed to remove the first portion of the p-type work function metal layer 745, and then a second etching operation may be performed to remove the first portion of the capping layer 730. In some embodiments, the first portion of the capping layer 730 and the first portion of the p-type work function metal layer 745 are removed together from the nanostructure channel 315a and the mesa region 310a in the same etching operation.

[0075] In some embodiments, wet etching techniques are used to remove a first portion of the capping layer 730 from the nanostructure channel 315a and from the mesa region 310a. For example, wet etchants (such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), a mixture of ammonia (NH3) and hydrogen peroxide (H2O2) (APM), and / or a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2) and water (HPM)) can be used to anisotropically etch the first portion of the capping layer 730 to remove the first portion of the capping layer 730 from the nanostructure channel 315a and from the mesa region 310a.

[0076] Similar to the etching of the second portion of capping layer 730, etching of the first portion of capping layer 730 may cause a portion of gate dielectric layer 715 to be removed from nanostructure channel 315a and from mesa region 310a. This may result in a decrease in fluorine concentration on the side of semiconductor device 105 (e.g., NMOS side) where the n-type gate structure 710a will be formed. The decrease in fluorine concentration on the NMOS side is schematically illustrated by arrows and circular portions 725 (representing the removal of fluorine atoms) and differently patterned circular portions 740 (representing vacancies where the removed fluorine atoms are located).

[0077] The removal of the capping layer 730 from both the NMOS and PMOS sides results in an equal or approximately equal reduction in the fluorine concentration in the gate dielectric layer 715 and / or interface layer 720 on both the NMOS and PMOS sides of the semiconductor device 105. Due to the balanced fluorine concentration between the PMOS and NMOS sides, the semiconductor device 105 will exhibit the same or similar electrical properties, performance, and reliability between the resulting GAA NFET and PFET. For example, the lack of a fluorine concentration difference between the PFET and NFET may result in the same or similar BTI and TDDB values ​​between adjacent PFETs and NFETs. In some embodiments, to achieve a balanced electrical property, performance, and reliability between the resulting GAA NFET and PFET, the ratio of the fluorine concentration in the gate dielectric layer 715 and / or interface layer 720 on the NMOS side to the fluorine concentration in the gate dielectric layer 715 and / or interface layer 720 on the PMOS side is included in the range of approximately 0.7:1 to approximately 1.4:1. However, other values ​​within this range are within the scope of some embodiments disclosed herein. In some embodiments, the concentration of fluorine in the gate dielectric layer 715 and / or interface layer 720 on the NMOS and PMOS sides may range from about 2 atoms / nm² to about 50 atoms / nm². However, other values ​​in this range are within the scope of some embodiments disclosed herein.

[0078] Subsequently, plasma ashing technology (e.g., using nitrogen (N2) plasma and hydrogen (H2) reactant gases) and / or another type of mask layer removal technology can be used to remove the mask layer 750 from the nanostructure channel 315b and from the mesa region 310b.

[0079] As illustrated in Figure 7G, an n-type work function metal layer 755 is formed on the gate dielectric layer 715 of the n-type gate structure 710a (e.g., on the NMOS side) and on the p-type work function metal layer 745 of the p-type gate structure 710b (e.g., on the PMOS side). After removing the first portion of the p-type work function metal layer 745 and the first portion of the capping layer 730 from the nanostructure channel 315a and the mesa region 310a, the n-type work function metal layer 755 can be formed around the nanostructure channel 315a, on the mesa region 310a, and on the second portion of the p-type work function metal layer 745. On the NMOS side, the n-type work function metal layer 755 surrounds the nanostructure channel 315a (e.g., on the four sides of the nanostructure channel 315a). The n-type work function metal layer 755 can also be formed on the mesa region 310a. In some embodiments, the n-type work function metal layer 755 encapsulating the nanostructure channels 315a completely fills the openings 705 between and around the nanostructure channels 315a, such that the n-type work function metal layer 755 is merged between the nanostructure channels 315a. On the PMOS side, the n-type work function metal layer 755 is conformally deposited on the exposed surface of the second portion of the p-type work function metal layer 745 around each of the nanostructure channels 315b and around the mesa region 310b.

[0080] The n-type work function metal layer 755 may include one or more metallic materials, which tune or adjust the work function of the n-type gate structure 710a to approach the conduction band of the material of the nanostructure channel 315a. In some embodiments, the n-type work function metal layer 755 includes tantalum (Ta), aluminum (Al), tantalum-containing metals, aluminum-containing metals, and / or another metal, metal oxide, metal nitride, and / or metal carbide.

[0081] An n-type work function metal layer 755 is formed such that it surrounds each of the nanostructure channels 315a. The n-type work function metal layer 755 may also be formed on the exposed portion of the mesa region 310a beneath the nanostructure channels 315a. Deposition tools can be used to deposit the n-type work function metal layer 755 using CVD, PVD, ALD, electroplating, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. The n-type work function metal layer 755 may be deposited in one or more deposition operations. In some embodiments, the n-type work function metal layer 755 is formed to a thickness ranging from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein. The thickness of the n-type work function metal layer 755 may depend on the spacing between the nanostructure channels 315a (e.g., openings 705). For example, the thickness of the n-type work function metal layer 755 may be sufficient to completely fill the openings 705 between and around the nanostructure channels 315a. In other words, the n-type work function metal layer 755 has sufficient thickness to merge between vertically adjacent nanostructure channels 315a. The n-type work function metal layer 755 can completely merge between vertically adjacent nanostructure channels 315a.

[0082] As illustrated in Figure 7H, a gate electrode layer 760 is formed for both the n-type gate structure 710a and the p-type gate structure 710b. In some embodiments, the same gate electrode layer 760 is formed for both the n-type gate structure 710a and the p-type gate structure 710b. In some embodiments, an independent and electrically isolated gate electrode layer 760 is formed for each of the n-type gate structure 710a and the p-type gate structure 710b. The gate electrode layer 760 may be formed on the n-type work function metal layer 755 above the nanostructure channel 315a of the n-type gate structure 710a, and on the n-type work function metal layer 755 above the nanostructure channel 315b of the p-type gate structure 710b.

[0083] The gate electrode layer 760 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), and other examples. In some embodiments, the gate electrode layer 760 comprises a conductive material, such as molybdenum nitride (MoN), tungsten nitride (WxNy), titanium nitride (TiN), aluminum titanium nitride (TiAlN), and / or another metal, metal nitride, and / or metal carbide. Deposition tools can be used to deposit the gate electrode layer 760 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The gate electrode layer 760 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the gate electrode layer 760 is deposited on the seed layer. In some embodiments, after depositing the gate electrode layer 760, a planarization tool can be used to planarize the gate electrode layer 760.

[0084] As illustrated in Figure 7I, semiconductor device 105 may include an interconnect layer 765 arranged in the Z-direction relative to n-gate structures 710a and p-gate structures 710b. For example, interconnect layer 765 may be located above n-gate structures 710a and p-gate structures 710b. Interconnect layer 765 may include conductive structures arranged to carry signals and / or provide power distribution throughout semiconductor device 105. Interconnect layer 765 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction (e.g., direction Z) substantially perpendicular to the top surface of semiconductor substrate 110. The dielectric layers may include an ILD layer 770 and an etch-stop layer (ESL) 775 arranged alternately in the Z-direction. ILD layer 770 and etch-stop layer 775 may extend in the X-direction and / or the Y-direction within semiconductor device 105.

[0085] ILD layers 770 may each comprise a low-dielectric-constant (low-k) oxide material, such as silica (SiOx) or undoped silicate glass (USG). Additionally and / or alternatively, ILD layers 770 may each comprise boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TES), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, ILD layers 770 comprise an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than approximately 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutene-based (BCB), polytetrafluoroethylene (PTFE), silicon oxide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx), as well as other examples.

[0086] The etch stop layers 775 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the ILD layer 770 and the etch stop layers 775 comprise different dielectric materials to provide etch selectivity, allowing various structures to be formed in the interconnect layer 765. For example, the ILD layer 770 may each comprise a low-dielectric-constant dielectric material, such as undoped silicon glass, and the etch stop layers 775 may each comprise a high-dielectric-constant dielectric material, such as silicon nitride (SixNy) or silicon carbide (SiC). Additionally and / or alternatively, two or more etch stop layers 775 may comprise different materials. For example, one or more first etch stop layers 775 may comprise silicon nitride (SixNy), and one or more second etch stop layers 775 may comprise silicon carbide (SiC).

[0087] Interconnect layer 765 includes a plurality of conductive structures arranged in the plurality of layers. The conductive structures may be electrically coupled and / or physically coupled to one or more of the gate electrode layers 760. The conductive structures provide electrical wiring that enables signals and / or power to be provided to, and / or from, the n-type gate structure 710a and the p-type gate structure 710b.

[0088] The conductive structure may include a plurality of metallization layers, each including a metallization structure 780, and a plurality of via layers, each including an interconnect structure 785.

[0089] The layer of the metallization structure 780 may be referred to as the M layer. The layer of the interconnect structure 785 may be referred to as the V layer. The metallization structure 780 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. The interconnect structure 785 may include vias, interconnects, and / or combinations of other types of conductive structures. The metallization structure 780 and the interconnect structure 785 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some embodiments, one or more pad layers are included between the dielectric layer of the interconnect layer 765 and the metallization structure 780, and / or between the dielectric layer of the interconnect layer 765 and the interconnect structure (metallization structure 780). The one or more pad layers may include barrier layer pads, adhesive pads, and / or another type of pad. Examples of materials used for one or more gaskets include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as other examples.

[0090] In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 780, the top layer of the interconnect structure 785) may be coupled to a connection structure at the top of the semiconductor device 105. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures. In some embodiments, the top layer of the conductive structure (e.g., the top layer of the metallization structure 780, the top layer of the interconnect structure 785) may be coupled to a bonding structure, such as bonding pads and / or bonding vias.

[0091] As indicated above, Figures 7A through 7I are provided as examples. Other examples may differ from those described with respect to Figures 7A through 7I.

[0092] Figures 8A through 8E are schematic diagrams of an exemplary implementation 800 of a replacement gate (RPG) process described in some embodiments of this disclosure. Exemplary implementation 800 includes an example of a replacement gate process for replacing a dummy gate structure 205 with a high-dielectric-constant / metal gate structure (e.g., a replacement gate structure) of a nanostructured transistor in a semiconductor device 105. Figures 8A through 8E are each drawn from a perspective view of cross section CC in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 800 are performed after the operations described in conjunction with Figures 1A through 6.

[0093] As illustrated in Figure 8A, the semiconductor device 105 in Exemplary Embodiment 800 includes an n-type gate structure 805a and a p-type gate structure 805b, which are similar to the n-type gate structure 710a and p-type gate structure 710b described in Exemplary Embodiment 700. The operations performed to produce a portion of the structure illustrated in Figure 8A are the same as or similar to the operations described in conjunction with Figures 7A to 7C of some embodiments of this disclosure. For example, the gate dielectric layer 810, interface layer 815, circular portion 820 representing fluorine atoms, and capping layer 825 are the same as or similar to the gate dielectric layer 715, interface layer 725, circular portion 725, and capping layer 730 of Exemplary Embodiment 700 described in conjunction with Figures 7A to 7C.

[0094] More specifically, an n-type gate structure 805a is formed in and around the nanostructure channels 315a of the NMOS nanostructure transistor in the semiconductor device 105. The n-type gate structure 805a occupies the area previously occupied by the sacrificial nanostructure layer 120, such that the n-type gate structure 805a encloses the nanostructure channel 315a and surrounds the nanostructure channel 315a on at least three sides. In some embodiments, the n-type gate structure 805a completely encloses the nanostructure channel 315a and surrounds the nanostructure channel 315a on all four sides.

[0095] A p-type gate structure 805b is formed in and around the nanostructure channels 315b of the PMOS nanostructure transistor in the semiconductor device 105. The p-type gate structure 805b occupies the area previously occupied by the sacrificial nanostructure layer 120, such that the p-type gate structure 805b encloses the nanostructure channel 315b and surrounds the nanostructure channel 315b on at least three sides. In some embodiments, the p-type gate structure 805b completely encloses the nanostructure channel 315b and surrounds the nanostructure channel 315b on all four sides.

[0096] Similar to gate dielectric layer 715, gate dielectric layer 810 is formed around nanostructure channels 315a and 315b, and on mesa regions 310a and 310b. In some embodiments, the gate dielectric layer 810 is a high-dielectric-constant gate dielectric layer, comprising one or more high-dielectric-constant materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2 – dielectric constant approximately 3.9)). Similar to interface layer 720, interface layer 815 may be formed around nanostructure channels 315a and 315b and on mesa regions 310a and 310b, such that interface layer 815 is disposed between gate dielectric layer 810 and nanostructure channels 315a and 315b, and between gate dielectric layer 810 and mesa regions 310a and 310b. Gate dielectric layer 810 may be formed around interface layer 815 around nanostructure channels 315a and 315b.

[0097] Similar to circular portion 725, circular portion 820 represents fluorine atoms of fluorine added to gate dielectric layer 810 and / or interface layer 815. Similar to capping layer 730 in Figure 7C, capping layer 825 is formed on gate dielectric layer 810 such that capping layer 825 encapsulates nanostructure channels 315a and 315b. Capping layer 825 is also formed on mesa regions 310a and 310b.

[0098] The material of the capping layer 825 completely fills the openings (e.g., spaces) between and around the nanostructure channels 315a and 315b. In some embodiments, the material of the capping layer 825 may be a metal, such as titanium (Ti), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), hafnium (Hf), lanthanum (La), and cobalt (Co), as well as other metals, oxides, nitrides, and / or carbides of one or more metals. For example, the material of the capping layer 825 may be aluminum nitride (AlxNy), titanium nitride (TixNy), tungsten nitride (WxNy), molybdenum nitride (MoxNy), aluminum oxide (AlxOy), titanium oxide (TixOy), tungsten oxide (WxOy), molybdenum oxide (MoxOy), aluminum carbide (AlxCy), and / or titanium carbide (TixCy). In some cases, when the capping layer 825 is formed of an insulating material (e.g., aluminum oxide (AlxOy), titanium oxide (TixOy), tungsten oxide (WxOy), molybdenum oxide (MoxOy), aluminum nitride (AlxNy)), the capping layer 825 can provide insulation functionality in addition to the gate dielectric layer 810 and the interface layer 815. In some cases, when the capping layer 825 is formed of a conductive material (e.g., titanium nitride (TixNy), tungsten nitride (WxNy), molybdenum nitride (MoxNy), aluminum carbide (AlxCy), titanium carbide (TixCy)), the capping layer 825 can provide work function tuning for the n-type gate structure 805a and the p-type gate structure 805b.

[0099] Deposition tools can be used to deposit capping layer 825 using PVD, ALD, CVD, oxidation, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. In some embodiments, the thickness of capping layer 825 may range from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein. The thickness of capping layer 825 may depend on the spacing (e.g., openings) between nanostructure channels 315a and 315b. For example, the thickness of capping layer 825 may be sufficient to completely fill the openings between and around nanostructure channels 315a and 315b. In other words, capping layer 825 has sufficient thickness to merge between vertically adjacent nanostructure channels 315a and between vertically adjacent nanostructure channels 315b. Capping layer 825 may completely merge between vertically adjacent nanostructure channels 315a and between vertically adjacent nanostructure channels 315b.

[0100] As further illustrated in Figure 8A, a p-type work function metal layer 830 is formed on the capping layer 825, wherein an n-type gate structure 805a will be formed (e.g., on the NMOS side) and a p-type gate structure 805b will be formed (e.g., on the PMOS side). On the NMOS and PMOS sides, the p-type work function metal layer 830 is conformally deposited around each of the nanostructure channels 315a and 315b and around the exposed surfaces of the capping layer 825 around the mesa regions 310a and 310b.

[0101] Since the p-gate structure 805b is a metallic gate structure, a p-type work function metal layer 830 may be included in the p-gate structure 805b for work function tuning. The p-type work function metal layer 830 may include one or more p-type metals, such as tungsten (W), titanium (Ti), cobalt (Co), molybdenum (Mo), ruthenium (Ru), tungsten nitride (WxNy), titanium nitride (TixNy), tantalum nitride (TaxNy), molybdenum nitride (MoxNy), and / or another metal, metal oxide, metal nitride, and / or metal carbide having a work function greater than approximately 4.7 eV, and other examples. The p-type work function metal layer 830 may be included to tune the work function of the PMOS nanostructure transistor, such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 315b. This enables the PMOS nanostructure transistor to achieve a relatively low threshold voltage, while also enabling the PMOS nanostructure transistor to achieve relatively low current leakage.

[0102] Deposition tools can be used to deposit a p-type work function metal layer 830 using PVD, ALD, CVD, oxidation, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. The p-type work function metal layer 830 can be deposited in one or more deposition operations. In some embodiments, the p-type work function metal layer 745 is formed to a thickness ranging from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein.

[0103] As illustrated in Figure 8B, the p-type work function metal layer 830 is removed from the first portion of the capping layer 825, which lies on the nanostructure channel 315a and the mesa region 310a. If the p-type work function metal layer 830 remains around the nanostructure channel 315a and the mesa region 310a, it may further cause the work function of the n-type gate structure 805a to be too far removed from the conductive band of the material in the nanostructure channel 315a.

[0104] A masking layer 835 may be formed on the nanostructure channel 315b and the mesa region 310b. During the process of removing a first portion of the p-type work function metal layer 830 from a first portion of the capping layer 825, the masking layer 835 may be used to cover a second portion of the p-type work function metal layer 830 on the nanostructure channel 315b and the mesa region 310a. A deposition tool may be used to deposit the masking layer 835 on the nanostructure channels 315a and 315b and the mesa regions 310a and 310b. The masking layer 835 may then be patterned by removing a portion of the masking layer 835 from the nanostructure channel 315a and from the mesa region 310a. An etching tool may be used to etch the masking layer 835 to pattern the masking layer 750.

[0105] During the process of removing a first portion of the p-type work function metal layer 830 from a first portion of the capping layer 825, the masking layer 835 prevents a second portion of the p-type work function metal layer 830 from being removed. Therefore, the second portion of the p-type work function metal layer 830 remains on the nanostructure channel 315b and the mesa region 310b. An etching tool can be used to remove the first portion of the p-type work function metal layer 830 from the first portion of the capping layer 825 (which is on the nanostructure channel 315a and the mesa region 310a) while the masking layer 835 protects the second portion of the p-type work function metal layer 830.

[0106] In some embodiments, wet etching techniques are used to remove a first portion of the p-type work function metal layer 830 from a first portion of the capping layer 825, which lies on the nanostructure channel 315a and the mesa region 310a. For example, solutions (such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), a mixture of ammonia (NH3) and hydrogen peroxide (H2O2) (APM), and / or a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2) and water (HPM)) can be used to etch the first portion of the p-type work function metal layer 830.

[0107] As illustrated in Figure 8B, the first and second portions of the capping layer 825 remain on the nanostructure channels 315a and 315b, and on the mesa regions 310a and 310b. During the removal of the work function metal layer, the first and second portions of the capping layer 825 protect the underlying gate dielectric layer 810. For example, during an etching operation that removes the first portion of the p-type work function metal layer 830 from the NMOS side, the first portion of the capping layer 825 acts as a buffer layer to prevent the removal of portions of the gate dielectric layer 810 formed around the nanostructure channel 315a and on the mesa region 310a. Therefore, the gate dielectric layer 810 and the underlying interface layer 815 on the NMOS side remain intact, with almost no reduction in fluorine concentration. This is schematically illustrated in Figures 8A and 8B by circular portions 820, which represent the same number of fluorine atoms before and after the removal of the first portion of the p-type work function metal layer 830. Therefore, the fluorine concentration on the NMOS and PMOS sides, as well as in the resulting GAA PFET and NFET, is the same or approximately the same, allowing for balanced device performance and reliability (e.g., the same or similar BTI and TDDB values) between adjacent PFETs and NFETs. Similar to exemplary embodiment 700, the ratio of fluorine concentration in the gate dielectric layer 810 and / or interface layer 815 on the NMOS side to the fluorine concentration in the gate dielectric layer 810 and / or interface layer 815 on the PMOS side is in the range of approximately 0.7:1 to approximately 1.4:1. However, other values ​​within this range are within the scope of some embodiments disclosed herein. In some embodiments, the fluorine concentration in the gate dielectric layer 810 and / or interface layer 815 on the NMOS and PMOS sides may be in the range of approximately 2 atoms / nm² to approximately 50 atoms / nm². However, other values ​​within this range are within the scope of some embodiments disclosed herein.

[0108] As illustrated in Figure 8C, an n-type work function metal layer 840 is formed on a first portion of the capping layer 825 of the n-type gate structure 805a (e.g., on the NMOS side) and on a p-type work function metal layer 830 of the p-type gate structure 805b (e.g., on the PMOS side). After removing the first portion of the p-type work function metal layer 830 from the first portion of the capping layer 825 (which is formed around the nanostructure channel 315a and the mesa region 310a), the n-type work function metal layer 840 can be formed on the first portion of the capping layer 825 and the second portion of the p-type work function metal layer 830. On the NMOS side, the n-type work function metal layer 840 is conformally deposited on the exposed surface of the first portion of the capping layer 825 around each of the nanostructure channels 315a and around the mesa region 310a. On the PMOS side, an n-type work function metal layer 840 is conformally deposited around each of the nanostructure channels 315b and around the exposed surface of the second portion of the p-type work function metal layer 830 around the mesa region 310b.

[0109] The n-type work function metal layer 840 may include one or more metallic materials, which tune or adjust the work function of the n-type gate structure 805a to be close to the conduction band of the material of the nanostructure channel 315a. In some embodiments, the n-type work function metal layer 840 includes tantalum (Ta), aluminum (Al), tantalum-containing metals, aluminum-containing metals, and / or another metal, metal oxide, metal nitride, and / or metal carbide.

[0110] Deposition tools can be used to deposit an n-type work function metal layer 840 using CVD, PVD, ALD, electroplating, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. The n-type work function metal layer 840 can be deposited in one or more deposition operations. In some embodiments, the n-type work function metal layer 840 is formed to a thickness ranging from approximately 5 angstroms to approximately 80 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein.

[0111] As illustrated in Figure 8D, a gate electrode layer 845 is formed for both the n-type gate structure 805a and the p-type gate structure 805b. In some embodiments, the same gate electrode layer 845 is formed for both the n-type gate structure 805a and the p-type gate structure 805b. In some embodiments, an independent and electrically isolated gate electrode layer 845 is formed for each of the n-type gate structure 805a and the p-type gate structure 805b. The gate electrode layer 845 may be formed on the n-type work function metal layer 840 above the nanostructure channel 315a of the n-type gate structure 805a, and on the n-type work function metal layer 840 above the nanostructure channel 315b of the p-type gate structure 805b.

[0112] The gate electrode layer 845 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), and other examples. In some embodiments, the gate electrode layer 845 comprises a conductive material, such as molybdenum nitride (MoN), tungsten nitride (WxNy), titanium nitride (TiN), titanium aluminum nitride (TiAlN), and / or another metal, metal nitride, and / or metal carbide. Deposition tools can be used to deposit the gate electrode layer 845 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The gate electrode layer 845 may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the gate electrode layer 845 is deposited on the seed layer. In some embodiments, after depositing the gate electrode layer 845, a planarization tool can be used to planarize the gate electrode layer 845.

[0113] As illustrated in Figure 8E, the semiconductor device 105 may include an interconnect layer 850 arranged in the Z-direction relative to an n-type gate structure 805a and a p-type gate structure 805b. For example, the interconnect layer 850 may be located above the n-type gate structure 805a and the p-type gate structure 805b. The interconnect layer 850 may include conductive structures arranged to carry signals and / or provide power distribution throughout the semiconductor device 105. The interconnect layer 850 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction (e.g., direction Z) substantially perpendicular to the top surface of the semiconductor substrate 110. The dielectric layers may include an ILD layer 855 and an etch stop layer 860 arranged alternately in the Z-direction. The ILD layer 855 and the etch stop layer 860 may extend in the X-direction and / or the Y-direction within the semiconductor device 105.

[0114] ILD layers 855 may each comprise a low dielectric constant (low k) oxide material, such as silica (SiOx) or undoped silicate glass (USG). Additionally and / or alternatively, ILD layers 855 may each comprise borosilicate glass (BSG), fluorosilicone glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, ILD layers 855 comprise an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than approximately 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), poly(p-xylene), bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxide (SiOC) polymers, porous HSQ, porous methylsilsesquioxane (MSQ), porous polyarylene ether (PAE) and / or porous silicon oxide (SiOx), and other examples.

[0115] The etch stop layers 860 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the ILD layer 855 and the etch stop layers 860 comprise different dielectric materials to provide etch selectivity, allowing various structures to be formed in the interconnect layer 850. For example, the ILD layer 855 may each comprise a low-dielectric-constant dielectric material, such as undoped silicon glass, and the etch stop layers 860 may each comprise a high-dielectric-constant dielectric material, such as silicon nitride (SixNy) or silicon carbide (SiC). Additionally and / or alternatively, two or more etch stop layers 860 may comprise different materials. For example, one or more first etch stop layers 860 may comprise silicon nitride (SixNy), and one or more second etch stop layers 860 may comprise silicon carbide (SiC).

[0116] Interconnect layer 850 includes a plurality of conductive structures arranged in the plurality of layers. The conductive structures may be electrically coupled and / or physically coupled to one or more of the gate electrode layers 845. The conductive structures provide electrical wiring that enables signals and / or power to be provided to, and / or from, n-type gate structures 805a and p-type gate structures 805b.

[0117] The conductive structure may include a plurality of metallization layers, each including a metallization structure 865, and a plurality of via layers, each including an interconnect structure 870.

[0118] The layer of the metallization structure 865 may be referred to as the M layer. The layer of the interconnect structure 870 may be referred to as the V layer. The metallization structure 865 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. The interconnect structure 870 may include vias, interconnects, and / or combinations of other types of conductive structures. The metallization structure 865 and the interconnect structure 870 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some embodiments, one or more pad layers are included between the dielectric layer of the interconnect layer 850 and the metallization structure 865, and / or between the dielectric layer of the interconnect layer 850 and the interconnect structure (metallization structure 865). The one or more pad layers may include barrier layer pads, adhesive pads, and / or another type of pad. Examples of materials used for one or more gaskets include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as other examples.

[0119] In some embodiments, the top layer of the conductive structure (e.g., the top layer of metallization structure 865, the top layer of interconnect structure 870) may be coupled to a connection structure at the top of semiconductor device 105. The connection structure may include solder balls, solder bumps, contact pads (e.g., planar grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapsed wafer connection (C4) bumps, and / or other types of connection structures. In some embodiments, the top layer of the conductive structure (e.g., the top layer of metallization structure 865, the top layer of interconnect structure 870) may be coupled to a bonding structure, such as bonding pads and / or bonding vias.

[0120] As indicated above, Figures 8A through 8E are provided as examples. Other examples may differ from those described with respect to Figures 8A through 8E.

[0121] Figure 9 is a schematic diagram of an exemplary process 900 for incorporating fluorine into a gate dielectric layer. More specifically, as illustrated in Figure 9, an interface layer 910 (which is the same as or similar to interface layers 720 and / or 815) may be formed on a semiconductor layer 905. The semiconductor layer 905 may be a nanostructure channel (e.g., nanostructure channels 315a, 315b) and / or a mesa region (e.g., mesa regions 310a, 310b). A gate dielectric layer 915 (which is the same as or similar to gate dielectric layers 715 and / or 820) may be formed on the interface layer 910. The fluorine incorporation process may include depositing a pad layer 920 on the gate dielectric layer 915, depositing a fluorine-containing source layer 925 on the pad layer 920, an annealing operation, and subsequently removing the fluorine-containing source layer 925 and the pad layer 920 from the gate dielectric layer 915. The fluorine atom is represented by the circular portion 930.

[0122] In some embodiments, the backing layer 920 comprises metals such as titanium (Ti), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), hafnium (Hf), lanthanum (La), and cobalt (Co), as well as oxides, nitrides, and / or carbides of one or more metals. For example, the material of the backing layer 920 may include alumina (AlxOy), titanium oxide (TixOy), tungsten oxide (WxOy), molybdenum oxide (MoxOy), aluminum nitride (AlxNy), titanium nitride (TixNy), tungsten nitride (WxNy), and / or molybdenum nitride (MoxNy). Deposition tools may be used to deposit the backing layer 920 using CVD, PVD, ALD, electroplating, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. In some embodiments, the backing layer 920 is formed to a thickness ranging from approximately 5 angstroms to approximately 50 angstroms. However, other values ​​in this range fall within the scope of some embodiments disclosed herein.

[0123] In some embodiments, the fluorine-containing source layer 925 comprises tungsten oxyfluoride (WxFyOz), tungsten fluoride nitride (WxFyNz), tungsten fluorocarbonide (WxFyCz), silicon fluorocarbonide (SiOxCyFz), tantalum carbonitride (TaFxCyNz), and / or other fluorine-containing metals, oxides, nitrides, and / or carbides of one or more metals containing fluorine. Deposition tools can be used to deposit the fluorine-containing source layer 925 using CVD, PVD, ALD, electroplating, thermal vapor deposition, pulsed vapor deposition, sputtering, electron gun deposition, and / or another suitable deposition technique. In some embodiments, the fluorine-containing source layer 925 is formed to a thickness ranging from approximately 5 angstroms to approximately 50 angstroms. However, other values ​​within this range are within the scope of some embodiments disclosed herein.

[0124] The annealing operation may be a drive-in annealing operation performed on the fluorine-containing source layer 925, the pad layer 920, the gate dielectric layer 915, and the interface layer 910 to drive fluorine from the fluorine-containing source layer 925 into the gate dielectric layer 915 and / or the interface layer 910. In some embodiments, the annealing operation is performed at a temperature ranging from about 100 degrees Celsius to about 2000 degrees Celsius. However, other values ​​in this range are within the scope of some embodiments disclosed herein. An etching tool may be used in one or more wet etching operations to remove the fluorine-containing source layer 925 and the pad layer 920 from the gate dielectric layer 915.

[0125] In some embodiments, for fluorine incorporation processes, the fluorine dosage ratio between n-type gate structures 710a, 805a and p-type gate structures 710b, 805b may be in the range of approximately 0.7:1 to approximately 1.4:1. However, other values ​​within this range are within the scope of some embodiments disclosed herein. The fluorine dosage added to the n-type gate structures 710a, 805a and the p-type gate structures 710b, 805b can be measured using energy dispersive x-ray spectroscopy (EDS) and / or electron energy loss spectroscopy (EELS) at the innermost nanostructure channels 315a, 315b.

[0126] As indicated above, Figure 9 is provided as an example. Other examples may differ from those described with respect to Figure 9.

[0127] Figure 10A illustrates an exemplary embodiment 1000, including a graph showing the fluorine distribution in an n-type transistor structure as described in some embodiments of the present disclosure. Figure 10B illustrates an exemplary embodiment 1010, including a graph showing the fluorine distribution in a p-type transistor structure as described in some embodiments of the present disclosure. In the graphs of exemplary embodiments 1000 and 1010, the vertical axis 1002 represents the concentration of fluorine through different layers of the n-type and p-type transistor structures, and the horizontal axis 1004 represents the depth of different layers. The concentration values ​​increase upwards along the vertical axis 1002, and the depth increases to the right along the horizontal axis 1004.

[0128] In the exemplary embodiment 1000 illustrated in Figure 10A, curve 1006 represents the fluorine distribution in different layers of the n-type transistor structure (e.g., GAA NFET) of the semiconductor device 105. For example, in exemplary embodiment 1000, the vertical axis 1002 represents the fluorine concentration in the nanostructure channel 315a, interface layer 720, gate dielectric layer 715, and n-type work function metal layer 755 of the n-type transistor structure of exemplary embodiment 700. As illustrated in Figure 10A, the peak fluorine concentration 1008 is located between the interface layer 720 and the central portion of the gate dielectric layer 715. However, in other embodiments, the peak fluorine concentration 1008 may be located at another location, such as at or near the interface between the interface layer 720 and the gate dielectric layer 715, in the interface layer 720, or in the gate dielectric layer 715 near the interface between the gate dielectric layer 715 and the n-type work function metal layer 755.

[0129] In the exemplary embodiment 1010 illustrated in Figure 10B, curve 1012 represents the fluorine distribution in different layers of the p-type transistor structure (e.g., GAA PFET) of the semiconductor device 105. For example, in exemplary embodiment 1010, the vertical axis 1002 represents the fluorine concentration in the nanostructure channel 315b, interface layer 720, gate dielectric layer 715, p-type work function metal layer 745, and n-type work function metal layer 755 of the p-type transistor structure of exemplary embodiment 700. As illustrated in Figure 10B, the peak fluorine concentration 1014 is located between the central portion of the interface layer 720 and the gate dielectric layer 715. However, in other embodiments, the peak fluorine concentration 1014 may be located at another location, such as at or near the interface between the interface layer 720 and the gate dielectric layer 715, in the interface layer 720, or in the gate dielectric layer 715 near the interface between the gate dielectric layer 715 and the p-type and n-type work function metal layers 745 / 755.

[0130] As can be seen from the comparison of curves 1006 and 1012, within a certain depth range, the ratio of fluorine concentration in the gate dielectric layer 715 and interface layer 720 of the n-type transistor to the fluorine concentration in the gate dielectric layer 715 and interface layer 720 of the p-type transistor structure is approximately 1:1. For example, as described in some embodiments of this disclosure, the ratio of fluorine concentration in the gate dielectric layer 715 and interface layer 720 of the n-type transistor structure to the fluorine concentration in the gate dielectric layer 715 and interface layer 720 of the p-type transistor structure may include a range of approximately 0.7:1 to approximately 1.4:1. In exemplary embodiments 1000 and 1010, the ratio of peak fluorine concentration 1008 to peak fluorine concentration 1014 may include a range of approximately 0.7:1 to approximately 1.4:1.

[0131] As indicated above, Figures 10A and 10B are provided as examples. Other examples may differ from those described with respect to Figures 10A and 10B.

[0132] Figure 11 is a flowchart of an exemplary process 1100 associated with a method of forming a semiconductor device. In some embodiments, one or more process steps of Figure 11 are performed using one or more semiconductor processing tools (such as deposition tools, exposure tools, developer tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or another type of semiconductor processing tool).

[0133] As illustrated in Figure 11, process 1100 may include forming a plurality of first nanostructure channel layers arranged in a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (step 1110). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a plurality of first nanostructure channel layers (e.g., nanostructure channel 315a) arranged in a direction (e.g., direction Z) substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0134] As further illustrated in Figure 11, process 1100 may include forming a plurality of second nanostructure channel layers arranged in a direction generally perpendicular to the semiconductor substrate (step 1120). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a plurality of second nanostructure channel layers (e.g., nanostructure channel 315b) arranged in a direction generally perpendicular to the semiconductor substrate.

[0135] As further illustrated in Figure 11, process 1100 may include forming a gate dielectric layer around each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers (step 1130). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 715) around each of the plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers.

[0136] As further illustrated in Figure 11, process 1100 may include forming a capping layer around each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers (step 1140). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a capping layer (e.g., capping layer 730) around each of the plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers. In some embodiments, the capping layer is formed on a gate dielectric layer.

[0137] As further illustrated in Figure 11, process 1100 may include removing a capping layer around each of the plurality of second nanostructure channel layers (step 1150). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to remove the capping layer around each of the plurality of second nanostructure channel layers.

[0138] As further illustrated in Figure 11, process 1100 may include forming a first work function metal layer on a capping layer around each of the plurality of second nanostructure channel layers and around each of the plurality of first nanostructure channel layers (step 1160). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a first work function metal layer (e.g., p-type work function metal layer 745) on a capping layer around each of the plurality of second nanostructure channel layers and around each of the plurality of first nanostructure channel layers.

[0139] As further illustrated in Figure 11, process 1100 may include removing a first work function metal layer and a capping layer around each of the plurality of first nanostructure channel layers (step 1170). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to remove the first work function metal layer and capping layer around each of the plurality of first nanostructure channel layers.

[0140] As further illustrated in Figure 11, process 1100 may include forming a second work function metal layer around each of the plurality of first nanostructure channel layers and around each of the plurality of first nanostructure channel layers (step 1180). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a second work function metal layer (e.g., an n-type work function metal layer 755) around each of the plurality of first nanostructure channel layers and around each of the plurality of first nanostructure channel layers.

[0141] Process 1100 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described elsewhere in conjunction with some embodiments disclosed herein.

[0142] In a first embodiment, a plurality of first nanostructure channel layers are spaced apart from each other in a direction generally perpendicular to the semiconductor substrate, wherein a plurality of second nanostructure channel layers are spaced apart from each other in a direction generally perpendicular to the semiconductor substrate, and wherein a capping layer fills a first space (e.g., opening 705) between the plurality of first nanostructure channel layers and a second space (e.g., opening 705) between the plurality of second nanostructure channel layers.

[0143] In the second embodiment, alone or in combination with the first embodiment, the covering layer includes at least one of a metal, a metal oxide, a metal nitride, or a metal carbide.

[0144] In the third embodiment, or in combination with one or more of the first and second embodiments, process 1100 includes adding fluorine to the gate dielectric layer before forming the capping layer.

[0145] In the fourth embodiment, adding fluorine to the gate dielectric layer, either alone or in combination with one or more of the first to third embodiments, includes depositing a pad layer (e.g., pad layer 920) on the gate dielectric layer (e.g., gate dielectric layer 915), depositing a fluorine source layer (e.g., fluorine-containing source layer 925) on the pad layer, performing an annealing operation on the gate dielectric layer, the pad layer and the fluorine source layer, and removing the pad layer and the fluorine source layer from the gate dielectric layer.

[0146] In the fifth embodiment, the fluorine source layer includes tungsten, either alone or in combination with one or more of the first to fourth embodiments.

[0147] In the sixth embodiment, the liner layer, alone or in combination with one or more of the first to fifth embodiments, includes at least one of a metal, a metal oxide, a metal nitride, or a metal carbide.

[0148] In the seventh embodiment, adding fluorine to the gate dielectric layer, either alone or in combination with one or more of the first to sixth embodiments, includes performing one of fluoride ion implantation, fluorine-containing gas plasma treatment, or fluorine-containing gas treatment.

[0149] In the eighth embodiment, or in combination with one or more of the first to seventh embodiments, process 1100 includes forming a mask layer (e.g., mask layer 735) on the plurality of first nanostructure channel layers before removing the capping layer from the plurality of second nanostructure channel layers.

[0150] In the ninth embodiment, or in combination with one or more of the first to eighth embodiments, process 1100 includes forming a mask layer (e.g., mask layer 750) over the plurality of second nanostructure channel layers before removing the first work function metal layer and the capping layer around each of the plurality of first nanostructure channel layers.

[0151] In the tenth embodiment, a first etching operation is performed alone or in combination with one or more of the first to ninth embodiments to remove a capping layer around each of the plurality of second nanostructure channel layers, wherein a second etching operation is performed to remove a capping layer around each of the plurality of first nanostructure channel layers, and wherein the first etching operation and the second etching operation are performed using at least one of a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), a mixture of ammonia (NH3) and hydrogen peroxide (H2O2) (APM), and / or hydrochloric acid (HCl), a mixture of hydrogen peroxide (H2O2) and water (HPM).

[0152] While Figure 11 illustrates exemplary steps of process 1100, in some embodiments, process 1100 includes additional steps, fewer steps, different steps, or steps arranged differently compared to those depicted in Figure 11. Additionally, or alternatively, two or more steps of process 1100 may be performed in parallel.

[0153] Figure 12 is a flowchart of an exemplary process 1200 associated with a method of forming a semiconductor device. In some embodiments, one or more process steps of Figure 12 are performed using one or more semiconductor processing tools (such as deposition tools, exposure tools, developer tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or another type of semiconductor processing tool).

[0154] As illustrated in Figure 12, process 1200 may include forming a plurality of first nanostructure channel layers arranged in a direction substantially perpendicular to the semiconductor substrate of the semiconductor device (step 1210). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a plurality of first nanostructure channel layers (e.g., nanostructure channel 315a) arranged in a direction (e.g., direction Z) substantially perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0155] As further illustrated in Figure 12, process 1200 may include forming a plurality of second nanostructure channel layers arranged in a direction generally perpendicular to the semiconductor substrate (step 1220). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a plurality of second nanostructure channel layers (e.g., nanostructure channel 315b) arranged in a direction generally perpendicular to the semiconductor substrate.

[0156] As further illustrated in Figure 12, process 1200 may include forming a gate dielectric layer around each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers (step 1230). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 810) around each of the plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers.

[0157] As further illustrated in Figure 12, process 1200 may include forming a capping layer around each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers (step 1240). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a capping layer (e.g., capping layer 825) around each of the plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers. In some embodiments, the capping layer is formed on a gate dielectric layer.

[0158] As further illustrated in Figure 12, process 1200 may include forming a first work function metal layer on a capping layer surrounding each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers (step 1250). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a first work function metal layer (e.g., p-type work function metal layer 830) on a capping layer surrounding each of a plurality of first nanostructure channel layers and a plurality of second nanostructure channel layers.

[0159] As further illustrated in Figure 12, process 1200 may include removing a first work function metal layer from the capping layer around each of the plurality of first nanostructure channel layers (step 1260). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to remove the first work function metal layer from the capping layer around each of the plurality of first nanostructure channel layers.

[0160] As further illustrated in Figure 12, process 1200 may include forming a second work function metal layer on a capping layer surrounding each of a plurality of first nanostructure channel layers and on a first work function metal layer surrounding each of a plurality of second nanostructure channel layers (step 1270). For example, as described in some embodiments of this disclosure, one or more semiconductor processing tools may be used to form a second work function metal layer (e.g., an n-type work function metal layer 840) on a capping layer surrounding each of a plurality of first nanostructure channel layers and on a first work function metal layer surrounding each of a plurality of second nanostructure channel layers.

[0161] Process 1200 may include additional implementations, such as any single implementation or any combination of other process descriptions described elsewhere and / or in conjunction with some embodiments disclosed herein.

[0162] In the first embodiment, a first portion of the cover layer is alternately stacked with corresponding first nanostructure channel layers of a plurality of first nanostructure channel layers, and a second portion of the cover layer is alternately stacked with corresponding second nanostructure channel layers of a plurality of first nanostructure channel layers.

[0163] In the second embodiment, forming the first work function metal layer, alone or in combination with the first embodiment, includes conformally depositing the first work function metal layer on the exposed surface of the capping layer surrounding each of the plurality of first nanostructure channel layers and the plurality of second nanostructure channel layers.

[0164] In the third embodiment, the second work function metal layer is formed individually or in combination with one or more of the first and second embodiments, comprising conformally depositing the second work function metal layer on the exposed surface of the capping layer around each of the plurality of first nanostructure channel layers and on the exposed surface of the first work function metal layer around each of the plurality of second nanostructure channel layers.

[0165] In the fourth embodiment, process 1200 includes forming a gate electrode layer (e.g., gate electrode layer 845) on the second work function metal layer, either alone or in combination with one or more of the first to third embodiments.

[0166] While Figure 12 illustrates exemplary steps of process 1200, in some embodiments, process 1200 includes additional steps, fewer steps, different steps, or steps arranged differently compared to those depicted in Figure 12. Additionally, or alternatively, two or more steps of process 1200 may be performed in parallel.

[0167] In this way, the fluorine concentration in the gate dielectric layer between GAA PFETs and NFETs can be balanced by including a capping layer on and around the gate dielectric layer during the gate replacement process. In some cases, combined with WFM deposition and patterning, portions of the capping layer can be removed from the surface of the gate dielectric layer in each of the PFET and NFET regions. Removing the capping layer from each region ensures the removal of an equal or approximately equal portion of the underlying fluorine-containing gate dielectric layer in each region. Therefore, due to the equal or approximately equal reduction in fluorine concentration in both the PFET and NFET regions, a balanced fluorine concentration may be achieved in adjacent PFETs and NFETs. Alternatively, the capping layer can be retained in the PFET and NFET regions to protect the underlying gate dielectric layer. In this case, WFM layers can be deposited on the remaining capping layers, which act as buffer layers to prevent the removal of portions of the gate dielectric layer during WFM patterning. Thus, the gate dielectric layer in each region remains intact, and the fluorine concentration in the PFET and NFET regions is minimally reduced. The same or approximately the same fluorine concentration in GAA PFETs and NFETs may result in balanced device performance and reliability between adjacent PFETs and NFETs.

[0168] As described in more detail above, some embodiments of this disclosure provide a method for forming a semiconductor device. The method includes forming a plurality of first nanostructure channel layers, the first nanostructure channel layers being arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a plurality of second nanostructure channel layers, the second nanostructure channel layers being arranged in a direction substantially perpendicular to the semiconductor substrate. The method includes forming a gate dielectric layer around each of the first and second nanostructure channel layers. The method includes forming a capping layer around each of the first and second nanostructure channel layers, wherein the capping layer is formed on the gate dielectric layer. The method includes removing the capping layer from around each of the second nanostructure channel layers. The method includes forming a first work function metal layer around each of the second nanostructure channel layers and on the capping layer around each of the first nanostructure channel layers. The method includes removing the first work function metal layer and the capping layer from around each of the first nanostructure channel layers. The method includes forming a second work function metal layer around each of the first nanostructured channel layers and on a first work function metal layer around each of the first nanostructured channel layers. In some embodiments, the first nanostructured channel layers are spaced apart from each other in a direction generally perpendicular to the semiconductor substrate, the second nanostructured channel layers are spaced apart from each other in a direction generally perpendicular to the semiconductor substrate, and a capping layer fills a first space between the first nanostructured channel layers and a second space between the second nanostructured channel layers. In some embodiments, the capping layer comprises at least one of a metal, a metal oxide, a metal nitride, or a metal carbide. In some embodiments, the method further includes adding fluorine to a gate dielectric layer prior to forming the capping layer. In some embodiments, adding fluorine to the gate dielectric layer comprises the following steps: depositing a pad layer on the gate dielectric layer; depositing a fluorine source layer on the pad layer; performing an annealing operation on the gate dielectric layer, the pad layer, and the fluorine source layer; removing the pad layer and the fluorine source layer from the gate dielectric layer. In some embodiments, the fluorine source layer comprises tungsten. In some embodiments, the liner layer comprises at least one of a metal, a metal oxide, a metal nitride, or a metal carbide. In some embodiments, adding fluorine to the gate dielectric layer comprises performing one of fluoride ion implantation, fluorine-containing gas plasma treatment, or fluorine-containing gas treatment. In some embodiments, the method further comprises forming a masking layer on the first nanostructured channel layer before removing the capping layer from the second nanostructured channel layer. In some embodiments, the method further comprises forming a masking layer on the second nanostructured channel layer before removing the first work function metal layer and the capping layer around each of the first nanostructured channel layers.In some embodiments, a first etching operation is performed to remove a capping layer around each of the second nanostructure channel layers, and a second etching operation is performed to remove a capping layer around each of the first nanostructure channel layers. The first and second etching operations are performed using at least one of a mixture of sulfuric acid and hydrogen peroxide, a mixture of ammonia and hydrogen peroxide, or a mixture of hydrochloric acid, hydrogen peroxide, and water.

[0169] As described in more detail above, some embodiments of this disclosure provide a method for forming a semiconductor device. The method includes forming a plurality of first nanostructure channel layers, the first nanostructure channel layers being arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a plurality of second nanostructure channel layers, the second nanostructure channel layers being arranged in a direction substantially perpendicular to the semiconductor substrate. The method includes forming a gate dielectric layer around each of the first and second nanostructure channel layers. The method includes forming a capping layer around each of the first and second nanostructure channel layers, wherein the capping layer is formed on the gate dielectric layer. The method includes forming a first work function metal layer on the capping layer around each of the first and second nanostructure channel layers. The method includes removing the first work function metal layer from the capping layer around each of the first nanostructure channel layers. The method includes forming a second work function metal layer on the capping layer around each of the first nanostructure channel layers and on the first work function metal layer around each of the second nanostructure channel layers. In some embodiments, a first portion of the capping layer is alternately stacked with a corresponding first nanostructured channel layer of the first nanostructured channel layer, and a second portion of the capping layer is alternately stacked with a corresponding second nanostructured channel layer of the first nanostructured channel layer. In some embodiments, forming a first work function metal layer involves conformally depositing the first work function metal layer on the exposed surface of the capping layer surrounding each of the first and second nanostructured channel layers. In some embodiments, forming a second work function metal layer involves conformally depositing the second work function metal layer on the exposed surface of the capping layer surrounding each of the first nanostructured channel layers and on the exposed surface of the first work function metal layer surrounding each of the second nanostructured channel layers. In some embodiments, the method further includes forming a gate electrode layer on the second work function metal layer.

[0170] As described in more detail above, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a plurality of first nanostructure channel layers arranged in a first direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a plurality of first dielectric layers disposed around each of the first nanostructure channel layers. The semiconductor device includes a plurality of second nanostructure channel layers arranged in the first direction, wherein the second nanostructure channel layers are adjacent to the first nanostructure channel layers in a second direction substantially perpendicular to the first direction. The semiconductor device includes a plurality of second dielectric layers disposed around each of the plurality of second nanostructure channel layers. The semiconductor device includes a first structure disposed around the first nanostructure channel layers and the first dielectric layers, the first structure including a first portion of a capping layer and a first portion of a first type metal layer on the first portion of the capping layer. The semiconductor device includes a second structure disposed around the second nanostructure channel layers and the second dielectric layers, the second structure including a second portion of a capping layer, a second type metal layer on the second portion of the capping layer, and a second portion of a first type metal layer on the second type metal layer. In some embodiments, the first dielectric layer and the second dielectric layer each contain fluorine, and the ratio of the concentration of fluorine in the first dielectric layer to the concentration of fluorine in the second dielectric layer is in the range of about 0.7:1 to about 1.4:1. In some embodiments, a first portion of the capping layer is disposed around a plurality of sides of each of the first nanostructure channel layers, and a second portion of the capping layer is disposed around a plurality of sides of each of the second nanostructure channel layers. In some embodiments, a first type metal layer contacts the first portion of the capping layer, and a second type metal layer contacts the second portion of the capping layer.

[0171] The terms "approximately," "roughly," and "substantially" can indicate the value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, given some embodiments of this disclosure, the terms "approximately," "roughly," and "substantially" can represent a percentage of the value of a given quantity.

[0172] The foregoing outlines features of several embodiments, enabling those skilled in the art to better understand the nature of some embodiments disclosed herein. Those skilled in the art should understand that they can readily use some embodiments disclosed herein as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments disclosed herein, and that various changes, substitutions, and alterations can be made to some embodiments disclosed herein without departing from the spirit and scope of these embodiments.

[0173] 100: Exemplary Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Nanostructure Layer 125: Nanostructured Channel Layer 130: Hard mask layer 135: Covering layer 140: Oxide layer 145: Nitride layer 150: Fin structure 150a: Fin structure 150b: Fin structure 155: Part 160: Fin section 160a: Fin portion 160b: Fin section 165: Padding 170: STI region 200: Exemplary Implementation 205: Virtual gate structure 210: Gate electrode layer 215: Hard mask layer 220: Spacer layer 225: Gate dielectric layer 300: Exemplary Implementation 305: Source / Drain Groove 310: Countertop area 310a: Countertop area 310b: Countertop area 315: Nanostructured Channel 315a: Nanostructured Channel 315b: Nanostructured Channel 400: Exemplary Implementation 405: cavity 410: Internal spacers 500: Exemplary Implementation 505: Buffer Area 510: Source / Drain Region 515: Covering layer 600: Exemplary Implementation 605: Dielectric layer 700: Exemplary Implementation 705: Opening 710a:n-type gate structure 710b: P-type gate structure 715: Gate Dielectric Layer 720: Interface Layer 725: Circular section 730: Covering layer 735: Masking layer 740: Circular section 745: p-type work function metal layer 750: Mask layer 755: n-type work function metal layer 760: Gate electrode layer 765: Interconnect Layer 770: ILD layer 775: Etching Stop Layer 780: Metallized Structure 785: Interconnection Architecture 800: Exemplary Implementation 805a: n-type gate structure 805b: P-type gate structure 810: Gate dielectric layer 815: Interface Layer 820: Circular section 825: Covering layer 830: p-type work function metal layer 835: Masking layer 840: n-type work function metal layer 845: Gate electrode layer 850: Interconnect layer 855: ILD layer 860: Etching Stop Layer 865: Metallized Structure 870: Interconnection Structure 900: Exemplary process 905: Semiconductor layer 910: Interface Layer 915: Gate dielectric layer 920: Padding layer 925: Fluorine-containing source layer 930: Circular section 1000: Exemplary Implementation 1002: Straight axis 1004: Horizontal axis 1006: Curve 1008: Peak fluoride concentration 1010: Exemplary Implementation 1012: Curve 1014: Peak fluoride concentration 1100: Process 1110: Steps 1120: Steps 1130: Steps 1140: Steps 1150: Steps 1160: Steps 1170: Steps 1180: Steps 1200: Process 1210: Steps 1220: Steps 1230: Steps 1240: Steps 1250: Steps 1260: Steps 1270: Steps AA: Cross section BB: Cross-section CC: Cross section X: Direction Y: direction Z: Direction

[0174] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: forming a plurality of first nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; forming a plurality of second nanostructure channel layers arranged in the direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer around each of the first and second nanostructure channel layers; forming a capping layer around each of the first and second nanostructure channel layers, wherein the capping layer is formed on the gate dielectric layer; removing the capping layer from around each of the second nanostructure channel layers; and forming a first work function metal layer on the capping layer around each of the second and first nanostructure channel layers. The first work function metal layer and the capping layer are removed from the vicinity of each of the first nanostructure channel layers; and a second work function metal layer is formed on the first work function metal layer around each of the first nanostructure channel layers and on the first work function metal layer around each of the first nanostructure channel layers.

2. The method as claimed in claim 1, wherein the first nanostructure channel layers are spaced apart from each other in a direction substantially perpendicular to the semiconductor substrate, wherein the second nanostructure channel layers are spaced apart from each other in a direction substantially perpendicular to the semiconductor substrate, and wherein the capping layer fills a first space between the first nanostructure channel layers and a second space between the second nanostructure channel layers.

3. The method as described in claim 1, further comprising adding fluorine to the gate dielectric layer prior to forming the capping layer.

4. The method as described in claim 3, wherein adding the fluorine to the gate dielectric layer comprises: depositing a pad layer on the gate dielectric layer; depositing a fluorine source layer on the pad layer; performing an annealing operation on the gate dielectric layer, the pad layer and the fluorine source layer; and removing the pad layer and the fluorine source layer from the gate dielectric layer.

5. The method as claimed in claim 1, wherein a first etching operation is performed to remove the capping layer from around each of the second nanostructure channel layers, wherein a second etching operation is performed to remove the capping layer from around each of the first nanostructure channel layers, and wherein the first etching operation and the second etching operation are performed using at least one of a mixture of sulfuric acid and hydrogen peroxide, a mixture of ammonia and hydrogen peroxide, or a mixture of hydrochloric acid, hydrogen peroxide, and water.

6. A method of forming a semiconductor device, comprising: forming a plurality of first nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of the semiconductor device; forming a plurality of second nanostructure channel layers arranged in the direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer around each of the first and second nanostructure channel layers; forming a capping layer around each of the first and second nanostructure channel layers, wherein the capping layer is formed on the gate dielectric layer; and forming a first work function metal layer on the capping layer around each of the first and second nanostructure channel layers. The first work function metal layer is removed from the capping layer around each of the first nanostructure channel layers; and a second work function metal layer is formed on the capping layer around each of the first nanostructure channel layers and on the first work function metal layer around each of the second nanostructure channel layers.

7. The method as described in claim 6, wherein a first portion of the capping layer is alternately stacked with a corresponding first nanostructure channel layer of the first nanostructure channel layers, and wherein a second portion of the capping layer is alternately stacked with a corresponding second nanostructure channel layer of the first nanostructure channel layers.

8. A semiconductor device comprising: a plurality of first nanostructure channel layers arranged in a first direction substantially perpendicular to a semiconductor substrate of the semiconductor device; a plurality of first dielectric layers disposed around each of the first nanostructure channel layers; a plurality of second nanostructure channel layers arranged in the first direction, wherein the second nanostructure channel layers are adjacent to the first nanostructure channel layers in a second direction substantially perpendicular to the first direction; a plurality of second dielectric layers disposed around each of the second nanostructure channel layers; a first structure disposed around the first nanostructure channel layers and the first dielectric layers, the first structure comprising: a first portion of a capping layer; and a first portion of a first type metal layer on the first portion of the capping layer; and a second structure disposed around the second nanostructure channel layers and the second dielectric layers, the second structure comprising: a second portion of the capping layer; A second type of metal layer on the second portion of the cover layer; and a second portion of the first type of metal layer on the second type of metal layer.

9. The semiconductor device of claim 8, wherein the first dielectric layer and the second dielectric layer each contain fluorine, and wherein a ratio of a concentration of fluorine in the first dielectric layer to a concentration of fluorine in the second dielectric layer is contained in a range of about 0.7:1 to about 1.4:

1.

10. The semiconductor device as claimed in claim 8, wherein the first portion of the capping layer is disposed around a plurality of sides of each of the first nanostructure channel layers, and wherein the second portion of the capping layer is disposed around a plurality of sides of each of the second nanostructure channel layers.

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