Apparatus and system with configurable functionality and method for configuring an integrated circuit

Abstract

Disclosed is an integrated circuit (IC) configurable for use on one of several possible platforms. The IC includes several different functional circuit blocks and a plurality of programmable registers. When programmed, these programmable registers can cause the corresponding functional circuit blocks to be completely or partially disabled. These different platforms support different groups of peripheral devices. The IC is therefore configured using these programmable registers for use on a particular platform to support its corresponding group of peripheral devices, while another instance of the IC can be configured for use on another platform to support its specific group of peripheral devices.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically to integrated circuits with configurable functionality. Prior Technology

[0002] As feature sizes have decreased, the amount of functionality that can be implemented on integrated circuits (ICs) has increased accordingly. Therefore, many functions previously distributed across multiple IC chips can now be integrated into a single IC. Furthermore, the integration levels on ICs have increased to the point where an entire system (called a SoC) can be consolidated onto a single IC. In particular, SoCs can integrate various functional circuit blocks, such as processor cores, graphics processors, memory controllers, image processing circuitry, circuit blocks supporting various types of wired I / O (e.g., high-speed serial links), and various types of input / output (I / O) circuits supporting radio frequency communications.

[0003] SoCs are used in a wide variety of systems. Some systems that use SoCs include smartwatches, mobile devices (e.g., smartphones, tablets), TV set-top boxes, desktop computers, servers, and so on. These various systems can utilize corresponding SoCs with different functional levels to meet the specific application requirements of each. Summary of the Invention

[0004] This disclosure relates to an IC that can be configured for use on any of several different platforms. In one embodiment, an integrated circuit (IC) includes a set of processing blocks for a computer system, the set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks. The IC includes a set of programmable registers associated with several of the set of processing blocks, wherein the IC is configured to disable a portion of a given set of processing blocks when a given set of programmable registers is set. The processing blocks in the set of processing blocks are configured to be at least partially disabled by setting several of the set of programmable registers, such that the IC can be configured for use on different computing platforms by partially or completely disabling different combinations of the set of processing blocks. At least two of these different computing platforms support different sets of peripheral devices.

[0005] In one embodiment, a method includes testing an IC having a plurality of functional circuit blocks, and determining, based on the test, that one or more of the plurality of functional circuit blocks on the IC are unable to perform their intended functions. The method further includes programming one or more of the programmable registers corresponding to the one or more of the plurality of functional circuit blocks that are determined to be unable to perform their intended functions. This programming may cause the counterparts of a plurality of power switches to be configured (e.g., open-circuited) to prevent power from being supplied to the counterparts of the plurality of functional circuit blocks. Subsequently, the method includes programming additional instances of the programmable registers to disable power supply to the counterparts of the functional circuit blocks, thus disabling these functional circuit blocks upon selection of a computing platform.

[0006] This disclosure further envisions a computer system having a set of processing blocks, wherein the computer system includes a set of programmable registers, wherein a given of these programmable registers corresponds to at least one of the set of processing blocks. The computer system is configured to receive a collection command that writes a disable value to a group of one or more of the programmable registers, the group of programmable registers corresponding to a group of the set of processing blocks that can be disabled for a selected computing platform configured for a plurality of different computing platforms. The computer system further includes one or more hardware circuits configured to execute one or more tasks after a given startup of the computer system, wherein the one or more tasks utilize circuitry in at least one of the group of processing blocks. A power control circuit is configured to temporarily disable the group of processing blocks after the one or more tasks have been executed, thereby configuring the computer system for the selected computing platform. Simple Explanation of the Diagram

[0007] The following implementation method will refer to the accompanying drawings, which will be briefly described below. [Figure 1] is a block diagram of an embodiment of an integrated circuit (IC). [Figure 2] is a block diagram of an embodiment of a system-on-a-chip (SoC). [Figure 3] is a block diagram of another embodiment of the IC. [Figure 4A] is a block diagram of another embodiment of the IC. [Figure 4B] is a block diagram of another embodiment of the IC, wherein the functional circuit blocks are enabled to perform tasks during a cold start before being deactivated. [Figure 4C] is a diagram illustrating the instance mechanism by which a functional circuit block can be disabled based on the setting of a programmable register. [Figure 5] is a diagram showing the product matrix of a specific IC / SoC design used on different platforms. [Figure 6] is a block diagram illustrating an embodiment of an IC / SoC that may be implemented on different platforms. [Figure 7] is a flowchart of one embodiment of a method for configuring an IC for use on a specific platform. [Figure 8] is a flowchart of another embodiment of a method for configuring an IC for use on a specific platform. [Figure 9] is a flowchart of another embodiment of a method for configuring an IC for use on a specific platform. [Figure 10] is a flowchart of an embodiment of performing a cold start in the system and then disabling certain functional circuit blocks. [Figure 11] is a block diagram of an embodiment of the test system. [Figure 12] is a block diagram of an embodiment of a computer-readable medium and manufacturing system for manufacturing circuits according to the present disclosure. Implementation

[0008] [Cross-reference to related applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 376,682, filed on September 22, 2022, entitled “Functional Circuit Block Harvesting in Integrated Circuits”, the entire contents of which are incorporated herein by reference.

[0009] This disclosure relates to various methods for configuring a SoC (and more generally, an IC) according to the specific system / computing platform in which it will be used. SoCs can be manufactured to incorporate a wide variety of different functions. Furthermore, companies manufacturing various electronic devices may sometimes adopt a common SoC architecture across a wide range of platforms. For example, a common SoC architecture (including a common instruction set architecture or ISA for the processing circuitry systems therein) can be used on a range of platforms including smartwatches, mobile computing devices (e.g., tablets, smartphones), set-top boxes for televisions, laptops and desktops, server systems, and so on. Despite a common SoC architecture, these different platforms may have different functional requirements. For example, while a smartphone may include a camera utilizing an image processing system, a set-top box using the same SoC architecture may not require any image processing.

[0010] At the end of the manufacturing process, the SoC / IC undergoes testing to verify its functionality. In some cases, certain circuit blocks may fail the tests. However, the failure of some circuit blocks does not necessarily render a particular instance of the SoC / IC unusable. For example, if the image processing system of a camera fails in a particular instance of the SoC, it may still be usable on platforms that do not utilize the camera (such as desktop computers or TV set-top boxes). Similarly, in another instance, in an SoC with several processor cores, an instance of the SoC with some faulty processor cores may still be useful in a system that does not require fully programmed processor cores. Therefore, an SoC that is unusable in a high-powered desktop computer due to some faulty processor cores may still be useful in a smartwatch, tablet, or other platforms with lower processing requirements.

[0011] Examples of SoCs (and more generally, ICs) that are still usable despite having some faulty circuit blocks can use programmable registers to disable those faulty circuit blocks. This prevents these circuit blocks from receiving any power and also prevents them from receiving clock signals. By disabling them to prevent them from receiving power and / or clock signals, it is possible to prevent these functional circuit blocks from inadvertently generating any signals that could adversely affect the operation of other circuit blocks that are functionally complete. Furthermore, disabling them by preventing power from being supplied to unused functional circuit blocks reduces the static power consumption of the IC / SoC.

[0012] When a particular instance of a SoC is designated for availability on a specific platform, it may have unused but still tested functional circuitry blocks thereon. Referring again to the example given above, a desktop computer may include an SoC with image processing circuitry fully capable of performing its intended functions, even without a requirement for such circuitry. Using another example given above, an SoC designated for implementation in a set-top box may also have functional image processing circuitry without a corresponding requirement.

[0013] This disclosure therefore envisions a specific design of SoC that can be used on a wide variety of different platforms. This disclosure further envisions various methods for collecting information about SoCs intended for use on such platforms. A specific design of SoC may include programmable registers for functional circuit blocks coupled to receive power via a power switch and thus capable of being powered off during operation (e.g., for entering sleep mode). When programmed, these programmable registers can prevent the corresponding functional circuit blocks from receiving power, effectively disabling them.

[0014] This disclosure envisions a programmable register as a single-programmable device with limited programmability. For example, the default state of a programmable register when unprogrammed may allow the corresponding functional circuit block to be enabled. However, programmable registers may cause the corresponding functional circuit block to be disabled upon programming. The limited programmability in various embodiments prevents programmable registers from being reprogrammed to subsequently enable previously disabled functional circuit blocks. Furthermore, the programmable registers of this disclosure may be single-programmable devices, wherein once a given functional circuit block is programmed to be disabled, such registers retain at least the remainder of a specific operational phase of the computing platform reached in that state (where the start of that phase may be indicated by a cold-start flag).

[0015] In one embodiment, the method includes testing the SoC and determining which of its various functional circuit blocks can perform their intended functions. Based on this test, functional circuit blocks that fail the test (if any) can be disabled by programming their corresponding programmable registers to prevent them from receiving power. Based on the results of which functional circuit blocks pass the test and are disabled, the SoC can be designated for use on one or more platforms that do not utilize the capabilities of the disabled circuits. Thus, for example, an instance of an SoC with image processing circuitry that is disabled through programming of corresponding programmable registers can be designated for use on servers, desktop computers, or set-top boxes (assuming other required capabilities are enabled), and excluded from use, for example, in smartphones or tablets that utilize this functionality in conjunction with a camera. In another example, an SoC with multiple (but not all) disabled processor cores can be designated for use in smartwatches, but excluded from use in high-power desktop computers.

[0016] This disclosure further envisions disabling additional functional circuitry blocks of a SoC (or more generally, an IC) by using some of these programmable registers. The computer system may receive collection commands (e.g., from cryptographic signatures or other sources) and may program the additional programmable registers to cause the additional functional circuitry blocks to be disabled.

[0017] In light of the foregoing, this disclosure further envisions a method for collecting ICs / SoCs based on test results and platform requirements. In one embodiment, the SoC may be tested to determine the ability of its various functional circuit blocks to perform their intended operations. After testing, if some functional circuit blocks fail while others remain functional, the SoC may be designated for use on one or more platforms where the functional circuit blocks that failed the test are not required. The SoC can then be selected for a specific platform, and configuration registers can be programmed during system startup (e.g., cold start) to ensure that any additional unnecessarily required functional circuit blocks remain powered down during SoC operation.

[0018] Regarding the IC / SoC according to this disclosure, at least one programmable register can be provided for each functional circuit block having a dedicated power switch, which allows the functional circuit block to be powered down independently of other functional circuit blocks when enabled. In some embodiments, a particular functional circuit block may include a programmable register, which, when both are programmed, causes power-on and clock-on of the particular functional circuit block.

[0019] This disclosure envisions a variety of functional circuit blocks that can be powered off independently of other functional circuit blocks. Examples of such functional circuit blocks include (but are not limited to) processor cores, memory controllers, graphics processing cores, image system processors, various input / output (I / O) circuits (such as various radio frequency communication circuits (e.g., cellular, WiFi, Bluetooth circuits), serial and parallel communication links for transmitting data to / from the SoC / IC, network interface circuits (e.g., Ethernet controllers)), and so on.

[0020] This disclosure further envisions some SoCs / ICs including "always-on" sections that communicate with other functional circuit blocks. As defined herein, an always-on circuit is a functional circuit block that continues to receive power and operate at any time the SoC / IC is receiving power (and therefore, is never put into a sleep state). An example of circuitry in an always-on functional circuit block is a processor in a smartphone SoC that responds to touchscreen inputs while other parts of the SoC are in a sleep state. This processor can wake up other parts of the SoC to allow resumption of operation. Because functional circuit blocks in the always-on sections of an SoC / IC can be configured to communicate with other functional circuit blocks in the SoC, it is possible to send signals to circuit systems that are disabled by using programmable registers. Therefore, this disclosure envisions additional programmable registers that can be used to disconnect communication between always-on circuit systems and functional circuit blocks that have been disabled due to failing tests or otherwise being unnecessarily required by a particular platform.

[0021] In some cases, specific functional circuit blocks that are intended to be deactivated may be required for certain functions during system startup (e.g., cold boot). For example, an IC / SoC may include built-in self-test (BIST) functionality, where a BIST controller is implemented in various functional circuit blocks (including those deactivated for a specific computing platform). These BIST controllers can be daisy-chained together and can perform tests and communicate with the main BIST controller during system startup. If a specific functional circuit block is deactivated, the communication link via the daisy chain to the main BIST controller is severed. Therefore, this disclosure envisions the selector programming of programmable registers to enable limited functionality during the system startup procedure to allow the performance of tasks (such as the aforementioned tests using the BIST controller), where the corresponding functional circuit blocks are subsequently deactivated. The deactivation of these functional circuit blocks can be performed after their designated tasks are completed and before the system software has access to them. The deactivated function circuit block can remain deactivated for all operating phases until the next cold start, after which the same cycle can be repeated.

[0022] The multi-platform IC / SoC and various embodiments of methods for configuring it for specific platforms will now be discussed in further detail. The description begins with a discussion of various embodiments of the IC / SoC, which can be configured for use on various platforms while implementing a common architecture across all platforms. Next, a product matrix and system diagram illustrating the use of different platforms with a given architecture of the SoC are discussed. Following this, a description of various methods for testing, configuring, implementing, and operating the disclosed IC / SoC is presented. The description concludes with a discussion of a test system for testing the IC / SoC and a computer-readable medium on which the IC / SoC's design is represented and subsequently used to manufacture it. Multi-platform IC / SoC Implementation Examples:

[0023] Figure 1 is a block diagram of one embodiment of an IC that can be configured for use on one of a variety of different platforms. IC 100 is shown here by way of example to illustrate a configurable IC, and it is not intended to limit this disclosure to any particular IC embodiment.

[0024] In the illustrated embodiment, IC 100 includes a programmable register file 103 and a plurality of power switches 104. The power switches are coupled to provide various supply voltages (e.g., Vdd1, Vdd2, etc.) to correspondingly coupled functional circuit blocks. In the illustrated embodiment, Vdd1 can be provided to the graphics processing unit (GPU) circuit block 110 (which includes several GPU cores) via switches S1 and S2; Vdd2 can be provided to the central processing unit (CPU) circuit block 105 (which includes several processor cores) via switches S3, S4, and S5; Vdd3 can be provided to the functional circuit block 115 via switch S6; and Vdd4 can be provided to the functional circuit block 116 via switch S7. Functional circuit blocks 115 and 116 can be one of several different types of circuits, such as image processing circuits, network interfaces, radio frequency (RF) circuits (e.g., WiFi transceivers), etc. The various circuit blocks including CPU circuit block 105 and GPU circuit block 110 can represent heterogeneous processing blocks implementing various functions of IC 100.

[0025] In this specific example, GPU circuit block 110 is at least partially disabled by means of the open circuit S2, which is a result of programming the corresponding programmable register in programmable register file 103. Therefore, the supply voltage Vdd1 is only provided to some, not all, of GPU circuit block 110. Similarly, CPU circuit block 105 is partially disabled by means of the open circuit state of S5 while switches S3 and S4 are closed to provide power to its portions. In this example, functional circuit block 115 is completely disabled by means of the open circuit switch S6, while functional circuit block 116 is fully enabled by means of the closed circuit state of S7. The open circuit state of these switches in this example is a result of programming the corresponding programmable register in programmable register file 103.

[0026] The deactivation of a specific circuit block or a portion thereof can be accomplished in the illustrated embodiment and can be implemented by programming several of the corresponding programmable registers (PR1 to PR7) in the programmable register file 103. In one embodiment, a specific programmable register can be programmed to cause its corresponding power switch to remain open to deactivate all or part of the functional circuit block. Generally, programmable registers according to this disclosure can be completely or partially deactivated by preventing the supply of power and / or clock signals (or both) to the corresponding functional circuit block.

[0027] It should be noted that although the programmable registers shown in Figure 1 are grouped into a single unit (programmable register file 103), this configuration is not intended to be limiting. On the contrary, the programmable registers can be distributed around IC 100 in any desired manner.

[0028] The programmable registers disclosed herein are implemented in various limited programmability embodiments. For example, a programmable register in its unprogrammed state may allow power to be supplied to the corresponding functional circuit block. When programmed, this same programmable register may cause the corresponding power switch to open, thereby disabling the functional circuit block by preventing it from receiving power. Once programmed to disable its corresponding functional circuit block, a particular programmable register may not be able to be reprogrammed to subsequently enable the same functional circuit block to perform its intended operation.

[0029] In various embodiments, one or more programmable registers may be switches with limited programmability (e.g., from enabled to disabled) and may further be single-programmable structures. For example, a switching circuit that cannot be closed again once open (or vice versa) during a particular operating phase can be used to implement a programmable register. Embodiments of programmable registers as programmable read-only memory (PROM) structures are also contemplated. In some embodiments, fuses can be used to implement at least some of the programmable registers, wherein a given fuse, when blown, disables a corresponding or portion thereof of a functional circuit block (e.g., prevents the supply of power and / or clock signals to it). Generally, programmable registers according to this disclosure are means or circuits that cannot be reprogrammed to a different state once programmed to a particular state, and further, can only be programmed to a specific value. Regarding a functional circuit block in a given embodiment, the programmable register according to this disclosure is restricted to being programmable from a preset state in which it is enabled to a state in which the corresponding functional circuit block is disabled, but not in the reverse direction.

[0030] It should be noted further that different types of programmable registers may be used in a single embodiment. For example, this disclosure contemplates embodiments of some programmable registers implemented using fuses and others implemented using unidirectionally operable switching circuits.

[0031] The IC 100 in the illustrated embodiment can be used in any of a plurality of different platforms. Using the programmable register of the programmable register unit 103 and the power switch 104, an instance of the IC can be configured for use on a particular platform by disabling or enabling various functional circuit blocks and processing blocks. This may include disabling some peripheral components while keeping others enabled, and may also include disabling portions of, for example, CPU circuit block 105 and GPU circuit block 110. In some platforms, peripherals are enabled or disabled on a demand-based basis. For example, for a desktop computer that does not use a camera, a corresponding instance of the IC / SoC may disable image processing circuit blocks designed to support camera operation.

[0032] Furthermore, the amount of processing power enabled and disabled can vary across platforms. Therefore, examples of IC / SoCs intended for use in high-performance desktop computers (e.g., gaming PCs) can utilize fully programmed CPU and GPU cores. On the other hand, examples of IC / SoCs used in entry-level smartphones can utilize reduced-scale CPU and GPU cores, and thus disable portions of individual CPU and GPU circuit blocks. Using this approach, a single IC / SoC design can be used across a variety of platforms, including (but not limited to) smartwatches, servers, desktop computers, laptops, tablets, smartphones, TV set-top boxes, etc., and within a given type of platform with different performance categories (e.g., high-performance desktop computers or mid-range desktop computers). The IC / SoC design can implement a common computing architecture across all such systems, with the main difference being the enabled or disabled capabilities.

[0033] Figure 2 is a block diagram of one embodiment of a SoC that can be used on a variety of platforms. In the illustrated embodiment, the SoC 200 includes several different functional circuit blocks and can be implemented on a variety of different platforms operating using a common computing architecture. These platforms include, but are not limited to, smartwatches, smartphones, tablets, laptops, desktop computers, monitors, set-top boxes, server computers, Internet of Things (IoT) devices, and various vehicle-based computing systems. The SoC 200 can utilize the common computing architecture that allows relatively seamless data transfer and communication across these different platforms for its various applicable devices. However, due to the large number of different functional circuit blocks present in the SoC 200, some functional circuit blocks may be unused on certain platforms. This disclosure describes examples of methods and mechanisms that can be used to configure the SoC 200 to disable unused or unnecessary functional circuit blocks for use on a particular platform. This can provide various advantages, such as reduced static power consumption and reduced parasitic noise that may otherwise be generated by unused circuitry.

[0034] The SoC 200 in the illustrated embodiment includes several different functional circuit blocks. Each of these functional circuit blocks can be powered via a corresponding power switch (not shown here) and can be powered on or off independently of other functional circuit blocks of the SoC 100.

[0035] The functional circuitry of SoC 200 includes a CPU block 203 with processor cores 211 and 212. In this embodiment, processor cores 211 and 212 are general-purpose processors optimized for different purposes. For example, processor core 211 may be optimized for high performance, capable of handling heavy workloads, while processor core 212 is optimized for handling lighter workloads and limiting power consumption. Although FIG2 includes four processor cores, this is not intended to limit the number of cores in a particular embodiment. For example, an embodiment with 16 processor cores is feasible and contemplated within the scope of this disclosure. Furthermore, while the illustrated embodiment contemplates heterogeneous multi-core processing, embodiments utilizing homogeneous multi-core processing are also feasible and contemplated. The number of processor cores enabled in a particular platform may vary depending on the processing requirements of that platform. Therefore, some processor cores of SoC 200 may be disabled in some platforms. For example, in a high-end desktop computer system, all processor cores may be enabled, while in an entry-level laptop, one of processor cores 211 and one of processor cores 212 may be disabled.

[0036] Various embodiments of the SoC 200 include a neural engine 255 that can be used to perform various machine learning functions. In some embodiments, the neural engine 255 may be a processor circuit that acts as a coprocessor for various processor cores 211. In such embodiments, the neural engine 255 may receive instructions from various processor cores 211, perform operations thereon, and return results to them. The neural engine 255 in various embodiments may include an array of processing elements, and these processing elements may be deactivated independently of other processing elements.

[0037] The SoC 200 in the illustrated embodiment also includes a graphics processing unit 214, which includes several different graphics cores 215 as functional circuit blocks. The graphics cores 215 may contain circuitry implementing various graphics processing functions, but in some embodiments, they may also implement circuitry with a degree of parallel processing capabilities. The number of graphics cores 215 enabled in the SoC 200 can vary across platforms. For example, desktop computers optimized for gaming or other graphics-intensive processing may enable all graphics cores, while applications such as smartwatches may use fewer graphics cores and therefore have fewer enabled graphics cores. In platforms where graphics processing is not required, all graphics cores 215 may be disabled.

[0038] The SoC 200 in this particular embodiment includes two memory controllers 205, although the number of memory controllers in other embodiments may be larger or smaller than shown here. Each of the memory controllers 215 includes circuitry for facilitating communication between system memory and other functional circuitry blocks, such as processor cores 211 and 212. Some platforms may utilize more memory controllers 205 than others. For example, a desktop computer may utilize multiple memory controllers 205, while a smartwatch may utilize only a single instance of a memory controller. Therefore, in the latter example, all memory controllers other than one memory controller 205 may be disabled.

[0039] In some embodiments, various memory controllers 205 may be associated with corresponding on-chip memories that share a common voltage supply. Because these memories share a common voltage supply, they cannot be independently powered off. Therefore, in such cases, it is desirable to drive various signals (such as reset signals) or, conversely, disable chip select signals to prevent unused memories from generating noise or leakage. This disclosure therefore contemplates providing support logic that will perform the function of controlling reset signals or chip select signals when the corresponding memory controller 205 is disabled. For example, the support logic may prevent the reset signal from de-establishing unused memories, thereby keeping unused memories in a reset state and preventing them from generating noise that could affect the operation of other circuitry. This support logic may be activated, for example, using a programmable register discussed elsewhere herein.

[0040] SoC 200 also includes a display controller 227. The display controller 227 may include circuitry that implements various functions related to controlling a display (such as a touchscreen, for example, for a smartphone or tablet) or a monitor coupled to a desktop computer. Some platforms (such as TV set-top boxes or servers) may not include a dedicated display, or in the latter case, may be coupled to it. In such platforms, the display controller 227 may be disabled.

[0041] The image system processor (ISP) 225 in the illustrated embodiment includes a circuitry that performs image processing in conjunction with a camera included in such a platform, such as a tablet or smartphone. This image processing circuitry may include pixel circuitry, sampling circuitry, analog-to-digital converters, and so on. The ISP 225 may be deactivated on some platforms that do not utilize a camera (such as a desktop computer, server computer, or television set-top box).

[0042] The SoC 200 in the illustrated embodiment includes several different input / output (I / O) circuits that facilitate communication with the outside world. These circuits include radio frequency (RF) circuits 223 and 224, a serial interface 231, a parallel interface 232, and a network interface 233.

[0043] RF circuits 223 and 224 may include transceiver and processing circuitry for various RF communication protocols, such as Bluetooth, WiFi, cellular communication (e.g., 4G, 5G), and Near Field Communication (NFC). The number of RF circuits in a given embodiment of SoC 200 may therefore differ from that shown herein. However, some RF circuitry implemented on SoC 200 may not be used in all possible platforms in which it may be included. For example, since desktop computers are not used for contactless payments, NFC communication circuitry may be disabled in one embodiment of SoC 200 implemented on that particular platform.

[0044] The number of serial interfaces 231 included in the SoC 200 may vary between embodiments. For example, several serial interfaces 231 of a circuit system having general serial bus communications for transfer via a wired link may be included on the SoC 200. Serial interfaces 231 for other communication protocols, such as inter-IC communication (I2C) and serial peripheral interface (SPI), may also be included on the SoC 200. Some platforms may not utilize the fully compiled serial interfaces 231, and may further not utilize certain serial interfaces specific to certain communication protocols. For example, a laptop may utilize fewer USB ports than a desktop computer, and therefore may have fewer serial interfaces 231 specific to this particular protocol. Therefore, serial interfaces 231 not used in a particular platform may be disabled.

[0045] One or more instances of parallel interface 232 can be used to facilitate parallel communication with other devices outside the SoC 100 according to various parallel communication protocols. Such protocols may include the High Performance Parallel Interface Protocol (HIPPI), the Parallel Peripheral Interface Protocol (PPI), and others. Platforms such as smartwatches or TV set-top boxes may not utilize parallel communication with external platforms, and therefore may disable at least some instances of parallel interface 232.

[0046] The network interface 233 in the illustrated embodiment may include circuitry for interfaced SoC 200 to a wired network according to a specific network protocol (such as Ethernet). Other instances of using other protocols to facilitate communication with the network are also feasible and envisioned. Because some platforms (such as smartwatches) do not utilize wired network communication, any instances of network interface 233 implemented in the SoC may be disabled when used in such a platform.

[0047] Although not explicitly shown here, the SoC 200 may also include several different power supply circuits. Such circuits may include various types of voltage regulators, such as switching regulators (buck and boost converters), low-dropout voltage regulators, and other types of circuitry for generating the supply voltage. In some cases, multiple functional circuit blocks coupled to receive power from a particular power supply circuit may be disabled, so that the power supply circuit has no load to provide the supply voltage to it. Therefore, such power supply circuits can be disabled using programmable registers according to this disclosure.

[0048] The SoC 200 in the illustrated embodiment also includes power control circuitry 265 for performing various functions. These functions include deactivating various functional circuit blocks according to programming of programmable registers according to this disclosure. In one embodiment, at system startup, power control circuitry 265 can read programmable register files 230 (in AON circuitry 217) and 240 to deactivate specified functional circuit blocks of the SoC 200 according to their programming. When a functional circuit block is deactivated, power control circuitry 265 can ensure that no power is supplied to it, for example, by causing a power switch to remain open. Power control circuitry 265 can also cause clock signals to be disabled to the deactivated functional circuit blocks. In the case of memory discussed above, power control circuitry 265 can ensure that a reset signal is established for any unused memory in the system by a corresponding memory controller (otherwise, the corresponding memory controller can be disabled). In addition, any unused power supplies on the SoC 200 that are not in use due to various loads being deactivated can also be shut down by the power control circuit 265.

[0049] In some embodiments, circuitry systems to be disabled according to a specified configuration of the SoC 200 may include functionality required during system initialization during a cold start (defined herein as a system startup that occurs after power has been applied to the system following a power-off state). Such functionality may include BIST functionality, initial memory calibration, memory repair, and so on. Therefore, the power control circuit 265 may allow such circuitry to be disabled to perform various tasks during the cold start procedure prior to their final deactivation. Tasks performed by such functional circuitry blocks (or portions thereof) may be executed before the loading of the operating system software begins. After these tasks are completed and before the start of operating system loading, the power control circuit 265 may disable such functional circuitry blocks or corresponding portions thereof according to the SoC configuration specified by the programming of various programmable registers.

[0050] The SoC 200 in the illustrated embodiment also includes an Always-On (AON) circuit 217. As defined herein, an AON circuit is circuitry in which one or more functional circuit blocks continue to operate at any time the SoC 200 is receiving power. The type of circuitry implemented in the AON circuit 217 may include one or more auxiliary processors performing various functions, such as responding to touch of a touchscreen, mouse movement, etc. For example, in one embodiment, a processor that wakes other parts of the SoC 200 from sleep in response to touch of a touchscreen may be included in the AON circuit 217. In various embodiments, the AON circuit 217 may also include a power management circuitry capable of performing various operations, such as setting the performance state of a particular functional circuit block or subsystem (wherein the performance state is defined as a unique combination of operating supply voltage and clock frequency)). In one embodiment, power control circuitry 265 may be implemented in the same power domain as the AON circuit 217.

[0051] One or more signal connections may exist between the circuitry of AON circuitry 217 and other functional circuitry blocks of SoC 200. However, because some of these functional circuitry blocks may be disabled in a given platform, this disclosure envisions disabling their connections to AON circuitry 217. This isolates signals output from AON circuitry 217 from the disabled functional circuitry blocks. For example, if AON circuitry 217 includes one or more signal connections to memory controller 205, which is disabled in a particular instance of SoC 200, these connections can also be disabled using the programmable registers disclosed herein. This prevents signals from being transmitted to these disabled functional circuitry blocks, thereby saving power and preventing unwanted system noise.

[0052] The deactivation of various functional circuit blocks in SoC 200 and their connections to AON circuit 217 can be implemented using programmable registers according to this disclosure. Additional circuitry, such as circuitry that could result in the tri-state of unused signal lines, can also be implemented. In the illustrated embodiment, AON circuit 217 includes a programmable register file 230 that can be used to deactivate various functional circuit blocks of SoC 200. Embodiments that integrate all programmable registers within programmable register file 230 (rather than having a separate programmable register file 240) are feasible and contemplated.

[0053] In one embodiment, the various registers of programmable register files 230 and 240 can be programmed during the system boot routine prior to the start of the operating system loading. This can be implemented, for example, by a boot loader that reads a signature file (such as a cryptographic signature) configured according to the specified computing platform of the SoC 200. The signature can also indicate which functional circuit blocks will be deactivated during operation, by, for example, by a tri-state circuit system configured to drive signals on these lines, between the deactivated functional circuit blocks and the AON circuit 217. By deactivating the signal lines coupled between the AON circuit 217 and other deactivated functional circuit blocks on the SoC 200, unwanted signal transmissions that do not otherwise contribute to system performance can be prevented.

[0054] Using programmable registers to disable functional circuit blocks of SoC 200 allows for more precise configuration of instances for specific platforms. Some functional circuit blocks of SoC 200 can be disabled in response to failure during manufacturing testing. Failed functional circuit blocks can render an instance of SoC 200 unusable on some platforms or specific types of platforms in some performance categories, but usable on others. For example, a failure of a single core, either 211 or 212, can render an instance of SoC 200 unusable for high-performance computing systems, but it can still retain its availability for mid-range systems. Therefore, in response to manufacturing test failures, any failed functional circuit block can be designated as completely disabled in the signature file. In embodiments where at least some of the programmable registers are implemented using fuses, such fuses can be blown after testing to disable the failed functional circuit block.

[0055] Once a given instance of SoC 200 has been designated for a specific platform, additional non-faulty functional circuitry blocks can be disabled for it. The number of possible platforms in which some functional circuitry blocks of an instance of SoC 200 fail testing may decrease. However, once an instance of SoC 200 is designated for use on a specific platform, there may be additional functional circuitry blocks that, while fully capable of performing their intended operation, are unnecessary and can therefore be disabled by using programmable registers described elsewhere in this document. For example, consider an instance of SoC 200 that includes functional circuitry blocks supporting cellular communication, which fails manufacturing testing. This instance of SoC 200 can be excluded from use in a smartphone, but the fully configured processor cores and GPU cores can still be retained, allowing its use in a high-power desktop computing system. An instance of SoC can also have a fully functional image processing system that can be used in a smartphone but not in a desktop computer. Therefore, instances of the SoC 200 can be specified for use in high-performance desktop computers, and the image processing system can be deactivated through programming of the corresponding programmable registers.

[0056] It should be noted that although the components of the SoC 200 in the illustrated embodiment are indicated herein as being on the same IC, this embodiment is not intended to be limiting. In some embodiments, various functional circuitry blocks of the SoC 200 may be implemented on separate IC dies that can be combined within or on a single package (e.g., a substrate or the like) that can be mounted on a printed circuit board. Thus, an alternative view of the SoC 200 illustrated in FIG2 may be a view in which various functional circuitry blocks are implemented on different IC dies subsequently combined into a single package.

[0057] Figure 3 is a block diagram of one embodiment of an IC having several different functional circuit blocks that operate according to supply voltages provided from different power supplies. In the illustrated embodiment, IC 300 includes several functional circuit blocks 311 to 314, respectively coupled to receive supply voltages Vdd1 to Vdd4. These supply voltages may be generated by different power supplies, which are collectively shown here as power supply 304. The various power supply circuits implemented in power supply 304 may include various types of voltage regulators, such as buck regulators, boost regulators, LDO regulators, etc. Each of these regulators may be coupled to its respective load (e.g., Vdd1 is provided to FCB 311, etc., via power switch S1) via power switch S1 to S4.

[0058] In the illustrated embodiment, each of the power switches S1 to S4 is associated with a corresponding programmable register in the programmable register file 320. More generally, each power switch on a given instance of an IC or system according to this disclosure (including the SoC 200 discussed above) may be associated with at least one programmable register, such that the corresponding functional circuitry can be deactivated based on the programming of the at least one programmable register. The actual mechanism for ensuring that no power is supplied to the corresponding functional circuitry block due to the programming may vary between embodiments. For example, in response to the programming of the corresponding register, the power control circuitry may cause the corresponding power switch via the designated functional circuitry block to remain open, thereby preventing it from receiving power. In some cases where the given functional circuitry block is the only load of the corresponding power supply, the power control circuitry may shut off the power supply.

[0059] In the illustrated embodiment, IC 300 also includes an AON circuit 330 that can continue to receive power at any time while IC 300 itself is receiving power. The AON circuit 330 may include several signal paths coupled to other functional circuit blocks. In this example embodiment, these signal paths are T5 to T8, each signal path including a corresponding switch S5 to S8. Examples exist of signal paths that can be used to transmit signals between various functional circuit blocks and the AON circuit 330 during operation. However, because some functional circuit blocks of IC 300 can be disabled, this disclosure also contemplates disabling correspondingly coupled signal paths by using programmable registers in programmable register file 320. In this example, disabling a signal path can be implemented by opening the corresponding switch; however, other mechanisms are feasible and contemplated (e.g., tri-state the driver circuit intended to transmit signals on the corresponding signal line). Disabling a signal path prevents signal transmission between the AON circuit 330 and the disabled functional circuit blocks.

[0060] The mechanism for programming the configuration register 320 may vary between embodiments. In one embodiment, the configuration register 320 may be programmed during a cold boot procedure before the operating system begins loading. This programming may be based on a signature stored elsewhere in the system that indicates a specific configuration for an instance of IC 320. In another embodiment, programming may be performed during a cold boot by booting a loader.

[0061] Similarly, the mechanism by which the configuration register 320 is coupled to the AON circuit 330 via its disabled functional circuit block or signal path can vary between embodiments. In one embodiment, when a particular register is programmed, it can result in the establishment of a signal that forces the corresponding power switch to remain open during operation, thereby preventing the corresponding functional circuit block from receiving power. Similarly, when the particular register is programmed, it can result in a signal being delivered to the circuitry within the AON circuit 330 to prevent it from attempting to transmit or receive signals from the corresponding disabled functional circuit block. Other disabled mechanisms based on the programming of the configuration register 320 (including the use of fuses) are also feasible and envisioned.

[0062] Generally, this disclosure envisions IC / SoC / packages used in a large number of platforms with different functional requirements. The IC / SoC / package may have several different functional circuit blocks within it to support the functional requirements of the various platforms in which it can be used. Furthermore, in some embodiments, additional functional circuit blocks of a given type may be implemented to improve manufacturing yield, for example, by providing additional capabilities in the event of a failure of a particular functional circuit block. Therefore, if a particular instance of a functional circuit block fails testing, but another instance providing the same functionality passes testing, the corresponding IC does not need to be scrapped. Moreover, because the IC can be used on a wide variety of different platforms with different functional requirements, functional circuit blocks that are not needed on a particular platform can be deactivated. This can occur as a response to a given functional circuit block failing manufacturing testing and being deactivated, thereby narrowing the list of platforms in which it can be appropriately used. Additional deactivation of functional circuit blocks can occur when a specified platform does not require them. Therefore, the IC / SoC / system and various methods revealed in this paper can allow for improved yield and high product differentiation with a single IC / SoC / package design, for example, with a specific computing architecture that can be used on a wide variety of platforms.

[0063] It should be noted that this disclosure envisions instances of ICs without fault-faulty functional circuit blocks passing through testing (e.g., all performing as expected). In such scenarios, any functional circuit blocks not required by the selected platform can be deactivated after testing via programmable programmable registers, as discussed above.

[0064] Regarding the programming of configuration register 320, this disclosure envisions the use of a signature file (such as a cryptographic signature) read by the start code during a cold start routine. The cryptographic signature indicates the intended system configuration and thus indicates which functional circuit blocks and any signal paths connected to the AON circuit 330 will be deactivated. It should be noted that once the configuration register is programmed, it may not be modifiable or cleared without another cold start.

[0065] Figure 4A is a block diagram illustrating certain aspects of another embodiment of the IC disclosed herein. In the illustrated embodiment, IC 400 includes an AON circuit 417 having a set of programmable registers 430, a boot loader 445, and a cryptographic signature 450. The boot loader 445 and the cryptographic signature 450 may be implemented on read-only memory or other non-volatile memory. An additional set of programmable registers 440 is shown here outside the AON circuit 417, although it should be noted that embodiments integrating all programmable registers into a single register file are feasible and contemplated.

[0066] The boot loader 445 in the illustrated embodiment may include boot codes for initiating a boot process during a cold start. During the boot process, the boot loader 445 may receive a collection command from a cryptographic signature 450 to obtain information about the specified configuration of the IC 400 and the platform in which the IC will be implemented. The information accessed from the cryptographic signature includes indications of any functional circuitry blocks that will be disabled for use on the specified platform. In some embodiments, the boot loader 445 may access additional programmable temporary register files 440 when determining which functional circuitry blocks will be disabled for the specified configuration.

[0067] The bootloader 445 can program the programmable registers of register files 430 and 440 using information about which functional circuit blocks will be disabled. This programming operation can be performed by the bootloader 445 before the operating system software begins loading. The information programmed into the various programmable registers is then accessed by a power control circuit (not shown here), which can perform various operations to disable the specified functional circuit blocks. This may include disabling power and clock signals to the disabled functional circuit blocks and cutting off communication links to them. Subsequently, when the operating system loads, the disabled functional circuit blocks are not visible to them. Therefore, the operating system software can be configured after loading to operate using only the enabled functional circuit blocks. When configuring for a specific platform, the operating system may omit loading parts that will not be used on that particular computing platform. For example, when the system is a desktop computing system, the operating system software can opt out of loading the driver for the image system processor that has been disabled by programming.

[0068] Figure 4B illustrates a block diagram of the limited use of some functional circuit blocks during cold start before they are deactivated. In the illustrated embodiment, system 460 includes functional circuit blocks 437 and 480. System 460 also includes a main BIST controller 461, a BIST controller 462 (in functional circuit block 470), and a BIST controller 464 (in functional circuit block 480).

[0069] In the daisy-chain configuration shown here, BIST controller 464 can communicate with master BIST controller 461 via BIST controller 480. Therefore, BIST controller 464 relies on BIST controller 462 (and thus on functional circuit block 470) to receive power for communication with master BIST controller 461. However, functional circuit block 470 can be designated to be disabled in system 400. In this case, a power control circuit configured to disable the functional circuit block based on information stored in a programmable register can delay the deactivation of functional circuit block 470 until the test by BIST controller 464 is completed and the results are sent to master BIST controller 461. This also allows master BIST controller 461 to send commands to BIST controller 464. Tests performed by the various BIST controllers in system 460 can be performed during the cold boot process before the operating system software is loaded. Therefore, after the various BIST controllers have been tested, the power control circuit can disable the function circuit block 470 according to the specified configuration of the system 460.

[0070] Generally, the deactivation of at least some functional circuit blocks that are disabled according to the specified system configuration can be delayed during the cold start procedure. This allows various tasks required for system initialization to take place, such as the examples discussed above. Once these tasks are completed, the power control circuits or other logic in the system can then allow the specified functional circuit blocks to be disabled before the operating system is loaded and initialized.

[0071] Figure 4C illustrates an example mechanism by which the functional circuit block can be disabled based on the setting of a programmable register. In the illustrated example, a power switch P1 is coupled between the supply voltage Vdd and the functional circuit block 490. The power switch P1 is implemented here as a PMOS transistor and is activated when its gate voltage is at least less than a threshold voltage of the voltage at its source coupled to Vdd.

[0072] The second switch S40 is coupled to the gate terminal of P1. In the embodiment, switch S40 is a single-pole double-throw switch. In the first position (shown here), S40 can couple the gate terminal of P40 to Vdd. In the second position, S40 couples the gate terminal of P1 to the Pwr Ctrl signal, which can be used to activate and deactivate switch P1 as desired. For example, when S40 is in the second position, the power control circuit can activate P1 to allow functional circuit block 480 to perform its intended function, and deactivate P1 to cause functional circuit block 480 to enter sleep mode.

[0073] In this example, the programmable register 491 is set or programmed to instruct the system configuration so that functional circuit block 490 remains disabled. Therefore, the power control circuit in this example can be programmed to cause S40 to remain in the first position during normal operation. This causes the gate terminal of P1 to be coupled to Vdd, preventing P1 from starting, and thus functional circuit block 490 does not receive a supply voltage.

[0074] The example in Figure 4C is merely one of several possible mechanisms that can be used, according to this disclosure, to disable a functional circuit block based on information stored in a programmable register. In general, any suitable mechanism can be used to disable a functional circuit block.

[0075] Platform for configurable ICs / SoCs: Figure 5 illustrates a product matrix of a specific design of an IC / SoC embodiment used on different platforms. In the illustrated embodiment, product matrix 500 illustrates the different configurations of the IC / SoC embodiment for use in the following products: tablet computers, high-end smartphones, mid-range smartphones, entry-level smartphones, high-performance desktop PCs (PCs), mid-range desktop PCs, TV set-top boxes, monitors / TVs (e.g., smart monitors or smart TVs), and laptop PCs. Functional circuit blocks that can be enabled / disabled in this example include a CPU complex (with one or more processor cores), a GPU complex, image system processing / camera circuitry, external display circuitry, internal display circuitry, and memory controller circuitry (MCC).

[0076] It should be noted that the product matrix is ​​shown here by way of example and is not intended to be limiting. Therefore, it is feasible and contemplated that embodiments of ICs / SoCs can be configured for use in different product ranges than those shown herein. Similarly, it is feasible and contemplated that embodiments of ICs have different ranges of functional circuit blocks that can be enabled or disabled.

[0077] In the illustrated examples, the IC embodiments are configured differently for the various products in which they can be used. For example, in a desktop computer, full functionality of all functional circuit blocks is used, while a high-end telephone utilizes most of the functional circuit blocks but does not support an external display. Furthermore, several products (such as mid-range telephones, mid-range desktop PCs, and set-top boxes) utilize only a portion of the CPU complex. Therefore, some processor cores are deactivated in these products. It should be noted that different processor cores may be deactivated relative to another product in the matrix. For example, some products may utilize at least one high-performance processor core and at least one processor core optimized for energy efficiency, while other products may optimize only the efficiency core.

[0078] When determining which specific processor cores, GPU cores, and other parts of specific functional circuitry should be disabled, other factors, such as thermal profiles, can be taken into consideration. For example, referring back to CPU block 203 in Figure 2, there are four processor cores 211 and 212 configured in a square orientation (two rows each for two different types of processor cores). If, by a specified system configuration, only one of processor cores 211 and one of processor cores 212 needs to be enabled and both are fully functional (as determined by manufacturing testing), the enabled cores can be kept diagonally oriented relative to each other. This minimizes the adjacent dimensions of two enabled cores, as they are only closest to each other at one corner. As a result, less heat is shared between two enabled cores during operation than if they were configured, for example, to keep two cores enabled in the same column. This makes it easier for excess heat to dissipate from the cores and thus simplifies overall thermal management on the chip.

[0079] Performance considerations can also be used to determine which functional circuit blocks will remain enabled. For example, if some GPU cores are to be disabled, the remaining enabled cores can be selected based on performance metrics collected during manufacturing testing, thus choosing the highest performer.

[0080] Returning to the example in Figure 5, the ISP / camera circuitry can be disabled, particularly for products that do not utilize cameras (such as desktop PCs, set-top boxes, and monitors / TVs). Full ISP / camera functionality is provided for tablets and high-end phones, while partial functionality is offered for mid-range and entry-level phones.

[0081] Generally, various embodiments of the IC / SoC disclosed herein can be used in a wide variety of different products implementing a common computing architecture. Specific instances of the IC / SoC can be configured according to the desired capabilities of such products, wherein unnecessary capabilities are disabled as discussed elsewhere herein. By utilizing a common computing architecture, various products utilizing one (or more) instances of the IC / SoC can seamlessly operate with each other for cross-platform communication.

[0082] Next, turning to Figure 6, a diagram illustrating examples of different computing platforms according to this disclosure is presented. The system 600 in the illustrated embodiment is a computing platform that can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 600 includes at least one instance of a system-on-a-chip (SoC) 606, which may include various types of processing units, such as one or more CPU cores, a GPU with several graphics processing cores, a communication mesh architecture, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 606 include multiple execution lanes and instruction dispatch queues. SoC 606 can implement a common computing architecture (e.g., using the same instruction set architecture) across various platforms shown herein. In various embodiments, SoC 606 is coupled to external memory 602, peripheral device 604, and power supply 608. In some system embodiments, multiple instances of SoC 606 can be combined to form a common computing element. It should be further noted that, as an alternative to SoC, various functional circuit blocks can be implemented on multiple ICs, and as part of the system implementation scheme, these ICs can be combined into a single package.

[0083] A power supply 608 is also provided, which supplies supply voltage to the SoC 606 and one or more supply voltages to the memory 602 and / or peripheral devices 604. In various embodiments, the power supply 608 represents a battery pack (e.g., a rechargeable battery pack in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 606 is included (and more than one external memory 602 is also included).

[0084] Memory 602 refers to any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices are mounted using a SoC or integrated circuit in a chip-on-chip configuration, package-on-package configuration, or multi-chip module configuration.

[0085] The SoC 606 in the illustrated embodiment can be configured according to various other SoC / IC configurations discussed above. That is, the SoC 606 can implement a common functional architecture that can be used in various of the different system embodiments shown in FIG. 6. Therefore, the SoC 606 can also be configured to disable certain functional circuit blocks depending on the specific system in which it is implemented. For example, a first set of functional circuit blocks can be disabled for an instance of the SoC 606 implemented in a smartwatch 660, while a second set of functional circuit blocks can be disabled for another instance of the SoC 606 implemented in a desktop computer 610.

[0086] The deactivation of various functional circuit blocks in a specific instance of SoC 606 can be implemented using programmable registers as discussed above. Some registers can be programmed in response to functional testing of the SoC 606 that occurs at the end of the manufacturing line. Based on any failed functional circuit block, the possibility of using a given instance of SoC 606 in some of the system embodiments shown herein can be ruled out. For example, if a functional circuit block including an RF circuitry system supporting cellular communication fails testing, the possibility of using the corresponding SoC 606 in some embodiments of mobile phone 640 and tablet computer 630 can be ruled out. However, while cellular communication may not be feasible for this particular instance of SoC 606, in other instances it may (depending on the test results of other functional circuit blocks) be available for use in other system embodiments, such as desktop computer 610, laptop computer 620, and monitor 650.

[0087] After excluding a given instance of SoC 606 from use on some platforms due to a faulty functional circuit block, it can then be designated for use on a specific system where it remains usable. However, because there may be additional functional circuit blocks that are not needed, a configuration register can be used to disable them. Using the example of a faulty RF circuit block for cellular communication given above, an instance of SoC 606 that has encountered this fault can be designated for use on desktop computer 610. However, since desktop computer 610 does not perform image system processing that supports onboard cameras, the functional circuit block containing the image system processor can also be disabled. This can be achieved by a boot code or a associated signature that causes the configuration register to be programmed during a cold boot. Therefore, at any time during system boot in this embodiment of desktop computer 610, the configuration register can be programmed to disable the image system processor. Additionally, some connections from always-on circuitry to disabling functional circuit blocks can also be disabled. Similarly, the connection that provides the clock signal to the circuitry that disables the functionality can itself be disabled. Thus, starting with the architecture of the SoC 606, which is designed to be applicable to all platforms shown in Figure 6 (as well as other feasible and envisioned platforms), a given instance can be configured for use in one of a particular system such that it provides the functionality required by that platform while disabling functionality not required by that platform.

[0088] Peripheral device 604 may include any desired circuitry depending on the type of system 600. For example, in one embodiment, peripheral device 604 includes means for various types of wireless communication (such as WiFi, Bluetooth, cellular, GPS, etc.). In some embodiments, peripheral device 604 may also include additional storage, including RAM, solid-state storage, or disk storage. Peripheral device 604 includes user interface devices such as a display screen (including a touch screen or multi-touch screen), a keyboard or other input device, a microphone, a speaker, etc.

[0089] As illustrated, system 600 is shown to have applications in a wide range of fields. For example, system 600 can be used as part of a chip, circuit system, component, etc., of a desktop computer 610, laptop computer 620, tablet computer 630, cellular or mobile phone 640, or television 650 (or a set-top box coupled to a television). A smartwatch and health monitoring device 660 are also illustrated. In some embodiments, smartwatch 660 may include a variety of general computing-related functions. For example, smartwatch 660 may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionalities. For example, the health monitoring device may monitor a user's vital signs, track a user's proximity to other users for the purpose of social distancing during an epidemic, contact tracing, and provide communication to emergency services in the event of a health crisis. Epidemiological functions (such as contact tracing), providing communication to emergency medical services, etc. In various embodiments, the smartwatches mentioned above may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0090] System 600 can be further used as part of (multiple) cloud-based services 670. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 600 can be used in one or more devices of home system 680 other than those previously mentioned. For example, home appliances can monitor and detect conditions of concern. For example, various devices in the home (e.g., refrigerators, air conditioning systems, etc.) can monitor the status of the devices and provide alerts to the homeowner when specific events are detected (or, for example, repair facilities). Alternatively, a thermostat can monitor the temperature in the home and automatically adjust the heating / cooling system based on the homeowner's historical responses to various conditions. Figure 6 also illustrates the application of System 600 to various modes of transportation. For example, system 600 can be used as an in-vehicle system 690 in the control and / or entertainment systems of airplanes, trains, buses, taxis, private cars, surface vessels ranging from private boats to cruise ships, locomotives (for rental or personal use), etc. In various cases, system 600 can be used to provide automated guidance (e.g., autonomous vehicles), general system control, and others. Many other embodiments are possible and contemplated. It should be noted that the devices and applications illustrated in FIG. 6 are illustrative only and are not intended to be limiting. Other devices are possible and contemplated.

[0091] Methods for configuring and operating ICs: Figure 7 is a flowchart of one embodiment of a method for configuring an IC for use in a particular platform on which it may be implemented. Various different platforms may share a common architecture, and therefore a specific instance of the IC according to this disclosure can be configured for use in any of them. Thus, method 700 contemplates the use of the IC / SoC as disclosed herein. Embodiments of the IC / SoC are not explicitly disclosed herein, but other embodiments configurable according to method 700 are also considered to fall within the scope of this disclosure.

[0092] Method 700 includes configuring an integrated circuit (IC) for use on a specific computing platform across a plurality of different computing platforms. The IC has a set of processing blocks including a central processing unit (CPU) circuit block, a graphics processing unit (GPU) circuit block, and one or more other circuit blocks (block 705). The configuration includes programming a plurality of a set of programmable registers associated with a plurality of the set of processing blocks (block 710). The configuration further includes disabling at least a portion of the corresponding portion of the set of processing blocks in response to programming a plurality of the set of programmable registers, wherein the processing blocks of the set of processing blocks are at least partially disabled in response to the programming, such that the IC can be configured for use on different computing platforms by partially or completely disabling different combinations of the set of processing blocks (block 715). At least two of the different computing platforms support different sets of peripherals. Furthermore, a specific computing platform supports a unique set of peripherals associated with the others of the plurality of computing platforms.

[0093] In one embodiment, the method includes configuring a first instance of an IC for use in a tablet computer having a first set of peripherals, the first set of peripherals including internal display peripherals and external display peripherals. This method embodiment further includes configuring a second instance of the IC for use in a media player having a second set of peripherals different from the first set of peripherals, wherein configuring the second instance includes partially disabling CPU circuit blocks and completely disabling display pipeline circuit blocks dedicated to the external display, and further includes disabling image signal processing circuit blocks for the camera. Embodiments of the method may also include configuring the IC to be used in a given one of a plurality of computing platforms of a plurality of different performance classes by selectively disabling portions of the set of heterogeneous processing blocks for one of a plurality of different performance classes.

[0094] In some embodiments, the method includes disabling a given clock signal to the set of processing blocks in response to a corresponding first instance of programming the set of programmable registers. Such embodiments may also include disabling the given power supply to the set of processing blocks in response to a corresponding second instance of programming the set of programmable registers.

[0095] In one embodiment, the IC includes an always-on circuit configured to remain operational while the IC is receiving power. Embodiments of a method involving an IC with an always-on circuit include disconnecting at least one communication link between the always-on circuit and a counterpart of the set of processing blocks in response to a counterpart of a programmable register.

[0096] Various method embodiments include executing one or more tasks utilizing a given processing block after the startup of a computing platform including an IC. These method embodiments also include deactivating at least a portion of the given processing block from software access after the completion of one or more tasks and based on a given programmable register.

[0097] Regarding programmable registers, a given programmable register is a single-programmable register, meaning that once a given programmable register is set, it cannot be cleared.

[0098] Figure 8 is a flowchart of another embodiment of a method for configuring an IC for use on a particular platform. Method 800 can be implemented for any embodiment of an IC / SoC as disclosed herein. Embodiments of IC / SoCs that can be configured according to method 800 are also considered to fall within the scope of this disclosure.

[0099] Method 800 includes testing an IC (block 805) having a plurality of functional circuit blocks. The IC can be designed for use on a wide variety of platforms with significantly different requirements. For example, the IC can be a SoC with a computing architecture suitable for various platforms including smartwatches, smartphones, desktop computers, servers, etc. At least some of these platforms can utilize combinations of functional circuit blocks different from those of other platforms, including different sets of peripheral devices and different sets of processing circuit blocks.

[0100] The method further includes determining, based on a test, that one or more functional circuit blocks on the IC are unable to perform their intended functions (block 810). After making this determination, the method includes programming one or more programmable registers corresponding to the one or more functional circuit blocks that were determined to be unable to perform their intended functions (block 815). The programming of these one or more programmable registers results in the counterparts of a plurality of power switches being unable to provide power to the counterparts of the plurality of functional circuit blocks.

[0101] A programmable register to disable a functional circuit block (or a portion thereof) from receiving power is only one possible mechanism for implementing this deactivation. Deactivating a functional circuit block according to this disclosure may include disabling the supply of clock signals to the functional circuit block, and may also include disabling it from receiving certain signals.

[0102] Because some functional circuit blocks that pass the test may not be required by the IC's intended platform, the method further includes programming one or more additional programmable registers during subsequent startup of the system including the IC (block 820), causing one or more additional power switches to fail to respond to the programming and supply power to their corresponding functional circuit blocks (block 825). Therefore, functional circuit blocks that are not needed but otherwise capable are also deactivated.

[0103] Generally, this disclosure envisions each individual power and clock domain of an IC including at least one programmable register (or bits thereof) corresponding to it to allow the deactivation of various functional circuitry systems that are unable to perform their intended function and / or are otherwise not required for a particular platform. Because this may include clock domains, the IC may include programmable registers that cause clock signals to be disabled or prevented from being provided to the disabled functional circuitry block. In various embodiments, the programmable registers may be single-programmable switches with limited programmability. Therefore, a programmable register can be programmed to disable a functional circuitry block, but once set, it cannot be reprogrammed to enable the same functional circuitry block. In various embodiments, the preset state of various programmable registers is to enable their corresponding functional circuitry block (or a portion thereof), wherein the programmed state is used to disable it.

[0104] This disclosure also envisions a scenario where all functional circuitry on an instance of the IC passes testing and remains fully enabled initially, and subsequently. After selecting a specific platform for that instance of the IC, unnecessary functional circuitry blocks can be deactivated via programmable registers, as discussed herein.

[0105] Programmable registers can be implemented in various ways. Generally, a programmable register can be a register that, when programmed (or set), causes a corresponding power switch to open, causes a clock signal to be disabled, or causes a corresponding functional circuit block to not operate fully or even partially. In some embodiments, at least one programmable register may be implemented using at least one fuse. A programmable register may also be implemented as a device that, when programmed, causes its terminals or nodes to connect to a specific voltage level or voltage rail. Programmable registers can also be implemented using various programmable read-only memory circuit structures.

[0106] Figure 9 is a flowchart of one embodiment of a method for configuring a SoC for a specific platform. Method 900 can be implemented for any embodiment of an IC / SoC according to this disclosure. Although not otherwise disclosed herein, embodiments of IC / SoCs that can be configured according to method 900 are also considered to fall within the scope of this disclosure.

[0107] Method 900 includes testing the SoC and identifying any faulty functional circuit blocks (block 905). The SoC, along with other instances thereof, can then be sorted based on the test results to determine the applicable platforms in which it can be used (block 910). Assuming the SoC does not have any critical faults (i.e., faults that would render it unusable on any platform), it is then designated for a specific platform (block 915). This designation may be made in part based on which functional circuit blocks fail the test, although other factors (e.g., product requirements) may also be considered. Following this designation, a determination is made as to whether there are any functional circuit blocks on the SoC that have passed the test (and are therefore fully capable of performing their intended functions) but are otherwise unusable on the specific platform. If no (block 920, No), the method is complete. Otherwise, if there are additional unused functional circuit blocks in the SoC (block 920, yes), a pre-OS boot code (e.g., via cryptographic signature or other suitable mechanism) can be set to disable the additional unused functional circuit blocks by programming the registers during the system cold boot process (block 925).

[0108] Figure 10 is a flowchart of an embodiment of a method for allowing limited use of functional circuit blocks during a cold start prior to their subsequent decommissioning. Method 1000 can be implemented by any of the IC / SoC and other hardware embodiments disclosed herein. Embodiments of ICs, SoCs, or systems capable of implementing method 1000 but not otherwise disclosed herein are considered to fall within the scope of this disclosure.

[0109] Method 1000 includes execution of one or more initialization tasks during a given startup of a computer system by utilizing the circuitry of a specific set of processing blocks within the computer system (block 1005). In various embodiments, the startup may be a cold start of the system from a power-off state to a power-on state. The tasks may be various tasks performed during the initialization of the system from a power-off state. For example, testing various processing blocks of the system using the implemented BIST circuitry and sending such results to the main BIST controller may occur at this time. The method further includes reading a single-programmable memory to retrieve values ​​indicating a desired configuration portion of the set of processing blocks that will prevent specific processing blocks from being accessed via software (block 1010). The single-programmable memory may include a plurality of programmable registers, wherein a given programmable register includes at least one storage location for a corresponding processing block in the system. Processing blocks may include various types of functional circuitry, including CPU circuitry, GPU circuitry, various types of peripheral circuitry, interface circuitry, etc. The method further includes temporarily preventing access to a specific processing block after one or more initialization tasks have been executed (block 1015). Deactivating a given processing block may include preventing power supply to it, preventing clock supply to it, and / or preventing the transmission of various signals to it. In one embodiment, temporary prevention of access to a specific processing block occurs until a subsequent startup of the computer system, after which method 1000 is repeated. The various operations of method 1000 can be performed before the start of loading of the operating system software running on the computer system. Therefore, the deactivated processing block is invisible to the operating system software.

[0110] Various embodiments of the method include receiving a collection command that writes the value to the single-programmable memory to set a desired configuration to one of a plurality of different computing platforms, at least two of which support different sets of peripheral devices. The collection command in various embodiments may be received from a source within the computer system. For example, an embodiment is envisioned that instructs the platform and / or system to store a signature (which may be cryptographic) of a specific configuration of its operation in non-volatile memory.

[0111] Method 1000 can be implemented for a wide variety of different computing platforms. In one embodiment, method 100 can be implemented for a plurality of computing platforms including a television set-top box. When the computing platform is a television set-top box, since the set-top box does not include an internal display, the method includes disabling the internal display interface circuitry of the television set-top box in response to receiving a collection command. Other processing blocks (such as an image system processor for a camera) may also be disabled in this embodiment. When the computing platform is a smartphone, since the smartphone utilizes an internal display, the method includes disabling the external display interface circuitry in response to receiving a collection command. IC testing system:

[0112] Figure 11 is a block diagram of one embodiment of an IC test system. In the illustrated embodiment, test system 1101 can be used to test IC 1105, which may be an IC according to any of the IC / SoC embodiments discussed elsewhere herein. Test system 1101 can perform end-of-manufacturing tests on IC 1105 to verify its functionality and further identify any functional circuit blocks that do not operate according to specifications.

[0113] To test IC 1105, test system 1101 can apply various stimuli in the form of analog and / or digital (logic) signals. IC 1105 can then return an output signal that is compared to the expected response. A fault function block can return an output signal that differs from the expected response and / or has a value outside a specified range.

[0114] In some embodiments, the test system 1101 may be configured to place the IC 1105 in a programmed mode. When in programmed mode, the test system 1101 may program at least a portion of the read-only memory (ROM) in the IC 1105 that stores a signature indicating its intended system configuration. This programming may indicate which functional circuit blocks of the IC 1105 (if present) failed the test and are therefore unusable. In doing so, consideration may be excluded for using the IC 1105 in some computing platforms, although the IC may be suitable for others. It should be noted that programming may be incomplete at this point because only the faulty functional circuit blocks may be considered, but not any additional circuit blocks that would be disabled for the computing platform in which it is ultimately implemented. It should be noted that in some embodiments, the IC 1105 may include a fuse, and therefore implementing programming in programmed mode may include blowing the fuse. In embodiments that do not utilize fuses, other mechanisms, such as the ROM discussed above, may be used. Computer-readable media and manufacturing systems:

[0115] Figure 12 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1220 is configured to process design information 1215 stored on a non-transitory computer-readable storage medium 1210 and manufacture an integrated circuit 1230 based on the design information 1215. This system can be used to manufacture an IC / SoC according to the present disclosure.

[0116] The non-transitory computer-readable storage medium 1210 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1210 may be an installation medium (e.g., CD-ROM, floppy disk, or magnetic tape device); a computer system memory or random access memory (such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.); a non-volatile memory (such as flash memory, magnetic media (e.g., hard disk), or optical storage); a scratchpad or other similar type of memory element. The non-transitory computer-readable storage medium 1210 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1210 may include two or more memory media that can reside in different locations (e.g., in different computer systems connected via a network).

[0117] Design information 1215 may be specified using any of a variety of suitable computer languages ​​(including hardware description languages), such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1215 may be used by semiconductor manufacturing system 1220 to manufacture at least a portion of integrated circuit 1230. For example, the format of design information 1215 may be recognizable by at least one semiconductor manufacturing system (such as semiconductor manufacturing system 1220). In some embodiments, design information 1215 may include a wiring lookup table specifying the elements of a cell library and their connectivity. One or more cell libraries used during the logic synthesis of circuits included in integrated circuit 1230 may also be included in design information 1215. Such cell libraries may include device or transistor level wiring lookup tables indicating the circuit elements included in the cell library, masking design data, characterization data, and similar information.

[0118] In various embodiments, the integrated circuit 1230 may include one or more custom macro cells, such as memory, analog or mixed-signal circuitry, and the like. In such cases, design information 1215 may include information relating to the included macro cells. This information may include, without limitation, a schematic capture database, masking design data, behavioral models, and device or transistor hierarchy lookup tables. As used herein, masking design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0119] The semiconductor manufacturing system 1220 may include any of a variety of suitable components configured to manufacture integrated circuits. For example, this may include components for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet light treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 1220 may also be configured to perform various tests on the manufactured circuitry to ensure proper operation.

[0120] In various embodiments, the integrated circuit 1230 is configured to operate according to a circuit design specified by design information 1215, and may include any of the functionalities described herein. For example, the integrated circuit 1230 may include any of the various elements shown or described herein. Furthermore, the integrated circuit 1230 may be configured to perform the various functions described herein in conjunction with other components. Further, the functions described herein may be performed by multiple interconnected integrated circuits.

[0121] As used herein, phrases in the form of "design information specifying a circuit configured to..." do not imply that the circuit in question must be manufactured to satisfy that element. Rather, this phrase indicates that a circuit described in the design information, once manufactured, will be configured to perform the indicated action or will include the specified components. ***

[0122] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is a different implementation or example of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives falling within the spirit or scope of this disclosure.

[0123] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all embodiments of these embodiments will necessarily exhibit any or all of the potential advantages. Whether the advantages realized for a particular embodiment depend on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why embodiments falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure (in conjunction with one of the disclosed embodiments) that renders one or more of the disclosed advantages ineffective or diminished. Furthermore, suboptimal design implementation of a particular embodiment (e.g., the embodiment technique or tooling) may also render the disclosed advantages ineffective or diminished. Even assuming a skilled embodiment, the realization of advantages may still depend on other factors, such as the environmental conditions in which the embodiment is deployed. For example, inputs applied to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, resulting in the inability to achieve the benefits of its solution. Given the existence of possible factors outside this disclosure, it is expressly intended that any potential advantages described herein not be construed as requiring compliance with the claims to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the (multiple) types of improvements available to designers who have the benefits of this disclosure. Such advantages described permissibly (e.g., stating that a particular advantage "may cause") are not intended to convey any doubt as to whether such advantages are actually achievable, but rather to acknowledge that the technical reality of achieving such advantages often depends on additional factors.

[0124] Unless otherwise stated, the embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of the draft claims based on this disclosure, even if only a single instance with respect to a particular feature is described. The disclosed embodiments are intended to be illustrative and not limiting, and there is no statement to the contrary in this disclosure. Therefore, this application is intended to allow the scope of the claims to cover the disclosed embodiments and such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to which this disclosure pertains.

[0125] For example, the features in this application can be combined in any suitable manner. Accordingly, during the examination of this application (or the application claiming priority), a new claim may be made for any such combination of features. Specifically, referring to the claims of the accompanying patent application, features from independent claims may be combined with features from other independent claims, including, where appropriate, claims attached to other subsidiary claims. Similarly, features from individual subsidiary claims may be combined, where appropriate.

[0126] Accordingly, while the accompanying subsidiary claims may be drafted such that each is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features of the subsidiary claims consistent with this disclosure is contemplated and may be claimed in this application or another application. In short, combinations are not limited to those specifically enumerated in the scope of the appended patent application.

[0127] Where appropriate, it is also envisioned that a request drafted in one format or statutory type (e.g., device) is intended to support a corresponding request in another format or statutory type (e.g., method). ***

[0128] Because this disclosure is a legal document, all terms and phrases used are subject to administrative and judicial interpretation. The following paragraphs and the definitions provided throughout this disclosure are intended to determine how to interpret the scope of any patent application drafted based on this disclosure.

[0129] Unless the context explicitly specifies otherwise, the singular form of an item (i.e., a noun or noun phrase preceded by "a / an" or "the") is intended to mean "one or more" (or "one or more"). Therefore, mentioning "an item" in a claim does not exclude additional instances of that item without accompanying context. "Plurality" refers to a set of one of two or more items.

[0130] In this article, the word "may" is used in the sense of permission (i.e., having the possibility or ability to) and not in the sense of mandatory (i.e., being required to).

[0131] The terms “comprising” and “including” and their forms are open-ended, meaning “including, but not limited to”.

[0132] When the term "or" is used in this disclosure with respect to a list of options, it is generally understood to be used in an inclusive sense unless the context otherwise provides. Therefore, the statement "x or y" is equivalent to "x or y, or both," thus: 1) covering x but not y; 2) covering y but not x; and 3) covering both x and y. On the other hand, phrases such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense.

[0133] The statements "w, x, y, or z, or any combination thereof" or "... at least one of ... w, x, y, and z" are intended to cover all possibilities involving a single element or at most a total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element of the set (e.g., w but not x, y, or z)), any two elements (e.g., w and x, but not y or z)), any three elements (e.g., w, x, and y, but not z)), and all four elements. Therefore, the phrase "...w, x, y, and z at least one" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase is not interpreted as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0134] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for a feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of that feature. Additionally, unless otherwise stated, the labels "first," "second," and "third," when applied to a feature, do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0135] The phrase "based on" is used to describe one or more factors that influence a decision. This term does not preclude the possibility that additional factors may influence the decision. That is, a decision may be based solely on a particular factor, or on that particular factor and other unspecified factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A, or that B influences the decision of A. This phrase does not preclude the possibility that A may also be determined based on other factors, such as C. This phrase is also intended to encompass an embodiment where A is determined solely based on B. As used herein, the term "based on" is synonymous with the term "based at least in part on."

[0136] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independently of any of the specified factors. That is, an effect may be a response to these factors alone, or it may be a response to these specified factors and other unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude the possibility that A may also be performed in response to another factor (such as C). This phrase also does not exclude the possibility that A may be performed in conjunction with responses to B and C. This phrase is also intended to cover instances where A is performed in response to B alone. As used herein, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to". ***

[0137] In this disclosure, different entities (which may be referred to differently as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This notation ("entity" configured to "perform one or more tasks") is used herein to refer to a structure (i.e., a physical object). Specifically, this notation indicates that the structure is configured to perform the one or more tasks during operation. Even if a structure is not currently being operated, it may still be said that the structure is "configured to" perform some tasks. Therefore, an entity described or stated as being "configured to" perform some tasks refers to a physical object, such as a device, circuit, system with a processing unit, memory storing executable program instructions to perform that task, etc. This phrase is not used herein to refer to intangible things.

[0138] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform such tasks / operations, even if not specifically mentioned.

[0139] The term "configured to" does not imply "configurable to". For example, an unprogrammed FPGA will not be considered "configured to" performing a specific function. However, this unprogrammed FPGA may be "configurable to" performing that function. After proper programming, the FPGA can then claim to be "configured to" performing a specific function.

[0140] For the purposes of this disclosed U.S. patent application, describing a structure "configured to" perform one or more tasks in a claim is expressly intended not to invoke 35 USC § 112(f) for the interpretation of that claim element. If the applicant intends to invoke section 112(f) during the examination of a U.S. patent application based on this disclosure, the claim element will be stated using the phrase "a component for 'performing a function'".

[0141] Different “circuit” may be described in this disclosure. These circuits or “circuitry” constitute hardware comprising various types of circuit elements, such as combinational logic, time-controlled storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuit systems may be custom-designed or taken from standard libraries. In various implementations, circuit systems may include digital components, analog components, or a combination of both, as needed. Certain types of circuits are often referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit systems.

[0142] Therefore, the disclosed circuits / units / components and other elements illustrated herein include hardware elements, such as those described in the preceding paragraphs. In many instances, the internal configuration of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" can be described as having the function of "processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units," meaning that the decoder unit is "configured to" perform this function. This description of function is sufficient for those skilled in the art of computer science to indicate a feasible set of structures for that circuit.

[0143] In various embodiments, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by their configured functionality or operation. This configuration and the associated circuits / cells / components and their interactions form the microarchitecture definition of the hardware, which is ultimately manufactured in integrated circuitry or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, this micro-hierarchical definition is a structure from which many physical implementations are recognized by those skilled in the art, all falling within the broad structure described by the micro-hierarchical definition. That is, those skilled in the art who propose the micro-hierarchical definition provided by this disclosure can implement this structure without excessive experimentation and by applying common knowledge, by encoding descriptions of circuits / cells / components in a hardware description language (HDL) (such as Verilog or VHDL). HDL descriptions are often expressed in a functional manner. However, for those with ordinary knowledge in the relevant technical field, this HDL description is used to transform the structure of a circuit, unit, or component into the details of a next-level implementation. This HDL description can take the form of behavioral code (which is generally not synthesizable), register transfer language (RTL) code (which is generally synthesizable, as opposed to behavioral code), or structured code (e.g., a wiring lookup table specifying logic gates and their connections). Subsequently, the HDL description can be synthesized based on a component library designed for a given integrated circuit manufacturing technique, and can be modified for timing, power, and other reasons to produce a final design database, which is sent to a manufacturing plant to create a mask, ultimately producing the integrated circuit. Some hardware circuitry or portions thereof can also be customized in a schematic editor and transferred to the integrated circuit design along with the synthesized circuit system. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement hardware circuitry, and / or discrete components may be used in some embodiments. Alternatively, HDL designs may be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA. The decoupling between the design of this group of circuits and subsequent lower-level implementations of these circuits typically results in a situation where, when this process is executed at a different stage of the circuit implementation, the circuit or logic designer never specifies a particular set of structures for the lower-level implementation that goes beyond the description of the actions the circuit is configured to perform.

[0144] In fact, many different lower-level combinations of circuit elements can be used to implement circuits of the same specifications, resulting in a large number of equivalent structures. As mentioned, these lower-level circuit implementations can vary depending on changes in manufacturing technology, the choice of manufacturer to produce integrated circuits, and the component library provided for a particular project. In many cases, the choice of different design tools or methodologies to produce these different implementations can be arbitrary.

[0145] Furthermore, for a single implementation of a circuit with a specific functional specification, it is common to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete description of the underlying structure for implementing a single embodiment, let alone an equivalent feasible implementation of a massive array. For this reason, this disclosure describes circuit structures using functional shorthand commonly used in the industry.

[0146] For those skilled in the art, numerous variations and modifications will become apparent once the foregoing disclosure is fully understood. The following patent application scope is intended to cover all such variations and modifications.

[0147] 100:IC 103: Programmable temporary register file; Programmable temporary register unit 104: Power switch 105: Central Processing Unit (CPU) Circuit Block 110: Graphics Processing Unit (GPU) Circuit Block 115: Functional Circuit Block 116: Functional Circuit Block 200:SoC 203: CPU Block 205: Memory Controller 211: Processor core; processing core 212: Processor core; processing core 214: Graphics Processing Unit 215: Graphics core; memory controller 217: Always On (AON) Circuit 223: Radio Frequency (RF) Circuits 224: Radio Frequency (RF) Circuits 225: Image System Processor (ISP) 227: Display controller 230: Programmable temporary register file 231: Serial Interface 232: Parallel Interfaces 233: Network Interface 240: Programmable temporary register file 255: Neural Engine 265: Power control circuit 300:IC 304: Power Supply 311: Functional Circuit Block; FCB 312: Functional Circuit Block 313: Functional Circuit Block 314: Functional Circuit Block 320: Programmable register file; configuration register 330: AON circuit 400: IC; System 417: AON Circuit 430: Programmable temporary register; temporary register file 437: Functional Circuit Block 440: Programmable temporary register; temporary register file 445: Startup loader 450: Password Signature 460: System 461: Main BIST Controller 462: BIST Controller 464: BIST controller 470: Functional Circuit Block 480: Functional Circuit Block 490: Functional Circuit Block 491: Programmable temporary register 500: Product Matrix 600: System 602: External memory; memory 604: Peripheral Equipment 606: System-on-a-Chip (SoC) 608: Power Supply 610: Desktop computer 620: Laptop 630: Tablet PC 640: Mobile Phone 650: Monitor; Television 660: Smartwatch; Health Monitoring Device 670: Cloud-based services 680: Home System 690: In-vehicle system 700: Method 705: Square 710: Square 715: Square 800: Method 805: Square 810: Square 815: Square 820: Square 825: Square 900: Method 905: Square 910: Square 915: Square 920: Square 925: Square 1000: Method 1005: Square 1010: Square 1015: Square 1101: Test System 1105:IC 1210: Non-transitory computer-readable storage media 1215: Design Information 1220: Semiconductor Manufacturing Systems 1230: Integrated Circuits P1: Power switch; switch PR1: Programmable temporary register Pwr Ctrl: Signal S1-S4: Switch; Power switch S5-S8: Switches S40: Second switch; switch T5-T8: Signal path Vdd: Supply voltage Vdd1-Vdd4: Supply voltage

Claims

1. A configurable device comprising: a system-on-a-chip (SoC) implemented on one or more co-packaged integrated circuit (IC) dies, the SoC including a plurality of processing blocks configurable for use on a plurality of different computing platforms, wherein the SoC is configured to: enable a first subset of the plurality of processing blocks based on receipt of a first collection command having a first set of parameters, such that the SoC can be used as a first computing platform of the plurality of different computing platforms; and enable a second different subset of the plurality of processing blocks based on receipt of a second collection command having a second set of parameters, such that the SoC can be used as a second computing platform of the plurality of different computing platforms.

2. The device as requested in item 1, wherein the group of processing blocks spans a plurality of such co-packaged IC die distributions.

3. The device of claim 1, wherein the first computing platform is a mobile phone computing platform for use in a mobile phone, and wherein the mobile phone computing platform includes an internal display peripheral device; and wherein the second computing platform is a tablet computing platform for use in a tablet computer, and wherein the tablet computing platform includes the internal display peripheral device and an external display peripheral device.

4. The device of claim 3, wherein the plurality of processing blocks include a central processing unit (CPU); wherein the SoC is further configured to: enable the internal display peripheral device, disable a portion of the CPU, and disable the external display peripheral device based on receiving the first collection command having the first set of parameters; and wherein the SoC is further configured to: enable the internal display peripheral device, enable that portion of the CPU, and enable the external display peripheral device based on receiving the second collection command having the second set of parameters.

5. The device of claim 1, wherein the plurality of processing blocks includes one or more of the following: a portion of a central processing unit, a portion of a graphics processing unit, an image signal processing (ISP) circuit block, a neural engine circuit block, an audio / video codec circuit block, and a display pipeline circuit block.

6. The device of claim 1, wherein the SoC can be configured for use in a given of different computing platforms of different performance classes by selectively disabling portions of the plurality of processing blocks for different performance classes.

7. The device of claim 1, wherein the SoC further includes a plurality of programmable registers, wherein a given of the programmable registers corresponds to at least one of the plurality of processing blocks; and wherein a plurality of the plurality of programmable registers are configured to, upon programming, cause one or more of the following to be exempted from being provided to a deactivated one of the plurality of processing blocks: a clock signal; or a power signal.

8. The device of claim 7, wherein the SoC further includes an always-on circuit configured to maintain operation while the SoC is receiving power, and wherein a given set of programmable registers is configured to, when programmed, disconnect at least one communication link between the always-on circuit and a deactivated one of the plurality of processing blocks.

9. The device of claim 7, wherein the SoC is configured, after each startup of the SoC, to: execute one or more tasks utilizing a given of the plurality of processing blocks; and to make the given processing block inaccessible by software based on a value of a corresponding to the set of programmable registers.

10. The device of claim 9, wherein the corresponding programmable register cannot be cleared prior to a subsequent startup of the SoC; and wherein the SoC is further configured to program the corresponding programmable register after the execution of one or more tasks and before the execution of system software.

11. A method for configuring an integrated circuit, the method comprising: configuring a system-on-a-chip (SoC) implemented on one or more co-packaged integrated circuit (IC) dies for use on a specific computing platform among a plurality of different computing platforms, wherein the configuration includes: The SoC receives a specific collection command that includes a first set of parameters; The SoC enables a subset of processing blocks based on the first set of parameters, wherein at least some of the processing blocks excluded from the subset of processing blocks are disabled, so that the SoC can be used on the particular computing platform; and wherein the particular computing platform utilizes a different set of peripheral devices than one or more of the plurality of different computing platforms.

12. The method of claim 11, wherein enabling the subset of processing blocks includes programming a subset of a set of programmable registers by the SoC; wherein a given of the programmable registers is associated with at least one corresponding processing block; and wherein programming the given programmable register to a specific state disables the at least one corresponding processing block.

13. The method of claim 12, wherein disabling the at least one corresponding processing block includes the SoC preventing a clock signal from reaching the at least one corresponding processing block based on the particular state.

14. The method of claim 12, wherein disabling the at least one corresponding processing block includes the SoC preventing a power signal from reaching the at least one corresponding processing block based on the particular state.

15. The method of claim 11, further comprising configuring a different instance of the SoC by the following steps: receiving a different collection command including a second set of parameters by the different instance; and enabling a different subset of the set of processing blocks by the different instance based on the second set of parameters, wherein processing blocks excluded from the subset of processing blocks are at least partially disabled, so that the SoC can be used on one of the plurality of different computing platforms.

16. A system with configurable functionality, the system comprising: a system-on-a-chip (SoC) implemented on one or more co-packaged integrated circuit (IC) dies, the SoC including: Multiple processing blocks, which can be configured for use on multiple different computing platforms; and a set of programmable registers, wherein a given of the programmable registers corresponds to at least one of the plurality of processing blocks; wherein a first instance of the SoC is configured to: receive a first collection command having a first set of parameters; set a subset of the set of programmable registers to a specific state based on the first set of parameters; and disable a first subset of the plurality of processing blocks based on the subset of programmable registers; and wherein, after disabling the first subset of processing blocks, the first instance can be used on a first computing platform of the plurality of different computing platforms.

17. The system of claim 16, wherein a second instance of the SoC is configured to: receive a second collection command having a second set of parameters; set a different subset of the set of programmable registers to the specific state based on the second set of parameters; and disable a second subset of the plurality of processing blocks that is different from the first subset based on the different subset of programmable registers; and wherein, After the processing blocks of the different subset are deactivated, the second instance can be used on a second different computing platform among the plurality of different computing platforms.

18. The system of claim 17, wherein the first computing platform is a first tablet computer of a first performance class, and the second computing platform is a second tablet computer of a second performance class lower than the first performance class; and wherein the second processing block subset includes a portion of a central processing unit (CPU); and wherein the portion of the CPU is excluded from the first processing block subset.

19. The system of claim 16, wherein the plurality of processing blocks includes one or more of the following: a portion of a central processing unit; a portion of a graphics processing unit; an image signal processing (ISP) circuit block; a neural engine circuit block; an audio / video codec circuit block; and a display pipeline circuit block.

20. The system of claim 16, wherein the plurality of different computing platforms include: A desktop computer; A laptop computer; A mobile phone; a tablet computer; a smartwatch; a display unit; A television set-top box; an Internet of Things (IoT) device; and a vehicle-based computing system.

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