Memory device and fabrication method thereof

Abstract

This disclosure provides a memory device and a method for fabricating the same. The method includes forming a high-dielectric-constant dielectric layer on a first substrate region and a second substrate region. A first sacrificial layer is formed directly over the first substrate region. Metal layers are formed on the first and second substrate regions. A second sacrificial layer is formed on the metal layers. The metal layer and the second sacrificial layer directly over the first substrate region are removed. An annealing process is performed on the metal layers to form a dipole region in the high-dielectric-constant dielectric layer directly over the second substrate region. The metal layer and the second sacrificial layer are then removed. Subsequently, a first high-dielectric-constant metal gate structure is formed directly over the first substrate region, and a second high-dielectric-constant metal gate structure is formed directly over the second substrate region.

Description

Technical Field

[0001] This disclosure relates to a memory device and its manufacturing method. Prior Technology

[0002] With the development of the semiconductor industry, high-k dielectric metal gates have been applied in memory devices to reduce leakage current and critical dimensions of semiconductor components. However, the work function of the gate is easily affected by the multiple layers in the high-k dielectric metal gate. For example, the metal layers inserted in the high-k dielectric metal gate increase the threshold voltage of the corresponding transistor, which makes the operation of the memory device more difficult. Summary of the Invention

[0003] This disclosure provides a method for fabricating a memory device, comprising forming a high-dielectric-constant dielectric layer on a first substrate region and a second substrate region. A first sacrificial layer is formed directly over the first substrate region. Metal layers are formed on the first sacrificial layer directly over the first substrate region and on the high-dielectric-constant dielectric layer directly over the second substrate region. A second sacrificial layer is formed on the metal layers. The metal layer and the second sacrificial layer directly over the first substrate region are removed. An annealing process is performed on the metal layers to form a dipole region in the high-dielectric-constant dielectric layer directly over the second substrate region. The metal layer and the second sacrificial layer are removed. A work function layer is formed on the high-dielectric-constant dielectric layer, a gate electrode layer is formed on the work function layer, and a gate capping layer is formed on the gate electrode layer. The gate capping layer, gate electrode layer, work function layer, and high-dielectric-constant dielectric layer are patterned to obtain a first high-dielectric-constant metal gate structure directly over the first substrate region and a second high-dielectric-constant metal gate structure directly over the second substrate region.

[0004] In some embodiments, the step of forming a first sacrificial layer directly over a first substrate region includes forming the first sacrificial layer on a high-dielectric-constant dielectric layer over both the first substrate region and the second substrate region. A hard mask is formed on the first sacrificial layer directly over the first substrate region. A portion of the first sacrificial layer exposed to the hard mask is removed.

[0005] In some embodiments, the step of removing the metal layer and the second sacrificial layer directly over the first substrate region includes forming a hard mask on the second sacrificial layer directly over the second substrate region. This involves removing a portion of the second sacrificial layer exposed to the hard mask, the metal layer directly beneath that portion of the second sacrificial layer, and the first sacrificial layer.

[0006] In some embodiments, the method further includes forming a third sacrificial layer on the second sacrificial layer and the high-dielectric-constant dielectric layer. A capping layer is formed on the third sacrificial layer. An annealing process is performed to drive metal elements in the metal layer into the high-dielectric-constant dielectric layer, thereby forming a dipole region. The third sacrificial layer and the capping layer are then removed.

[0007] In some embodiments, the second high dielectric constant metal gate structure is applied to an n-type transistor, and the metal element is lanthanum.

[0008] In some embodiments, the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are made of the same material.

[0009] In some embodiments, the method further includes forming an interface layer between the high dielectric constant dielectric layer and the first substrate region and between the high dielectric constant dielectric layer and the second substrate region, wherein after the annealing process is performed, metal elements in the metal layer diffuse into the interface layer.

[0010] In some embodiments, after the annealing process is completed and before the second sacrificial layer is removed, the dipole region is located below the top surface of the high dielectric constant dielectric layer and above the bottom surface of the interface layer.

[0011] In some embodiments, after a gate cap layer is formed on the gate electrode layer, metal elements in the dipole region diffuse into the work function layer.

[0012] In some embodiments, the method further includes forming a diffusion layer on a first substrate region, wherein the top surface of the diffusion layer is coplanar with the top surface of the second substrate region.

[0013] In some embodiments, the method further includes forming shallow trench isolation regions in the substrate to divide the substrate into a first substrate region and a second substrate region.

[0014] Another embodiment disclosed herein is a memory device comprising a first transistor having a first conductivity type and a second transistor having a second conductivity type different from the first conductivity type. The first transistor includes a first substrate region and a first high-dielectric-constant metal gate structure on the first substrate region. The second transistor includes a second substrate region, a second high-dielectric-constant metal gate structure on the second substrate region, and a dipole region within the second high-dielectric-constant metal gate structure. The dipole region contains a metallic element, and a high-dielectric-constant dielectric layer in the second high-dielectric-constant metal gate structure is contained within the dipole region.

[0015] In some embodiments, the dipole region comprises lanthanum, the high dielectric constant dielectric layer comprises hafnium dioxide, and the weight fraction ratio of lanthanum to hafnium in the high dielectric constant dielectric layer is between 10% and 20%.

[0016] In some embodiments, the dipole region comprises lanthanum, the second substrate region comprises silicon, and the weight fraction of lanthanum to the weight fraction of silicon in the second substrate region is between 0% and 5%.

[0017] In some embodiments, the dipole region is separated from the second substrate region.

[0018] In some embodiments, the second high dielectric constant metal gate structure includes an interface layer under a high dielectric constant dielectric layer, a work function layer on the high dielectric constant dielectric layer, a gate electrode layer on the work function layer, and a gate cap layer on the gate electrode layer.

[0019] In some embodiments, the dipole region extends across the work function layer, the high dielectric constant dielectric layer, and the interface layer.

[0020] In some embodiments, the maximum weight fraction of the metal element is located in a high dielectric constant dielectric layer or a work function layer.

[0021] In some embodiments, the work function of the work function layer is greater than 4.0.

[0022] In some embodiments, the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0023] In summary, the method for fabricating a memory device disclosed herein includes driving metal elements from a metal layer into a high-dielectric-constant dielectric layer to form a dipole region in the high-dielectric-constant metal gate of a second transistor. The dipole region can be used to reduce the threshold voltage for operating the second transistor having a certain conductivity type. The method also includes forming a first sacrificial layer above the substrate region corresponding to the first transistor to prevent the metal layer from directly contacting the high-dielectric-constant dielectric layer in the first transistor and to prevent metal elements from the metal layer from diffusing into the first transistor having a different conductivity type. Simple Explanation of the Diagram

[0024] To make the objectives, features, advantages, and embodiments of this disclosure more apparent and understandable, the detailed description of the accompanying drawings is as follows: Figure 1 is a flowchart of an exemplary method for manufacturing a memory device according to some embodiments of the present disclosure. Figures 2 through 10 are cross-sectional views of memory devices according to some embodiments of this disclosure at different manufacturing stages. Figure 11 illustrates the elemental distribution in a dipole region of a memory device according to some embodiments of the present disclosure. Implementation

[0025] The following drawings disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in a simple schematic manner in the drawings, and in all drawings, the same reference numerals will be used to denote the same or similar elements. And, where feasible, features of different embodiments can be applied interchangeably.

[0026] Furthermore, relative terms, such as "below" or "bottom" and "above" or "top," are used to describe the relationship between one element and another shown in the accompanying drawings. It is understandable that relative terms are used to describe different orientations of the device beyond those depicted in the drawings. For example, if a device in a drawing is flipped, an element that was originally described as being "below" other elements will be oriented as being "above" other elements.

[0027] This disclosure provides a memory device and a method for fabricating a memory device. The method includes forming a first sacrificial layer directly on a substrate region of a first transistor, followed by forming a dipole region containing a metal element in a high-dielectric-constant metal gate of a second transistor to prevent the metal element in the dipole region from diffusing into the first transistor. In this way, the threshold voltage required to operate the first transistor can be kept stable, and when the threshold voltage required to operate the second transistor decreases...

[0028] Figure 1 is a flowchart of an exemplary method S100 of a method for manufacturing a memory device according to some embodiments of the present disclosure. Figure 1 can be viewed in conjunction with Figures 2 through 10, which are cross-sectional views of the memory device of some embodiments of the present disclosure at different manufacturing stages. Method S100 is merely an example; additional steps may be performed before, during, or after method S100, and in other embodiments of method S100, some steps may be replaced. In some other embodiments of the memory device illustrated in Figures 2 through 10, additional technical features may be added, or the mentioned technical features may be replaced or modified.

[0029] As shown in step S110, method S100 includes forming shallow trench isolation regions in the substrate to divide the substrate into a first substrate region and a second substrate region. Referring to Figure 2, in one embodiment of step S110, a substrate 110 is provided to form a memory device. In some embodiments, the substrate 110 may be an elemental semiconductor substrate, such as a silicon substrate. Optionally, the substrate 110 may be a compound semiconductor substrate and / or a semiconductor alloy. The substrate 110 may include a single-crystal semiconductor substrate, such as Si, Ge, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, but is not limited thereto.

[0030] A shallow trench isolation region 120 is formed in the substrate 110, extending from the top surface of the substrate 110 to the bottom surface of the substrate 110. The bottom surface of the shallow trench isolation region 120 is located within the substrate 110, as shown in Figure 2. In some other embodiments, the shallow trench isolation region 120 may also extend through the substrate 110, such that the bottom surface of the shallow trench isolation region 120 is exposed from the substrate 110. The shallow trench isolation region 120 divides the substrate 110 into a first substrate region 112 and a second substrate region 114, with the first substrate region 112 adjacent to the second substrate region 114 in the x-axis direction. In other words, the shallow trench isolation region 120 is interposed between the first substrate region 112 and the second substrate region 114. The first substrate region 112 and the second substrate region 114 can serve as substrates for transistors of different conductivity types. For example, the first substrate region 112 can be a substrate of a p-type metal-oxide semiconductor (PMOS) in a memory device, while the second substrate region 114 can be a substrate of an n-type metal-oxide semiconductor (NMOS) in a memory device.

[0031] In some embodiments, the shallow trench isolation region 120 is an oxide material, such as silicon dioxide. The shallow trench isolation region 120 can be formed by forming trenches in the substrate 110 and then filling the trenches with an oxide material. Even though in Figure 2 the shallow trench isolation region 120 is depicted as a trapezoidal shape with a wider width at the top surface and a narrower width at the bottom surface of the substrate 110, in other embodiments, the shallow trench isolation region 120 may have other shapes. After forming the shallow trench isolation region 120, a planarization process, such as chemical mechanical polishing (CMP), is performed so that the substrate 110 and the shallow trench isolation region 120 have flush top surfaces, facilitating subsequent processes for fabricating other components on the substrate 110.

[0032] In some embodiments, a doped layer 130 is formed on a substrate 110 to serve as a channel region for a transistor having a specific conductivity type. Referring to Figure 2, the doped layer 130 is formed on a first substrate region 112 to serve as a channel region between a subsequently fabricated gate and the first substrate region 112. In some embodiments, where the first substrate region 112 and the second substrate region 114 are used in transistors of different conductivity types, the doped layer 130 is not formed on the second substrate region 114. In such embodiments, the top surfaces of the doped layer 130, the shallow trench isolation region 120, and the second substrate region 114 are coplanar, wherein the top surface of the first substrate region 112 is completely covered by the doped layer 130.

[0033] In some embodiments, the first substrate region 112 is applied to a p-type transistor, and the doped layer 130 on the first substrate region 112 may comprise a crystalline semiconductor material, such as SiGe, but is not limited thereto. For example, the doped layer 130 may be formed by implanting germanium in the substrate 110. In other exemplary embodiments, the doped layer 130 may be formed by epitaxially growing a SiGe layer or depositing a SiGe layer on the substrate 110, wherein the deposited SiGe layer may be, for example, chemical vapor deposition, low-pressure chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes. During the fabrication of the doped layer 130, the second substrate region 114 may be covered by a masking layer (not shown).

[0034] In step S120, method S100 includes forming an interface layer, a high-dielectric-constant dielectric layer, and a first sacrificial layer on a substrate and on a shallow trench isolation region. Referring to Figure 2, in one embodiment of step S120, the interface layer 140 is first formed on the substrate 110 and the shallow trench isolation region 120. In some embodiments where the doped layer 130 is formed on the first substrate region 112, the second substrate region 114, the shallow trench isolation region 120, and the top surface of the doped layer 130 are all covered by the interface layer 140. The high-dielectric-constant dielectric layer 150 is then formed on the top surface of the interface layer 140, and then the first sacrificial layer 160 is formed on the top surface of the high-dielectric-constant dielectric layer 150. The sidewalls of the interface layer 140, the high-dielectric-constant dielectric layer 150, and the first sacrificial layer 160 may be coplanar to form a film stack with parallel top surfaces.

[0035] In some embodiments, the interface layer 140 may be an oxide material, such as silicon dioxide. In this embodiment, the interface layer 140 is also referred to as a gate oxide layer. The high-dielectric-constant dielectric layer 150 may be made of a material having a dielectric constant higher than that of silicon dioxide, such as HfO2, HfSiOx, TiO2, ZrO2, other dielectric materials with a dielectric constant greater than 3.9, or combinations thereof. The first sacrificial layer 160 may be made of a hard masking material, which can be used to prevent metal elements from entering the high-dielectric-constant dielectric layer 150 in subsequent processes. For example, the first sacrificial layer 160 may be a nitride, such as titanium nitride or silicon nitride. The interface layer 140, the high-dielectric-constant dielectric layer 150, and the first sacrificial layer 160 may be fabricated through a series of chemical vapor deposition, low-pressure chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes. Planarization processes, such as chemical mechanical polishing, can be performed after each of the deposited interface layer 140, the high dielectric constant dielectric layer 150, and the first sacrificial layer 160 to provide a flat top surface for each layer.

[0036] In step S130, method S100 includes patterning a first sacrificial layer to remove the first sacrificial layer directly on the second substrate region. Referring to Figure 3, in one embodiment of step S130, the first sacrificial layer 160 directly on the first substrate region 112 is covered by a hard mask 165, while the first sacrificial layer 160 directly on the second substrate region 114 is exposed to the hard mask 165. The exposed portion of the first sacrificial layer 160 is further removed by an etching process, exposing the high-dielectric-constant dielectric layer 150 directly on the second substrate region 114. The first sacrificial layer 160 directly on the shallow trench isolation region 120 can also be removed by an etching process. For example, the etching process can be wet etching with an etch selectivity for the first sacrificial layer 160 and other materials. Alternatively, for example, the etching process can be dry etching. After patterning the first sacrificial layer 160, the hard mask 165 is removed.

[0037] In step S140, method S100 includes forming a metal layer and a second sacrificial layer on the first sacrificial layer and the high-dielectric-constant dielectric layer. Referring to Figure 4, in one embodiment of step S140, the metal layer 170 is formed on the first substrate region 112 and the second substrate region 114. The metal layer 170 covers the top surface of the first sacrificial layer 160, the sidewalls of the first sacrificial layer 160, and the exposed top surface of the high-dielectric-constant dielectric layer 150. In some embodiments, the metal layer 170 may be formed from a metal element contained in a gate structure directly on the second substrate region 114. For example, in some embodiments where the second substrate region 114 is used in an n-type transistor, the metal layer 170 may contain lanthanum. Since the high dielectric constant dielectric layer 150 and the metal layer 170 directly on the first substrate region 112 are separated by the first sacrificial layer 160, the first sacrificial layer 160 will prevent the metal elements in the metal layer 170 from diffusing into the high dielectric constant dielectric layer 150 directly on the first substrate region 112, which is used in p-type transistors.

[0038] A second sacrificial layer 180 is then formed on the metal layer 170, wherein the second sacrificial layer 180 conformally covers the metal layer 170. In some embodiments, the second sacrificial layer 180 is made of the same material as the first sacrificial layer 160, such that the second sacrificial layer 180 can also prevent metal elements in the metal layer 170 from diffusing upwards to other layers above the second sacrificial layer 180 in subsequent processes. For example, both the first sacrificial layer 160 and the second sacrificial layer 180 can be made of titanium nitride.

[0039] In some embodiments, the thickness of the sacrificial layer in the z-axis direction is greater than the thickness of the metal layer 170. For example, the thickness T1 of the first sacrificial layer 160 and the thickness T3 of the second sacrificial layer 180 can be between 2 nm and 10 nm, such as 2 nm, 4 nm, 6 nm, 8 nm, or 10 nm. The thickness T2 of the metal layer 170 is between 2 Å and 15 Å, such as 2 Å, 5 Å, 10 Å, or 15 Å. The metal layer 170 and the second sacrificial layer 180 can be fabricated using a process with high conformability, such that the top surfaces of the second sacrificial layer 180 directly on the first substrate region 112 and the second sacrificial layer 180 directly on the second substrate region 114 are not coplanar. For example, the metal layer 170 can be fabricated by atomic layer deposition, sputtering, or electroplating, while the second sacrificial layer 180 can be fabricated by methods such as atomic layer deposition or chemical vapor deposition.

[0040] In step S150, method S100 includes patterning a metal layer and a second sacrificial layer to remove the metal layer and the second sacrificial layer directly on the first substrate region. Referring to Figure 5, in one embodiment of step S150, the second sacrificial layer 180 directly on the second substrate region 114 is covered by a hard mask 185, while the second sacrificial layer 180 directly on the first substrate region 112 is exposed to the hard mask 185. The exposed portion of the second sacrificial layer 180, along with the metal layer 170 and the first sacrificial layer 160 directly below the exposed portion of the second sacrificial layer 180, are removed by an etching process, exposing the high-dielectric-constant dielectric layer 150 directly on the first substrate region 112. The portion of the second sacrificial layer 180 and the metal layer 170 directly above the shallow trench isolation region 120 and adjacent to the first substrate region 112 is also removed in this etching process. For example, the etching process can be wet etching, and has an etching selectivity for the second sacrificial layer 180, the metal layer 170, and other materials. Alternatively, for example, the etching process can be dry etching. After the patterned metal layer 170 and the second sacrificial layer 180, the hard mask 185 is removed.

[0041] As shown in step S160, method S100 includes forming a third sacrificial layer and a capping layer on the second sacrificial layer and the high-dielectric-constant dielectric layer. Referring to Figure 6, in one embodiment of step S160, the third sacrificial layer 190 is first formed on the first substrate region 112 and the second substrate region 114. The third sacrificial layer 190 covers the top surface of the second sacrificial layer 180, the sidewalls of the second sacrificial layer 180, and the exposed top surface of the high-dielectric-constant dielectric layer 150. In some embodiments, the material of the third sacrificial layer 190 may be the same as that of the first sacrificial layer 160 and the second sacrificial layer 180, so that the third sacrificial layer 190 can also be used to prevent metal elements in the metal layer 170 from diffusing upward to the layer above the third sacrificial layer 190 in subsequent processes. The third sacrificial layer 190 can also be used to protect the high-dielectric-constant dielectric layer 150 directly on the first substrate region 112. For example, the third sacrificial layer 190 and the second sacrificial layer 180 may both be made of titanium nitride, and the capping layer 200 is then formed on the third sacrificial layer 190, and the capping layer 200 conformally covers the third sacrificial layer 190. The material of the capping layer 200 is different from that of the third sacrificial layer 190; for example, the material of the capping layer 200 may be amorphous silicon.

[0042] In some embodiments, the thickness of the capping layer 200 in the z-axis direction is greater than the thickness of the sacrificial layer. For example, the thickness T3 of the second sacrificial layer 180 and the thickness T4 of the third sacrificial layer 190 can be between 2 nm and 10 nm, such as 2 nm, 4 nm, 6 nm, 8 nm, or 10 nm, and the thickness T3 can be the same as the thickness T4. The thickness T5 of the capping layer 200 is between 5 nm and 30 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm. The third sacrificial layer 190 and the capping layer 200 can be fabricated using a process with high conformability, such that the top surfaces of the capping layer 200 directly on the first substrate region 112 and the capping layer 200 directly on the second substrate region 114 are not coplanar. For example, the third sacrificial layer 190 and the capping layer 200 can be fabricated by methods such as atomic layer deposition or chemical vapor deposition.

[0043] As shown in step S170, method S100 includes performing an annealing process to form a dipole region in a high-dielectric-constant dielectric layer directly on the second substrate region. Referring to Figure 7, in one embodiment of step S170, an annealing process is performed on the structure shown in Figure 6. The annealing process drives metal elements in metal layer 170 into the high-dielectric-constant dielectric layer 150 below metal layer 170. Therefore, the portion of the first sacrificial layer 160 directly on the second substrate region 114 is doped with metal elements from metal layer 170, thereby forming a dipole region 210 in the high-dielectric-constant dielectric layer 150. The metal elements in metal layer 170 may also be further driven into interface layer 140, such that the dipole region 210 extends from the high-dielectric-constant dielectric layer 150 into the interface layer 140 along the z-axis direction.

[0044] In some embodiments where the first substrate region 112 is used for a p-type transistor and the second substrate region 114 is used for an n-type transistor, lanthanum is included directly in the dipole region 210 on the second substrate region 114 to reduce the threshold voltage of the n-type transistor. Since the metal layer 170 directly on the first substrate region 112 has been removed from the high-k dielectric layer 150, the metal element (i.e., lanthanum) in the metal layer 170 will not diffuse into the high-k dielectric layer 150 directly on the first substrate region 112. This ensures the stability of the threshold voltage of the p-type transistor. Furthermore, the second sacrificial layer 180 and the third sacrificial layer 190 can be used to prevent the metal element from diffusing upwards into the capping layer 200. In some embodiments, the threshold voltage of the p-type transistor can be reduced by a silicon-germanium doped layer 130, while the threshold voltage of the n-type transistor can be reduced by introducing the dipole region 210.

[0045] In some embodiments, the dipole region 210 can be formed between the top surface of the high dielectric constant dielectric layer 150 and the bottom surface of the interface layer 140 by controlling the annealing process. In other words, the dipole region 210 and the second substrate region 114 are spaced apart. For example, the annealing process can be a flash annealing process, performed at a temperature between approximately 700 degrees Celsius and 1050 degrees Celsius for approximately 1 to 5 seconds, so that the diffusion depth of the metal elements in the metal layer 170 stops at the interface layer 140. The dipole region 210 is closer to the sidewall of the first substrate region 112 and is substantially aligned with the sidewall of the metal layer 170. During this stage, the distribution of metal elements from the metal layer 170 in the dipole region 210 decreases from the top surface of the dipole region 210 to the bottom surface of the dipole region 210.

[0046] As shown in step S180, method S100 includes removing the layers on the high-k dielectric layer. Referring to Figure 8, in one embodiment of step S180, an etching process is performed on the structure shown in Figure 7 to remove the capping layer 200, the third sacrificial layer 190, the second sacrificial layer 180, and the metal layer 170. The etching process may include multiple wet or dry etching passes, and the etching process terminates at the top surface of the high-k dielectric layer 150. After the etching process is completed, the dipole region 210, the high-k dielectric layer 150, and the interface layer 140 remain substantially unetched.

[0047] As shown in step S190, method S100 includes forming a work function layer, a gate electrode layer, and a gate capping layer on a high-dielectric-constant dielectric layer. Referring to Figure 9, in one embodiment of step S190, a work function layer 220 is first formed on the top surface of the high-dielectric-constant dielectric layer 150. A gate electrode layer 225 is then formed on the top surface of the work function layer 220, wherein the gate electrode layer 225 includes a first conductive layer 230 and a second conductive layer 240 on the first conductive layer 230. A gate capping layer 250 is then formed on the top surface of the gate electrode layer 225. The sidewalls of the work function layer 220, the gate electrode layer 225, and the gate capping layer 250 are substantially coplanar, such that the formed film stack has parallel top surfaces.

[0048] In some embodiments, the work function layer 220 may be a metal-containing material layer with a work function greater than 4.0. The material of the work function layer 220 may be, for example, titanium nitride. The first conductive layer 230 may be a non-metal-containing material, such as polycrystalline silicon. The second conductive layer 240 may be a metal-containing material, such as tungsten, titanium, tantalum, nitrides of the aforementioned metals, or alloys thereof. The gate cap layer 250 may be an insulating material, such as silicon nitride. The work function layer 220, the gate electrode layer 225, and the first conductive layer 230 may be fabricated using suitable deposition processes such as multi-pass chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating. After the work function layer 220, the gate electrode layer 225, and the gate cap layer 250 are deposited, a planarization process, such as chemical mechanical polishing, is performed to provide a flat top surface for the layers.

[0049] After the layers on the high-dielectric-constant dielectric layer 150 are fabricated, metal elements in the dipole region 210 may diffuse upwards to layers adjacent to the high-dielectric-constant dielectric layer 150. For example, lanthanum in the dipole region 210 may diffuse into the work function layer 220. In this configuration, the work function layer 220 can be used to prevent lanthanum from further diffusing into the first conductive layer 230, while the interface layer 140 also prevents lanthanum from diffusing into the second substrate region 114. In other words, the dipole region 210 can extend across the work function layer 220, the high-dielectric-constant dielectric layer 150, and the interface layer 140.

[0050] Figure 11 illustrates the elemental distribution in a dipole region 210 of a memory device according to some embodiments of this disclosure. The distribution of lanthanum indicates that the dipole region 210 extends across the work function layer 220, the high dielectric constant layer 150, and the interface layer 140. The strength of the dipole of the metal element in the high dielectric constant layer 150 is sufficient to reduce the threshold voltage. For example, when the dipole region 210 contains lanthanum and the high dielectric constant layer 150 contains hafnium dioxide, the weight fraction ratio of lanthanum to hafnium in the high dielectric constant layer 150 is between 10% and 20%. The maximum weight fraction of the metal element is found in either the high dielectric constant layer 150 or the work function layer 220. Furthermore, because the metal element has difficulty diffusing into the first conductive layer 230 and the second substrate region 114, the weight fraction of the metal element in the first conductive layer 230 and the second substrate region 114 will be very low. For example, in the second substrate region 114 formed of silicon or the first conductive layer 230 formed of polycrystalline silicon, the weight fraction of lanthanum to the weight fraction of silicon is between 0% and 5%.

[0051] In step S200, method S100 includes patterning a layer stack from the gate cap layer to the dielectric layer to obtain a first metal gate structure directly on the first substrate region and a second metal gate structure directly on the second substrate region. Referring to Figure 10, in one embodiment of step S200, the gate cap layer 250, gate electrode layer 225, work function layer 220, high dielectric constant dielectric layer 150, and interface layer 140 directly on the first substrate region 112 are patterned to form a first high dielectric constant metal gate structure 262. Similarly, the gate cap layer 250, gate electrode layer 225, work function layer 220, high dielectric constant dielectric layer 150, and interface layer 140 directly on the second substrate region 114 are patterned to form a second high dielectric constant metal gate structure 264, and the second high dielectric constant metal gate structure 264 is spaced apart from the first high dielectric constant metal gate structure 262.

[0052] After the first high-dielectric-constant metal gate structure 262 and the second high-dielectric-constant metal gate structure 264 are formed, the first transistor 302 and the second transistor 304, separated by the shallow trench isolation region 120, are provided in the memory device 300. The first transistor 302 has a first conductivity type, while the second transistor 304 has a different second conductivity type. The first transistor 302 includes a first substrate region 112, a doped layer 130, and the first high-dielectric-constant metal gate structure 262. The second transistor 304 includes a second substrate region 114, the second high-dielectric-constant metal gate structure 264, and a dipole region 210 in the second high-dielectric-constant metal gate structure 264. The first high dielectric constant metal gate structure 262 and the second high dielectric constant metal gate structure 264 are high dielectric constant metal gate structures, which include an interface layer 140, a high dielectric constant dielectric layer 150, a work function layer 220, a gate electrode layer 225 and a gate cap layer 250.

[0053] In some embodiments, the first transistor 302 is a p-type transistor and the second transistor 304 is an n-type transistor. The high-dielectric-constant metal gate structure in either the first transistor 302 or the second transistor 304 helps reduce leakage current between it and the source / drain regions. Compared to an n-type transistor without a dipole region, the dipole region 210 in the second high-dielectric-constant metal gate structure 264 helps reduce the threshold voltage for operating the second transistor 304. Furthermore, because the dipole region 210 in the above process does not diffuse into the first transistor 302, the threshold voltage for operating the first transistor 302 can remain stable, while the threshold voltage for operating the second transistor 304 can be adjusted.

[0054] In summary, the method for fabricating a memory device disclosed herein includes driving metal elements from a metal layer into a high-dielectric-constant dielectric layer to form a dipole region in the high-dielectric-constant metal gate of a second transistor. The dipole region can be used to reduce the threshold voltage for operating the second transistor having a certain conductivity type. The method also includes forming a first sacrificial layer above the substrate region corresponding to the first transistor to prevent the metal layer from directly contacting the high-dielectric-constant dielectric layer in the first transistor and to prevent metal elements from the metal layer from diffusing into the first transistor having a different conductivity type.

[0055] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art can make various modifications and alterations without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

[0056] 110:Substrate 112: First substrate region 114: Second substrate region 120: Shallow trench isolation zone 130: Doped layer 140: Interface Layer 150: High dielectric constant dielectric layer 160: First Sacrifice Layer 165: Hard Mask 170: Metal layer 180: Second Sacrificial Layer 185: Hard Mask 190: Third Sacrificial Layer 200: Cap layer 210: Dipole Region 220: Work Function Layer 225: Gate electrode layer 230: First conductive layer 240: Second conductive layer 250: Gate cap layer 262: First high dielectric constant metallic gate structure 264: Second Highest Dielectric Constant Metal Gate Structure 300: Memory device 302: First transistor 304: Second transistor S100: Method S110, S120, S130, S140, S150, S160, S170, S180, S190, S200: Steps T1, T2, T3, T4, T5: Thickness x, y, z: axes

Claims

1. A method for fabricating a memory device, comprising: forming a high-dielectric-constant dielectric layer on a first substrate region and a second substrate region; forming a first sacrificial layer directly above the first substrate region; forming a metal layer directly above the first sacrificial layer and directly above the high-dielectric-constant dielectric layer on the second substrate region; forming a second sacrificial layer on the metal layer; removing the metal layer and the second sacrificial layer directly above the first substrate region; performing an annealing process on the metal layer to form a dipole region in the high-dielectric-constant dielectric layer directly above the second substrate region; and removing the metal layer and the second sacrificial layer. A work function layer is formed on the high dielectric constant dielectric layer, a gate electrode layer is formed on the work function layer, and a gate cap layer is formed on the gate electrode layer; and the gate cap layer, the gate electrode layer, the work function layer and the high dielectric constant dielectric layer are patterned to obtain a first high dielectric constant metal gate structure directly above the first substrate region and a second high dielectric constant metal gate structure directly above the second substrate region.

2. The method as claimed in claim 1, wherein the step of forming the first sacrificial layer directly over the first substrate region comprises: forming the first sacrificial layer on the high dielectric constant dielectric layer over the first substrate region and the second substrate region; forming a hard mask on the first sacrificial layer directly over the first substrate region; and removing a portion of the first sacrificial layer exposed to the hard mask.

3. The method as described in claim 1, wherein the step of removing the metal layer and the second sacrificial layer directly above the first substrate region comprises: forming a hard mask on the second sacrificial layer directly above the second substrate region; and removing a portion of the second sacrificial layer exposed to the hard mask, the metal layer directly below the portion of the second sacrificial layer, and the first sacrificial layer.

4. The method as described in claim 1 further comprises: forming a third sacrificial layer on the second sacrificial layer and the high dielectric constant dielectric layer; forming a capping layer on the third sacrificial layer; performing the annealing process to drive metal elements in the metal layer into the high dielectric constant dielectric layer, thereby forming the dipole region; and removing the third sacrificial layer and the capping layer.

5. The method as described in claim 4, wherein the second high dielectric constant metal gate structure is applied to an n-type transistor, and the metal element is lanthanum.

6. The method as described in claim 4, wherein the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are made of the same material.

7. The method as described in claim 1 further comprises: forming an interface layer between the high dielectric constant dielectric layer and the first substrate region and between the high dielectric constant dielectric layer and the second substrate region, wherein after the annealing process is performed, metal elements in the metal layer diffuse into the interface layer.

8. The method as described in claim 7, wherein after the annealing process is completed and before the second sacrificial layer is removed, the dipole region is located below the top surface of the high dielectric constant dielectric layer and above the bottom surface of the interface layer.

9. The method as described in claim 1, wherein after the gate cap layer is formed on the gate electrode layer, the metal element in the dipole region diffuses into the work function layer.

10. The method as claimed in claim 1 further comprises: forming a diffusion layer on the first substrate region, wherein the top surface of the diffusion layer is coplanar with the top surface of the second substrate region.

11. The method as described in claim 1 further comprises: forming a shallow trench isolation region in a substrate to divide the substrate into the first substrate region and the second substrate region.

12. A memory device comprising: a first transistor having a first conductivity type, wherein the first transistor includes: a first substrate region; and a first high-dielectric-constant metal gate structure on the first substrate region; and a second transistor having a second conductivity type different from the first conductivity type, wherein the second transistor includes: a second substrate region; a second high-dielectric-constant metal gate structure on the second substrate region; and a dipole region in the second high-dielectric-constant metal gate structure, wherein the dipole region includes a metal element, and a high-dielectric-constant dielectric layer in the second high-dielectric-constant metal gate structure is contained in the dipole region.

13. The memory device as claimed in claim 12, wherein the dipole region comprises lanthanum, the high dielectric constant dielectric layer comprises hafnium dioxide, and the weight fraction of lanthanum to hafnium in the high dielectric constant dielectric layer is between 10% and 20%.

14. The memory device as claimed in claim 12, wherein the dipole region comprises lanthanum, the second substrate region comprises silicon, and the weight fraction of lanthanum to the weight fraction of silicon in the second substrate region is between 0% and 5%.

15. The memory device as claimed in claim 12, wherein the dipole region is separated from the second substrate region.

16. The memory device as claimed in claim 12, wherein the second high-dielectric-constant metal gate structure includes an interface layer under the high-dielectric-constant dielectric layer, a work function layer on the high-dielectric-constant dielectric layer, a gate electrode layer on the work function layer, and a gate cap layer on the gate electrode layer.

17. The memory device as claimed in claim 16, wherein the dipole region extends across the work function layer, the high dielectric constant dielectric layer, and the interface layer.

18. The memory device as claimed in claim 16, wherein the maximum weight fraction of the metal element is located in the high dielectric constant dielectric layer or the work function layer.

19. The memory device as described in claim 16, wherein the work function of the work function layer is greater than 4.

0.

20. The memory device as claimed in claim 12, wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.

Images