Instruction processing method, instruction processing device, computer-readable storage medium and computer equipment

Abstract

The instruction processing method includes: obtaining the type percentage value of the instruction sequence; wherein each type percentage value represents the proportion of a corresponding type of instruction in the instruction sequence; determining the launch path used for each type of instruction based on the type percentage value; and launching the instructions to be launched in the instruction sequence to the corresponding pipeline execution unit via the corresponding launch path.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of integrated circuits, and particularly to an instruction processing method, an instruction processing apparatus, a computer-readable storage medium, and a computer device. Prior Technology

[0002] A thread is the smallest unit of computation that an operating system can schedule. Threads are contained within processes and are the actual units of operation within a process. A thread refers to a single, sequential flow of control within a process; multiple threads can run concurrently within a process, each performing different tasks.

[0003] An execution wrap contains multiple execution threads. Instructions are issued from the execution wrap to the execution unit for execution. In related technologies, the instruction issuance path is relatively simple, with all instructions being issued to the execution unit through the same path, resulting in low instruction issuance performance. Summary of the Invention

[0004] In view of this, embodiments of this application provide an instruction processing method, an instruction processing apparatus, a computer-readable storage medium, and a computer device, which can improve the efficiency of instruction issuance.

[0005] The technical solution of this application embodiment is implemented as follows: This application embodiment provides an instruction processing method, the instruction processing method includes: obtaining a type proportion value of an instruction sequence; wherein, each type proportion value represents the proportion of an instruction of a corresponding type in the instruction sequence; based on the type proportion value, determining the launch path used by the instruction of each type; and launching the instruction to be launched in the instruction sequence to the corresponding pipeline execution unit via the corresponding launch path.

[0006] In the above scheme, determining the transmission path used by each type of instruction based on the type proportion value includes: determining that at least two types of instructions whose type proportion values ​​meet the merging conditions are used by the same transmission path.

[0007] In the above scheme, determining that at least two types of instructions whose type proportion values ​​meet the merging conditions are to use the same transmission path includes: if the type proportion value of the first instruction is lower than a threshold, then the first instruction and other types of instructions are determined to use the same transmission path; and / or, if the type proportion values ​​of the second instruction and the third instruction are both higher than the threshold, and neither the second instruction nor the third instruction is the highest instruction, then the second instruction and the third instruction are determined to use the same transmission path; wherein, the highest instruction has the highest type proportion value.

[0008] In the above scheme, obtaining the type proportion value of the instruction sequence includes: after the instruction sequence is compiled, counting the number of times each type of instruction appears in the instruction sequence; and calculating the type proportion value based on the number of times each type of instruction appears.

[0009] In the above scheme, obtaining the type proportion value of the instruction sequence further includes: determining the type proportion value of the instruction sequence based on historical data.

[0010] In the above scheme, sending the command to be sent to the corresponding pipeline execution unit includes: obtaining pre-decoding information of the command to be sent; the pre-decoding information includes: waiting period; the waiting period represents the number of cycles that the command to be sent needs to wait before being sent; and sending the command to be sent when the command to be sent reaches the corresponding waiting period.

[0011] In the above scheme, the waiting period of the command to be launched is set based on the data dependency of the command to be launched; the command to be launched does not have preparation information set, wherein the preparation information indicates whether the data dependency is released.

[0012] This application embodiment also provides an instruction processing apparatus, the instruction processing apparatus comprising: a thread controller, multiple emitter paths, and multiple pipelined execution units; wherein, the first ends of the multiple emitter paths are all electrically connected to the thread controller; each pipelined execution unit is electrically connected to the second end of at least one corresponding emitter path; the thread controller is electrically connected to an execution thread bundle; the thread controller comprises: a first control module; the first control module is configured to acquire a type proportion value of an instruction sequence; and, based on the type proportion value, determine the emitter path used by each type of instruction; and, emit the instruction to be emitted in the instruction sequence from the execution thread bundle, via the corresponding emitter path, to the corresponding pipelined execution unit; wherein each type proportion value represents the proportion of a corresponding type of instruction in the instruction sequence.

[0013] In the above scheme, the execution thread controller further includes: a second control module; the second control module is configured to retrieve the instruction from the instruction register to the execution thread; and to decode the retrieved instruction.

[0014] In the above scheme, each of the transmission paths is provided with a configuration register; the first control module is also configured to configure type information for the instruction to be transmitted based on the type ratio value; and to compare the type information with the information in the configuration register of each of the transmission paths. If the comparison result is a match, the instruction to be transmitted is stored in the corresponding configuration register.

[0015] In the above scheme, the first control module is further configured to determine that at least two types of instructions whose type proportion values ​​meet the merging conditions are to use the same transmission path.

[0016] In the above scheme, the first control module is further configured to determine the first instruction and other types of instructions to use the same transmission path if the type proportion value of the first instruction is lower than a threshold; and / or, if the type proportion values ​​of the second instruction and the third instruction are both higher than the threshold, and neither the second instruction nor the third instruction is the highest instruction, then the second instruction and the third instruction are determined to use the same transmission path; wherein the type proportion value of the highest instruction is the highest.

[0017] In the above scheme, the first control module is further configured to acquire pre-decoding information of the command to be launched; the pre-decoding information includes: a waiting period; and, when the command to be launched reaches the corresponding waiting period, to launch the command to be launched.

[0018] In the above scheme, the first control module is further configured to receive and respond to the execution bundle transmit enable signal, continuously transmit the instruction to be transmitted in the execution bundle, or pause the transmission of the instruction to be transmitted in the execution bundle.

[0019] This application also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in an electronic device, the processor in the electronic device executes the steps in the above method.

[0020] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method.

[0021] This application also provides a computer device, including the instruction processing device described in the above solution.

[0022] Therefore, in this embodiment, based on the type ratio, a corresponding transmission path is configured for each type of instruction. This allows for the parallel transmission of different types of instructions, balancing the number of instructions carried on different transmission paths. This improves the utilization efficiency of the transmission paths, and congestion on a single path will not block instructions on other paths, thus improving the efficiency of instruction transmission. Simple Explanation of the Diagram

[0023] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 is a schematic diagram of the implementation flow of the instruction processing method provided in an embodiment of this application; Figure 2 is a schematic diagram of the implementation flow of the instruction processing method provided in the embodiment of this application; Figure 3 is a schematic diagram of the implementation flow of the instruction processing method provided in the embodiment of this application; Figure 4 is a schematic diagram of the implementation flow of the instruction processing method provided in the embodiments of this application; Figure 5 is a schematic diagram of the implementation flow of the instruction processing method provided in the embodiments of this application; Figure 6 is a schematic diagram of the composition structure of the instruction processing device provided in an embodiment of this application; Figure 7 is a schematic diagram of the composition structure of the thread controller provided in the embodiment of this application; Figure 8 is a schematic diagram of the composition structure of the instruction processing device provided in an embodiment of this application; Figure 9 is a schematic diagram of the composition structure of the instruction processing device provided in the embodiment of this application; Figure 10 is a schematic diagram of the hardware of the computer device provided in the embodiment of this application. Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0027] This application provides an instruction processing method that can be executed by a processor of a computer device. The computer device can refer to a server, laptop, tablet, desktop computer, smart TV, set-top box, or mobile device (such as a mobile phone, portable video player, personal digital assistant, dedicated messaging device, or portable gaming device) or any other device with data processing capabilities.

[0028] Figure 1 is a schematic diagram of the implementation flow of an instruction processing method provided in an embodiment of this application. As shown in Figure 1, the method includes steps S101 to S103.

[0029] Step S101: Obtain the type percentage value of the instruction sequence.

[0030] In this embodiment, each type percentage value represents the proportion of the corresponding type of instruction in the instruction sequence.

[0031] Table 1 below shows the percentage of different test sets (i.e., instruction sequences used for testing). The following explanation will be based on Table 1. test set FP32 INT32 BIT other 3DMark11_GT1 46.67% 1.79% 1.45% 50.09% 51_Meet_Lumen 49.33% 9.41% 6.65% 34.61% PUBG_DaTing 61.78% 5.37% 3.36% 29.49% 51_WDP 29.64% 21.93% 7.74% 40.71%

[0032] Table 1 above lists the percentage of floating-point instruction FP32, integer instruction INT32, and bitwise operation instruction BIT. For example, in the 3DMark11_GT1 test set, floating-point instruction FP32 accounts for 46.67%, integer instruction INT32 accounts for 1.79%, and bitwise operation instruction BIT accounts for 1.45%. It should be noted that floating-point instruction FP32, integer instruction INT32, and bitwise operation instruction BIT all belong to ALU (Arithmetic and Logic Unit) instructions.

[0033] In this embodiment, after compiling the instruction sequence, the compiler can calculate the proportion of different types of instructions in the instruction sequence, that is, calculate the type proportion value of the instruction sequence. Accordingly, before the instructions in the instruction sequence are issued, the type proportion value of the instruction sequence can be obtained from the compiler.

[0034] Step S102: Based on the type percentage value, determine the transmission path used for each type of instruction.

[0035] Step S103: The instruction to be issued in the instruction sequence is issued to the corresponding pipeline execution unit through the corresponding issuance path.

[0036] It should be noted that the instruction issuance path is the critical path for instructions to move from the compilation stage to the execution stage. Therefore, whether the issuance path is unobstructed directly affects the efficiency of instruction issuance.

[0037] In related technologies, the transmission paths of commands are not effectively controlled and planned. This can lead to some transmission paths being overloaded with commands and becoming congested, while other transmission paths may be idle with fewer commands. As a result, the transmission paths are not fully utilized, causing a waste of resources and reducing the efficiency of command transmission.

[0038] In this embodiment, a corresponding launch path can be configured for each type of instruction based on the type ratio. Then, for each instruction to be launched in the instruction sequence, the instruction can be launched to the corresponding pipeline execution unit via the launch path corresponding to the type of the instruction to be launched, for execution.

[0039] In this embodiment, if a certain type of instruction accounts for a large proportion, a separate transmission path can be allocated for that type of instruction; simultaneously, multiple types of instructions with smaller proportions can be combined and transmitted using another transmission path. Alternatively, if a certain type of instruction accounts for a large proportion, that type of instruction can be transmitted using multiple selectable transmission paths.

[0040] Understandably, by configuring a corresponding launch path for each type of instruction based on the type ratio, different types of instructions can be launched in parallel, balancing the number of instructions carried on different launch paths. This improves the utilization efficiency of the launch paths, and congestion on one path will not block instructions on other paths, thus improving the efficiency of instruction launch.

[0041] In some embodiments of this application, step S201 shown in FIG2 can be used to implement step S102 shown in FIG1, and will be described in conjunction with each step.

[0042] Step S201: Determine that at least two types of instructions whose type proportion values ​​meet the merging conditions are to use the same transmission path.

[0043] In this embodiment, during the process of determining the emission path used for each type of instruction, the type proportion value can be determined according to the merging condition. Furthermore, if the type proportion values ​​of at least two types of instructions meet the merging condition, these types of instructions can be merged and use the same emission path. Correspondingly, instructions that do not meet the merging condition use a separate emission path according to their type.

[0044] It is understandable that instructions that meet the merging conditions are merged using the same transmit path; in this way, while ensuring instruction transmission efficiency, the number of transmit paths occupied can be reduced; thus, resource consumption can be saved and power consumption reduced.

[0045] In some embodiments of this application, step S201 shown in FIG2 can be implemented by step S202 and / or step S203 shown in FIG3, and will be described in conjunction with each step.

[0046] Step S202: If the proportion of the first instruction type is lower than the threshold, then the first instruction and other types of instructions are determined to use the same transmission path.

[0047] In this embodiment, the first instruction is any type of instruction. Other types of instructions are any type of instruction in the instruction sequence other than the first instruction.

[0048] It should be noted that the threshold for the type percentage can be set according to requirements. In this embodiment, a threshold of 5% is used as an example for illustration.

[0049] Referring to Table 1 above, for example, in the 3DMark11_GT1 test set, the proportion of integer instruction INT32 is 1.79%, and the proportion of bit operation instruction BIT is 1.45%, both of which are below the threshold of 5%. Therefore, the two types of instructions (integer instruction INT32 and bit operation instruction BIT) can be determined to use the same issue path; or, the three types of instructions (integer instruction INT32, bit operation instruction BIT, and floating-point instruction FP32) can also be determined to use the same issue path.

[0050] Referring again to Table 1, for example, in the test set PUBG_DaTing, the proportion of bit manipulation instruction (BIT) is 3.36%, which is lower than the threshold of 5%. Therefore, the two types of instructions (bit manipulation instruction (BIT) and floating-point instruction (FP32)) can be determined to use the same issue path; or, the two types of instructions (integer instruction (INT32) and bit manipulation instruction (BIT)) can also be determined to use the same issue path.

[0051] It is understandable that if the proportion of the first instruction type is lower than the threshold, it indicates that the first instruction accounts for a very small proportion in the test sequence. Therefore, merging the first instruction with other types of instructions using the same transmission path will not significantly increase the number of instructions transmitted in the transmission path used, and can reduce the number of transmission paths occupied, thereby saving resources and reducing power consumption.

[0052] Step S203: If the type proportion values ​​of the second instruction and the third instruction are both higher than the threshold, and neither the second instruction nor the third instruction is the highest instruction, then the second instruction and the third instruction are determined to use the same transmission path.

[0053] In this embodiment, the highest type of instruction has the highest percentage; referring to Table 1 above, among the four test sets listed in Table 1, the floating-point instruction FP32 has the highest percentage, that is, the floating-point instruction FP32 is the highest type of instruction. The second and third instructions are both instructions of any type.

[0054] Referring to Table 1 above, for example, in the test set 51_Meet_Lumen, the proportion of integer instruction INT32 is 9.41%, and the proportion of bit operation instruction BIT is 6.65%. Both are higher than the threshold of 5%, but neither is the highest instruction. Therefore, the two types of instructions (integer instruction INT32 and bit operation instruction BIT) can be determined to use the same issue path.

[0055] Understandably, the proportions of the second and third instruction types are both higher than the threshold. If the second or third instruction is merged into the highest instruction transmission path, it will significantly increase the number of instructions transmitted in that path, leading to an imbalance in the number of instructions configured across transmission paths and thus affecting instruction transmission efficiency. Therefore, merging the second and third instructions into a single transmission path will not only maintain transmission efficiency but also reduce the number of transmission paths used, thereby saving resources and reducing power consumption.

[0056] In some embodiments of this application, step S101 shown in Figure 1 can be implemented by steps S301 to S302 shown in Figure 4, and will be described in conjunction with each step.

[0057] Step S301: After the instruction sequence is compiled, count the number of times each type of instruction appears in the instruction sequence.

[0058] Step S302: Calculate the type percentage based on the number of times each type of instruction appears.

[0059] In this embodiment, after the instructions in the instruction sequence are compiled, the frequency of occurrence of each type of instruction in the instruction sequence can be counted; for example, the frequency of occurrence of floating-point instruction FP32, integer instruction INT32, and bitwise operation instruction BIT can be counted respectively. Then, the frequency of occurrence of each type of instruction can be divided by the total number of instructions in the instruction sequence, thereby obtaining the type proportion value corresponding to each type of instruction.

[0060] Understandably, this involves counting the occurrences of each type of instruction in the instruction sequence and calculating the type percentage. This provides a more accurate type percentage, reflecting the true proportion of each type of instruction in the instruction sequence, and thus enabling more precise allocation of launch paths for each type of instruction.

[0061] In some embodiments of this application, step S101 shown in Figure 1 can be implemented by step S303 shown in Figure 4, and will be described in conjunction with each step.

[0062] Step S303: Based on historical data, determine the type proportion of the instruction sequence.

[0063] In this embodiment, the compiler software can statistically analyze the historical frequency of each type of instruction during the writing of operands, that is, it can obtain historical data on the type percentage. Therefore, the historical data on the type percentage can be directly used as the type percentage of the current instruction sequence to allocate a launch path for each type of instruction.

[0064] It is understandable that using historical data on type percentages as the type percentages for the current instruction sequence avoids the need for real-time calculation of the type percentages for the instruction sequence, saving time and thus improving the efficiency of instruction issuance.

[0065] In some embodiments of this application, step S401 to S402 shown in FIG5 can be used to implement step S103 shown in FIG1, which will be described in conjunction with each step.

[0066] Step S401: Obtain the pre-decoding information of the command to be transmitted; the pre-decoding information includes: waiting period.

[0067] It should be noted that Table 2 below shows the pre-decoding information for each instruction. vld rdy resv op wcys Instr words info

[0068] In Table 2 above, vld (Verify Load) is mainly used for data loading verification to check whether the loaded data meets expectations or is valid.

[0069] `rdy(Ready, readiness information)` indicates that a device, data, or status is ready to proceed to the next step, ensuring the correct action is taken at the right time. `rdy` can also indicate whether the command removes data dependencies.

[0070] `resv` (Reserve) is used to reserve resources for a specific operation or data, indicating whether an instruction is reserved. When retrieving a jump instruction, `resv` also retrieves the subsequent instructions; these subsequent instructions are not executed until a decision is made regarding whether to jump, and are discarded if not executed.

[0071] op(Operation, operation information) is used to indicate the operation type.

[0072] wcys(wait cycles) represents the number of cycles that an instruction needs to wait for.

[0073] The `info` instr words indicate other relevant information about the command, which does not affect the launch.

[0074] Step S402: When the waiting period for the launch command reaches the corresponding waiting period, launch the launch command.

[0075] In this embodiment, the compiler can set corresponding data dependencies and wait cycles for each instruction while compiling the instruction sequence. The data dependency of an instruction means that the execution of that instruction depends on the results of other instructions. The wait cycle of an instruction represents the number of cycles that the instruction needs to wait before being issued; that is, the instruction needs to wait for a certain number of cycles before being issued.

[0076] It should be noted that when the execution thread enters the ready state, the instruction processing unit can retrieve the instructions that the instruction to be issued depends on from the instruction register. If the results of the instructions that the instruction to be issued depends on can be retrieved, the instruction to be issued can be de-data dependent. However, since the process of retrieving instructions takes time, waiting to de-data depend before issuing the instruction to be issued is not conducive to improving the issuance efficiency.

[0077] In some embodiments of this application, the waiting period for a command to be launched is set based on the data dependency of the command. The command to be launched does not have preparation information (rdy), where preparation information indicates whether the data dependency has been released.

[0078] In other words, in this embodiment, the number of cycles to wait can be set based on the data dependency of each instruction; at the same time, the rdy of the instruction to be issued can be left unset. In this way, when the instruction to be issued reaches the corresponding number of cycles to wait, the instruction to be issued can be issued in advance, thereby improving the issuance efficiency and the utilization rate of the instruction pipeline.

[0079] In this embodiment, it can be determined whether to transmit based on the pre-decoding information of the command to be transmitted. If the rdy characterization of the command to be transmitted indicates data dedependency removal, and the number of cycles the command has been waiting for reaches wcys, then the command to be transmitted can be transmitted. On the other hand, the rdy characterization of the command to be transmitted can be omitted, so that if the number of cycles the command has been waiting for reaches wcys, the command to be transmitted can still be transmitted.

[0080] For example, for the following instructions a, b, c, and d: FADD.wcys0 R0, R1, R2 / / Instruction a; FADD.wcys0 R3, R4, R5 / / Command b; FMA.wcys5 R6, R7, R8, R9 / / Command c; FADD.wcys0 R1, R9, R6 / / Command d.

[0081] Instruction a represents writing R1+R2 into R0; instruction b represents writing R4+R5 into R3; instruction c represents writing R7+R8*R9 into R6; and instruction d represents writing R9+R6 into R1.

[0082] Since the data of instruction d depends on the execution result R6 of instruction c, if the fence dependency mechanism is used for detection, it is necessary to wait for R6 to be written into the general data register, then remove the data dependency of instruction d, and then select to issue instruction d. In this way, it takes about 8 cycles to issue instruction d.

[0083] However, with the introduction of the wcys mechanism, instruction c sets the wcys5 signal during the compilation phase. When there are no other dependencies or emission issues, instruction d, which depends on instruction c, can be emitted as long as the wcys5 signal is satisfied (that is, only 5 cycles need to be waited). This reduces 3 waiting cycles and improves the utilization of the instruction pipeline.

[0084] Figure 6 is a schematic diagram of the composition structure of an instruction processing device provided in an embodiment of this application. As shown in Figure 6, the instruction processing device 800 includes: a thread controller 810, multiple send paths 820, and multiple pipelined execution units 830. The first ends of the multiple send paths 820 are all electrically connected to the thread controller 810; each pipelined execution unit 830 is electrically connected to the second end of at least one corresponding send path 820; and the thread controller 810 is electrically connected to the thread bundle.

[0085] In some embodiments of this application, referring to FIG7, the thread controller 810 includes a first control module 811. The first control module 811 is configured to acquire a type percentage value of the instruction sequence; and, based on the type percentage value, determine the launch path 820 used for each type of instruction; and launch the instructions to be launched in the instruction sequence from the thread bundle, via the corresponding launch path 820, to the corresponding pipeline execution unit 830. Each type percentage value represents the proportion of a corresponding type of instruction in the instruction sequence.

[0086] In this embodiment, the first control module 811 can configure a corresponding transmission path 820 for each type of instruction based on the type ratio value; in this way, different types of instructions can be transmitted in parallel; thus, congestion in a single path will not block instructions in other paths, thereby improving the efficiency of instruction transmission.

[0087] In some embodiments of this application, continuing to refer to FIG7, the thread controller 810 further includes a second control module 812. The second control module 812 is configured to retrieve instructions from the instruction register to the thread; and to decode the retrieved instructions.

[0088] In this embodiment, the first control module 811 is used to control the transmission of commands, while the second control module 812 is used to retrieve and decode commands. That is, the first control module 811 and the second control module 812 in the thread controller 810 are designed as separate structures; the first control module 811 and the second control module 812 can operate independently without affecting each other.

[0089] In other words, if there is sufficient space in the execution thread and no problems such as "missing instruction buffer lines, ambiguous jump addresses, or failure to reach the end instruction" occur, the second control module 812 can continuously retrieve instructions until the execution thread ends. Correspondingly, the first control module 811 only needs to check "whether data dependencies have been released, whether the waiting period has been reached, and whether the transmit enable is enabled" to select the corresponding transmit instruction from the instruction sequence for transmission.

[0090] It is understandable that the first control module 811 and the second control module 812 are designed as separate structures; in this way, the first control module 811, which is used to transmit commands, and the second control module 812, which is used to retrieve commands and decode them, can operate independently; thereby avoiding mutual interference and improving their respective operating efficiency.

[0091] In some embodiments of this application, the first control module 811 is further configured to determine that at least two types of instructions whose type proportion values ​​meet the merging conditions are to use the same transmission path 820.

[0092] In some embodiments of this application, the first control module 811 is further configured to determine that the first instruction and other types of instructions use the same transmission path 820 if the type proportion value of the first instruction is lower than a threshold; and / or, if the type proportion values ​​of the second instruction and the third instruction are both higher than the threshold, and neither the second instruction nor the third instruction is the highest instruction, then the second instruction and the third instruction are determined to use the same transmission path 820; wherein, the type proportion value of the highest instruction is the highest.

[0093] It is understandable that instructions that meet the merging conditions are merged using the same transmit path; in this way, while ensuring instruction transmission efficiency, the number of transmit paths occupied can be reduced; thus, resource consumption can be saved and power consumption reduced.

[0094] In some embodiments of this application, the first control module 811 is further configured to count the number of occurrences of each type of instruction in the instruction sequence after the instruction sequence is compiled; and to calculate the type percentage based on the number of occurrences of each type of instruction.

[0095] Understandably, this involves counting the occurrences of each type of instruction in the instruction sequence and calculating the type percentage. This provides a more accurate type percentage, reflecting the true proportion of each type of instruction in the instruction sequence, and thus enabling more precise allocation of launch paths for each type of instruction.

[0096] In some embodiments of this application, the first control module 811 is also configured to determine the type proportion of the instruction sequence based on historical data.

[0097] It is understandable that using historical data on type percentages as the type percentages for the current instruction sequence avoids the need for real-time calculation of the type percentages for the instruction sequence, saving time and thus improving the efficiency of instruction issuance.

[0098] In some embodiments of this application, referring to FIG8, each transmission path 820 is provided with a configuration register 840. The first control module 811 is also configured to configure type information for the instruction to be transmitted based on the type ratio value; and to compare the type information with the information in the configuration register 840 of each transmission path 820. If the comparison result is a match, the instruction to be transmitted is stored in the corresponding configuration register 840.

[0099] In this embodiment, the driver pre-configures the type information of multiple transmit paths 820 in the configuration register 840, that is, the information of the configuration register 840; then, the thread controller 810 can compare the type information of the instruction to be transmitted (i.e., the op information in Table 2) with the information of the configuration register 840. If the comparison result is a match, the matching instruction to be transmitted is selected and stored in the corresponding configuration register 840, that is, the instruction to be transmitted is passed to the corresponding transmit path 820.

[0100] Figure 9 illustrates an optional structure of the instruction processing device 800. As shown in Figure 9, the instruction processing device 800 includes: an ALU issue path 821, a stream processor-internal vector issue path 822, a stream processor-external vector issue path 823, a matrix instruction issue path 824, and a scalar instruction issue path 825. The instruction processing device 800 also includes: a floating-point ALU pipelined execution unit 831, an integer ALU pipelined execution unit 832, a stream processor-internal pipelined execution unit 833, a stream processor-external pipelined execution unit 834, a matrix instruction pipelined execution unit 835, a control instruction pipelined execution unit 836, and a scalar instruction pipelined execution unit 837.

[0101] Referring to Figure 9 and Table 1, the floating-point ALU pipelined execution unit 831 is used to execute floating-point type instructions FP32, which can be issued via ALU issue path 821. The integer ALU pipelined execution unit 832 is used to execute integer instructions INT32, which can be issued via ALU issue path 821 or the stream processor's internal vector issue path 822. Bit manipulation type instructions (BIT) can also be issued via ALU issue path 821 or the stream processor's internal vector issue path 822.

[0102] Other instructions in Table 1 may include: stream processor in-vector instructions, stream processor out-vector instructions, matrix instructions, and scalar instructions. These other instructions are also passed to the corresponding pipeline execution units via the corresponding issue paths shown in Figure 9.

[0103] In some embodiments of this application, referring to FIG7, the first control module 811 is further configured to acquire pre-decoding information of a command to be transmitted; wherein the pre-decoding information includes: a waiting period; and, when the command to be transmitted reaches the corresponding waiting period, to transmit the command to be transmitted.

[0104] In some embodiments of this application, the waiting period for the command to be launched is set based on the data dependency of the command to be launched; the command to be launched does not have preparation information, wherein the preparation information indicates whether the data dependency is released.

[0105] In this embodiment, the waiting period can be set based on the data dependency of each instruction. When the instruction to be transmitted reaches the corresponding waiting period, the instruction to be transmitted can be transmitted in advance, thereby improving transmission efficiency and the utilization rate of the instruction pipeline.

[0106] In some embodiments of this application, referring to FIG7, the first control module 811 is also configured to receive and respond to an execution bundle transmit enable signal, continuously transmit the instruction to be transmitted in the execution bundle, or suspend the transmission of the instruction to be transmitted in the execution bundle.

[0107] In this embodiment of the application, the transmit enable signal is used to control whether the instructions in the execution bundle can be transmitted; if the transmit enable signal is turned on, the execution bundle is in an enabled state, and the instructions in the execution bundle can be transmitted; if the transmit enable signal is turned off, the execution bundle is in an disabled state, and the instructions in the execution bundle are suspended from being transmitted.

[0108] For example, if the program is set to wait 5 seconds for a Sleep, then during these 5 seconds, the transmit enable signal is turned off, and the instructions in the execution sequence will not be transmitted temporarily; when the required 5-second wait is completed, the transmit enable signal is turned on, and the instruction sequence in the execution sequence can re-enter the selectable transmit state.

[0109] It should be noted that the transmit enable signal of an execution thread is used to control whether the current execution thread can continue to transmit commands. When the execution thread itself does not depend on cycle wait or data dependency wait, but depends on other factors that require pausing transmission, the transmit enable signal can be used to control the execution thread to be in an enabled state. In other cases, as long as the execution thread is valid, it will always be in an enabled state.

[0110] However, when a jump instruction is issued, the subsequent jump path cannot be known until execution is complete. In this case, the issue enable signal needs to be disabled. Additionally, when issuing a mutex instruction to acquire a mutex semaphore, if it is not acquired, the issue enable signal must also be disabled to prevent subsequent instructions from being issued. Other related instructions include the sleep instruction, synchronous wait instructions, overlapped safety check instructions, and instructions to wait for output buffer completion.

[0111] It is understandable that by transmitting an enable signal to control the state of the execution thread, instruction transmission can be paused in a timely manner as needed to avoid errors in instruction execution.

[0112] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. In some embodiments, the functions or modules included in the device provided in this application can be used to execute the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0113] It should be noted that, in the embodiments of this application, if the above-described instruction processing method is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard disks, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0114] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0115] This application provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0116] This application provides a computer program including computer-readable code. When the computer-readable code is run in a computer device, the processor in the computer device executes some or all of the steps in the above method.

[0117] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0118] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0119] Figure 10 is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. As shown in Figure 10, the hardware entity of the computer device 1100 includes a processor 1101 and a memory 1102. The memory 1102 stores a computer program that can run on the processor 1101. When the processor 1101 executes the program, it implements the steps in the method of any of the above embodiments.

[0120] The memory 1102 stores computer programs that can run on the processor. The memory 1102 is configured to store instructions and applications that can be executed by the processor 1101. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data and video communication data) in the processor 1101 and various modules in the computer device 1100. This can be achieved through flash memory or random access memory (RAM).

[0121] The processor 1101 executes the instruction processing steps of any of the above-mentioned methods when executing a program. The processor 1101 typically controls the overall operation of the computer device 1100.

[0122] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the instruction processing method as described in any of the above embodiments.

[0123] It should be noted that the descriptions of the storage media and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage media and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0124] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0125] The aforementioned computer storage media / memory can be Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory, optical discs, or Compact Disc Read-Only Memory (CD-ROM), etc.; it can also be various terminals that include one or any combination of the above-mentioned memory types, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0126] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0127] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0128] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or elements can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interface, and the indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0129] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0130] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0131] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as removable storage devices, ROMs, magnetic disks, or optical disks.

[0132] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0133] 800: Instruction Processing Unit 810: Thread Controller 811: First Control Module 812: Second Control Module 820: Launch Path 821: ALU Transmission Path 822: Stream Processor Intra-Vectored Issue Path 823: Stream Processor Outer Vector Emit Path 824: Matrix Command Issuance Path 825: Scalar command issuance path 830: Pipeline Execution Unit 831: Floating-point ALU Pipeline Execution Unit 832: Integer ALU Pipeline Execution Unit 833: Pipeline Execution Unit within a Stream Processor 834: Stream Processor External Pipeline Execution Unit 835: Matrix Instruction Pipeline Execution Unit 836: Control Command Pipeline Execution Unit 837: Scalar Instruction Pipeline Execution Unit 840: Configuration Register 1100: Computer Equipment 1101: Processor 1102: Memory S101, S102, S103, S201, S202, S203, S301, S302, S303, S401, S402: Steps

Claims

1. An instruction processing method, applied to an instruction processing device, the instruction processing method comprising: Obtain the type percentage value of the instruction sequence; wherein each type percentage value represents the proportion of a corresponding type of instruction in the instruction sequence; determine the launch path used by the instruction of each type based on the type percentage value; and launch the instruction to be launched in the instruction sequence to the corresponding pipeline execution unit via the corresponding launch path, wherein determining the launch path used by the instruction of each type based on the type percentage value includes: if the type percentage value of the first instruction is lower than a threshold, then the first instruction and the instructions of other types are determined to use the same launch path; and / or, if the type percentage values ​​of the second instruction and the third instruction are both higher than the threshold, and the second instruction and the third instruction are not the highest instruction, then the second instruction and the third instruction are determined to use the same launch path; wherein the highest instruction has the highest type percentage value.

2. The instruction processing method as described in claim 1, wherein, Obtaining the type percentage of the instruction sequence includes: after the instruction sequence is compiled, counting the number of times each type of instruction appears in the instruction sequence; and calculating the type percentage based on the number of times each type of instruction appears.

3. The instruction processing method as described in claim 1, wherein, Obtaining the type percentage value of the instruction sequence further includes: determining the type percentage value of the instruction sequence based on historical data.

4. The instruction processing method as described in claim 1, wherein sending the instruction to be sent to the corresponding pipeline execution unit includes: Obtain the pre-decoding information of the command to be transmitted; The pre-decoding information includes: a waiting period; the waiting period represents the number of periods that the command to be launched needs to wait before it is launched; and the command to be launched is launched when the command to be launched reaches the corresponding waiting period.

5. The instruction processing method as described in claim 4, wherein the waiting period of the instruction to be transmitted is set based on the data dependency of the instruction to be transmitted; and the instruction to be transmitted does not have preparation information set, wherein, The prepared information indicates whether data dependency has been removed.

6. An instruction processing apparatus, wherein the instruction processing apparatus comprises: The system comprises a thread controller, multiple emitter paths, and multiple pipelined execution units; wherein the first ends of each of the multiple emitter paths are electrically connected to the thread controller; each pipelined execution unit is electrically connected to the second end of at least one corresponding emitter path; the thread controller is electrically connected to an execution thread bundle; the thread controller includes: a first control module configured to acquire a type percentage value of an instruction sequence, and based on the type percentage value, determine the emitter path used for each type of instruction, and emit the instruction to be emitted from the execution thread bundle, via the corresponding emitter path, to the corresponding pipelined execution unit; wherein each type percentage value represents the proportion of an instruction of a corresponding type in the instruction sequence; The first control module is further configured to determine that if the type proportion value of the first instruction is lower than a threshold, the first instruction and other types of instructions are used to adopt the same transmission path; and / or, if the type proportion values ​​of the second instruction and the third instruction are both higher than the threshold, and neither the second instruction nor the third instruction is the highest instruction, the second instruction and the third instruction are determined to adopt the same transmission path; wherein the type proportion value of the highest instruction is the highest.

7. The instruction processing apparatus of claim 6, wherein the thread controller further comprises: Second control module; The second control module is configured to retrieve the instruction from the instruction register to the execution thread, and to decode the retrieved instruction.

8. The instruction processing apparatus of claim 6, wherein each of the transmission paths is provided with a configuration register; the first control module is further configured to configure type information for the instruction to be transmitted based on the type percentage value; and to compare the type information with information in the configuration register of each of the transmission paths, and if the comparison result is a match, to store the instruction to be transmitted into the corresponding configuration register.

9. The instruction processing apparatus as claimed in claim 6, wherein the first control module is further configured to acquire pre-decoding information of the instruction to be transmitted; The pre-decoding information includes: Waiting period; And when the pending launch command reaches the corresponding waiting period, the pending launch command is launched.

10. The instruction processing apparatus of claim 6, wherein the first control module is further configured to receive and respond to an execution bundle transmit enable signal to continuously transmit the instruction to be transmitted in the execution bundle, or to suspend the transmission of the instruction to be transmitted in the execution bundle.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the steps of the instruction processing method described in any one of requests 1 to 5.

12. A computer device comprising the instruction processing apparatus described in any one of claims 6 to 10.

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