Camera device and light receiving element

Abstract

An imaging device according to one embodiment of the present disclosure includes: a first semiconductor layer having a photoelectric conversion unit and a charge accumulation unit for accumulating signal charges generated by the photoelectric conversion unit in each pixel; a second semiconductor layer stacked on the first semiconductor layer, including a first surface of a pixel transistor having a three-dimensional structure and reading signal charges from the charge accumulation unit; and a through wiring that directly connects the charge accumulation unit to the gate electrode of the pixel transistor.

Description

[Technical Field]

[0001] This disclosure relates to a camera device and light-receiving element having a three-dimensional structure. [Previous Technology]

[0002] For example, Patent Document 1 discloses an imaging element that laminates a first substrate having sensor pixels for photoelectric conversion and a second substrate having readout circuitry, wherein the first substrate and the second substrate are electrically connected to each other by through wiring disposed within an interlayer insulating film. [Prior Art Documents] [Patent Documents]

[0003] Patent Document 1: International Publication No. 2019 / 131965 [Summary of the Invention]

[0004] However, in the three-dimensional imaging element as described above, it is sought to improve the area efficiency of the second substrate forming the readout circuit.

[0005] It is desirable to provide a camera device that can improve area efficiency.

[0006] An imaging device according to one embodiment of the present disclosure includes: a first semiconductor layer having a photoelectric conversion unit and a charge accumulation unit for accumulating signal charges generated by the photoelectric conversion unit in each pixel; a second semiconductor layer stacked on the first semiconductor layer, including a first surface of a pixel transistor having a three-dimensional structure and reading signal charges from the charge accumulation unit; and a through wiring that directly connects the charge accumulation unit to the gate electrode of the pixel transistor.

[0007] One embodiment of the light-receiving element disclosed herein includes: a first semiconductor layer having a photoelectric conversion section and a charge accumulation section for accumulating signal charges generated by the photoelectric conversion section; a second semiconductor layer deposited on the first semiconductor layer, including a first surface of a transistor having a three-dimensional structure and reading signal charges from the charge accumulation section; and a through wiring that directly connects the charge accumulation section to the gate electrode of the transistor.

[0008] In one embodiment of the imaging device and another embodiment of the light-receiving element disclosed herein, a charge accumulation portion disposed on a first semiconductor layer is directly connected to a pixel transistor with a three-dimensional structure disposed on a second semiconductor layer via a through wiring. This reduces the area formed outside the pixel transistor within the plane of the second semiconductor layer.

Implementation Method

[0010] Hereinafter, one embodiment of this disclosure will be described in detail with reference to the drawings. The following description is a specific example of this disclosure, and this disclosure is not limited to the following embodiment. Furthermore, the arrangement, size, size ratio, etc. of the constituent elements shown in the figures of this disclosure are not limited to these. In addition, the order of description is as follows. 1. First Embodiment (Example 1 of an imaging device having a multilayer structure of three substrates, in which a floating diffusion region and an amplifying transistor are directly connected by a through-wire) 2. Variation 2-1. Variation 1 (Another example of the structure of the first substrate side) 2-2. Variation 2 (Another example 1 of the structure of a pixel transistor) 2-3. Variation 3 (Another example 2 of the structure of a pixel transistor) 2-4. Variation 4 (Another example of the connection method between the floating diffusion region and the amplifying transistor) 2-5. Variation 5 (Another example of the connection method between the floating diffusion region and the amplifying transistor) 2-6. Variation 6 (Another example of the structure of a through-wire connecting the floating diffusion region and the amplifying transistor) 2-7. Variation 7 (Another example of the connection method between transistors within a pixel circuit) 2-8. Variation 8 (An example of a method for manufacturing a transistor with a fin structure) 3. Second Embodiment (Example 2 of an imaging device having a multilayer structure of three substrates, in which the floating diffusion region and the amplifying transistor are directly connected by a through-wire) 4. Variation 4-1. Variation 9 (Another example 1 of the structure of the amplifying transistor) 4-2. Variation 10 (Another example 2 of the structure of the amplifying transistor) 4-3. Variation 11 (Another example 3 of the structure of the amplifying transistor) 5. Variation 12 (Example 1 of a planar configuration) 6. Variation 13 (Example 2 of a planar configuration) 7. Variation 14 (Example 3 of a planar configuration) 8. Variation 15 (Example of having a contact portion between substrates in the central portion of the pixel array section) 9. Variation 16 (Example of having a planar transmission transistor) 10. Variation 17 (Example of connecting one pixel to one pixel circuit) 11. Variation 18 (Example of the structure of the pixel separation section) 12. Variation 19 (Another example of a method for connecting the floating diffusion region and the amplifying transistor) 13. Variation Example 20 (Example of directly connecting the floating diffusion region and the reset transistor through wiring) 14. Variation Example 21 (Example of electrically connecting transistors at the same potential using polysilicon wiring) 15. Variation Example 22 (Example of separately forming multiple transistors constituting the pixel circuit on two semiconductor layers of a multilayer stack) 16. Application Example (Camera System) 17. Application Example

[0011] <1. First Embodiment> [Functional Configuration of Camera Device 1] FIG1 is a block diagram showing an example of the functional configuration of the camera device (camera device 1) according to the first embodiment of the present disclosure.

[0012] The camera device 1 in FIG1 includes, for example, an input unit 510A, a column drive unit 520, a timing control unit 530, a pixel array unit 540, a row signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0013] The pixel array section 540 has pixels 541 arranged in an array. More specifically, the pixel sharing unit 539, which contains a plurality of pixels, is a repeating unit, and is arranged in an array including the column direction and the row direction. In addition, for convenience, in this specification, the column direction is referred to as the H direction and the row direction orthogonal to the column direction is referred to as the V direction. In the example of FIG1, one pixel sharing unit 539 contains four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (shown in FIG6, etc., described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG4, described later). In other words, there is one pixel circuit (pixel circuit 210, described later) for every four pixels (pixels 541A, 541B, 541C, and 541D). By causing the pixel circuit to operate in a time-division multiplexing manner, the pixel signals of pixels 541A, 541B, 541C, and 541D are read out sequentially. Pixels 541A, 541B, 541C, and 541D are arranged, for example, in a 2-column × 2-row configuration. In the pixel array section 540, along with pixels 541A, 541B, 541C, and 541D, a plurality of column drive signal lines 542 and a plurality of vertical signal lines (row readout lines) 543 are provided. The column drive signal lines 542 drive the pixels 541 contained in each of the plurality of pixel shared units 539 arranged side-by-side in the column direction within the pixel array section 540. They also drive the pixels arranged side-by-side in the column direction within the pixel shared units 539. The following detailed description refers to FIG4, but a plurality of transistors are provided in the pixel shared unit 539. To drive the plurality of transistors respectively, a plurality of rows of drive signal lines 542 are connected to a pixel shared unit 539. The pixel shared unit 539 is connected to a vertical signal line (row readout line) 543. Pixel signals are read from each of the pixels 541A, 541B, 541C, and 541D contained in the pixel shared unit 539 via the vertical signal line (row readout line) 543.

[0014] The column driver unit 520 includes, for example, a column address control unit that determines the position of the column used for pixel driving, in other words, a column decoder unit, and a column driver circuit unit that generates signals for driving pixels 541A, 541B, 541C, and 541D.

[0015] The horizontal signal processing unit 550 includes a load circuit section connected to, for example, the vertical signal line 543, and forming a source follower circuit with pixels 541A, 541B, 541C, and 541D (pixel common unit 539). The horizontal signal processing unit 550 may also include an amplification circuit section that amplifies the signal read from the pixel common unit 539 via the vertical signal line 543. The horizontal signal processing unit 550 may also include a noise processing section. In the noise processing section, for example, the system noise level is removed from the signal read from the pixel common unit 539 as a result of photoelectric conversion.

[0016] The line signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, a signal read from the pixel common unit 539 or an analog signal processed by the aforementioned noise reduction is converted into a digital signal. The ADC includes, for example, a converter section and a counter section. In the converter section, the analog signal to be converted is compared with a reference signal to be compared. In the counter section, the time until the comparison result of the converter section reverses is measured. The line signal processing unit 550 may also include a horizontal scanning circuit section for controlling the scanning readout lines.

[0017] The timing control unit 530 supplies control timing signals to the column drive unit 520 and the row signal processing unit 550 based on the reference clock signal or timing control signal input to the device.

[0018] The image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging action of the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0019] One example of signal processing performed in the image signal processing unit 560 is tone curve correction processing. When the image data converted from an analog-to-digital converter (AD converter) is data depicting a dark subject, it aims to increase the grayscale level; when the image data converted from an AD converter is data depicting a bright subject, it aims to decrease the grayscale level. In this case, it is desirable to determine the tone curve used to correct the grayscale level of the image data, or to pre-memorize the characteristic data of the tone curve in the data storage unit of the image signal processing unit 560.

[0020] The input unit 510A is used, for example, to input the aforementioned reference clock signal, timing control signal, and characteristic data from outside the device to the camera device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, used to store in the data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0021] Input terminal 511 is an external terminal for inputting data. Input circuit section 512 is used to capture the signal input to input terminal 511 and transmit it to the internal storage of the imaging device 1. In input amplitude conversion section 513, the amplitude of the signal captured by input circuit section 512 is converted into an amplitude that is easily utilized within the imaging device 1. In input data conversion circuit section 514, the arrangement of the data rows of the input data is changed. Input data conversion circuit section 514 is, for example, configured as a serial-to-parallel conversion circuit. In this serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Alternatively, input amplitude conversion section 513 and input data conversion circuit section 514 may be omitted from input section 510A. Power supply section supplies power of various voltages required by the internal storage of the imaging device 1 based on the power supplied from the outside to the imaging device 1.

[0022] When the camera device 1 is connected to an external memory device, a memory interface circuit for receiving data from the external memory device may also be provided in the input section 510A. The external memory device may be, for example, flash memory, SRAM (Static Random-Access Memory), and DRAM (Dynamic Random Access Memory).

[0023] The output unit 510B outputs image data to the outside of the device. The image data may be, for example, image data captured by the camera device 1, or image data processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude conversion unit 516, an output circuit unit 517, and an output terminal 518.

[0024] The output data conversion circuit 515 is, for example, composed of a parallel-to-serial conversion circuit. In the output data conversion circuit 515, the parallel signal used inside the imaging device 1 is converted into a serial signal. The output amplitude changing unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude becomes easier to use in external devices connected to the outside of the imaging device 1. The output circuit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device. The output circuit 517 drives the wiring outside the imaging device 1 connected to the output terminal 518. Data is output from the imaging device 1 to the outside of the device through the output terminal 518. In the output unit 510B, the output data conversion circuit 515 and the output amplitude changing unit 516 may also be omitted.

[0025] When the camera device 1 is connected to an external memory device, a memory interface circuit for outputting data to the external memory device may also be provided in the output section 510B. The external memory device may be, for example, flash memory, SRAM and DRAM.

[0026] [Schematic Configuration of Camera Device 1] Figures 2 and 3 show an example of the schematic configuration of camera device 1. Camera device 1 includes three substrates (first substrate 100, second substrate 200, and third substrate 300). Figure 2 schematically shows the planar configuration of each of the first substrate 100, second substrate 200, and third substrate 300, and Figure 3 schematically shows the cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 stacked together. Figure 3 corresponds to the cross-sectional configuration along line III-III' shown in Figure 2. Camera device 1 is a three-dimensional camera device constructed by bonding the three substrates (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. For convenience, the wiring and surrounding interlayer insulating film of each of the first substrate 100, the second substrate 200, and the third substrate 300 are collectively referred to as wiring layers (100T, 200T, 300T) disposed on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are sequentially stacked, and semiconductor layer 100S, wiring layer 100T, semiconductor layer 200S, wiring layer 200T, wiring layer 300T, and semiconductor layer 300S are sequentially arranged along the stacking direction. The specific configuration of the first substrate 100, the second substrate 200, and the third substrate 300 is described below. The arrows shown in Figure 3 indicate the incident direction of light L towards the imaging device 1. In this specification, for convenience, the light-incident side of the imaging device 1 is referred to as "lower," "lower side," or "below" in the following cross-sectional views, and the side opposite to the light-incident side is referred to as "upper," "upper side," or "above." Furthermore, for convenience, for a substrate having a semiconductor layer and a wiring layer, the wiring layer side is referred to as the front side, and the semiconductor layer side is referred to as the back side. However, the description in this specification is not limited to the above-mentioned naming methods. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of a first substrate 100 having a photodiode.

[0027] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using the first substrate 100 and the second substrate 200. On the first substrate 100, a plurality of pixels 541A, 541B, 541C, and 541D of the pixel sharing unit 539 are provided. Each of these pixels 541 has a photodiode (PD, described later) and a transmission transistor (TR, described later). On the second substrate 200, a pixel circuit (pixel circuit 210, described later) of the pixel sharing unit 539 is provided. The pixel circuit reads the pixel signals transmitted via the transmission transistor from the photodiodes of each of the pixels 541A, 541B, 541C, and 541D, or reconfigures the photodiodes. In addition to the pixel circuit, the second substrate 200 also has a plurality of column drive signal lines 542 extending in the column direction and a plurality of vertical signal lines 543 extending in the row direction. The second substrate 200 further has power lines 544 extending in the column direction (such as power lines VDD described later). The third substrate 300 has, for example, an input section 510A, a column drive section 520, a timing control section 530, a row signal processing section 550, an image signal processing section 560, and an output section 510B. The column drive section 520 is disposed in a region overlapping with the pixel array section 540 in, for example, the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the column drive section 520 is disposed in a region overlapping with the end of the pixel array section 540 in the H direction in the stacking direction (FIG. 2). The line signal processing unit 550 is disposed in a region overlapping with the pixel array unit 540, for example, in the stacking direction. More specifically, the line signal driving unit 550 is disposed in a region overlapping with the V-direction end of the pixel array unit 540 in the stacking direction (FIG. 2). Although not shown in the figure, the input unit 510A and the output unit 510B can be disposed in a portion other than the third substrate 300, or they can be disposed on, for example, the second substrate 200. Alternatively, the input unit 510A and the output unit 510B can be disposed on the back side (light incident surface) of the first substrate 100. In addition, the pixel circuit disposed on the second substrate 200 is sometimes referred to by other names such as pixel transistor circuit, pixel transistor group, pixel transistor, pixel readout circuit, or readout circuit. In this specification, the term pixel circuit is used.

[0028] The first substrate 100 and the second substrate 200 are electrically connected, for example, by through electrodes (through electrodes 120E and 121E in FIG. 6 described later). The second substrate 200 and the third substrate 300 are electrically connected, for example, via contact portions 201, 202, 301, and 302. Contact portions 201 and 202 are provided on the second substrate 200, and contact portions 301 and 302 are provided on the third substrate 300. Contact portion 201 of the second substrate 200 is connected to contact portion 301 of the third substrate 300, and contact portion 202 of the second substrate 200 is connected to contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R with a plurality of contact portions 201 and a contact region 202R with a plurality of contact portions 202. The third substrate 300 has a contact region 301R with a plurality of contact portions 301 and a contact region 302R with a plurality of contact portions 302. The contact regions 201R and 301R are disposed between the pixel array portion 540 and the column drive portion 520 in the stacking direction (Fig. 3). In other words, the contact regions 201R and 301R are disposed, for example, in the region where the column drive portion 520 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. The contact regions 201R and 301R are disposed at, for example, the ends in the H direction of such regions (Fig. 2). In the third substrate 300, for example, in a portion of the column drive portion 520, specifically, at a position overlapping with the end of the column drive portion 520 in the H direction, the contact region 301R is provided (Figs. 2 and 3). Contact portions 201 and 301 connect, for example, the column drive portion 520 disposed on the third substrate 300 and the column drive signal line 542 disposed on the second substrate 200. Contact portions 201 and 301 may also connect, for example, the input portion 510A disposed on the third substrate 300 to the power supply line 544 and the reference potential line (VSS described later). Contact regions 202R and 302R are disposed between the pixel array portion 540 and the horizontal signal drive portion 550 in the stacking direction (Fig. 3). In other words, contact regions 202R and 302R are disposed, for example, in the region where the horizontal signal processing portion 550 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlap in the stacking direction, or in a nearby region. Contact regions 202R and 302R are disposed at the V-direction end of such regions (Fig. 2). In the third substrate 300, for example, in a portion of the horizontal signal processing unit 550, specifically at a position overlapping with the V-direction end of the horizontal signal processing unit 550, a contact region 302R is provided (Figs. 2 and 3). The contact portions 202 and 302 are, for example, used to connect the pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion of the photodiode) output from each of the plurality of pixel common units 539 in the pixel array unit 540 to the horizontal signal processing unit 550 provided on the third substrate 300.The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0029] Figure 3 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, contact portions 201, 202, 301, and 302 are formed by electrodes made of conductive material. The conductive material is formed of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R can electrically connect the second substrate and the third substrate by, for example, directly joining the wiring formed as electrodes to each other, thereby inputting and / or outputting signals from the second substrate 200 and the third substrate 300.

[0030] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as shown in FIG3 as contact regions 201R, 202R, 301R, and 302R, it can also be provided in a region that overlaps with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion can be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it can also be provided in a region that overlaps with the peripheral portion disposed on the outer side of the pixel array portion 540 in the stacking direction.

[0031] Connection holes H1 and H2 are provided on the first substrate 100 and the second substrate 200. Connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 3). Connection holes H1 and H2 are disposed outside the pixel array portion 540 (or the portion overlapping with the pixel array portion 540) (FIG. 2). For example, connection hole H1 is disposed further outward than the pixel array portion 540 in the H direction, and connection hole H2 is disposed further outward than the pixel array portion 540 in the V direction. For example, connection hole H1 reaches the input portion 510A disposed on the third substrate 300, and connection hole H2 reaches the output portion 510B disposed on the third substrate 300. Connection holes H1 and H2 may be voids, or at least a portion of them may contain conductive material. For example, they are configured to connect bonding lines to electrodes formed as the input portion 510A and / or the output portion 510B. Alternatively, the configuration may include connecting electrodes formed as input portions 510A and / or output portions 510B to conductive materials disposed in connection holes H1 and H2. The conductive materials disposed in connection holes H1 and H2 may also be embedded in a portion or all of connection holes H1 and H2, and the conductive materials may also be formed on the sidewalls of connection holes H1 and H2.

[0032] Furthermore, Figure 3 shows a configuration where an input portion 510A and an output portion 510B are provided on the third substrate 300, but this is not a limitation. For example, the input portion 510A and / or the output portion 510B can be disposed on the second substrate 200 by transmitting signals from the third substrate 300 to the second substrate 200 via wiring layers 200T and 300T. Similarly, the input portion 510A and / or the output portion 510B can be disposed on the first substrate 100 by transmitting signals from the second substrate 200 to the first substrate 100 via wiring layers 100T and 200T.

[0033] Figure 4 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4, four pixels 541A, 541B, 541C, and 541D are shown), a pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically an amplifying transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 sequentially outputs the pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) contained in the pixel sharing unit 539 to the vertical signal line 543 by causing the pixel circuit 210 to operate in a time-division multiplexing manner. A pixel circuit 210 is connected to a plurality of pixels 541. The state in which the pixel signals of the plurality of pixels 541 are output in a time-division manner through a pixel circuit 210 is called "a plurality of pixels 541 sharing a pixel circuit 210".

[0034] Pixels 541A, 541B, 541C, and 541D share common constituent elements. Hereinafter, to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, an identification number 1 is assigned to the end of the symbol of the constituent element of pixel 541A, an identification number 2 is assigned to the end of the symbol of the constituent element of pixel 541B, an identification number 3 is assigned to the end of the symbol of the constituent element of pixel 541C, and an identification number 4 is assigned to the end of the symbol of the constituent element of pixel 541D. When it is not necessary to distinguish the constituent elements of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the symbols of the constituent elements of pixels 541A, 541B, 541C, and 541D are omitted.

[0035] Pixels 541A, 541B, 541C, and 541D have, for example, a photodiode PD, a transmission transistor TR electrically connected to the photodiode PD, and a floating diffusion region FD electrically connected to the transmission transistor TR. In the photodiode PD (PD1, PD2, PD3, PD4), the cathode is electrically connected to the source of the transmission transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on the incident light, generating a charge corresponding to the amount of light received. The transmission transistor TR (transmission transistors TR1, TR2, TR3, TR4) is, for example, an n-type CMOS (Complementary Metal Oxide Semiconductor) transistor. In the transmission transistor TR, the drain is electrically connected to the floating diffusion region FD, and the gate is electrically connected to a drive signal line. This drive signal line is connected to a portion of a plurality of drive signal lines 542 (see Figure 1) of a pixel common unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion region FD. The floating diffusion regions FD (FD1, FD2, FD3, FD4) are n-type diffusion layer regions formed in the p-type semiconductor layer. The floating diffusion regions FD are charge holding mechanisms that temporarily hold the charge transferred from the photodiode PD, and also charge-voltage conversion mechanisms that generate a voltage corresponding to the amount of charge.

[0036] The four floating diffusion regions FD (FD1, FD2, FD3, and FD4) contained in the pixel shared unit 539 are electrically connected to each other and electrically connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. This drive signal line is connected to a portion of the plurality of drive signal lines 542 of the pixel shared unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is connected to a portion of the plurality of drive signal lines 542 of the pixel shared unit 539. The gate of the amplifying transistor AMP is connected to the floating diffusion region FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line 543, and the gate of the select transistor SEL is connected to the drive signal line. This drive signal line is connected to a portion of the plurality of drive signal lines 542 of a pixel shared unit 539.

[0037] If the transmission transistor TR is in the ON state, the transmission transistor TR transfers the charge of the photodiode PD to the floating diffusion region FD. The gate (transmission gate TG) of the transmission transistor TR includes, for example, a so-called vertical electrode, as shown in FIG. 6 described later, extending from the front side of the semiconductor layer (semiconductor layer 100S in FIG. 6 described later) to the depth reaching the PD. The reset transistor RST resets the potential of the floating diffusion region FD to a specific potential. If the reset transistor RST is in the ON state, the potential of the floating diffusion region FD is reset to the potential of the power line VDD. The select transistor SEL controls the timing of the pixel signal output from the pixel circuit 210. The amplifying transistor AMP generates a signal of voltage corresponding to the charge level held in the floating diffusion region FD, as the pixel signal. The amplifying transistor AMP is connected to the vertical signal line 543 via the select transistor SEL. In the horizontal signal processing unit 550, the amplifying transistor AMP, together with the load circuit unit (see FIG. 1) connected to the vertical signal line 543, forms a source follower. If the selected transistor SEL is in the ON state, the amplifying transistor AMP outputs the voltage of the floating diffusion region FD to the horizontal signal processing unit 550 via the vertical signal line 543. The reset transistor RST, amplifying transistor AMP, and selected transistor SEL are, for example, N-type CMOS transistors.

[0038] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusion region FD. Generally, in low-light photography, the pixel signal is smaller. Based on Q=CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion region FD (FD capacitance C) is large, the voltage V converted by the amplifying transistor AMP will be smaller. On the other hand, in bright light, because the pixel signal is larger, if the FD capacitance C is not increased, the charge of the photodiode PD cannot be fully received in the floating diffusion region FD. Furthermore, in order to prevent the voltage V converted by the amplifying transistor AMP from being too large (in other words, to make it smaller), the FD capacitance C must be increased. In view of these circumstances, when the FD conversion gain switching transistor FDG is turned on, the overall FD capacitance C increases because the gate capacitance of part of the FDG is increased. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. Thus, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitor C can be varied, thereby allowing for switching of the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0039] Alternatively, the configuration may be without the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is configured with three transistors: an amplifying transistor AMP, a selecting transistor SEL, and a resetting transistor RST. The pixel circuit 210 has at least one of the pixel transistors, such as the amplifying transistor AMP, the selecting transistor SEL, the resetting transistor RST, and the FD conversion gain switching transistor FDG.

[0040] The select transistor SEL can also be positioned between the power supply line VDD and the amplifying transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifying transistor AMP, and the gate of the select transistor SEL is electrically connected to the column drive signal line 542 (see Figure 1). The source of the amplifying transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. Furthermore, although the illustration is omitted, the number of pixels 541 sharing one pixel circuit 210 can be more than four. For example, two or eight pixels 541 can also share one pixel circuit 210.

[0041] Figure 5 shows an example of the connection pattern of a plurality of shared pixel units 539 and vertical signal lines 543. For example, four shared pixel units 539 arranged in the row direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. In Figure 5, for the sake of simplicity, an example is shown where each of the four groups has one shared pixel unit 539, but each of the four groups may also contain a plurality of shared pixel units 539. Thus, in the imaging device 1, a plurality of shared pixel units 539 arranged in the row direction can be divided into groups containing one or a plurality of shared pixel units 539. For example, a vertical signal line 543 and a row signal processing unit 550 are connected to each of these groups, and pixel signals can be read from each group simultaneously. Alternatively, in the imaging device 1, a single vertical signal line 543 may be connected to a plurality of shared pixel units 539 arranged in the row direction. At this time, the pixel signals are read out sequentially from the plurality of pixel shared units 539 connected to a vertical signal line 543 in a time-division manner.

[0042] [Specific Configuration of Imaging Device 1] Figure 6 shows an example of the cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 in a direction perpendicular to the main surface. Figure 6 is a schematic display for easy understanding of the positional relationship of the constituent elements and may differ from the actual cross-section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are sequentially stacked. The imaging device 1 further has a light-receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may also be provided between the light-receiving lens 401 and the first substrate 100. The light-receiving lens 401 is provided in, for example, pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The camera device 1 has a pixel array section 540 disposed in the center and a peripheral section 540B disposed outside the pixel array section 540.

[0043] The first substrate 100, starting from the light-receiving lens 401 side, sequentially comprises an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. For example, the semiconductor layer 100S has a p-well layer 115 in a portion of its front side (the side of the wiring layer 100T) and its vicinity, and an n-type semiconductor region 114 in the remaining area (the region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn-junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0044] FIG. 7A shows an example of the planar configuration of the first substrate 100. FIG. 7A mainly shows the planar configuration of the pixel separation section 117, photodiode PD, floating diffusion region FD, VSS contact area 118 and transmission transistor TR of the first substrate 100. The configuration of the first substrate 100 will be explained using FIG. 6 and FIG. 7A.

[0045] Near the front side of the semiconductor layer 100S, a floating diffusion region FD and a VSS contact region 118 are provided. The floating diffusion region FD is composed of an n-type semiconductor region disposed within the p-well layer 115. The floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) of each of the pixels 541A, 541B, 541C, and 541D are disposed close to each other in the center of the pixel common unit 539 (Fig. 7A). Details are described below, but the four floating diffusion regions (floating diffusion regions FD1, FD2, FD3, and FD4) contained in the pixel common unit 539 are electrically connected to each other within the first substrate 100 (more specifically, within the wiring layer 100T) via an electrical connection mechanism (the pad portion 120 described later). Furthermore, the floating diffusion region FD is connected from the first substrate to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical mechanism (the through electrode 120E described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion region FD is electrically connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG via this electrical mechanism.

[0046] The VSS contact region 118 is electrically connected to the reference potential line VSS and is configured separately from the floating diffusion region FD. For example, in pixels 541A, 541B, 541C, and 541D, a floating diffusion region FD is configured at one end of the V direction of each pixel, and a VSS contact region 118 is configured at the other end (FIG. 7A). The VSS contact region 118 is composed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Thereby, a reference potential is supplied to the semiconductor layer 100S.

[0047] A transmission transistor TR is provided on the first substrate 100 together with a photodiode PD, a floating diffusion region FD, and a VSS contact region 118. The photodiode PD, floating diffusion region FD, VSS contact region 118, and transmission transistor TR are disposed in pixels 541A, 541B, 541C, and 541D. The transmission transistor TR is disposed on the front side of the semiconductor layer 100S (opposite to the light incident surface side, on the second substrate 200 side). The transmission transistor TR has a transmission gate TG. The transmission gate TG includes, for example, a horizontal portion TGb facing the front side of the semiconductor layer 100S, and a vertical portion TGa disposed within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is connected to the horizontal portion TGb, and the other end is disposed within the n-type semiconductor region 114. By using a vertically oriented transistor (TR) to transmit the signal, pixel signal transmission defects are less likely to occur, thus improving the readout efficiency of the pixel signal.

[0048] The horizontal portion TGb of the transmission gate TG extends towards the center of the pixel sharing unit 539 in the H direction from a position opposite to the vertical portion TGA (FIG. 7A). This allows the position in the H direction of the through electrode (through electrode TGV, described later) reaching the transmission gate TG to be close to the position in the H direction of the through electrode (through electrodes 120E, 121E, described later) connected to the floating diffusion region FD, VSS contact region 118. For example, a plurality of pixel sharing units 539 disposed on the first substrate 100 have the same configuration (FIG. 7A).

[0049] In the semiconductor layer 100S, a pixel separation portion 117 is provided to separate pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed extending in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel separation portion 117 is arranged to separate pixels 541A, 541B, 541C, and 541D from each other, and has a planar shape, for example, a grid shape (Figs. 7A and 7B). The pixel separation portion 117, for example, electrically and optically separates pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W). The insulating film 117B is disposed between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separation portion 117 has, for example, an FTI (Full Trench Isolation) structure that penetrates the semiconductor layer 100S. Although not shown, the pixel separation portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may also be a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0050] In the semiconductor layer 100S, there are, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is disposed near the back side of the semiconductor layer 100S, between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is disposed on the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are, for example, composed of a p-type semiconductor region.

[0051] A fixed charge film 112 with a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. By means of the electric field induced by the fixed charge film 112, a first pinning region 113 of a hole accumulation layer is formed at the interface on the light-receiving surface (back side) side of the semiconductor layer 100S. This suppresses the generation of dark current caused by the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed of, for example, an insulating film with a negative fixed charge. Examples of materials for the insulating film with the negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

[0052] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may also be continuously disposed with the light-shielding film 117A constituting the pixel separation section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively disposed, for example, at a position facing the pixel separation section 117 within the semiconductor layer 100S. The insulating film 111 is disposed to cover the light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0053] The wiring layer 100T disposed between the semiconductor layer 100S and the second substrate 200, starting from the semiconductor layer 100S side, sequentially comprises an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124. A horizontal portion TGb of the transmission gate TG is disposed on, for example, this wiring layer 100T. The interlayer insulating film 119 is disposed across the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. Furthermore, the configuration of the wiring layer 100T is not limited to the above; any configuration having wiring and an insulating film is acceptable.

[0054] Figure 7B, together with the planar configuration shown in Figure 7A, illustrates the configuration of the pad portions 120 and 121. The pad portions 120 and 121 are disposed in selective areas on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) of each of pixels 541A, 541B, 541C, and 541D to each other. For example, the pad portion 120 is disposed in the central portion of the pixel common unit 539 when viewed from above (Figure 7B). This pad portion 120 is disposed across the pixel separation portion 117 and overlaps with at least a portion of each of the floating diffusion regions FD1, FD2, FD3, and FD4 (Figures 6 and 7B). Specifically, the pad portion 120 is formed in a region overlapping with the front surface of the semiconductor layer 100S, relative to at least a portion of each of the plurality of floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, FD4) of the shared pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) of the shared pixel circuit 210. A connection via 120C is provided in the interlayer insulating film 119 for electrically connecting the pad portion 120 to the floating diffusion regions FD1, FD2, FD3, FD4. The connection via 120C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, by embedding a portion of the pad portion 120 into the connection via 120C, the pad portion 120 is electrically connected to the floating diffusion regions FD1, FD2, FD3, FD4.

[0055] The pad portion 121 is used to connect a plurality of VSS contact areas 118 to each other. For example, the VSS contact areas 118 of pixels 541C and 541D of adjacent pixel sharing units 539 in the V direction, and the VSS contact areas 118 of pixels 541A and 541B of another pixel sharing unit 539 are electrically connected by the pad portion 121. The pad portion 121 is arranged, for example, across the pixel separation portion 117, and overlaps with at least a portion of each of the four VSS contact areas 118. Specifically, the pad portion 121 is formed in a region that overlaps with at least a portion of each of the plurality of VSS contact areas 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact areas 118 in a direction perpendicular to the front side of the semiconductor layer 100S. A connection via 121C is provided on the interlayer insulating film 119 for electrically connecting the pad portion 121 to the VSS contact area 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, the pad portion 121 is electrically connected to the VSS contact area 118 by embedding a portion of the pad portion 121 into the connection via 121C. For example, the pad portions 120 and 121 of each of the plurality of pixel shared units 539 arranged in the V direction are arranged at substantially the same position in the H direction (FIG. 7B).

[0056] By providing the pad portion 120, the wiring used to connect from each floating diffusion region FD to the pixel circuit 210 (e.g., the gate electrode of the amplifying transistor AMP) can be reduced throughout the entire chip. Similarly, by providing the pad portion 121, the wiring supplying potential to each VSS contact area 118 can be reduced throughout the entire chip. This reduces the overall area of ​​the chip, suppresses electrical interference between wirings in the miniaturized pixels, and / or reduces costs due to the reduction in the number of components.

[0057] The solder pads 120 and 121 can be disposed at desired positions on the first substrate 100 and the second substrate 200. Specifically, the solder pads 120 and 121 can be disposed on either the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. When disposed on the wiring layer 100T, the solder pads 120 and 121 can also be in direct contact with the semiconductor layer 100S. Specifically, the solder pads 120 and 121 can also be configured to be directly connected to at least a portion of each of the floating diffusion region FD and / or VSS contact region 118. Alternatively, the solder pads 120 and 121 can be disposed at desired positions on the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S by providing connecting vias 120C and 121C to each of the floating diffusion region FD and / or VSS contact region 118 connected to the solder pads 120 and 121.

[0058] In particular, when the pad portions 120 and 121 are provided on the wiring layer 100T, the wiring in the insulating region 212 of the semiconductor layer 200S connected to the floating diffusion region FD and / or VSS contact region 118 can be reduced. This reduces the area of ​​the insulating region 212 on the second substrate 200 forming the pixel circuit 210, which forms the through wiring connecting the floating diffusion region FD to the pixel circuit 210. Therefore, the area of ​​the second substrate 200 forming the pixel circuit 210 can be maximized. By maximizing the area of ​​the pixel circuit 210, a larger pixel transistor can be formed, which helps to reduce noise and improve image quality.

[0059] In particular, when the pixel separation section 117 is constructed using an FTI structure, since the floating diffusion area FD and / or VSS contact area 118 are preferably provided in each pixel 541, the wiring connecting the first substrate 100 and the second substrate 200 can be greatly reduced by using the construction of the pad sections 120 and 121.

[0060] Furthermore, as shown in FIG7B, for example, the pad portion 120 for connecting a plurality of floating diffusion regions FD and the pad portion 121 for connecting a plurality of VSS contact regions 118 are arranged alternately in a straight line in the V direction. The pad portions 120 and 121 are formed at positions surrounded by a plurality of photodiodes PD, a plurality of transmission gates TG, or a plurality of floating diffusion regions FD. In this way, components other than the floating diffusion regions FD and VSS contact regions 118 can be freely arranged in the first substrate 100 forming a plurality of components, thereby improving the efficiency of the overall chip layout. Furthermore, the symmetry of the layout of components formed in the pixel common unit 539 can be ensured, suppressing characteristic deviations of each pixel 541.

[0061] The pad portions 120 and 121 are made of, for example, polysilicon (Poly Si), and more specifically, doped polysilicon with added impurities. Preferably, the pad portions 120 and 121 are made of conductive materials with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). In this way, after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100, a pixel circuit 210 can be formed. The reasons for this will be explained below. Furthermore, in the following description, the method of forming the pixel circuit 210 by bonding the semiconductor layers 200S of the first substrate 100 and the second substrate 200 will be referred to as the first manufacturing method.

[0062] Here, it is also possible to form the pixel circuit 210 on the second substrate 200 and then attach it to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrical connection electrodes are pre-formed on both the front side of the first substrate 100 (the front side of the wiring layer 100T) and the front side of the second substrate 200 (the front side of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are attached, the electrical connection electrodes formed on both the front side of the first substrate 100 and the front side of the second substrate 200 simultaneously come into contact with each other. Thereby, an electrical connection is formed between the wiring contained in the first substrate 100 and the wiring contained in the second substrate 200. Therefore, by setting the configuration of the imaging device 1 using the second manufacturing method, for example, a high-quality, high-performance imaging device can be manufactured by using an appropriate process according to the configuration of the first substrate 100 and the second substrate 200.

[0063] In this second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, alignment errors may sometimes occur due to the bonding manufacturing apparatus. Furthermore, the first substrate 100 and the second substrate 200 have a size, for example, a diameter of several tens of centimeters. However, when the first substrate 100 and the second substrate 200 are bonded together, there is a risk of substrate shrinkage in the microscopic regions of each of the first substrate 100 and the second substrate 200. This substrate shrinkage is caused by a slight deviation in the timing of contact between the substrates. Sometimes, due to this shrinkage of the first substrate 100 and the second substrate 200, errors may occur in the position of the electrical connection electrodes formed on the front surfaces of the first substrate 100 and the second substrate 200. In the second manufacturing method, it is preferable to take countermeasures beforehand to ensure that even if such errors occur, the electrodes of the first substrate 100 and the second substrate 200 are in contact with each other. Specifically, considering the aforementioned errors, it is preferable to increase the size of at least one of the electrodes of the first substrate 100 and the second substrate 200 in advance, preferably both. Therefore, if the second manufacturing method is used, for example, the size (size in the substrate plane direction) of the electrode formed on the front side of the first substrate 100 or the second substrate 200 is greater than the size of the internal electrode extending from the interior of the first substrate 100 or the second substrate 200 in the thickness direction to the front side.

[0064] On the other hand, the first manufacturing method described above can be used by using heat-resistant conductive materials to form the pad portions 120 and 121. In the first manufacturing method, after forming a first substrate 100 including a photodiode PD and a transmission transistor TR, the first substrate 100 is bonded to a second substrate 200 (semiconductor layer 2000S). At this time, the second substrate 200 is in a state where the pattern constituting the active element and wiring layer of the pixel circuit 210 has not been formed. Since the second substrate 200 is in a state before the pattern is formed, it is assumed that when the first substrate 100 and the second substrate 200 are bonded, even if an error occurs at the bonding position, the alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200 will not occur due to the bonding error. This is because the pattern of the second substrate 200 is formed only after the first substrate 100 and the second substrate 200 are bonded. Furthermore, when forming a pattern on the second substrate, for example in an exposure apparatus used to form the pattern, the pattern formed on the first substrate is used as the alignment target while forming the pattern. Based on the above reasons, the error in the bonding position between the first substrate 100 and the second substrate 200 is not a problem in the manufacturing of the imaging device 1 in the first manufacturing method. For the same reason, the error in the expansion and contraction of the substrate generated by the second manufacturing method is also not a problem in the manufacturing of the imaging device 1 in the first manufacturing method.

[0065] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, an active element is formed on the second substrate 200. Subsequently, through electrodes 120E, 121E and through electrode TGV (FIG. 6) are formed. The through electrodes 120E, 121E and TGV are formed, for example, from above the second substrate 200 using a reduced-projection exposure apparatus to form a pattern of through electrodes. Since a reduced-projection exposure is used, even if an error occurs in the alignment of the second substrate 200 and the exposure position, the magnitude of the error in the second substrate 200 is only a fraction of the error in the second manufacturing method described above (the reciprocal of the reduced-projection magnification). Therefore, by configuring the imaging device 1 using the first manufacturing method, the alignment of the elements formed on the first substrate 100 and the second substrate 200 becomes easier, and a high-quality, high-performance imaging device can be manufactured.

[0066] The imaging device 1 manufactured using this first manufacturing method has features different from those of the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a conical shape, they have a conical shape with a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV facilitates miniaturization of the pixels 541.

[0067] Here, if the imaging device 1 is manufactured using the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, an active element is formed on the second substrate 200. Therefore, the heat treatment required to form the active element also affects the first substrate 100. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided on the first substrate 100. For example, it is preferable to use a material with a melting point higher than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200 (i.e., high heat resistance) for the pad portions 120 and 121. For example, conductive materials with high heat resistance such as doped polycrystalline silicon, tungsten, titanium, or titanium nitride are used for the pad portions 120 and 121. In this way, the imaging device 1 can be manufactured using the first manufacturing method described above.

[0068] The passivation film 122 is provided across the entire front surface of the semiconductor layer 100S, for example, covering the pads 120 and 121 (FIG. 6). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. An interlayer insulating film 123 covers the pads 120 and 121 across the passivation film 122. This interlayer insulating film 123 is provided across the entire front surface of the semiconductor layer 100S, for example. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. A bonding film 124 is provided at the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided across the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film or a silicon oxide film.

[0069] The light-receiving lens 401 faces the semiconductor layer 100S, for example, through the fixed charge film 112 and the insulating film 111 (Fig. 6). The light-receiving lens 401 is disposed at a position, for example, facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0070] The second substrate 200, starting from the first substrate 100, sequentially comprises a semiconductor layer 200S and a wiring layer 200T. The semiconductor layer 200S is, for example, composed of a silicon substrate. A well region 211 is provided throughout the thickness direction of the semiconductor layer 200S. The well region 211 is, for example, a p-type semiconductor region. A pixel circuit 210 is provided on the second substrate 200, disposed in each pixel common unit 539. This pixel circuit 210 is disposed, for example, on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 with the back side (semiconductor layer 200S side) of the second substrate 200 facing the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0071] Figures 8, 9 to 12 are schematic representations of an example of the planar configuration of the second substrate 200. Figure 8 shows the configuration of the pixel circuit 210 disposed near the front side of the semiconductor layer 200S. Figure 9 is a schematic representation of the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later) and the semiconductor layer 200S connected to the wiring layer 200T and various parts of the first substrate 100. Figures 10 to 12 are schematic representations of an example of the planar configuration of the wiring layer 200T. Hereinafter, together with Figure 6, Figures 8, 9 to 12 will be used to describe the configuration of the second substrate 200. In Figures 8 and 9, the outline of the photodiode PD (the boundary between the pixel separation portion 117 and the photodiode PD) is indicated by dashed lines, and the boundaries of the semiconductor layer 200S and the element separation region 213 or insulating region 212 that overlap with the gate electrodes of each transistor constituting the pixel circuit 210 are indicated by dotted lines. In the portion overlapping with the gate electrode of the amplifying transistor AMP, on one side of the channel width direction, there is a boundary between the semiconductor layer 200S and the element separation region 213, and a boundary between the element separation region 213 and the insulating region 212.

[0072] On the second substrate 200, there is an insulating region 212 that divides the semiconductor layer 200S and an element separation region 213 that is disposed in a portion of the thickness direction of the semiconductor layer 200S (FIG. 6). For example, in the insulating region 212 disposed between two adjacent pixel circuits 210 in the H direction, through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel common units 539 of the two pixel circuits 210 are disposed (FIG. 9).

[0073] The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 200S (FIG. 6). The semiconductor layer 200S is interrupted by the insulating region 212. Through electrodes 120E, 121E and through electrode TGV are disposed in the insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0074] Through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wiring of the wiring layer 200T (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4, described later). The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and their lower ends are connected to the pad portions 120 and 121 (Fig. 6). The through electrode 120E is used to electrically connect the pad portion 120 to the pixel circuit 210. That is, the floating diffusion region FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by means of the through electrode 120E. The through electrode 121E is used to electrically connect the solder pad portion 121 to the reference potential line VSS of the wiring layer 200T. That is, through the through electrode 121E, the VSS contact area 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200.

[0075] A through electrode TGV is provided that penetrates the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is provided that penetrates the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transmission gate TG (FIG. 6). This through electrode TGV is used to electrically connect the transmission gate TG (transmission gate TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring of the wiring layer 200T (a part of the column drive signal line 542, specifically, the wiring TRG1, TRG2, TRG3, TRG4 in FIG. 11 described later). That is, by means of the through electrode TGV, the transmission gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200, and drive signals are sent to each of the transmission transistors TR (transmission transistors TR1, TR2, TR3, TR4).

[0076] The insulating region 212 is a region used to insulate the aforementioned through electrodes 120E, 121E and through electrodes TGV used for electrically connecting the first substrate 100 and the second substrate 200 from the semiconductor layer 200S. For example, in the insulating region 212 disposed between two adjacent pixel circuits 210 (pixel sharing unit 539) in the H direction, through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 are disposed. The insulating region 212 extends in the V direction, for example (Figs. 8 and 9). Here, by focusing on the arrangement of the horizontal portion TGb of the transmission gate TG, the position of the through electrode TGV in the H direction is arranged closer to the position of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa (Figs. 7A and 9). For example, the through electrode TGV is positioned in the H direction at approximately the same location as the through electrodes 120E and 121E. This allows the through electrodes 120E, 121E, and TGV to be disposed together within the insulating region 212 extending in the V direction. As another configuration example, the horizontal portion TGb can also be disposed only in the area overlapping the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, for example, disposed approximately at the center of each pixel 541 in both the H and V directions. In this case, the position of the through electrode TGV in the H direction is significantly offset from the position of the through electrodes 120E and 121E in the H direction. To electrically insulate it from the adjacent semiconductor layer 200S, an insulating region 212 is provided around the through electrode TGV and the through electrodes 120E and 121E. When the position of the through electrode TGV in the H direction is significantly different from that of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide insulating regions 212 around each of the through electrodes 120E, 121E, and TGV. This allows for a finer segmentation of the semiconductor layer 200S. In contrast, arranging the through electrodes 120E, 121E, and TGV within the insulating regions 212 extending in the V direction increases the size of the semiconductor layer 200S in the H direction. Therefore, a larger area can be ensured for the semiconductor element formation region in the semiconductor layer 200S. This, for example, allows for an increase in the size of the amplifying transistor AMP and suppression of noise.

[0077] The pixel sharing unit 539, as described with reference to FIG4, has a structure in which floating diffusion regions FD disposed in each of a plurality of pixels 541 are electrically connected, and the plurality of pixels 541 share a single pixel circuit 210. Furthermore, the electrical connection between the floating diffusion regions FD is achieved by a pad portion 120 disposed on the first substrate 100 (FIGs 6 and 7B). The electrical connection portion (pad portion 120) disposed on the first substrate 100 and the pixel circuit 210 disposed on the second substrate 200 are electrically connected via a single through electrode 120E. As another configuration example, the electrical connection portion between the floating diffusion regions FD can also be disposed on the second substrate 200. In this case, four through electrodes connected to each of the floating diffusion regions FD1, FD2, FD3, and FD4 are provided in the pixel sharing unit 539. Therefore, in the second substrate 200, the number of through electrodes in the semiconductor layer 200S increases, and the insulating region 212 surrounding these through electrodes becomes larger. In contrast, the structure of providing pad portions 120 in the first substrate 100 (Figs. 6 and 7B) reduces the number of through electrodes and decreases the insulating region 212. Therefore, it is possible to ensure a larger area for the semiconductor element formation region in the semiconductor layer 200S. This allows, for example, an increase in the size of the amplifying transistor AMP and suppression of noise.

[0078] A component separation region 213 is provided on the front side of the semiconductor layer 200S. The component separation region 213 has an STI (Shallow Trench Isolation) structure. In this component separation region 213, the semiconductor layer 200S is recessed in the thickness direction (a direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the recessed area. The insulating film is made of, for example, silicon oxide. The component separation region 213 separates the plurality of transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, well region 211) extends below the component separation region 213 (deep within the semiconductor layer 200S).

[0079] Here, referring to FIG7A, FIG7B and FIG8, the difference between the outer shape (outer shape in the plane direction of the substrate) of the pixel sharing unit 539 in the first substrate 100 and the outer shape of the pixel sharing unit 539 in the second substrate 200 is explained.

[0080] In the camera device 1, a pixel sharing unit 539 is provided spanning both the first substrate 100 and the second substrate 200. For example, the external shape of the pixel sharing unit 539 provided on the first substrate 100 is different from the external shape of the pixel sharing unit 539 provided on the second substrate 200.

[0081] In Figures 7A and 7B, the outlines of pixels 541A, 541B, 541C, and 541D are represented by a single-line diagram, and the outline of the pixel sharing unit 539 is represented by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 is composed of two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 is composed of four pixels 541 arranged in two adjacent columns × two rows, and the pixel sharing unit 539 of the first substrate 100 has a generally square outline. In the pixel array section 540, such pixel sharing units 539 are arranged adjacently in the H direction with a spacing of 2 pixels (equivalent to a spacing of 2 pixels 541) and in the V direction with a spacing of 2 pixels (equivalent to a spacing of 2 pixels 541).

[0082] In Figures 8 and 9, the outlines of pixels 541A, 541B, 541C, and 541D are represented by a single-point chain line, and the outline of pixel sharing unit 539 is represented by a thick line. For example, the outline of pixel sharing unit 539 of the second substrate 200 is smaller than that of pixel sharing unit 539 of the first substrate 100 in the H direction and larger than that of pixel sharing unit 539 of the first substrate 100 in the V direction. For example, pixel sharing unit 539 of the second substrate 200 is formed in the H direction with a size (area) equivalent to 1 pixel and in the V direction with a size equivalent to 4 pixels. That is, pixel sharing unit 539 of the second substrate 200 is formed with a size equivalent to 1 column × 4 rows of adjacent pixels, and pixel sharing unit 539 of the second substrate 200 has a generally rectangular outline.

[0083] For example, in each pixel circuit 210, the select transistor SEL, amplifying transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG are arranged sequentially in the V direction (Fig. 8). By setting the external shape of each pixel circuit 210 to a generally rectangular shape as described above, four transistors (selector transistor SEL, amplifying transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) can be arranged in one direction (the V direction in Fig. 8). In this way, the drain of the amplifying transistor AMP and the drain of the reset transistor RST can be shared in one diffusion region (the diffusion region connected to the power line VDD). For example, the forming region of each pixel circuit 210 can also be set to a generally square shape. In this case, with two transistors arranged in one direction, it is difficult to share the drain of the amplifying transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation area of ​​the pixel circuit 210 to a roughly rectangular shape, it is easy to arrange the four transistors close together, thus reducing the formation area of ​​the pixel circuit 210. That is, pixel miniaturization is possible. Furthermore, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, the formation area of ​​the amplifying transistor AMP can be increased to suppress noise.

[0084] For example, near the front side of the semiconductor layer 200S, in addition to the select transistor SEL, amplifying transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is also provided. The VSS contact region 218 is composed of, for example, a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via wiring of the wiring layer 200T and through electrode 121E. The VSS contact region 218 is located, for example, adjacent to the source of the FD conversion gain switching transistor FDG, separated by the component separation region 213 (FIG. 8).

[0085] Next, referring to Figures 7B and 8, the positional relationship between the pixel sharing unit 539 disposed on the first substrate 100 and the pixel sharing unit 539 disposed on the second substrate 200 will be explained. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (e.g., the upper part of the paper in Figure 7B) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., the left side of the paper in Figure 8). For example, the other of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (e.g., the lower part of the paper in Figure 7B) is connected to the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., the right side of the paper in Figure 8).

[0086] For example, in the two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is approximately equal to the layout in which the internal layout of the other pixel sharing unit 539 is reversed in the V and H directions. The effect obtained by this layout will be explained below.

[0087] In the two pixel sharing units 539 arranged in the V direction of the first substrate 100, each pad portion 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, at the center of the pixel sharing unit 539 in both the V and H directions (FIG. 7B). On the other hand, as described above, the pixel sharing unit 539 of the second substrate 200 has a generally rectangular outer shape that is longer in the V direction. Therefore, for example, the amplifying transistor AMP connected to the pad portion 120 is disposed at a position that is biased towards the upper part of the paper from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, the distance between the amplifying transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the upper part of the paper in FIG. 7B) becomes relatively short. However, the distance between the amplifying transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (e.g., the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper in FIG7B) becomes longer. Therefore, there is a risk that the wiring area required for the connection between the amplifying transistor AMP and the pad portion 120 will increase, and the wiring layout of the pixel sharing unit 539 will become more complex. This situation may affect the miniaturization of the imaging device 1.

[0088] In contrast, in the two pixel sharing units 539 arranged in the H direction of the second substrate 200, by reversing their internal layout at least in the V direction, the distance between the amplifying transistor AMP and the pad portion 120 of the two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, it is easier to miniaturize the imaging device 1. Furthermore, the planar layout of each of the plurality of pixel sharing units 539 of the second substrate 200 is symmetrical from left to right within the range shown in FIG8, but if the layout of the first wiring layer W1 shown in FIG9 described later is included, it is asymmetrical from left to right.

[0089] Furthermore, the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is preferably reversed in the H direction as well. The reason for this will be explained below. As shown in FIG9, the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are respectively connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are disposed at the center of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by reversing the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 in the H direction as well as in the H direction, the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, it is easier to miniaturize the imaging device 1.

[0090] Furthermore, the position of the outer contour line of the pixel sharing unit 539 of the second substrate 200 may not be consistent with the position of any outer contour line of the pixel sharing unit 539 of the first substrate 100. For example, in one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., the left side of the paper in FIG9), one of the outer contour lines in the V direction (e.g., the upper side of the paper in FIG9) is disposed outside the outer contour line in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (e.g., the upper side of the paper in FIG7B). Also, in the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., the right side of the paper in FIG9), another outer contour line in the V direction (e.g., the lower side of the paper in FIG9) is disposed outside the outer contour line in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (e.g., the lower side of the paper in FIG7B). In this way, by mutually configuring the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0091] Furthermore, the positions of the outer contours of the plurality of pixel-sharing units 539 on the second substrate 200 may also be inconsistent. For example, two pixel-sharing units 539 arranged in the H direction on the second substrate 200 may be configured with their outer contours staggered in the V direction. This reduces the distance between the amplifying transistor AMP and the pad portion 120. Therefore, miniaturization of the imaging device 1 is easier.

[0092] Referring to FIGS. 7B and 9, the repeated arrangement of pixel sharing units 539 in the pixel array section 540 will be described. The pixel sharing units 539 of the first substrate 100 have a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction (FIG. 7B). For example, in the pixel array section 540 of the first substrate 100, pixel sharing units 539 of the size of four pixels 541 are arranged adjacent to each other in the H direction with a spacing of 2 pixels (equivalent to the distance between two pixels 541) and in the V direction with a spacing of 2 pixels (equivalent to the distance between two pixels 541). Alternatively, a pair of pixel sharing units 539 arranged adjacent to each other in the V direction may be provided in the pixel array section 540 of the first substrate 100. In the pixel array portion 540 of the first substrate 100, for example, the pair of pixel sharing units 539 are arranged adjacently and repeatedly in the H direction with a spacing of 2 pixels (equivalent to the spacing between 2 pixels 541) and in the V direction with a spacing of 4 pixels (equivalent to the spacing between 4 pixels 541). The pixel sharing units 539 of the second substrate 200 have a size of 1 pixel 541 in the H direction and a size of 4 pixels 541 in the V direction (FIG. 9). For example, in the pixel array portion 540 of the second substrate 200, there is a pair of pixel sharing units 539 comprising 2 pixel sharing units 539 with a size equivalent to the 4 pixels 541. The pixel sharing units 539 are arranged adjacently in the H direction and staggered in the V direction. In the pixel array portion 540 of the second substrate 200, for example, a pair of pixel-sharing units 539 are arranged adjacently and repeatedly without gaps in the H direction with a 2-pixel spacing (equivalent to the distance between 2 pixels 541) and in the V direction with a 4-pixel spacing (equivalent to the distance between 4 pixels 541). By repeating this arrangement of pixel-sharing units 539, the pixel-sharing units 539 can be arranged without gaps. Therefore, it is easy to miniaturize the imaging device 1.

[0093] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). The passivation film 221 is, for example, in contact with the front side of the semiconductor layer 200S, covering the entire front side of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of the select transistor SEL, the amplifying transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The plurality of wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 is made of, for example, silicon oxide.

[0094] In the wiring layer 200T, for example, starting from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 are sequentially provided, which are insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 is provided with a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to their underlying layers. The connection portions are portions in which conductive material is embedded in the connection holes provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 is provided with a connection portion 218V that connects the first wiring layer W1 to the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of the connection portion connecting the components of the second substrate 200 to each other is different from the aperture of the through electrodes 120E, 121E and TGV. Specifically, the aperture of the connection hole connecting the components of the second substrate 200 to each other is preferably smaller than the aperture of the through electrodes 120E, 121E and TGV. The reason for this will be explained below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and TGV. Therefore, it is easier to embed conductive material into the connection hole compared to the through electrodes 120E, 121E and TGV. By making the aperture of the connection hole smaller than the aperture of the through electrodes 120E, 121E and TGV, it is easier to miniaturize the imaging device 1.

[0095] For example, the through electrode 120E is connected to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaching the source of the FD conversion gain switching transistor FDG) via the first wiring layer W1. The first wiring layer W1 connects, for example, the through electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0096] Next, the planar configuration of the wiring layer 200T will be described using Figures 10 to 12. Figure 10 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Figure 11 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Figure 12 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0097] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL (FIG. 11) extending in the H direction (column direction). These wirings correspond to the plurality of column drive signal lines 542 described with reference to FIG. 4. Wirings TRG1, TRG2, TRG3, and TRG4 are used to send drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. Wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transmission gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through electrode 120E, respectively. Wiring SELL is used to send a drive signal to the gate of the select transistor SEL, wiring RSTL is used to send a signal to the gate of the reset transistor RST, and wiring FDGL is used to send a signal to the gate of the FD conversion gain switching transistor FDG. The wiring SELL, RSTL, and FDGL are connected to the gates of the select transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and the connection part, respectively.

[0098] For example, the fourth wiring layer W4 includes a power line VDD, a reference potential line VSS, and a vertical signal line 543 (FIG. 12) extending in the V direction (horizontal direction). The power line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. Furthermore, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connector.

[0099] The contact portions 201 and 202 may be disposed at a position overlapping with the pixel array portion 540 when viewed from above (e.g., FIG. 3), or may be disposed on the peripheral portion 540B outside the pixel array portion 540 (e.g., FIG. 6). The contact portions 201 and 202 are disposed on the front side of the second substrate 200 (the side facing the wiring layer 200T). The contact portions 201 and 202 are made of metals such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the front side of the wiring layer 200T (the side facing the third substrate 300). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300, and for bonding between the second substrate 200 and the third substrate 300.

[0100] Figure 6 illustrates an example where peripheral circuitry is provided on the peripheral portion 540B of the second substrate 200. This peripheral circuitry may also include a portion of the column driving section 520 or a portion of the row signal processing section 550. Furthermore, as shown in Figure 3, the peripheral circuitry may not be provided on the peripheral portion 540B of the second substrate 200, and the connecting holes H1 and H2 may be positioned near the pixel array section 540.

[0101] Preferably, the pixel transistors (amplifier transistor AMP, select transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 have a three-dimensional structure, such as a fin-type structure with a concave-convex structure in the channel region (e.g., Fin-FET (Field-Effect Transistor), Tri-Gate FET, or Dual-Gate FET). In particular, by making the amplifier transistor AMP a three-dimensional structure, the effective gate width is increased, which can suppress noise.

[0102] Figure 13 is a schematic diagram showing an example of the cross-sectional configuration of the first substrate 100 and the second substrate 200 when the pixel transistor constituting the pixel circuit 210 is configured as a fin-type FD-SOI (Fully Depletion SOI (Silicon-On-Insulator)). Figure 14 shows an example of the layout of the pixel circuit 210 in the second substrate 200 when the pixel transistor is configured as a three-dimensional structure. In addition, Figure 13 shows a simplified cross-section of the A-A' line and BB line shown in Figure 14. Figure 15 is a comparative example showing the state in which the through electrode 120E passes through the insulating region 212 as described above, and the pad portion 120 is electrically connected to the gate AG of the amplifying transistor AMP via the first wiring layer W1 and other wiring, corresponding to the cross-sectional view shown in Figure 13. Figure 16 shows the layout of the pixel circuits in the second substrate 200 with the cross-sectional structure shown in Figure 15.

[0103] In the imaging device 1 shown in FIG13, the gate of the pixel transistor extends from the front side (surface 200S1) to the back side (surface 200S2) of the semiconductor layer 200S. In particular, when the amplifying transistor AMP has this structure, as shown in FIG13 and FIG14, the pad portion 120 and the amplifying transistor AMP can be directly connected by the through electrode 120E. Specifically, for example, as shown in FIG8, the amplifying transistor AMP in the pixel transistors arranged in the Y direction extends from the center of the pixel common unit 539 in the V and H directions to above the pad portion 120, as shown in FIG14, thereby the through electrode 120E penetrates the gate AG of the amplifying transistor AMP.

[0104] This eliminates the need for an insulating region 212 that electrically insulates the area surrounding the through electrode 120E. That is, the area of ​​the insulating region 212 in the second substrate 200 forming the pixel circuit 210, which forms the through wiring connecting the floating diffusion region FD and the pixel circuit 210, can be reduced. Therefore, the area of ​​the second substrate 200 forming the pixel circuit 210 can be increased. This ensures a larger area for the pixel circuit 210, thereby allowing for the formation of a larger pixel transistor.

[0105] Furthermore, in this configuration, the floating diffusion region FD and the amplifying transistor AMP are directly connected via the through electrode 120E. Therefore, compared to the case shown in FIG. 15, where the floating diffusion region FD and the amplifying transistor AMP are electrically connected via the first wiring layer W1 in addition to the through electrode 120E, the wiring length between the floating diffusion region FD and the amplifying transistor AMP can be shortened. Therefore, compared to the wiring configuration shown in FIG. 15, the wiring capacitance can be reduced, thus improving the conversion efficiency. Also, noise can be reduced.

[0106] The wiring structure shown in Figures 13 and 14 can be manufactured as follows, for example. Figures 17A to 17D show one example of the manufacturing steps.

[0107] First, as shown in FIG17A, a wiring layer 100T is formed on the semiconductor layer 100S, and a bonding film 124 is formed on the back side (surface 200SA2) of the silicon substrate 200SA. Next, as shown in FIG17B, after the silicon substrate 200SA is bonded to the wiring layer 100T via the bonding film 124, the silicon substrate 200SA is thinned to form a semiconductor layer 200S with a specific film thickness. Here, the specific film thickness is the film thickness required to form the pixel circuit 210. Specifically, the film thickness of the semiconductor layer 200S is the height of the fin pixel transistor (e.g., tens of nm to hundreds of nm).

[0108] Next, as shown in FIG17C, the semiconductor layer 200S is appropriately separated to form a pixel circuit 210 including an amplifying transistor AMP. Next, as shown in FIG17D, a passivation film 221 (not shown) and an interlayer insulating film 222 are formed, and then through electrodes 120E, 121E and a connection portion 218V are formed. The front side is planarized, for example, by CMP (Chemical Mechanical Polishing). Subsequently, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3 and a fourth wiring layer W4 are formed to form a wiring layer 200T. Thus, the imaging device shown in FIG13 is manufactured.

[0109] The third substrate 300, for example, has a wiring layer 300T and a semiconductor layer 300S sequentially arranged from the side of the second substrate 200. For example, the front side of the semiconductor layer 300S is disposed on the side of the second substrate 200. The semiconductor layer 300S is constructed of a silicon substrate. Circuitry is provided on the front side of the semiconductor layer 300S. Specifically, at least a portion of, for example, an input section 510A, a column driver section 520, a timing control section 530, a row signal processing section 550, an image signal processing section 560, and an output section 510B are provided on the front side of the semiconductor layer 300S. The wiring layer 300T disposed between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact sections 301 and 302. Contact portions 301 and 302 are exposed on the front side (the side facing the second substrate 200) of the wiring layer 300T. Contact portion 301 is connected to contact portion 201 of the second substrate 200, and contact portion 302 is connected to contact portion 202 of the second substrate 200. Contact portions 301 and 302 are electrically connected to a circuit formed on the semiconductor layer 300S (e.g., at least one of the input portion 510A, column driver portion 520, timing control portion 530, row signal processing portion 550, image signal processing portion 560, and output portion 510B). Contact portions 301 and 302 are made of metals such as Cu (copper) and Al (aluminum). For example, external terminal TA is connected to input portion 510A via connection hole H1, and external terminal TB is connected to output portion 510B via connection hole H2.

[0110] Here, the features of the camera device 1 will be explained.

[0111] Generally speaking, a camera device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal and allowing the camera device to output better image data (image information). Conversely, increasing the size of the transistors in the pixel circuit (especially enlarging the size of the transistors) reduces the noise generated in the pixel circuit, resulting in an improved S / N ratio of the image signal and allowing the camera device to output better image data (image information).

[0112] However, in an imaging device where the photodiode and pixel circuit are mounted on the same semiconductor substrate, it is believed that if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor equipped in the pixel circuit will decrease. Furthermore, it is believed that if the size of the transistor equipped in the pixel circuit is increased, the area of ​​the photodiode will decrease.

[0113] To solve these problems, for example, the imaging device 1 of this embodiment uses a plurality of pixels 541 sharing a single pixel circuit 210, and the shared pixel circuit 210 is arranged in an overlapping configuration with a photodiode PD. This allows for maximizing the area of ​​the photodiode PD and maximizing the size of the transistors mounted on the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the signal-to-noise ratio (S / N) of the pixel signal, enabling the imaging device 1 to output better image data (image information).

[0114] When a plurality of pixels 541 share a single pixel circuit 210 and are configured to overlap with a photodiode PD, a plurality of wirings extend from the floating diffusion regions FD of each of the plurality of pixels 541 to the single pixel circuit 210. To ensure a large area of ​​the semiconductor layer 200S forming the pixel circuit 210, for example, these extended plurality of wirings can be interconnected to form a single connection wiring. The same applies to the plurality of wirings extending from the VSS contact region 118; these extended plurality of wirings can be interconnected to form a single connection wiring.

[0115] For example, it is believed that if a connecting line is formed in the semiconductor layer 200S forming the pixel circuit 210 to connect multiple lines extending from the floating diffusion regions FD of each of the multiple pixels 541, the area of ​​the transistor contained in the pixel circuit 210 will be reduced. Similarly, it is believed that if a connecting line is formed in the semiconductor layer 200S forming the pixel circuit 210 to connect multiple lines extending from the VSS contact region 118 of each of the multiple pixels 541 and concentrate them into one line, the area of ​​the transistor contained in the pixel circuit 210 will be reduced.

[0116] In order to solve these problems, for example, the camera device 1 of this embodiment may have the following structure: a plurality of pixels 541 share a pixel circuit 210, and the shared pixel circuit 210 is overlapped with the photodiode PD, and a connection line is provided on the first substrate 100 to connect the floating diffusion regions FD of each of the plurality of pixels 541 to form a single line, and a connection line to connect the VSS contact areas 118 provided on each of the plurality of pixels 541 to form a single line.

[0117] Here, as a manufacturing method for providing a connection wiring on the first substrate 100 that connects the floating diffusion regions FD of each of the plurality of pixels 541 into a single line, and a connection wiring that connects the VSS contact areas 118 of each of the plurality of pixels 541 into a single line, if the second manufacturing method described above is used, for example, a high-quality, high-performance imaging device can be manufactured by using an appropriate process according to the configuration of the first substrate 100 and the second substrate 200. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be easily formed by the process. Specifically, when using the second manufacturing method described above, electrodes connected to the floating diffusion regions FD and electrodes connected to the VSS contact areas 118 are respectively provided on the front surface of the first substrate 100 and the front surface of the second substrate 200, which form the bonding boundary between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to increase the number of electrodes formed on the front sides of the two substrates in such a way that even if there is a positional shift between the electrodes disposed on the front sides of the two substrates when the first substrate 100 and the second substrate 200 are bonded together, the electrodes formed on the front sides of the two substrates will still be in contact with each other. In this case, it is considered difficult to arrange the aforementioned electrodes within the limited area of ​​each pixel of the imaging device 1.

[0118] To address the problem of requiring a large electrode at the bonding boundary between the first substrate 100 and the second substrate 200, the imaging device 1 of this embodiment can, for example, use the first manufacturing method described above, in which a plurality of pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is overlapped with a photodiode PD. This facilitates the alignment of components formed on the first substrate 100 and the second substrate 200, enabling the manufacture of a high-quality, high-performance imaging device. Furthermore, it can possess the inherent structure produced by using this manufacturing method. That is, it has a structure in which the semiconductor layer 100S of the first substrate 100, the wiring layer 100T, the semiconductor layer 200S of the second substrate 200, and the wiring layer 200T are sequentially stacked. In other words, the first substrate 100 and the second substrate 200 are stacked face to face, and it has through electrodes 120E and 121E that penetrate from the front side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to the front side of the semiconductor layer 100S of the first substrate 100.

[0119] In a structure on the first substrate 100 that provides a connection wiring that connects the floating diffusion regions FD of each of the plurality of pixels 541 to form a single line and a connection wiring that connects the VSS contact regions 118 of each of the plurality of pixels 541 to form a single line, if the structure is laminated to the second substrate 200 using the first manufacturing method described above, and a pixel circuit 210 is formed on the second substrate 200, there is a possibility that the heat treatment required when forming the active element equipped on the pixel circuit 210 may affect the connection wiring formed on the first substrate 100.

[0120] Therefore, in order to solve the problem that the heat treatment during the formation of the above-mentioned active element affects the above-mentioned connection wiring, the imaging device 1 of this embodiment preferably uses a conductive material with high heat resistance for the connection wiring that connects the floating diffusion areas FD of each of the plurality of pixels 541 to each other and to form a single connection wiring that connects the VSS contact areas 118 of each of the plurality of pixels 541 to each other and to form a single connection wiring. Specifically, the conductive material with high heat resistance can be a material whose melting point is higher than at least a portion of the wiring material contained in the wiring layer 200T of the second substrate 200.

[0121] Thus, for example, the imaging device 1 of this embodiment has (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face to back (specifically, the semiconductor layer 100S of the first substrate 100, the wiring layer 100T of the first substrate 100, and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked sequentially); (2) a structure in which through electrodes 120E and 121E are provided from the front side of the semiconductor layer 200S of the second substrate 200 through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to the front side of the semiconductor layer 100S of the first substrate 100; (3) a structure in which heat-resistant The high conductivity material forms a connection wiring that connects the floating diffusion regions FD of each of the plurality of pixels 541 into a single line and the VSS contact area 118 of each of the plurality of pixels 541 into a single line. The interface between the first substrate 100 and the second substrate 200 does not have a large electrode. Instead, the first substrate 100 has the connection wiring that connects the floating diffusion regions FD of each of the plurality of pixels 541 into a single line and the VSS contact area 118 of each of the plurality of pixels 541 into a single line.

[0122] [Operation of Camera Device 1] Next, the operation of camera device 1 will be explained using Figures 18 and 19. Figures 18 and 19 are figures 3 with added arrows indicating the paths of various signals. Figure 18 shows the paths of input signals, power supply potentials, and reference potentials from external input to camera device 1 using arrows. Figure 19 shows the signal paths of pixel signals output from camera device 1 to the outside using arrows. For example, input signals (e.g., pixel clock and synchronization signals) input to camera device 1 via input unit 510A are transmitted to column drive unit 520 of third substrate 300, where column drive unit 520 generates column drive signals. These column drive signals are then sent to second substrate 200 via contact units 301 and 201. Furthermore, these column drive signals reach each pixel common unit 539 of pixel array unit 540 via column drive signal lines 542 within wiring layer 200T. Of the drive signals arriving at the pixel common unit 539 on the second substrate 200, drive signals other than the transmission gate TG are input to the pixel circuit 210 to drive each transistor contained in the pixel circuit 210. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 on the first substrate 100 via the through electrode TGV to drive pixels 541A, 541B, 541C, and 541D (Fig. 18). Furthermore, the power supply potential and reference potential supplied from the input section 510A (input terminal 511) on the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and supplied to the pixel circuits 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is then also supplied to pixels 541A, 541B, 541C, and 541D on the first substrate 100 via the through electrode 121E. On the other hand, the pixel signals of pixels 541A, 541B, 541C, and 541D of the first substrate 100, after photoelectric conversion, are sent to the pixel circuit 210 of the second substrate 200 via the through electrode 120E and according to the pixel common unit 539. The pixel signal based on the pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 202 and 302. After being processed by the line signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, the pixel signal is output to the outside via the output unit 510B.

[0123] [Effect] In this embodiment, the pixel transistor constituting the pixel circuit 210 is configured in three dimensions, and the floating diffusion region FD disposed on the first substrate 100 and the pixel circuit 210 (specifically, the gate AG of the amplifying transistor AMP) disposed on the second substrate 200 are directly connected by a through electrode 120E. This reduces the formation area of ​​the insulating region 212 formed in the plane of the semiconductor layer 200S, ensuring the area of ​​the second substrate 200 on which the pixel circuit 210 is formed.

[0124] A CMOS image sensor (CIS) is configured to include a light-receiving sensor section and a pixel circuit section containing a source follower circuit. Due to technological advancements, the size of the cell has been decreasing year by year. However, on the other hand, the requirement to form a certain area of ​​the pixel circuit section has become difficult to miniaturize. Therefore, as described above, the development of imaging elements with a three-dimensional structure in which the light-receiving sensor section and the source follower circuit are formed on different substrates and stacked together continues to advance.

[0125] However, in the above-described three-dimensional imaging element, each substrate (corresponding to the first substrate 100 and the second substrate 200 in this embodiment) having a light-receiving sensor section and a source follower circuit is electrically connected via wiring formed in the horizontal direction relative to the main surface of the substrate having the through wiring and the source follower circuit. In this case, since electrical insulation is required around the through wiring, the substrate having the source follower circuit needs an insulating area, thus limiting the area where the element can be disposed.

[0126] In contrast, in this embodiment, the pixel transistor constituting the pixel circuit 210 is configured as a fin-type FD-SOI, and the floating diffusion region FD (specifically, the pad portion 120 formed in the region that overlaps with at least a portion of each of the plurality of floating diffusion regions FD1, FD2, FD3, FD4 of the shared pixel circuit 210) and the pixel circuit 210 (specifically, the gate AG of the amplifying transistor AMP) are directly connected by a through electrode 120E.

[0127] Based on the above, in this embodiment, by reducing the area of ​​the insulating region 212 formed in the plane of the semiconductor layer 200S, the area of ​​the semiconductor layer 200S forming the pixel circuit 210 is ensured. That is, the area efficiency of the pixel transistor constituting the pixel circuit 210 in the second substrate 200 can be improved.

[0128] Furthermore, in this embodiment, since the floating diffusion region FD and the amplifying transistor AMP are directly connected via the through electrode 120E, as shown in FIG15, compared to the case where they are connected via the first wiring layer W1 and the connection portion 218V in addition to the through electrode 120E, the wiring length can be shortened. Therefore, wiring capacitance can be reduced, and conversion efficiency can be improved. Also, noise can be reduced.

[0129] Hereinafter, variations of the first embodiment (variations 1-8), variations of the second embodiment (variations 9-11), and variations of the first and second embodiments and variations 1-11 (variations 12-18) will be described. Hereinafter, the same symbols will be used to mark the constituent elements that are the same as those in the above embodiments, and their descriptions will be omitted as appropriate.

[0130] <2. Variations> (2-1. Variation 1) FIG20 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, an example is shown in which a plurality of pixels 541 (e.g., pixels 541A, 541B, 541C, 541D) share one pixel circuit 210. However, as shown in FIG20, this technology can also be applied to a structure in which one pixel circuit 210 is formed for one pixel 541, and the same effect as in the first embodiment described above can be obtained.

[0131] (2-2. Variation 2) Figure 21 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, an example is shown in which the amplifying transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG constituting the pixel circuit 210 are set as fin-type FD-SOI (Fully Depletion SOI). However, the pixel transistors other than the amplifying transistor AMP can also be set as shown in Figure 21, for example, as a planar structure.

[0132] (2-3. Variation 3) Figure 22 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, it is shown that all gates of the amplifying transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG constituting the pixel circuit 210 are connected through the semiconductor layer 200S. However, the gates of the pixel transistors other than the amplifying transistor AMP may also not be connected through the semiconductor layer 200S, as shown in Figure 22.

[0133] (2-4. Variation 4) Figure 23 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, an example is shown where the gate AG of the amplifying transistor AMP is connected to the source of, for example, the reset transistor RST, the pad portion 120 is connected to the gate AG of the amplifying transistor AMP, and a through electrode 120E is connected through the gate AG to the first wiring layer W1, but it is not limited to this.

[0134] Specifically, the connection between the solder pad 120 and the gate AG of the amplifying transistor AMP, and the connection between the gate AG of the amplifying transistor AMP and the first wiring layer W1, can also be made separately. In this variation, as shown in FIG23, the solder pad 120 and the gate AG of the amplifying transistor AMP, and the gate AG of the amplifying transistor AMP and the first wiring layer W1 are connected by through electrodes 120E1 and 120E2, respectively. In this way, compared with the structure shown in FIG13, the connection between the solder pad 120 and the gate AG of the amplifying transistor AMP can be more secure.

[0135] Furthermore, in this variation, at least the end of the gate AG of the through semiconductor layer 200S of the amplifying transistor AMP protrudes from the surface 200S2 of the semiconductor layer 200S toward the first substrate 100. This prevents the through electrode 120E1 from contacting the semiconductor layer 200S.

[0136] (2-5. Variation 5) FIG24 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. FIG25 is a schematic planar view of the second substrate 200 of the imaging device 1 shown in FIG24. In the first embodiment described above, an example is shown in which the connection between the pad portion 120 and the through-transistor 120E of the amplifying transistor AMP is made by passing through the gate AG of the amplifying transistor AMP with the through electrode 120E. However, the through electrode 120E may not pass through the gate AG of the amplifying transistor AMP. For example, as shown in FIG24, the pad portion 120 and the amplifying transistor AMP may be connected by making the through electrode 120E and the side of the gate AG of the amplifying transistor AMP in contact. In this way, the processing of the through electrode 120E becomes easier compared with the structure shown in FIG13.

[0137] In this case, as shown in FIG24, the portion of the through electrode 120E connecting the gate AG of the amplifying transistor AMP to the first wiring layer W1 is preferably formed such that a portion of the through electrode 120E is mounted on the upper surface of the gate AG of the amplifying transistor AMP. This ensures a reliable connection between the through electrode 120E and the gate AG of the amplifying transistor AMP.

[0138] (2-6. Variation 6) Figure 26 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, an example is shown where the through electrode 120E has a single width (single diameter). However, as shown in Figure 26, the through electrode 120E formed between the first wiring layer W1 and the gate AG of the amplifying transistor AMP can also be made to have a larger width. Specifically, it can be formed to be larger than the fin-to-fin spacing of the amplifying transistor AMP. In this way, the through electrode 120E and the gate AG of the amplifying transistor AMP can be reliably connected.

[0139] (2-7. Variation 7) Figure 27 is a schematic cross-sectional view of the main components of the imaging device 1 of the first embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In the first embodiment described above, an example is shown in which the gate AG of the amplifying transistor AMP and the source of the reset transistor RST are connected via the through electrode 120E, the first wiring layer W1 and the connection portion 218V, but it is not limited to this.

[0140] For example, as shown in Figure 27, the gate AG of the amplifying transistor AMP can be extended horizontally, and the gate AG of the amplifying transistor AMP can be directly connected to the source of the reset transistor RST. This shortens the wiring length between the amplifying transistor AMP and the reset transistor RST. Therefore, compared to the configuration shown in Figure 13, wiring capacitance can be reduced, thereby improving conversion efficiency. Furthermore, noise can be reduced.

[0141] (2-8. Variation 8) Figures 29A to 29D show one example of the manufacturing steps of the pixel transistor set on the second substrate 200 described in the first embodiment above.

[0142] In the first embodiment described above, FIG13 shows an example in which the gate (e.g., gate AG) of the pixel transistor containing the amplifying transistor AMP passes through the semiconductor layer 200S. However, in order to reduce noise in such an amplifying transistor AMP, it is desirable to make the height of the fins approximately uniform.

[0143] However, in the first manufacturing method described above, the method of forming a pixel circuit 210 by bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 may result in unevenness on the front side of the interlayer insulating film 123 (for example, see Figure 28A) due to the influence of the horizontal portion TGb of the transmission gate TG formed on the semiconductor layer 100S of the first substrate 100 or the pad portions 120, 121, etc., and unevenness may also be formed on the front side (surface 200S1) of the thinned semiconductor layer 200S (for example, see Figure 28B). When the fins of the amplification transistor AMP are processed under this condition, the height of the fins becomes uneven, which becomes a cause of noise. Therefore, generally speaking, the following method is used to eliminate the unevenness of the fin height.

[0144] First, as shown in FIG28C, after the semiconductor layer 200S is cut off to form fin 223 by dry etching, for example, as shown in FIG28D, an oxide film 231 is used for backfilling. Then, as shown in FIG28E, after the front side height of the oxide film 231 and fin 223 is planarized by, for example, CMP, as shown in FIG28F, the oxide film 231 is etched to a specific depth again by dry etching. However, in this manufacturing method, due to the unevenness of the planarization by CMP or the unevenness of the etching depth, it is difficult to sufficiently reduce the height unevenness of the fin 223 exposed from the oxide film 231.

[0145] In contrast, in this variation, firstly, for example, the fin 223 is backfilled using a film (light absorption film 232) that absorbs ultraviolet light (UV). Examples of materials for the light absorption film 232 include silicon oxide (SiN). Hereinafter, an example of the manufacturing steps of the pixel transistor of this variation will be described using Figures 29A to 29D.

[0146] First, as shown in FIG29A, fins 223 are embedded in the light-absorbing film 232. Next, as shown in FIG29B, the front surfaces of the light-absorbing film 232 and fins 223 are planarized, for example, by CMP. Next, as shown in FIG29C, UV light is irradiated, for example, to break the bond of the light-absorbing film 232, forming a layer 232A with a faster etching rate within the light-absorbing film 232, followed by etching. Thus, as shown in FIG29D, a planar etched surface (surface 232S) is formed on the light-absorbing film 232. In this way, compared with the above manufacturing method, the height unevenness of the fins 223 exposed from the light-absorbing film 232 due to etching can be further reduced.

[0147] Furthermore, the penetration length of UV light into the light-absorbing film 232 can be changed according to the intensity of the irradiated UV light. Therefore, in order to eliminate the unevenness of planarization caused by CMP, by changing the intensity of UV light according to the front shape of the light-absorbing film 232, the height unevenness of the fins 223 exposed from the light-absorbing film 232 can be reduced.

[0148] Furthermore, the light-absorbing film 232 may be any material that absorbs light of a specific wavelength, but is not limited to UV light. Other materials for the light-absorbing film 232 include, for example, silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide. The light irradiated onto the light-absorbing film 232 may also be light other than UV light, but considering the effects of light energy or diffraction, it is preferable to use short-wavelength light.

[0149] Furthermore, this technology can also be applied to the manufacture of pixel transistors, such as the select transistor SEL and reset transistor RST as shown in FIG22, where the fins 223 are not independent of each other.

[0150] Figures 30A to 30D illustrate an example of a method for manufacturing a pixel transistor in which the fins 223 are not independent of each other. As shown in Figure 30A, after forming continuous fins 223 while retaining a portion of the semiconductor layer 200S, as shown in Figure 30B, a light-absorbing film 232 is formed on the semiconductor layer 200S, and the fins 223 are embedded therein, thus flattening the front surfaces of the light-absorbing film 232 and the fins 223. Next, as shown in Figure 30C, for example, UV light is irradiated to form a layer 232A with a faster etching rate in the light-absorbing film 232, and then etching is performed. In this way, as shown in Figure 30D, the height unevenness of the fins 223 exposed from the light-absorbing film 232 is reduced.

[0151] Figures 31A to 31D show another example of the manufacturing steps of the pixel transistor disposed on the second substrate 200 in this variation. Alternatively, a light absorption film 232 with a higher absorption coefficient than the light absorption film 232 can be pre-formed on the front side of the fin 223.

[0152] First, as shown in FIG. 31A, a light-absorbing film 232 is formed on the front side of the fin 223 and on the first substrate 100. Next, as shown in FIG. 31B, the light-absorbing film 232 is formed in the same manner as above. After the fin 223 is embedded, the front side of the light-absorbing film 232 and the fin 223 is planarized. Next, as shown in FIG. 31C, UV light is irradiated to form a layer 232A with a faster etching rate in the light-absorbing film 232. Subsequently, as shown in FIG. 31D, etching is performed. In this way, since the absorption coefficient of the film formed on the front side of the fin 223 is higher than that of the light-absorbing film 232, the formation of defects caused by irradiating the fin 223 with UV light can be reduced.

[0153] <3. Second Embodiment> FIG32 is a schematic cross-sectional view of the first substrate 100 and the second substrate 200 as key parts of the imaging device 1 of the second embodiment disclosed herein. FIG33 is a schematic planar view of the second substrate 200 of the imaging device 1 shown in FIG32. In addition, FIG32 shows a simplified cross-section of the C-C' line shown in FIG33. In the first embodiment described above, an example is shown in which the amplifying transistor AMP, which is directly connected to the pad portion 120 by the through electrode 120E, is set as a fin-type FD-SOI (Fully Depletion SOI) (for example, see FIG13), but the amplifying transistor AMP may also have other three-dimensional structures. In this embodiment, the case where the amplifying transistor AMP has a GAA (Gate All Around) structure is described in detail.

[0154] [Structure of Amplifying Transistor AMP] Figure 34 is an enlarged view of the amplifying transistor AMP shown within the dotted line in Figure 32. The amplifying transistor AMP has a GAA structure in which a gate AG is continuously provided around the channel 224. In the amplifying transistor AMP of this embodiment, a portion of the gate insulating film 225, which electrically insulates the gate AG from the channel 224, is formed to be wider than the width of the channel 224. Specifically, in the gate insulating film 225 provided around the channel 224 extending in the Y direction, the gate insulating film 225 provided on the surface (lower surface) of the channel 224 opposite to the pad portion 120 is formed to be wider than the width of the channel 224 in the H direction. More specifically, the gate insulating film 225 extending to the outer side of the lower surface of the channel 224 is close to the first substrate 100, and extends to a position lower than the gate insulating film 225 provided on the lower surface of the channel 224. Furthermore, similar to the first embodiment described above, a through electrode 120E is connected to the gate AG. In this embodiment, the through electrode 120E also serves as the gate AG of the amplifying transistor AMP formed below the channel 224.

[0155] [Manufacturing Method of Amplifying Transistor AMP] Hereinafter, the manufacturing method of the amplifying transistor AMP of this embodiment will be described. Figures 35A to 35I show an example of the manufacturing steps of the amplifying transistor AMP shown in Figures 32 to 34.

[0156] First, as shown in FIG35A, the semiconductor layer 200S is bonded to the first substrate 100, and an insulating region 212 and a component separation region 213 are formed at specific locations. Next, as shown in FIG35B, an opening H3 reaching the solder pad 120 is formed in the insulating region 212 formed above the solder pad 120. Next, as shown in FIG35C, after embedding, for example, polysilicon into the opening H3, the polysilicon disposed on the semiconductor layer 200S is removed, for example, by CMP, and the front side of the semiconductor layer 200S including the insulating region 212 and the component separation region 213 is planarized. Thereby, a through electrode 120E that also serves as the gate AG of the amplifying transistor AMP is formed.

[0157] Next, as shown in FIG35D, a silicon oxide film 225X and a polycrystalline silicon film 224X are sequentially formed on the semiconductor layer 200S, which includes the insulating region 212, the component separation region 213, and the through electrode 120E. Then, the polycrystalline silicon film 224X and the silicon oxide film 225X are processed, for example, by photolithography and etching. Thereby, as shown in FIG35E, a gate insulating film 225A is formed covering the channel 224 of the amplifying transistor AMP and the lower surface of the channel 224. Subsequently, a thermal oxide film is formed on the front side of the through electrode 120E and the channel 224 by an annealing process. This thermal oxide film is a gate insulating film 225B extending further outward than the upper surface and side surface of the channel 224 and the lower surface of the channel 224.

[0158] Next, as shown in FIG35F, a photoresist film 234 with an opening at a specific location is formed, for example, by photolithography. Next, as shown in FIG35G, after removing the thermal oxide film on the through electrode 120E exposed from the photoresist film 234 by etching, for example, the photoresist film 234 is removed, and a polycrystalline silicon film 226X is formed on the semiconductor layer 200S, which includes the insulating region 212, the element separation region 213, the through electrode 120E, and the channel 224 disposed on the through electrode 120E.

[0159] Next, as shown in FIG35H, a polycrystalline silicon film 226X is processed, for example, by photolithography and etching. This forms the gate AG of the amplifying transistor AMP and the gates (not shown) of other pixel transistors covering the side and top surfaces of the channel 224. Based on the above, the amplifying transistor AMP with a gate insulating film 225 is completed. This gate insulating film 225 extends wider than the width of the channel 224 in the H direction, and a gate insulating film 225B extending wider than the width of the channel 224 in the H direction is formed at a position lower than the gate insulating film 225A disposed on the lower surface of the channel 224. Subsequently, as shown in FIG35H, a passivation film 221 is formed covering the gate AG of the amplifying transistor AMP and the gates (not shown) of other pixel transistors.

[0160] Next, as shown in FIG35I, after forming an interlayer insulating film 222 on the passivation film 221, a connection portion 218V reaching the gate of the pixel transistor containing the amplifying transistor AMP, and a through electrode 121E reaching the pad portion 121, etc. (not shown), are formed. Thereafter, a first wiring layer W1 is formed. Based on the above, the second substrate 200 of the imaging device 1 shown in FIG32 is formed.

[0161] [Effect] Based on the above, in this embodiment, the amplifying transistor AMP is configured as a GAA structure, and the floating diffusion region FD (specifically, the pad portion 120) is directly connected to the amplifying transistor AMP via the through electrode 120E. Therefore, for example, compared with the general pixel circuit 210 layout shown in FIG. 36, the formation area of ​​the pixel circuit 210 in the second substrate 200 can be ensured to be larger (refer to FIG. 33). That is, similar to the first embodiment described above, the area efficiency of the pixel transistor constituting the pixel circuit 210 in the second substrate 200 can be improved.

[0162] Furthermore, in this embodiment, similar to the first embodiment described above, the wiring length between the pad portion 120 and the amplifying transistor AMP can be shortened, thereby reducing wiring capacitance and improving conversion efficiency. Also, noise can be reduced.

[0163] Furthermore, when a GAA structure amplifying transistor AMP is formed on the second substrate 200 using a general manufacturing method, when a gate insulating film is formed around the channel, an oxide film is also formed on the part that contacts the floating diffusion region FD (e.g., the front side of the pad portion 120), which may prevent the connection with the floating diffusion region FD.

[0164] In contrast, in this embodiment, an opening H3 leading to the pad portion 120 is pre-formed, and polysilicon is embedded within the opening H3 to form a through electrode 120E, thus forming a channel 224. A gate insulating film 225 is then formed by annealing. This prevents the formation of an oxide film on the front side of the pad portion 120, thereby ensuring conductivity between the pad portion 120 and the amplifying transistor AMP. Therefore, manufacturing yield and reliability can be improved.

[0165] <4. Variations> (4-1. Variation 9) Figure 37 is a schematic cross-sectional view of the main components of the imaging device 1 of the second embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. In this variation, a widened portion 120EA is provided above the through electrode 120E of the gate AG, which is embedded in the insulating region 212 and also serves as the channel 224 of the amplifying transistor AMP, on the lower surface side, which is different from the second embodiment described above.

[0166] Figures 38A to 38E show one example of the manufacturing steps of the amplifier transistor AMP shown in Figure 37.

[0167] First, as shown in FIG38A, the semiconductor layer 200S is bonded to the first substrate 100, and an insulating region 212 and a component separation region 213 are formed at specific locations. Then, an opening H3 reaching the solder pad 120 and an opening H4 wider than the opening H3 are formed in the insulating region 212 formed above the solder pad 120. Next, similar to the second embodiment described above, as shown in FIG38B, polycrystalline silicon is embedded in the openings H3 and H4. For example, a silicon oxide film 225X and a polycrystalline silicon film 224X are formed on the semiconductor layer 200S including the insulating region 212, the component separation region 213 and the through electrode 120E.

[0168] Next, as shown in FIG38C, after processing the polycrystalline silicon film 224X and the silicon oxide film 225X to form the channel 224 and the gate insulating film 225A, a thermal oxide film serving as the gate insulating film 225B is formed on the front side of the through electrode 120E and the channel 224 by annealing. Next, as shown in FIG38D, for example by photolithography, a photoresist film 234 having openings at specific locations is formed.

[0169] Next, similar to the second embodiment described above, for example, after removing the thermal oxide film on the through electrode 120E exposed from the photoresist film 234 by etching, the photoresist film 234 is removed, and a polycrystalline silicon film 226X is formed on the semiconductor layer 200S, which includes the insulating region 212, the component separation region 213, the through electrode 120E, and the channel 224 disposed on the through electrode 120E. Next, as shown in FIG38E, for example, the polycrystalline silicon film 226X is processed by photolithography and etching to form the gate AG. Thereafter, similar to the second embodiment described above, a passivation film 221, an interlayer insulating film 222, and a first wiring layer W1 are formed sequentially. Based on the above, the second substrate 200 of the imaging device 1 shown in FIG37 is formed.

[0170] Thus, in this variation, a widened portion 120EA is provided above the through electrode 120E of the gate AG, which is embedded in the insulating region 212 and also serves as the channel 224 of the amplifier transistor AMP. In other words, a protrusion with a larger diameter than the wiring diameter of the through electrode 120E is provided in the portion of the gate AG embedded in the insulating region 212 around the channel 224. As shown by the arrow in FIG38E, compared with the second embodiment described above, the distance between the end of the gate insulating film 225B and the contact portion between the through electrode 120E and the gate AG is increased, thus increasing the margin for poor conduction between the solder pad portion 120 and the amplifier transistor AMP, thereby improving manufacturing yield and reliability.

[0171] (4-2. Variation 10) Figure 39 is a schematic cross-sectional view of the main components of the imaging device 1 of the second embodiment described above, that is, another example of the cross-sectional configuration of the first substrate 100 and the second substrate 200. Figure 40 shows a magnified view of the magnifying transistor AMP within the dotted line shown in Figure 39. In this variation, the difference from the second embodiment described above is that a thermal oxide film 227 is formed below the channel 224 within the gate AG, which is separate from the channel 224 and the gate insulating film 225 and is wider than the channel 224 in the H direction.

[0172] Figures 41A to 41E show one example of the manufacturing steps of the amplifier transistor AMP shown in Figures 39 and 40.

[0173] First, as shown in FIG41A, a sacrificial layer 235 comprising silicon germanium (SiGe) and a polycrystalline silicon film 224X are sequentially formed on the semiconductor layer 200S comprising the insulating region 212, the element separation region 213 and the through electrode 120E. Next, as shown in FIG41B, the polycrystalline silicon film 224X is processed, for example by photolithography and wet etching, to form the channel 224, and the sacrificial layer 235 is removed.

[0174] Next, by performing an annealing process, as shown in FIG41C, a gate insulating film 225 and a thermal oxide film 227 are formed on the front side of the through electrode 120E and the channel 224, respectively. Next, as shown in FIG41D, similar to the second embodiment described above, a photoresist film 234 with an opening at a specific position is formed. Next, for example, by etching to remove the thermal oxide film 227 exposed on the through electrode 120E from the photoresist film 234, the photoresist film 234 is removed, and a polycrystalline silicon film 226X is formed on the semiconductor layer 200S including the insulating region 212, the element separation region 213, the through electrode 120E, and the channel 224 disposed on the through electrode 120E. Next, as shown in FIG41E, a polycrystalline silicon film 226X is processed by photolithography and etching, for example, to form the gate AG. Then, in the same manner as in the second embodiment described above, a passivation film 221, an interlayer insulating film 222, and a first wiring layer W1 are formed sequentially. Based on the above, the second substrate 200 of the imaging device 1 shown in FIG39 is formed.

[0175] As described above, in this variation, a sacrificial layer 235 and a polycrystalline silicon film 224X are sequentially formed on the semiconductor layer 200S, which includes the insulating region 212, the element separation region 213, and the through electrode 120E. Then, the polycrystalline silicon film 224X is processed to form a channel 224, and a gate insulating film 225 is formed by thermal oxidation. Therefore, in addition to the effects of the first embodiment described above, similar to the second embodiment described above, compared to the manufacturing method using a conventional amplifier transistor (AMP) with a GAA structure, manufacturing yield and reliability can be improved.

[0176] Furthermore, this variation, as shown in FIG. 42, can also be combined with Variation 9. Also, by controlling the formation range of the photoresist film 234, etching time, and conditions, as shown in FIG. 43, the thermal oxide film 227 can be formed with a narrower width in the H direction than the channel 224. In this way, since the distance between the end of the thermal oxide film 227 and the contact portion between the through electrode 120E and the gate AG is increased, the margin for poor conduction between the pad portion 120 and the amplifying transistor AMP is further increased, thereby improving manufacturing yield and reliability.

[0177] (4-3. Variation 11) In this variation, a method is described in which the sacrificial layer 235 below the channel 224 is selectively removed and the sacrificial layer 235 formed below the source 224S and drain 224D at both ends of the channel 224 is retained when the amplifying transistor AMP is formed using the method described in Variation 10 above.

[0178] When forming an amplifying transistor AMP using the method shown in Variation 10 above, the sacrificial layer 235 formed below the polysilicon film 224X constituting the channel 224 is removed by wet etching or the like during processing of the polysilicon film 224X. However, it is desirable to retain the sacrificial layer 235 below the polysilicon films 224X constituting the source 224S and drain 224D at both ends of the channel 224 without peeling off the polysilicon film 224X. Therefore, generally speaking, the polysilicon film 224X of the source 224S and drain 224D portions is processed to be larger than that of the channel 224 portion, for example, as shown in FIG44.

[0179] Figures 45A to 45J show one example of the manufacturing steps of the amplifier transistor AMP in this variation. In addition, in Figures 45B to 45J, (A) shows the cross-section of the C-C' line shown in Figure 44 (channel 224 portion), and (B) shows the cross-section of the D-D' line (drain 224D portion).

[0180] First, as shown in FIG45A, the sacrificial layer 235 and the polycrystalline silicon film 224X, which are formed on the semiconductor layer 200S including the insulating region 212, the element separation region 213 and the through electrode 120E, are processed into a specific shape. Next, as shown in FIG45B, a photoresist film 236 is formed at both ends of the polycrystalline silicon film 224X, which becomes the source electrode 224S and the drain electrode 224D.

[0181] Next, as shown in FIG45C, the sacrificial layer 235 directly beneath the polysilicon film 224X that will become channel 224 is removed, for example, by wet etching. At this time, the sacrificial layer 235 directly beneath the polysilicon film 224X that will become source 224S and drain 224D is not removed because it is covered by photoresist film 236. Subsequently, photoresist film 236 is removed. Next, as shown in FIG45D, a thermal oxide film is formed on the front side of polysilicon film 224X and the front side of through electrode 120E by annealing. This thermal oxide film is the gate insulating film 225 and thermal oxide film 227 shown in FIG39 and FIG40.

[0182] Next, as shown in FIG45E, after forming a photoresist film 237 covering the polycrystalline silicon film 224X, as shown in FIG45F, the thermal oxide film 227 exposed from the photoresist film 237 and formed on the surface above the through electrode 120E is removed by etching. Next, as shown in FIG45G, a polycrystalline silicon film 226X is formed on the semiconductor layer 200S that includes the insulating region 212, the element separation region 213, the through electrode 120E, and the polycrystalline silicon film 224X that forms the channel 224, the source 224S, and the drain 224D.

[0183] Next, as shown in FIG45H, a photoresist film 238 is formed at a specific position on the polycrystalline silicon film 226X. Specifically, the photoresist film 238 is formed on the polycrystalline silicon film 224X that forms the channel 224. Next, as shown in FIG45I, after forming the gate AG by etching the polycrystalline silicon film 226X, a passivation film 221 is formed. Subsequently, as shown in FIG45J, an interlayer insulating film 222, a connection portion 218B, and a first wiring layer W1 are formed sequentially.

[0184] In the amplifying transistor AMP formed using the above manufacturing method, the sacrificial layer 235 directly beneath the polycrystalline silicon film 224X that serves as the source 224S and drain 224D can be retained. Therefore, for example, as shown in FIG46, the source 224S and drain 224D can be formed with approximately the same width as the channel 224. Therefore, the overall wafer size of the pixel circuit 210 can be reduced, thus, for example, the yield within a single silicon wafer can be improved.

[0185] Furthermore, the two ends of the polycrystalline silicon film 224X that forms the source 224S and drain 224D can also be curved with the corners removed, as shown in FIG47. Also, in the above variation 10 and this variation, SiGe is listed as the material of the sacrificial layer 235, but the sacrificial layer 235 is not limited to this, for example, a conductive film or an insulating film can also be used to form it.

[0186] Furthermore, there are cases where the gate length is insufficient even if the amplifying transistor AMP is configured as a GAA structure. In this case, the polycrystalline silicon film 224X constituting the channel 224 can be changed, for example, as shown in FIG48A, to a multilayer film 228 formed by alternating layers of a Si film 228X1 containing polycrystalline silicon and a sacrificial layer 228X2 containing, for example, SiGe. This ensures the gate length.

[0187] Thus, when using a multilayer film 228 in which Si film 228X1 and sacrificial layer 228X2 are alternately stacked, the processing of the channel 224 portion, the source 224S and the drain 224D portion can be performed as follows.

[0188] Furthermore, after the multilayer film 228 is processed into a specific shape, as shown in FIG48A, except for the sacrificial layer 228X2 of the bottommost layer of the multilayer film 228 that forms the channel 224, the multilayer film 228 is covered by an inverted conical photoresist film 239. The inverted conical photoresist film 239 can be formed, for example, by using a negative photoresist. Next, for example, by performing wet etching, as shown in FIG48B, the sacrificial layer 228X2 of the bottommost layer of the channel 224 exposed from the photoresist film 239 is selectively removed. Thereafter, the photoresist film 239 is removed. Next, as shown in FIG48C, in the same manner as above, the gate insulating film 225, the thermal oxide film 227, the gate AG, the passivation film 221, the interlayer insulating film 222, the connection portion 218B, and the first wiring layer W are formed in sequence.

[0189] Furthermore, in the second embodiment and variations 9 to 11 described above, an example of setting the amplifying transistor AMP to a GAA structure was shown. However, all transistors constituting the pixel circuit 210 can also be set to a GAA structure. In this case, the semiconductor layer 200S can be set as a multilayer film 228, as described above, in which Si film 228X1 and sacrificial layer 228X2 are alternately deposited. In this case, since the thickness of the multilayer film 228 is thinner than that of the semiconductor layer 200S, the thickness of the second substrate 200 can be reduced. Therefore, since the aspect ratio of the through electrodes 120E and 121E is reduced, the processability or stability is improved, and the yield can be increased.

[0190] <5. Variation Example 12> Figures 49 to 53 show a variation of the planar configuration of the imaging device 1 in the above-described embodiments. Figure 49 schematically shows the planar configuration near the front side of the semiconductor layer 200S of the second substrate 200, corresponding to Figure 8 described in the first embodiment. Figure 50 schematically shows the configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and various parts of the first substrate 100, corresponding to Figure 9 described in the first embodiment. Figure 51 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to Figure 10 described in the first embodiment. Figure 52 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to Figure 11 described in the first embodiment. Figure 53 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, which corresponds to Figure 12 described in the first embodiment above.

[0191] In this variation, as shown in FIG50, the internal layout of one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (e.g., the right side of the paper) is configured such that the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper) is reversed only in the H direction. Furthermore, the offset in the V direction between the outer contour lines of one pixel sharing unit 539 and the outer contour lines of the other pixel sharing unit 539 is greater than the offset described in the first embodiment above (FIG. 9). Thus, by increasing the offset in the V direction, the distance between the amplifying transistor AMP of the other pixel sharing unit 539 and the pad portion 120 connected to it (the other (bottom side of the paper) pad portion 120 of the two pixel sharing units 539 arranged in the V direction as shown in FIG. 7B) can be reduced. With this arrangement, in Variation 12 of the imaging device 1 described in Figures 49-53, the planar layout of the two pixel sharing units 539 arranged in the H direction does not need to be reversed in the V direction, and their area is set to be the same as the area of ​​the pixel sharing units 539 of the second substrate 200 described in the first embodiment. Furthermore, the planar layout of the pixel sharing units 539 of the first substrate 100 is the same as the planar layout described in the first embodiment (Figures 7A and 7B). Therefore, the imaging device 1 of this variation can achieve the same effect as the imaging device 1 described in the first embodiment. The arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangements described in the first and second embodiments and this variation.

[0192] <6. Variation Example 13> Figures 54 to 59 show a variation of the planar configuration of the imaging device 1 in the above-described embodiments. Figure 54 schematically shows the planar configuration of the first substrate 100, corresponding to Figure 7A described in the first embodiment. Figure 55 schematically shows the planar configuration near the front side of the semiconductor layer 200S of the second substrate 200, corresponding to Figure 8 described in the first embodiment. Figure 56 schematically shows the configuration of the first wiring layer W1 and the semiconductor layer 200S connected to the first wiring layer W1 and the various parts of the first substrate 100, corresponding to Figure 9 described in the first embodiment. Figure 57 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to Figure 10 described in the first embodiment. Figure 58 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to Figure 11 described in the first embodiment. Figure 59 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, which corresponds to Figure 12 described in the first embodiment above.

[0193] In this variation, each pixel circuit 210 has a generally square planar shape (Fig. 55, etc.). The planar configuration of the imaging device 1 in this variation is different from the planar configuration of the imaging device 1 described in the first embodiment above.

[0194] For example, the pixel sharing unit 539 of the first substrate 100 is the same as that described in the first embodiment above, and is formed over a pixel area of ​​2 columns × 2 rows, having a generally square planar shape (FIG. 54). For example, in each pixel sharing unit 539, the horizontal portion TGb of the transmission gates TG1 and TG3 of pixels 541A and 541C of one pixel row extends in the H direction toward the center of the pixel sharing unit 539 (more specifically, toward the outer edge of pixels 541A and 541C, and toward the center of the pixel sharing unit 539) from the position where it overlaps with the vertical portion TGa, and the horizontal portion TGb of the transmission gates TG2 and TG4 of pixels 541B and 541D of another pixel row extends in the H direction toward the outside of the pixel sharing unit 539 (more specifically, toward the outer edge of pixels 541B and 541D, and toward the outside of the pixel sharing unit 539) from the position where it overlaps with the vertical portion TGa. The pad portion 120 connected to the floating diffusion region FD is disposed in the central part of the pixel common unit 539 (the central part of the pixel common unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact area 118 is disposed at least in the H direction (the H direction and the V direction in FIG54) at the end of the pixel common unit 539.

[0195] As another configuration example, it is also possible to provide the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 only in the region opposite to the vertical portion TGa. In this case, as described in the first embodiment above, it is easy to divide the semiconductor layer 200S into finer segments. Therefore, it is difficult to form a larger transistor in the pixel circuit 210. On the other hand, if the horizontal portions TGb of the transmission gates TG1, TG2, TG3, and TG4 extend in the H direction from the position overlapping with the vertical portion TGa, as in the variation described above, the width of the semiconductor layer 200S can be increased, as in the first embodiment above. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transmission gates TG1 and TG3 in the H direction can be arranged close to the position of the through electrode 120E, and the positions of the through electrodes TGV2 and TGV4 connected to the transmission gates TG2 and TG4 in the H direction can be arranged close to the position of the through electrode 121E (Fig. 56). Consequently, similar to the description of the first embodiment above, the width (size in the H direction) of the semiconductor layer 200S extending in the V direction can be increased. Therefore, the size of the transistors in the pixel circuit 210, especially the size of the transistor AMP, can be increased. As a result, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0196] The pixel common unit 539 of the second substrate 200 is approximately the same size in the H and V directions as the pixel common unit 539 of the first substrate 100, and is provided in a region corresponding to approximately 2 columns × 2 rows of pixel areas. For example, in each pixel circuit 210, the select transistor SEL and the amplifying transistor AMP are arranged in the V direction on a semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the V direction on a semiconductor layer 200S extending in the V direction. The semiconductor layer 200S with the select transistor SEL and the amplifying transistor AMP and the semiconductor layer 200S with the FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the H direction with an insulating region 212. The insulating region 212 extends in the V direction, for example (FIG 55).

[0197] Here, referring to FIGS. 55 and 56, the external shape of the pixel sharing unit 539 of the second substrate 200 will be described. For example, the pixel sharing unit 539 of the first substrate 100 shown in FIG. 54 is connected to an amplifying transistor AMP and a selector transistor SEL provided on one side of the pad portion 120 in the H direction (left side of the paper in FIG. 56), and an FD conversion gain switching transistor FDG and a reset transistor RST provided on the other side of the pad portion 120 in the H direction (right side of the paper in FIG. 56). The external shape of the pixel sharing unit 539 of the second substrate 200, including the amplifying transistor AMP, the selector transistor SEL, the FD conversion gain switching transistor FDG, and the reset transistor RST, is determined by the following four outer edges.

[0198] The first outer edge is the outer edge of one end (the upper end of the paper in FIG56) of the semiconductor layer 200S containing the select transistor SEL and the amplifying transistor AMP in the V direction. This first outer edge is disposed between the amplifying transistor AMP contained in the pixel shared unit 539 and the select transistor SEL contained in the pixel shared unit 539 adjacent to one side of the pixel shared unit 539 in the V direction (the upper end of the paper in FIG56). More specifically, the first outer edge is disposed at the center of the element separation region 213 in the V direction between the amplifying transistor AMP and the select transistor SEL. The second outer edge is the outer edge of the other end (the lower end of the paper in FIG56) of the semiconductor layer 200S containing the select transistor SEL and the amplifying transistor AMP in the V direction. The second outer edge is disposed between the select transistor SEL included in the pixel shared unit 539 and the amplifying transistor AMP included in the pixel shared unit 539 adjacent to the other side of the pixel shared unit 539 in the V direction (bottom of the paper in FIG. 56). More specifically, the second outer edge is disposed at the center of the element separation region 213 in the V direction between the select transistors SEL and the amplifying transistor AMP. The third outer edge is the outer edge of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG at the other end of the V direction (bottom of the paper in FIG. 56). The third outer edge is disposed between the FD conversion gain switching transistor FDG included in the pixel shared unit 539 and the reset transistor RST included in the pixel shared unit 539 adjacent to the other side of the pixel shared unit 539 in the V direction (bottom of the paper in FIG. 56). More specifically, the third outer edge is located at the center of the element separation region 213 in the V direction between the FD conversion gain switching transistor (FDG) and the reset transistor (RST). The fourth outer edge is the outer edge of one end (the upper end of the paper in FIG. 56) of the semiconductor layer 200S containing the reset transistor (RST) and the FD conversion gain switching transistor (FDG). This fourth outer edge is located between the reset transistor (RST) included in the pixel shared unit 539 and the FD conversion gain switching transistor (FDG) (not shown) included in the pixel shared unit 539 adjacent to one side of the pixel shared unit 539 in the V direction (the upper end of the paper in FIG. 56). More specifically, the fourth outer edge is located at the center of the element separation region 213 (not shown) in the V direction between the reset transistor (RST) and the FD conversion gain switching transistor (FDG).

[0199] In the shape of the pixel common unit 539 of the second substrate 200 including the first, second, third, and fourth outer edges, the third and fourth outer edges are offset to one side of the V direction relative to the first and second outer edges (in other words, offset to one side of the V direction). By using this arrangement, the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close as possible to the pad portion 120. Therefore, the area of ​​the wiring connecting these components is reduced, making it easier to miniaturize the imaging device 1. In addition, the VSS contact area 218 is provided between the semiconductor layer 200S containing the select transistor SEL and the amplifying transistor AMP, and the semiconductor layer 200S containing the reset transistor RST and the FD conversion gain switching transistor FDG. For example, a plurality of pixel circuits 210 have the same configuration.

[0200] The imaging device 1 having this second substrate 200 can also achieve the same effect as described in the first embodiment above. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the first, second embodiments and this variation.

[0201] <7. Variation Example 14> Figures 60 to 65 show a variation of the planar configuration of the imaging device 1 in the above-described embodiments. Figure 60 schematically shows the planar configuration of the first substrate 100, corresponding to Figure 7B described in the first embodiment. Figure 61 schematically shows the planar configuration near the front side of the semiconductor layer 200S of the second substrate 200, corresponding to Figure 8 described in the first embodiment. Figure 62 schematically shows the configuration of the first wiring layer W1 and the semiconductor layer 200S connected to the first wiring layer W1 and the various parts of the first substrate 100, corresponding to Figure 9 described in the first embodiment. Figure 63 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to Figure 10 described in the first embodiment. Figure 64 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to Figure 11 described in the first embodiment. Figure 65 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, which corresponds to Figure 12 described in the first embodiment above.

[0202] In this variation, the semiconductor layer 200S of the second substrate 200 extends in the H direction (Fig. 62). That is, it roughly corresponds to the configuration of rotating the planar configuration of the imaging device 1 shown in Fig. 55, etc., by 90 degrees.

[0203] For example, the pixel sharing unit 539 of the first substrate 100 is the same as that described in the first embodiment above, and is formed over a pixel area of ​​2 columns × 2 rows, having a generally square planar shape (FIG. 60). For example, in each pixel sharing unit 539, the transmission gates TG1 and TG2 of pixels 541A and 541B of one pixel column extend toward the center of the pixel sharing unit 539 in the V direction, and the transmission gates TG3 and TG4 of pixels 541C and 541D of another pixel column extend to the outside of the pixel sharing unit 539 in the V direction. The pad portion 120 connected to the floating diffusion region FD is provided at the center of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at least in the V direction (V direction and H direction in FIG. 60) at the end of the pixel sharing unit 539. At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 are close to the V-direction position of the through electrode 120E, and the V-direction positions of the through electrodes TGV3 and TGV4 of the transmission gates TG3 and TG4 are close to the V-direction position of the through electrode 121E (Fig. 62). Therefore, for the same reasons as described in the first embodiment above, the width (size in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. Therefore, the size of the amplifying transistor AMP can be increased, and noise can be suppressed.

[0204] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL in the V direction across the insulating region 212 (Fig. 61). The FD conversion gain switching transistor FDG and the reset transistor RST are arranged in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction (Fig. 64), and the fourth wiring layer W4 extends in the V direction (Fig. 65).

[0205] The imaging device 1 having this second substrate 200 can also achieve the same effect as described in the first embodiment above. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the first and second embodiments and this variation. For example, the semiconductor layer 200S described in the first and second embodiments and variation 12 above can also extend in the H direction.

[0206] <8. Variation 15> Figure 66 shows a variation of the cross-sectional configuration of the imaging device 1 in the above-described embodiments. Figure 66 corresponds to Figure 3 described in the first embodiment above. In this variation, the imaging device 1, in addition to the contact portions 201, 202, 301, and 302, has contact portions 203, 204, 303, and 304 at positions corresponding to the center of the pixel array portion 540. The imaging device 1 in this variation differs from the imaging device 1 described in the first embodiment above in this respect.

[0207] Contact portions 203 and 204 are disposed on the second substrate 200, exposing their mating surfaces with the third substrate 300. Contact portions 303 and 304 are disposed on the third substrate 300, exposing their mating surfaces with the second substrate 200. Contact portions 203 are connected to contact portions 303, and contact portions 204 are connected to contact portions 304. That is, in this imaging device 1, the second substrate 200 and the third substrate 300 are connected not only by contact portions 201, 202, 301, and 302, but also by contact portions 203, 204, 303, and 304.

[0208] Next, the operation of the imaging device 1 will be explained using Figures 67 and 68. Figure 67 shows the paths of the input signal, power supply potential, and reference potential from the external input to the imaging device 1 using arrows. Figure 68 shows the signal paths of the pixel signal output from the imaging device 1 to the external input using arrows. For example, the input signal input to the imaging device 1 via the input section 510A is transmitted to the column drive section 520 of the third substrate 300, where the column drive section 520 generates a column drive signal. This column drive signal is then sent to the second substrate 200 via the contact sections 303 and 203. Furthermore, this column drive signal reaches each of the pixel common units 539 of the pixel array section 540 via the column drive signal line 542 in the wiring layer 200T. The drive signal other than the transmission gate TG in the column drive signal reaching the pixel common unit 539 of the second substrate 200 is input to the pixel circuit 210, driving each transistor contained in the pixel circuit 210. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, driving pixels 541A, 541B, 541C, and 541D. Furthermore, the power supply potential and reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via contacts 303 and 203, and then supplied to the pixel circuits 210 of each of the pixel common units 539 via wiring within the wiring layer 200T. The reference potential is further supplied to pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, the pixel signals from pixels 541A, 541B, 541C, and 541D of the first substrate 100, after photoelectric conversion, are sent to the pixel circuit 210 of the second substrate 200 via the pixel sharing unit 539. The pixel signal based on this pixel signal is then sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 204 and 304. After being processed by the line signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, the pixel signal is output to the outside via the output unit 510B.

[0209] The camera device 1 having such contact portions 203, 204, 303, and 304 can also achieve the same effect as described in the first embodiment above. The position and number of the contact portions can be changed according to the design of the circuit of the third substrate 300, etc., at the connection end of the wiring via the contact portions 303 and 304.

[0210] <9. Variation 16> FIG69 shows a variation of the cross-sectional configuration of the imaging device 1 of the above-described embodiments. FIG69 corresponds to FIG6 described in the first embodiment above. In this variation, a transmission transistor TR with a planar structure is provided on the first substrate 100. The imaging device 1 of this variation differs from the imaging device 1 described in the first embodiment above in this respect.

[0211] The transmission transistor TR consists only of the horizontal portion TGb forming the transmission gate TG. In other words, the transmission gate TG does not have a vertical portion TGa, which is positioned opposite to the semiconductor layer 100S.

[0212] The imaging device 1 with this planar structure of the transmission transistor TR can also achieve the same effect as described in the first embodiment above. Furthermore, it is also believed that by providing a planar transmission gate TG on the first substrate 100, compared with the case where a vertical transmission gate TG is provided on the first substrate 100, the photodiode PD is formed closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation signal quantity (Qs). In addition, it is also believed that the method of forming a planar transmission gate TG on the first substrate 100 has fewer manufacturing steps than the method of forming a vertical transmission gate TG on the first substrate 100, and is less likely to produce adverse effects on the photodiode PD due to manufacturing steps.

[0213] <10. Variation 17> Figure 70 shows a variation of the pixel circuit of the imaging device 1 in the above-described embodiments. Figure 70 corresponds to Figure 4 described in the first embodiment above. In this variation, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 may not be shared by multiple pixels. The imaging device 1 in this variation differs from the imaging device 1 described in the first embodiment above in this respect.

[0214] The imaging device 1 of this variation has the same points on which the pixel 541A and the pixel circuit 210 are disposed on different substrates (first substrate 100 and second substrate 200) as the imaging device 1 described in the first embodiment above. Therefore, the imaging device 1 of this variation can also obtain the same effect as that described in the first embodiment above.

[0215] <11. Variation 18> FIG71 shows a variation of the planar configuration of the pixel separation portion 117 described in the above embodiments. A gap may also be provided in the pixel separation portion 117 surrounding each of pixels 541A, 541B, 541C, and 541D. That is, the pixel separation portion 117 may not completely surround the pixels 541A, 541B, 541C, and 541D. For example, the gap in the pixel separation portion 117 may be provided near the pad portions 120 and 121 (see FIG7B).

[0216] In the first embodiment described above, an example of the pixel separation portion 117 having an FTI structure that penetrates the semiconductor layer 100S has been described (see Figure 6). However, the pixel separation portion 117 may also have a structure other than an FTI structure. For example, the pixel separation portion 117 may not be provided in a manner that completely penetrates the semiconductor layer 100S, and may also have a so-called DTI (Deep Trench Isolation) structure.

[0217] <12. Variation 19> Figure 72 is a schematic cross-sectional view of the main components of the imaging device 1 of Variation 19 disclosed herein. Figure 73 is a schematic planar view of the second substrate 200 of the imaging device shown in Figure 72. Furthermore, Figure 72 shows a cross-section corresponding to the E-E' line shown in Figure 73. The imaging device 1 with a GAA structure AMP described in the second embodiment above can be formed, for example, as follows.

[0218] First, a sacrificial layer 120A is pre-formed on the pad portion 120 that connects the floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, FD4) of each of the pixels 541A, 541B, 541C, and 541D, for example, using chemical vapor deposition (CVD).

[0219] As a material for the sacrificial layer 120A, a material whose etch selectivity with the silicon oxide film increases due to oxidation can be used, for example. Examples of such materials include Ge. Furthermore, as a material for the sacrificial layer 120A, a material whose etch selectivity with the silicon oxide film increases can be used, for example. Examples of such materials include III-V compound semiconductor materials (e.g., InGaAs, InP, and GaAs) or amorphous carbon. Hereinafter, the case of using Ge to form the sacrificial layer 120A will be described as an example.

[0220] Subsequently, similar to the second embodiment described above, the semiconductor layer 200S is bonded to the first substrate 100, and an insulating region 212 and a component separation region 213 are formed at specific locations.

[0221] Next, as shown in FIG74A, a sacrificial layer 235 and a polycrystalline silicon film 224X are deposited on the semiconductor layer 200S, for example, and a Si thin film layer having an insulating film 212X is attached to the lower surface of the sacrificial layer 235, which is opposite to the polycrystalline silicon film 224X side. Next, as shown in FIG74B, the polycrystalline silicon film 224X is processed, for example, by photolithography and reactive ion etching (RIE), to form an opening 224H through the polycrystalline silicon film 224X.

[0222] Next, for example, an alkaline aqueous solution (e.g., an etching solution of hydrogen fluoride: hydrogen peroxide: acetic acid = 1:200:3) with a SiGe / Si selectivity ratio of 10 or higher and a SiO2 / Si selectivity ratio of 7.5 or higher is prepared to etch the sacrificial layer 235. At this time, the sacrificial layer 235 also recedes in the planar direction, removing the sacrificial layer 235 below the channel 224. Next, as shown in FIG74C, after forming a photoresist film 234 protecting an opening 224H on the polycrystalline silicon film 224X, for example, the insulating region 212 and the wiring layer 100T are etched by dry etching using a gas containing halogen elements such as F, Cl, and Br, to form an opening 100H reaching the sacrificial layer 120A. Next, after removing the photoresist film 234, an annealing process is performed, as shown in FIG74D, to form a thermal oxide film serving as a gate insulating film 225 on the front side of the polycrystalline silicon film 224X containing the channel 224. At this point, the sacrificial layer 120A exposed at the bottom of the opening 100H is also oxidized, for example, forming a GeO2 layer 120X. Subsequently, it is washed, for example, with pure water. Thus, as shown in FIG74E, the GeO2 layer 120X is removed.

[0223] Alternatively, when a group III-V material is used to form the sacrificial layer 120A, the sacrificial layer 120A can be removed, for example, by washing with hydrochloric acid. When amorphous carbon is used to form the sacrificial layer 120A, the oxidized sacrificial layer 120A can be removed, for example, by washing with sulfuric acid / hydrogen peroxide.

[0224] Next, as shown in FIG74F, a polycrystalline silicon film 226X is formed around the channel 224 and the opening 100H, for example, using a CVD method. Herein, a through electrode 120E electrically connecting the gate AG and the amplifying transistor AMP to the floating diffusion region FD is also formed. Subsequently, similar to the second embodiment described above, a passivation film 221, an interlayer insulating film 222, and a first wiring layer W1 are formed sequentially. Based on the above, the second substrate 200 of the imaging device 1 shown in FIG72 is formed.

[0225] Furthermore, the imaging device 1 with an amplifying transistor AMP having a GAA structure described in the second embodiment above can be formed, for example, as follows.

[0226] First, as described above, a sacrificial layer 120A is pre-formed on the pad portion 120. Then, as in the second embodiment described above, the semiconductor layer 200S is bonded to the first substrate 100, and an insulating region 212 and a component separation region 213 are formed at specific locations.

[0227] Next, as shown in FIG75A, the polycrystalline silicon film 224X is bonded to the semiconductor layer 200S. Next, as shown in FIG75B, after processing the polycrystalline silicon film 224X by, for example, photolithography and RIE, an opening 224H is formed through the polycrystalline silicon film 224X.

[0228] Next, for example, wet etching is performed using fluoric acid diluted to an ultra-low concentration to remove the insulating region 212 below the polycrystalline silicon film 224X between the openings 224H. Next, as shown in FIG75C, after forming a photoresist film 234 protecting the opening 224H on the polycrystalline silicon film 224X, for example, dry etching is performed using a gas containing halogen elements such as F, Cl, and Br to etch the insulating region 212 and the wiring layer 100T, forming the opening 100H reaching the sacrificial layer 120A. Next, after removing the photoresist film 234, an annealing process is performed, as shown in FIG75D, to form a thermal oxide film serving as a gate insulating film 225 on the front side of the polycrystalline silicon film 224X. At this time, the sacrificial layer 120A exposed at the bottom of the opening 100H is also oxidized, forming a GeO2 layer 120X. Afterward, for example, it is washed with pure water. Therefore, as shown in Figure 75E, the GeO2 layer 120X is removed.

[0229] Next, as shown in FIG75F, a polycrystalline silicon film 226X is formed, for example, around the channel 224 and the opening 100H. Herein, a through electrode 120E electrically connecting the gate AG and the amplifying transistor AMP to the floating diffusion region FD is also formed. Subsequently, similar to the second embodiment described above, a passivation film 221, an interlayer insulating film 222, and a first wiring layer W1 are formed sequentially. Based on the above, the second substrate 200 of the imaging device 1 shown in FIG72 is formed.

[0230] As described above, in this variation, a sacrificial layer 120A is formed on the pad portion 120 beforehand. This allows for the simultaneous formation of a through electrode 120E that electrically connects the gate AG and the amplifying transistor AMP to the floating diffusion region FD. In addition to the effects of the second embodiment described above, this simplifies the manufacturing process and reduces the bonding resistance. Furthermore, since the amplifying transistor AMP can be formed without stripping the oxide film around the channel 224, the instability of the threshold voltage in the second substrate 200 caused by parasitic transistors at nearby contacts can be reduced.

[0231] <13. Variation 20> Figure 76 is a schematic cross-sectional view of the main components of the imaging device 1 of Variation 20 disclosed herein. Figure 77 is an equivalent circuit diagram of the imaging device 1 shown in Figure 76. In the first embodiment described above, an example is shown in which the floating diffusion region FD is directly connected to the gate AG of the amplifying transistor AMP via a through electrode 120E. However, for example, the floating diffusion region FD can also be directly connected to the source RS of the reset transistor RST via a through electrode 120E1.

[0232] In the above embodiments, a pixel circuit 210 including an FD conversion gain switching transistor FDG is shown, but the FD conversion gain switching transistor FDG may be omitted. In this case, as shown in FIG77, the source RS of transistor RST is reset to the same potential as the floating diffusion region FD and the gate AG of amplification transistor AMP.

[0233] In this variation, the reset transistor RST has a finned FD-SOI structure, with its source and drain formed from the front side (surface 200S1) and back side (surface 200S2) of the semiconductor layer 200S. Therefore, as shown in FIG76, by connecting the through electrode 120E1 to the surface 200S2 of the semiconductor layer 200S where the source RS of the reset transistor RST is formed, the floating diffusion region FD can be electrically connected to the source RS of the reset transistor RST. Such an imaging device 1 can be formed, for example, as follows.

[0234] First, as shown in FIG78A, wiring such as pad portions 120 and 121 and gate TGb of transmission transistor TR is formed on semiconductor layer 100S. Next, as shown in FIG78B, after forming an interlayer insulating film 123 covering the wiring on semiconductor layer 100S, a through electrode 120E1 reaching the pad portion 120 is provided to form wiring layer 100T.

[0235] Next, as shown in FIG78C, the semiconductor layer 200S is attached to the wiring layer 100T. Next, as shown in FIG78D, a source follower circuit or amplifying transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD conversion gain switching transistor FDG are formed on the semiconductor layer 200S. At this time, the gate RG of at least the reset transistor RST is configured to penetrate the fin structure of the semiconductor layer 200S. Thereby, the source RS of the reset transistor RST and the floating diffusion region FD are electrically connected via the through electrode 120E1. There are no restrictions on other transistors, but for the purpose of simplifying the number of steps or the structure, it is preferable to configure them with the same fin structure as the reset transistor RST.

[0236] Subsequently, an interlayer insulating film 222 or various wirings are installed to form a wiring layer 200T. Based on the above, the camera device 1 shown in Figure 76 is completed.

[0237] Thus, in this variation, the floating diffusion region FD and the source RS of the reset transistor RST are directly connected via the through electrode 120E1. This eliminates the need for additional wiring to electrically connect the floating diffusion region FD and the reset transistor RST, thereby reducing the area of ​​the insulating region 212 formed in the plane of the semiconductor layer 200S and ensuring the area of ​​the semiconductor layer 200S forming the pixel circuit 210. In other words, the area efficiency of the pixel transistor constituting the pixel circuit 210 in the second substrate 200 can be improved.

[0238] Furthermore, this variation shows an example where, in order to directly connect the floating diffusion region FD and the source RS of the reset transistor RST via the through electrode 120E1, the floating diffusion region FD and the source RS of the reset transistor RST are arranged in an overlapping manner in the stacking direction when viewed from above. However, this is not limited to this. For example, as shown in FIG79, wiring extending in the in-plane direction can also be provided in the wiring layer 100T and used as part of the through electrode 120E1 connecting the floating diffusion region FD and the source RS of the reset transistor RST. This increases the freedom of layout of the pixel transistors provided in the semiconductor layer 200S.

[0239] Furthermore, in this variation, an example is shown where the floating diffusion region FD and the source RS of the reset transistor RST are directly connected by the through electrode 120E1, but this can also be combined with, for example, variation 5. That is, as shown in FIG80, the side surface of the source RS of the reset transistor RST and the side surface of the gate AG of the amplification transistor AMP are connected to the through electrode 120E of the through semiconductor layer 200S and the wiring layer 100T. In this way, the area of ​​the insulating region 212 formed in the plane of the semiconductor layer 200S can be reduced. That is, the area efficiency of the pixel transistor constituting the pixel circuit 210 in the second substrate 200 can be improved.

[0240] <14. Variation 21> Figure 81 is a schematic cross-sectional view of the main components of the imaging device 1 of Variation 21 disclosed herein. Figure 82 is a schematic planar view of the second substrate 200 of the imaging device 1 shown in Figure 81. In the above embodiments, an example is shown in which the gate AG of the amplifying transistor AMP and the source FS of the FD conversion gain switching transistor FDG are electrically connected via the connection portion 218V and the first wiring W1, but it is not limited to this.

[0241] In this variation, the imaging device 1 extends the polysilicon 226 forming the gate of the pixel transistor between the amplifying transistor AMP and the FD conversion gain switching transistor FDG, and uses it to electrically connect the gate AG of the amplifying transistor AMP to the source FS of the FD conversion gain switching transistor FDG. Such an imaging device 1 can be formed, for example, as follows.

[0242] First, as shown in FIG83A, a semiconductor layer 200S is processed, and fins 223 constituting various transistors of the pixel circuit 210 are formed on the wiring layer 100T. Then, a silicon oxide film serving as a gate insulating film 225 is formed around the fins 223.

[0243] Next, as shown in FIG83B, a photoresist film 240 with a specific pattern is formed on the wiring layer 100T, forming an opening 100H that reaches the solder pad portion 120. Next, as shown in FIG83C, the opening 100H is buried on the wiring layer 100T, and a photoresist film 241 covering the fins 223 constituting the FD conversion gain switching transistor FDG is formed, and the gate insulating film 225 disposed around the source electrode FS of the fins 223 constituting the FD conversion gain switching transistor FDG is peeled off.

[0244] Next, after removing the photoresist film 241, as shown in FIG83D, a polycrystalline silicon film 226X covering the fin 223 and having an opening 100H embedded is formed. Next, as shown in FIG83E, the polycrystalline silicon film 226X is processed. Thereby, a polycrystalline silicon 226 is formed that connects the gates AG and FG of the amplifying transistor AMP and the FD conversion gain switching transistor FDG, the gate AG of the amplifying transistor AMP and the source FS of the FD conversion gain switching transistor FDG, and a through electrode 120E1 connected thereto.

[0245] Subsequently, an interlayer insulating film 222 or various wirings are installed to form a wiring layer 200T. Based on the above, the camera device 1 shown in Figure 81 is completed.

[0246] Thus, in this variation, the gate AG of the amplifying transistor AMP and the source FS of the FD conversion gain switching transistor FDG, which are at the same potential, are electrically connected using polysilicon 226 forming the gate of the pixel transistor. This polysilicon film and the pad portion 120 are electrically connected via a through electrode 120E1. This eliminates the need for a through wiring (e.g., through electrode 120E) between the first substrate 100 and the second substrate 200. Therefore, by reducing the area of ​​the insulating region 212 formed in the plane of the semiconductor layer 200S, the area of ​​the semiconductor layer 200S forming the pixel circuit 210 is ensured. That is, the area efficiency of the pixel transistor constituting the pixel circuit 210 in the second substrate 200 can be improved.

[0247] Furthermore, since it is not necessary to form the gate AG of the amplification transistor AMP with the same potential as the floating diffusion region FD above the pad portion 120, or the source FS of the FD conversion gain switching transistor FDG, the degree of freedom in the layout of the pixel transistors set on the semiconductor layer 200S is increased.

[0248] Furthermore, Figure 81 shows an example of connecting the connection portion 218V connected to the first wiring layer W1 to the FD conversion gain switching transistor FDG, but it is not limited to this. For example, as shown in Figure 84, the connection portion 218V can also be connected to the amplifying transistor AMP. Alternatively, as shown in Figure 85, the connection portion 218V can be connected to the polysilicon 226, and the polysilicon 226 connects the gate AG of the amplifying transistor AMP to the source FS of the FD conversion gain switching transistor FDG.

[0249] Alternatively, as shown in FIG86, the gate AG of the amplifying transistor AMP and the source FS of the FD conversion gain switching transistor FDG can be arranged in a straight line and connected by a polysilicon 226. This shortens the wiring length of the polysilicon 226 connecting the gate AG of the amplifying transistor AMP and the source FS of the FD conversion gain switching transistor FDG, thus reducing capacitance.

[0250] Alternatively, as shown in FIG87, a silicon oxide film may be retained around the source FS of the FD conversion gain switching transistor FDG, and the source FS of the FD conversion gain switching transistor FDG may be electrically connected to the polysilicon 226 via the connection portion 218V. <15. Variation 22> FIG88 is a schematic cross-sectional view of the main components of the imaging device 1 of Variation 22 disclosed herein. FIG89 is an equivalent circuit diagram of the imaging device 1 shown in FIG88. In the above embodiment, an example is shown in which the pixel circuit 210 is disposed on the second substrate 200, but it is not limited thereto. For example, a fourth substrate 400 including a semiconductor layer 400S may be disposed between the second substrate 200 and the third substrate 300, and a plurality of transistors constituting the pixel circuit 210 may be separately disposed on the semiconductor layers 200S and 400S.

[0251] Specifically, as shown in Figures 88 and 89, the amplifying transistor AMP and the selection transistor SEL among the plurality of transistors constituting the pixel circuit 210 can be disposed on the semiconductor layer 200S, and the reset transistor RST and the FD conversion gain switching transistor FDG can be disposed on the semiconductor layer 400S. This reduces the pixel pitch and ensures the formation area of ​​the pixel transistors such as the amplifying transistor AMP.

[0252] Furthermore, when the amplifying transistor AMP and the selecting transistor SEL are disposed on the semiconductor layer 200S, and the reset transistor RST and the FD conversion gain switching transistor FDG are disposed on the semiconductor layer 400S, it is preferable to arrange them in the following planar layout. For example, it is preferable to arrange the source or drain of the transmission transistor TR, the gate AG of the amplifying transistor AMP, and the source of the FD conversion gain switching transistor FDG in an overlapping manner when viewed from above. In this way, by making the through electrode 120E extend to the fourth substrate 400, the source or drain of the transmission transistor TR, the gate AG of the amplifying transistor AMP, and the source of the FD conversion gain switching transistor FDG can be electrically connected by the through electrode 120E. That is, the wiring length can be minimized, and in principle, the FD capacitance can be minimized. In addition, since the number of vias used to electrically connect each pixel transistor is reduced, the pixel pitch can be further reduced. Furthermore, by reducing the stress caused by through-holes, the characteristic variations of the transistor can be reduced.

[0253] This camera device 1 can be formed, for example, as follows.

[0254] First, as shown in FIG90A, for example, by etching the semiconductor layer 200S, fins 233 of the amplifying transistor AMP and the selector transistor SEL are formed on the wiring layer 100T. Next, as shown in FIG90B, by forming the insulating region 212 and forming and processing the polysilicon film, the gates (e.g., gate AG) of the amplifying transistor AMP and the selector transistor SEL are formed.

[0255] Next, as shown in FIG90C, after forming the interlayer insulating film 222, as shown in FIG90D, the gate AG of the through-amplifier transistor AMP is formed, and the through electrode 120E is formed on the pad portion 120 disposed on the source or drain of the transmission transistor TR. Next, as shown in FIG90E, the semiconductor layer 400S is bonded to the wiring layer 200T.

[0256] Next, as shown in FIG90F, for example, after etching the semiconductor layer 400S, an insulating region 412 is formed. Next, as shown in FIG90G, the gates RG and FG of the reset transistor RST and the FD conversion gain switching transistor FDG are formed respectively. Thereafter, an interlayer insulating film 422 or various wirings are provided to form a wiring layer 400T. Based on the above, the imaging device 1 shown in FIG88 is completed.

[0257] Thus, in this variation, the amplifying transistor AMP and the selecting transistor SEL, which constitute the pixel circuit 210, are disposed on the semiconductor layer 200S, and the resetting transistor RST and the FD conversion gain switching transistor FDG are disposed on the semiconductor layer 400S. This reduces the pixel pitch and ensures the formation area of ​​the pixel transistors such as the amplifying transistor AMP.

[0258] Furthermore, since the source or drain of the transmission transistor TR, the gate AG of the amplification transistor AMP, and the source of the FD conversion gain switching transistor FDG overlap when viewed from above, they can be electrically connected by the through electrode 120E. Therefore, the FD capacitance can be minimized in principle. Also, by reducing the number of vias used to electrically connect the pixel transistors, the pixel pitch can be further reduced. In addition, by reducing the stress caused by the vias, the characteristic variation of the transistors can be reduced.

[0259] Furthermore, Figures 88 and 89 show an example of a plurality of transistors constituting the pixel circuit 210, including the FD conversion gain switching transistor FDG. However, as shown in Figure 92, the FD conversion gain switching transistor FDG can also be omitted. In this case, for example, as shown in Figure 91, the source or drain of the transmission transistor TR, the gate AG of the amplification transistor AMP, and the source of the reset transistor RST overlap when viewed from above, and these are electrically connected by the through electrode 120E.

[0260] Furthermore, Figures 88 and 91 show examples where the amplifying transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG constituting the pixel circuit 210 are disposed in semiconductor layer 200S, and the reset transistor RST and the FD conversion gain switching transistor FDG are disposed in semiconductor layer 400S, but this is not a limitation. For example, as shown in Figures 93 and 94, the reset transistor RST and the FD conversion gain switching transistor FDG may also be disposed in semiconductor layer 200S, and the amplifying transistor AMP and the selection transistor SEL may be disposed in semiconductor layer 400S.

[0261] This camera device 1 can be formed, for example, as follows.

[0262] First, as shown in FIG95A, after forming the through electrode 120E1 on the wiring layer 100T, the semiconductor layer 200S is bonded to the wiring layer 100T, for example by etching the semiconductor layer 200S. Next, as shown in FIG95B, after forming the insulating region 212, the gates RG and FG of the reset transistor RST and the FD conversion gain switching transistor FDG are formed on the semiconductor layer 200S, respectively.

[0263] Next, as shown in FIG95C, an interlayer insulating film 222 and a through electrode 120E2 penetrating the interlayer insulating film 222 are formed. Next, as shown in FIG95D, a semiconductor layer 400S is attached to a wiring layer 200T. Next, as shown in FIG95E, for example, by etching the semiconductor layer 400S, fins 433 of an amplifying transistor AMP and a selector transistor SEL are formed respectively.

[0264] Next, as shown in FIG95F, the gates (e.g., gate AG) of the amplifying transistor AMP and the selecting transistor SEL are formed by forming and processing polysilicon. Next, as shown in FIG95G, the insulating region 412 and the interlayer insulating film 422 are formed. Subsequently, various wirings are provided to form the wiring layer 400T. Based on the above, the imaging device 1 shown in FIG93 is completed.

[0265] Furthermore, Figure 93 shows an example in which the gate AG of the amplifying transistor AMP is electrically connected to the source of the FD conversion gain switching transistor FDG via a through electrode 120E1, and the source of the FD conversion gain switching transistor FDG is electrically connected to the gate AG of the amplifying transistor AMP via a through electrode 120E2, but this is not a limitation. For example, as shown in Figure 96, the through electrode 120E can be used to reach the surface 400S2 of the semiconductor layer 400S via the semiconductor layer 200S, and electrically connect the gate AG of the amplifying transistor AMP, the source of the FD conversion gain switching transistor FDG, and the gate AG of the amplifying transistor AMP. Furthermore, as shown in Figure 97, the through electrode 120E can be used to pass through the gate AG of the amplifying transistor AMP disposed on the fourth substrate.

[0266] Alternatively, as shown in FIG98, the contact portions 201 and 401 respectively disposed on the front side of the wiring layer 200T of the second substrate 200 opposite to the fourth substrate 400 and on the front side of the wiring layer 400T1 disposed on the side of the surface 400S2 of the fourth substrate 400 opposite to the second substrate 200 can be joined together and electrically connected to each other.

[0267] (Other variations) The above variations 1 to 22 can also be combined with each other.

[0268] <16. Applicable Example> Figure 99 shows one example of the general configuration of a camera system 7 having the above-described embodiments of a camera device 1.

[0269] The camera system 7 is an electronic device such as a digital camera or camcorder, or a portable terminal device such as a smartphone or tablet. The camera system 7 includes, for example, the camera device 1, DSP (digital signal processing) circuit 243, frame memory 244, display unit 245, memory unit 246, operation unit 247, and power supply unit 248 as described in the above embodiment. In the camera system 7, the camera device 1, DSP circuit 243, frame memory 244, display unit 245, memory unit 246, operation unit 247, and power supply unit 248 as described in the above embodiment are interconnected via busbar 249.

[0270] The imaging device 1 of the above embodiments outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 of the above embodiments. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 in frame units. The display unit 245 includes a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging device 1 of the above embodiments. The memory unit 246 records the image data of the moving or still images captured by the imaging device 1 of the above embodiments into a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands related to various functions of the imaging system 7 according to the user's operation. The power supply unit 248 will appropriately supply various power sources to the camera device 1, DSP circuit 243, frame memory 244, display unit 245, memory unit 246 and operation unit 247 in the above-described embodiments.

[0271] Next, the camera sequence of camera system 7 will be explained.

[0272] Figure 100 is an example of a flowchart showing the camera operation of the camera system 7. The user instructs the camera to start by operating the operation unit 247 (step S101). Then, the operation unit 247 sends the camera command to the camera device 1 (step S102). After receiving the camera command, the camera device 1 (specifically, the system control circuit 36) performs camera operation in a specific camera mode (step S103).

[0273] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 243. Here, the image data refers to the data of all pixels based on the pixel signal generated by the charge temporarily held in the floating diffusion region FD. The DSP circuit 243 performs specific signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data after specific signal processing in the frame memory 244, and the frame memory 244 stores the image data in the memory section 246 (step S105). In this way, imaging by the imaging system 7 is performed.

[0274] In this application example, the camera device 1 of the above-described embodiments is applied to the camera system 7. This allows for miniaturization or high-resolution imaging of the camera device 1, thus providing a small or high-resolution camera system 7.

[0275] <17. Application Examples> [Application Example 1] The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein can also be implemented as a device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, drones, ships, and robots.

[0276] Figure 101 is a block diagram showing a schematic configuration example of a mobile body control system to which the technology disclosed herein is applicable, namely a vehicle control system.

[0277] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG101, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0278] The drive system control unit 12010 controls the operation of devices associated with the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or drive motor to generate drive force for the vehicle, a drive force transmission mechanism to transmit drive force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a braking device to generate braking force for the vehicle.

[0279] The vehicle system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for keyless start systems, smart key systems, power windows, or various lighting fixtures such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves or various switch signals sent by a portable device that replaces the key can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 accepts such radio waves or signal inputs and controls the vehicle's door lock devices, power window devices, lighting fixtures, etc.

[0280] The exterior information detection unit 12030 detects information about the exterior of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can also perform object detection processing or distance detection processing, such as detection of people, vehicles, obstacles, signs, or text on the road surface, based on the received images.

[0281] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0282] The in-vehicle information detection unit 12040 detects information inside the vehicle. A driver status detection unit 12041, which detects, for example, the driver's state, is connected to the in-vehicle information detection unit 12040. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, and can also determine whether the driver is dozing off.

[0283] The microcomputer 12051 can calculate the control target values ​​of the drive force generating device, steering mechanism, or braking device based on the information obtained from the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing ADAS (Advanced Driver Assistance System) functions, including avoiding vehicle collisions or mitigating impacts, following based on inter-vehicle distance, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0284] Furthermore, the microcomputer 12051 controls the drive force generating device, steering mechanism or braking device, etc., based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, and performs coordinated control for the purpose of autonomous driving without relying on the driver's operation.

[0285] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control such as switching the high beams to low beams to achieve anti-glare purposes.

[0286] The audio-visual output unit 12052 sends an output signal of at least one of sound and image to an output device that can provide visual or auditory notification information to the occupants of the vehicle or to the external visual or auditory information. In the example of FIG57, an amplifier 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. The display unit 12062 may also include at least one of, for example, an in-vehicle display and a head-up display.

[0287] Figure 102 is an example of the installation position of the camera unit 12031.

[0288] In Figure 102, the vehicle 12100 has camera units 12101, 12102, 12103, 12104, and 12105 as camera unit 12031.

[0289] Camera units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front bumper, side mirrors, rear bumper, tailgate, and above the windshield inside the vehicle 12100. Camera unit 12101, mounted on the front bumper, and camera unit 12105, mounted above the windshield inside the vehicle, primarily acquire images of the front of the vehicle 12100. Camera units 12102 and 12103, mounted on the side mirrors, primarily acquire images of the sides of the vehicle 12100. Camera unit 12104, mounted on the rear bumper or tailgate, primarily acquires images of the rear of the vehicle 12100. The images acquired by cameras 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lane markings ahead.

[0290] Furthermore, Figure 102 shows an example of the camera range of camera units 12101 to 12104. Camera range 12111 shows the camera range of camera unit 12101 installed on the front bumper; camera ranges 12112 and 12113 show the camera ranges of camera units 12102 and 12103 installed on the side mirrors, respectively; and camera range 12114 shows the camera range of camera unit 12104 installed on the rear bumper or tailgate. For example, by overlaying the image data captured by camera units 12101 to 12104, a top-down view of vehicle 12100 can be obtained.

[0291] At least one of the camera units 12101 to 12104 may also have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a camera containing a plurality of camera elements, or a camera element having pixels for phase difference detection.

[0292] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 calculates the distances between itself and various three-dimensional objects within the camera range 12111 to 12114, and the time variation of these distances (relative speed to vehicle 12100). This allows it to capture, in particular, the nearest three-dimensional object on the path of vehicle 12100 traveling at a specific speed (e.g., 0 km / h or higher) in a direction roughly the same as vehicle 12100, as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-defined distance from the vehicle ahead and perform automatic braking control (including follow-stop control) or automatic acceleration control (including follow-start control), etc. This allows for coordinated control aimed at autonomous driving without driver intervention.

[0293] For example, the microcomputer 12051 can classify and capture three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the cameras 12101 to 12104, for automatic obstacle avoidance. For example, the microcomputer 12051 can identify obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Furthermore, the microcomputer 12051 determines the collision risk, which indicates the degree of danger of colliding with each obstacle. When the collision risk is above a set value and there is a possibility of collision, it outputs an alarm to the driver via the loudspeaker 12061 or the display unit 12062, or performs forced deceleration or evasive steering via the drive system control unit 12010, thereby providing driving support for collision avoidance.

[0294] At least one of the camera units 12101 to 12104 may also be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the image captured by the camera units 12101 to 12104. The pedestrian identification is performed based on, for example, the order in which feature points of the image captured by the camera units 12101 to 12104, which are infrared cameras, are captured, and the order in which pattern matching processing is performed on a series of feature points representing the outline of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the image captured by the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay a square outline of the identified pedestrian for emphasis. Alternatively, the audio-visual output unit 12052 can also control the display unit 12062 to display icons representing pedestrians at desired locations.

[0295] The above has described an example of a mobile body control system to which the disclosed technology is applicable. The technology disclosed herein is applicable to the camera unit 12031 in the configuration described above. Specifically, the camera device 1 of the above-described embodiments is applicable to the camera unit 12031. By applying the technology disclosed herein to the camera unit 12031, high-resolution photographic images with less noise can be obtained, thus enabling high-precision control using the photographic images in the mobile body control system.

[0296] <Application Example 2> Figure 103 is a diagram showing an example of the general structure of an endoscopic surgical system to which the technology disclosed herein (the technology) is applicable.

[0297] Figure 103 illustrates the situation where the surgeon (doctor) 11131 uses the endoscopic surgical system 11000 to perform surgery on the patient 11132 on the bed 11133. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflator 11111 or energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a trolley 11200 equipped with various devices for endoscopic surgery.

[0298] The endoscope 11100 consists of an endoscope tube 11101 inserted into the body cavity of the patient 11132 at a specific distance from its tip, and a camera head 11102 connected to the base of the endoscope tube 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid endoscope tube 11101, but the endoscope 11100 can also be a so-called flexible endoscope having a flexible endoscope tube.

[0299] An opening for inserting a receiving lens is provided at the front end of the endoscope 11101. A light source device 11203 is connected to the endoscope 11100. The light generated by the light source device 11203 is guided to the front end of the endoscope 11101 by a light guide extending inside the endoscope 11101, and then illuminates the object to be observed inside the body cavity of the patient 11132 through the receiving lens. In addition, the endoscope 11100 can be a direct viewing endoscope, or an oblique viewing endoscope or a side viewing endoscope.

[0300] An optical system and an imaging element are provided inside the camera head 11102. Reflected light from the observed object (observation light) is focused onto the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is sent as RAW data to the camera control unit (CCU) 11201.

[0301] The CCU11201 is composed of a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing on the image signals, such as image processing (de-mosaic processing), to display the image based on the image signals.

[0302] The display device 11202 displays an image based on the image signal after image processing performed by the CCU11201, under the control of the CCU11201.

[0303] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies the illumination light used when photographing the surgical area to the endoscope 11100.

[0304] Input device 11204 is an input interface for the endoscopic surgery system 11000. Users can input various information or instructions into the endoscopic surgery system 11000 via input device 11204. For example, users can input instructions to change the imaging conditions of the endoscope 11100 (type of illumination light, magnification, and focal length, etc.).

[0305] The treatment device control device 11205 controls the operation of the energy treatment device 11112 used for tissue cauterization, incision, or vascular sealing. The pneumoperitoneum device 11206, for the purpose of ensuring the field of vision of the endoscope 11100 and ensuring the operator's working space, introduces gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111. The recorder 11207 is a device that can record various information related to the surgery. The printer 11208 is a device that can print various information related to the surgery in various forms such as text, images, or charts.

[0306] Furthermore, the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be, for example, an LED, a white light source composed of a laser light source, or a combination of the above. When a white light source is composed of a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision, thus allowing for white balance adjustment of the photographic image within the light source device 11203. In this case, by illuminating the observed object with laser light from each of the RGB laser light sources in a time-division manner, and synchronously controlling the driving of the imaging element of the camera head 11102 with the illumination timing, images corresponding to each of the RGB light sources can also be captured in a time-division manner. According to this method, color images can be obtained even without setting a color filter on the imaging element.

[0307] Furthermore, the light source device 11203 can also be controlled to change the intensity of the light to be output at specific intervals. By controlling the driving of the imaging element of the camera head 11102 in sync with the timing of the change in light intensity, images are acquired in time-division multiplexing and the images are synthesized, thereby producing images with high dynamic range that are free from underexposure and overexposure.

[0308] Furthermore, the light source device 11203 can also be configured to supply light of a specific wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow band imaging utilizes the wavelength dependence of light absorption by body tissues, irradiating a light with a narrower band than the illumination light used in normal observation (i.e., white light), thereby capturing images of specific tissues such as blood vessels on the surface of mucous membranes with high contrast. Alternatively, in special light observation, fluorescence observation can also be performed, obtaining images by irradiating fluorescence generated by excitation light. In fluorescence observation, excitation light can be irradiated onto body tissues to observe the fluorescence from those tissues (self-fluorescence observation), or reagents such as indocyanine green (ICG) can be locally injected into body tissues, and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissues to obtain a fluorescence image. The light source device 11203 can be configured to supply narrow band light and / or excitation light corresponding to this type of special light observation.

[0309] Figure 104 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU11201 shown in Figure 103.

[0310] The camera head 11102 includes a lens unit 11401, an image capturing unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 can be communicatively connected to each other via a transmission cable 11400.

[0311] The lens unit 11401 is an optical system disposed at the connection part with the lens barrel 11101. The observation light extracted from the front end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is composed of a plurality of lenses including a zoom lens and a focusing lens.

[0312] The camera unit 11402 is composed of camera elements. The camera element constituting the camera unit 11402 can be a single element (so-called single-plate type) or multiple elements (so-called multi-plate type). When the camera unit 11402 is composed of multiple elements, for example, by generating image signals corresponding to RGB values ​​from each camera element, a color image can be obtained by combining these signals. Alternatively, the camera unit 11402 can also be configured with a pair of camera elements for separately acquiring right-eye and left-eye image signals corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. Furthermore, when the camera unit 11402 is composed of multiple elements, multiple lens units 11401 can be provided corresponding to each camera element.

[0313] Furthermore, the camera unit 11402 may not necessarily be located on the camera head 11102. For example, the camera unit 11402 may also be located inside the lens barrel 11101, directly behind the object lens.

[0314] The drive unit 11403 is configured by an actuator, and under the control of the camera head control unit 11405, the zoom lens and focusing lens of the lens unit 11401 are moved a specific distance along the optical axis. In this way, the magnification and focus of the image captured by the imaging unit 11402 can be adjusted appropriately.

[0315] The communication unit 11404 is composed of a communication device for sending and receiving various information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the camera unit 11402 as RAM data to the CCU 11201 via the transmission cable 11400.

[0316] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera head 11102 and supplies them to the camera head control unit 11405. The control signals include information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0317] Furthermore, the aforementioned image capture conditions, such as frame rate, exposure value, magnification, and focus, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function are equipped on the endoscope 11100.

[0318] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0319] The communication unit 11411 is composed of a communication device for transmitting and receiving various information with the camera head 11102. The communication unit 11411 receives image signals transmitted via the transmission cable 11400 from the camera head 11102.

[0320] Furthermore, the communication unit 11411 sends control signals to the camera head 11102 to control the driving of the camera head 11102. The image signal or control signal can be transmitted via electrical communication or optical communication, etc.

[0321] The image processing unit 11412 performs various image processing on the RAM data, i.e., the image signal, sent by the camera head 11102.

[0322] The control unit 11413 performs various controls related to taking pictures of the surgical area using the endoscope 11100 and displaying the images obtained by taking pictures of the surgical area. For example, the control unit 11413 generates control signals to control the drive of the camera head 11102.

[0323] Furthermore, the control unit 11413, based on the image signal processed by the image processing unit 11412, causes the display device 11202 to display the camera image mapped onto the surgical area, etc. At this time, the control unit 11413 can also use various image recognition technologies to identify various objects within the camera image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific biological parts, bleeding, and mist when using the energy treatment device 11122 by detecting the edge shape or color of objects contained in the camera image. The control unit 11413 can also use the recognition results to overlay various surgical support information onto the image of the surgical area when displaying the camera image on the display device 11202. By overlaying the surgical support information to prompt the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0324] The transmission cable 11400 connecting the camera head 11102 and CCU11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable of the like.

[0325] Here, in the example shown, a wired communication is made using a transmission cable 11400, but wireless communication between the camera head 11102 and the CCU 11201 is also possible.

[0326] The above has described an example of an endoscopic surgical system to which the technology disclosed herein is applicable. The technology disclosed herein is preferably applicable to the imaging unit 11402 of the camera head 11102 of the endoscope 11100 in the configuration described above. By applying the technology disclosed herein to the imaging unit 11402, the imaging unit 11402 can be miniaturized or made more precise, thus providing a miniaturized or highly precise endoscope 11100.

[0327] Although the first and second embodiments and their variations 1 to 22, applicable examples and application examples have been given above to illustrate this disclosure, this disclosure is not limited to the above embodiments and can be varied in various ways. For example, in the above embodiments, the camera device 1 was used as an example to illustrate this technology, but this technology can also be applied to light-receiving elements and the like.

[0328] Furthermore, the effects described in this specification are merely illustrative. The effects disclosed herein are not limited to those described in this specification. This disclosure may also have effects other than those described in this specification.

[0329] Also, the present disclosure may also take the following configuration. According to the following configuration, since the charge accumulation portion disposed on the first semiconductor layer and the pixel transistor with a three-dimensional structure disposed on the second semiconductor layer are directly connected by a through wiring, the formation area other than the pixel transistor in the second semiconductor substrate can be reduced, and the area efficiency can be improved. (1) An imaging device comprising: a first semiconductor layer having a photoelectric conversion portion in each pixel and a charge accumulation portion for accumulating signal charge generated by the photoelectric conversion portion; a second semiconductor layer stacked on the first semiconductor layer, including a first surface of a pixel transistor having a three-dimensional structure and reading the signal charge from the charge accumulation portion; and a through wiring that directly connects the charge accumulation portion to the gate electrode of the pixel transistor. (2) The imaging device as described in (1) above, wherein the pixel transistor has a fin-type structure. (3) The imaging device described in (1) or (2) above, wherein the second semiconductor layer has a second surface opposite to the first semiconductor layer on the side opposite to the first surface, and the gate electrode passes through the first surface and the second surface of the second semiconductor layer. (4) The imaging device described in (3) above, wherein the end of the through portion of the gate electrode passing through the second semiconductor layer protrudes from the second surface of the second semiconductor layer. (5) The imaging device described in (4) above, wherein the through wiring connects the charge accumulation portion to the end of the gate electrode protruding from the second surface of the second semiconductor layer. (6) The imaging device described in any one of (3) to (5) above, wherein the through wiring is connected to the side surface of the gate electrode passing through the second semiconductor layer. (7) The imaging device described in (6) above, wherein the through wiring is connected to a portion of the upper surface of the gate electrode. (8) The imaging device described in any one of (3) to (7) above, wherein the pixel transistor has a plurality of fins, and the first width of the through wiring passing through the plurality of fins is narrower than the second width of the through wiring extending above the gate electrode. (9) The imaging device described in any one of (1) to (8) above, wherein the pixel transistor has a gate-enclosed structure.(10) The imaging device described in (9) above, wherein the pixel transistor comprises: a semiconductor layer disposed on the first surface side of the second semiconductor layer and extending in a direction substantially parallel to the planar direction of the second semiconductor layer; a gate electrode covering a portion of the upper surface, lower surface, and a pair of side surfaces of the semiconductor layer; a first insulating film and a second insulating film disposed between the semiconductor layer and the gate electrode, wherein the first insulating film covers the upper surface and the pair of side surfaces of the semiconductor layer, and the second insulating film covers the lower surface of the semiconductor layer; the second insulating film is provided to be wider than a third width in a direction orthogonal to the extension direction of the semiconductor layer. (11) The imaging device described in (10) above, wherein the extension portion of the second insulating film extending to the outer side of the third width of the semiconductor layer is formed below the second insulating film covering the lower surface of the semiconductor layer. (12) The imaging device described in (10) or (11) above, wherein the gate electrode has a protrusion on the side opposite to the first semiconductor layer that is wider than the through wiring. (13) The imaging device described in (12) above, wherein the width of the protrusion is wider than the wiring diameter of the through wiring. (14) The imaging device described in any one of (10) to (13) above, wherein the pixel transistor has: a semiconductor layer disposed on the first side of the second semiconductor layer and extending in a direction substantially parallel to the plane direction of the second semiconductor layer; the gate electrode covering a portion of the upper surface and lower surface and a pair of side surfaces of the semiconductor layer; and a third insulating film disposed between the semiconductor layer and the gate electrode, covering the upper surface and lower surface and the pair of side surfaces of the semiconductor layer; and the imaging device further has: a fourth insulating film disposed with a specific gap below the semiconductor layer. (15) The imaging device described in (14) above, wherein the fourth insulating film is provided to be wider than the third width of the semiconductor layer. (16) The imaging device described in (14) above, wherein the fourth insulating film is provided to be narrower than the third width of the semiconductor layer. (17) The imaging device described in (15) or (16) above, wherein the gate electrode has a protrusion on the side opposite to the first semiconductor layer that is wider than the fourth insulating film. (18) The imaging device described in (17) above, wherein the width of the protrusion is wider than the wiring diameter of the through wiring.(19) The imaging device described in any one of (10) to (18) above, wherein the pixel transistor is disposed on the first surface side of the second semiconductor, and the semiconductor layer extending in a direction substantially parallel to the planar direction of the second semiconductor layer has a source region and a drain region at both ends, and a sacrificial layer is further provided directly below the semiconductor layer of the source region and the drain region, the sacrificial layer having a side surface substantially the same as the side surface of the semiconductor layer. (20) The imaging device described in (19) above, wherein the semiconductor layer has a substantially constant width relative to the extending direction. (21) The imaging device described in any one of (1) to (20) above, wherein the pixel transistor has an amplifying transistor, a resetting transistor, a selecting transistor and an FD conversion gain switching transistor. (22) The imaging device described in (21) above, wherein the amplifying transistor, the resetting transistor, the selecting transistor and the FD conversion gain switching transistor each have the above three-dimensional structure. (23) The imaging device described in (22) above, wherein the gate electrode of at least one of the amplifying transistor, the reset transistor, the select transistor, and the FD conversion gain switching transistor extends between the first surface and the second surface of the second semiconductor layer, the second surface being opposite to the first surface and facing the first semiconductor layer. (24) The imaging device described in any one of (21) to (23) above, wherein the amplifying transistor has the three-dimensional structure, and the reset transistor, the select transistor, and the FD conversion gain switching transistor have a planar structure. (25) A light-receiving element comprising: a first semiconductor layer having a photoelectric conversion section and a charge accumulation section for accumulating signal charges generated by the photoelectric conversion section; a second semiconductor layer deposited on the first semiconductor layer, including a first surface of a transistor having a three-dimensional structure and reading out the signal charges from the charge accumulation section; and a through wiring that directly connects the charge accumulation section to the gate electrode of the transistor. (26) A method for manufacturing an imaging device, wherein a photoelectric conversion section and a charge accumulation section for accumulating signal charges generated by the photoelectric conversion section are formed for each pixel in the first semiconductor layer; a second semiconductor layer is deposited on the first surface of the first semiconductor layer, separating a first insulating film; a pixel transistor having a three-dimensional structure that reads out the signal charges from the charge accumulation section is formed in the second semiconductor layer; and a through wiring is formed that penetrates the first insulating film and directly connects the charge accumulation section to the gate electrode of the pixel transistor.(27) The method for manufacturing an imaging device as described in (26) above, wherein the pixel transistor is processed to form the second semiconductor layer to form a fin, the fin is embedded in a light-absorbing film that absorbs a first light of a specific wavelength, the first light is irradiated, and after forming layers with different etch rates on the light-absorbing film, the light-absorbing film is etched. (28) The method for manufacturing an imaging device as described in (27) above, wherein the second semiconductor layer is processed to form a fin, a high light absorption film with a higher absorption coefficient for the first light is formed on the front side of the fin, and the fin is embedded in the light-absorbing film. (29) The method of manufacturing an imaging device as described in any one of (26) to (28) above, wherein after the pixel transistor forms the through wiring, a second insulating film and a polycrystalline silicon film constituting the pixel transistor are sequentially deposited on the second semiconductor layer containing the through wiring, the second insulating film and the polycrystalline silicon film are processed into a specific shape of the pixel transistor, and a thermal oxide film is formed on the front side of the polycrystalline silicon film and the front side of the through wiring by means of annealing, and at least a portion of the thermal oxide film formed on the front side of the through wiring that is further outward than the polycrystalline silicon film when viewed from above is removed. (30) The method of manufacturing an imaging device as described in any one of (26) to (28) above, wherein after the pixel transistor forms the through wiring, a first sacrificial layer and a polycrystalline silicon film constituting the pixel transistor are sequentially deposited on the second semiconductor layer containing the through wiring, the first sacrificial layer and the polycrystalline silicon film are processed into a specific shape of the pixel transistor, the first sacrificial layer formed in the channel portion of the pixel transistor is removed, and a thermal oxide film is formed on the front side of the polycrystalline silicon film and the front side of the through wiring by annealing, and at least a portion of the thermal oxide film formed on the front side of the through wiring that is further outward than the polycrystalline silicon film when viewed from above is removed. (31) The method of manufacturing an imaging device as described in any one of (26) to (28) above, wherein after the pixel transistor forms the through wiring, a first sacrificial layer and a polycrystalline silicon film constituting the pixel transistor are sequentially deposited on the second semiconductor layer containing the through wiring, the first sacrificial layer and the polycrystalline silicon film are processed into a specific shape of the pixel transistor, and the first sacrificial layer formed below the channel portion of the pixel transistor is selectively removed by etching with an alkaline aqueous solution. (32) The method of manufacturing an imaging device as described in any one of (26) to (31) above, wherein after the charge accumulation portion is formed for each pixel, a second sacrificial layer is formed on the charge accumulation portion. (33) The method of manufacturing an imaging device as described in (32) above, wherein the second sacrificial layer is formed using a material whose etching selectivity with the first insulating film increases due to oxidation.(34) The method for manufacturing an imaging device as described in (33) above, wherein germanium is used to form the second sacrificial layer. (35) The method for manufacturing an imaging device as described in (32) above, wherein a material with greater etching selectivity than the first insulating film is used to form the second sacrificial layer. (36) The method for manufacturing an imaging device as described in (35) above, wherein a III-V compound semiconductor material is used to form the second sacrificial layer. (37) The method for manufacturing an imaging device as described in (32) above, wherein amorphous carbon is used to form the second sacrificial layer.

[0330] This application claims priority based on Japanese Patent Application No. 2020-178463 filed with the Japan Patent Office on October 23, 2020, and incorporates all contents of that application by reference.

[0331] If one is skilled in the art, various modifications, combinations, sub-combinations and alterations may be conceived based on design requirements or other reasons, but it should be understood that such modifications, combinations and alterations are included within the scope of the appended claims or their equivalents. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a block diagram showing an example of the functional configuration of the imaging device according to the first embodiment of the present disclosure. Figure 2 is a top view showing the general configuration of the imaging device shown in Figure 1. Figure 3 is a cross-sectional view showing the configuration along line III-III' shown in Figure 2. Figure 4 is an equivalent circuit diagram of the pixel sharing unit shown in Figure 1. Figure 5 is a diagram showing an example of the connection pattern of a plurality of pixel sharing units and a plurality of vertical signal lines. Figure 6 is a cross-sectional view showing an example of the specific configuration of the imaging device shown in Figure 3. Figure 7A is a schematic diagram showing an example of the planar configuration of an important part of the first substrate shown in Figure 6. Figure 7B is a schematic diagram showing the planar configuration of the pad portion together with the important part of the first substrate shown in Figure 7A. Figure 8 is a schematic diagram showing an example of the planar configuration of the second substrate (semiconductor layer) shown in Figure 6. Figure 9 is a schematic diagram showing an example of the planar configuration of the pixel circuit and an important part of the first substrate, together with the first wiring layer shown in Figure 6. Figure 10 is a schematic diagram showing an example of the planar configuration of the first and second wiring layers shown in Figure 6. Figure 11 is a schematic diagram showing an example of the planar configuration of the second and third wiring layers shown in Figure 6. Figure 12 is a schematic diagram showing an example of the planar configuration of the third and fourth wiring layers shown in Figure 6. Figure 13 is a schematic diagram showing a cross-sectional configuration of an important part of the imaging device shown in Figure 1. Figure 14 is a schematic diagram showing an example of the planar configuration of the second substrate shown in Figure 13. Figure 15 is a schematic diagram showing a cross-sectional configuration of a comparative example of an important part of the imaging device shown in Figure 13. Figure 16 is a schematic diagram showing an example of the planar configuration of the second substrate shown in Figure 15. Figure 17A is a flowchart showing the manufacturing steps of an important part of the imaging element shown in Figure 13. Figure 17B is a cross-sectional schematic diagram showing the steps following Figure 17A. Figure 17C is a cross-sectional schematic diagram showing the steps following Figure 17B. Figure 17D is a cross-sectional schematic diagram showing the steps following Figure 17C. Figure 18 is a schematic diagram illustrating the path of the input signal to the camera device shown in Figure 3. Figure 19 is a schematic diagram illustrating the signal path of the pixel signal of the camera device shown in Figure 3. Figure 20 is a cross-sectional schematic diagram showing the important parts of the camera device of Variation 1 of this disclosure. Figure 21 is a cross-sectional schematic diagram showing the important parts of the camera device of Variation 2 of this disclosure. Figure 22 is a cross-sectional schematic diagram showing the important parts of the camera device of Variation 3 of this disclosure. Figure 23 is a cross-sectional schematic diagram showing the important parts of the camera device of Variation 4 of this disclosure. Figure 24 is a cross-sectional schematic diagram showing the important parts of the camera device of Variation 5 of this disclosure. Figure 25 is a schematic diagram showing an example of the planar configuration of the second substrate of the imaging device shown in Figure 24. Figure 26 is a schematic diagram showing the cross-sectional configuration of an important part of the imaging device of Variation 6 of this disclosure.Figure 27 is a schematic cross-sectional view showing the important components of the imaging device of Variation 7 of this disclosure. Figure 28A is a flowchart showing one example of the manufacturing steps of Variation 8 of this disclosure. Figure 28B is a schematic cross-sectional view showing the steps following Figure 28A. Figure 28C is a schematic cross-sectional view showing the steps following Figure 28B. Figure 28D is a schematic cross-sectional view showing the steps following Figure 28C. Figure 28E is a schematic cross-sectional view showing the steps following Figure 28D. Figure 28F is a schematic cross-sectional view showing the steps following Figure 28E. Figure 29A is a flowchart showing another example of the manufacturing steps of Variation 8 of this disclosure. Figure 29B is a schematic cross-sectional view showing the steps following Figure 29A. Figure 29C is a schematic cross-sectional view showing the steps following Figure 29B. Figure 29D is a schematic cross-sectional view showing the steps following Figure 29C. Figure 30A is a flowchart showing another example of the manufacturing steps of Variation 8 of this disclosure. Figure 30B is a cross-sectional view showing the steps following Figure 30A. Figure 30C is a cross-sectional view showing the steps following Figure 30B. Figure 30D is a cross-sectional view showing the steps following Figure 30C. Figure 31A is a flowchart showing one example of the manufacturing steps of Variation 8 of this disclosure. Figure 31B is a cross-sectional view showing the steps following Figure 31A. Figure 31C is a cross-sectional view showing the steps following Figure 31B. Figure 31D is a cross-sectional view showing the steps following Figure 31C. Figure 32 is a cross-sectional view showing the cross-sectional structure of an important part of the camera device of the second embodiment of this disclosure. Figure 33 is a view showing an example of the planar structure of the camera device shown in Figure 32. Figure 34 is an enlarged view illustrating the structure of an important part of the camera device shown in Figure 32. Figure 35A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 32. Figure 35B is a cross-sectional view showing the steps following Figure 35A. Figure 35C is a cross-sectional view showing the steps following Figure 35B. Figure 35D is a cross-sectional view showing the steps following Figure 35C. Figure 35E is a cross-sectional view showing the steps following Figure 35D. Figure 35F is a cross-sectional view showing the steps following Figure 35E. Figure 35G is a cross-sectional view showing the steps following Figure 35F. Figure 35H is a cross-sectional view showing the steps following Figure 35G. Figure 35I is a cross-sectional view showing the steps following Figure 35H. Figure 36 is a cross-sectional view showing a comparative example of the cross-sectional structure of an important part of the camera device shown in Figure 33. Figure 37 is a cross-sectional view showing the cross-sectional structure of an important part of the camera device of Variation 9 of this disclosure. Figure 38A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 37. Figure 38B is a cross-sectional view showing the steps following Figure 38A. Figure 38C is a cross-sectional view showing the steps following Figure 38B. Figure 38D is a cross-sectional view showing the steps following Figure 38C.Figure 38E is a cross-sectional schematic diagram showing the steps following Figure 38D. Figure 39 is a schematic diagram showing an example of the cross-sectional structure of an important part of the camera device of Variation 10 of this disclosure. Figure 40 is an enlarged view illustrating the structure of the important part of the camera device shown in Figure 39. Figure 41A is a flowchart showing an example of the manufacturing steps of the important part of the camera device shown in Figure 39. Figure 41B is a cross-sectional schematic diagram showing the steps following Figure 41A. Figure 41C is a cross-sectional schematic diagram showing the steps following Figure 41B. Figure 41D is a cross-sectional schematic diagram showing the steps following Figure 41C. Figure 41E is a cross-sectional schematic diagram showing the steps following Figure 41D. Figure 42 is a schematic diagram showing another example of the cross-sectional structure of an important part of the camera device of Variation 10 of this disclosure. Figure 43 is a schematic diagram showing another example of the cross-sectional structure of an important part of the camera device of Variation 10 of this disclosure. Figure 44 is a schematic diagram showing an example of the planar structure of the imaging device according to Variation 11 of this disclosure. Figure 45A is a flowchart showing an example of the manufacturing steps of an important part of the imaging device of this disclosure. Figure 45B is a cross-sectional schematic diagram showing the steps following Figure 45A. Figure 45C is a cross-sectional schematic diagram showing the steps following Figure 45B. Figure 45D is a cross-sectional schematic diagram showing the steps following Figure 45C. Figure 45E is a cross-sectional schematic diagram showing the steps following Figure 45D. Figure 45F is a cross-sectional schematic diagram showing the steps following Figure 45E. Figure 45G is a cross-sectional schematic diagram showing the steps following Figure 45F. Figure 45H is a cross-sectional schematic diagram showing the steps following Figure 45G. Figure 45I is a cross-sectional schematic diagram showing the steps following Figure 45H. Figure 45J is a cross-sectional schematic diagram showing the steps following Figure 45I. Figure 46 is a schematic diagram showing one example of the planar configuration of the imaging device of Variation 11 of this disclosure. Figure 47 is a schematic diagram showing another example of the planar configuration of the imaging device of Variation 11 of this disclosure. Figure 48A is a flowchart showing one example of the manufacturing steps of another example of the imaging device of Variation 11 of this disclosure. Figure 48B is a cross-sectional schematic diagram showing the steps following Figure 48A. Figure 48C is a cross-sectional schematic diagram showing the steps following Figure 48B. Figure 49 is a schematic diagram showing one example of the planar configuration of the second substrate (semiconductor layer) shown in Figure 8. Figure 50 is a schematic diagram showing the planar configuration of the first wiring layer and important parts of the first substrate together with the pixel circuit shown in Figure 49. Figure 51 is a schematic diagram showing one example of the planar configuration of the second wiring layer together with the first wiring layer shown in Figure 50. Figure 52 is a schematic diagram showing one example of the planar configuration of the third wiring layer together with the second wiring layer shown in Figure 51. Figure 53 is a schematic diagram showing an example of the planar configuration of the fourth wiring layer, together with the third wiring layer shown in Figure 52. Figure 54 is a schematic diagram showing a variation of the planar configuration of the first substrate shown in Figure 7A.Figure 55 is a schematic diagram showing an example of a planar configuration of the second substrate (semiconductor layer) stacked on the first substrate shown in Figure 54. Figure 56 is a schematic diagram showing an example of a planar configuration of the first wiring layer together with the pixel circuit shown in Figure 55. Figure 57 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in Figure 56. Figure 58 is a schematic diagram showing an example of a planar configuration of the third wiring layer together with the second wiring layer shown in Figure 57. Figure 59 is a schematic diagram showing an example of a planar configuration of the fourth wiring layer together with the third wiring layer shown in Figure 58. Figure 60 is a schematic diagram showing another example of a planar configuration of the first substrate shown in Figure 54. Figure 61 is a schematic diagram showing an example of a planar configuration of the second substrate (semiconductor layer) stacked on the first substrate shown in Figure 60. Figure 62 is a schematic diagram showing an example of a planar configuration of the first wiring layer together with the pixel circuit shown in Figure 61. Figure 63 is a schematic diagram showing an example of the planar configuration of the second wiring layer together with the first wiring layer shown in Figure 62. Figure 64 is a schematic diagram showing an example of the planar configuration of the third wiring layer together with the second wiring layer shown in Figure 63. Figure 65 is a schematic diagram showing an example of the planar configuration of the fourth wiring layer together with the third wiring layer shown in Figure 64. Figure 66 is a cross-sectional schematic diagram showing another example of the imaging device shown in Figure 3. Figure 67 is a schematic diagram illustrating the path of the input signal to the imaging device shown in Figure 66. Figure 68 is a schematic diagram illustrating the signal path of the pixel signal of the imaging device shown in Figure 66. Figure 69 is a cross-sectional schematic diagram showing another example of the imaging device shown in Figure 6. Figure 70 is a diagram showing another example of the equivalent circuit shown in Figure 4. Figure 71 is a top view showing another example of the pixel separation section shown in Figures 7A, etc. Figure 72 is a schematic diagram showing an example of the cross-sectional configuration of an important part of the camera device of Variation 19 disclosed herein. Figure 73 is a schematic diagram showing an example of the planar configuration of the camera device shown in Figure 72. Figure 74A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 72. Figure 74B is a schematic cross-sectional view showing the steps following Figure 74A. Figure 74C is a schematic cross-sectional view showing the steps following Figure 74B. Figure 74D is a schematic cross-sectional view showing the steps following Figure 74C. Figure 74E is a schematic cross-sectional view showing the steps following Figure 74D. Figure 74F is a schematic cross-sectional view showing the steps following Figure 74E. Figure 75A is a flowchart showing another example of the manufacturing steps of an important part of the camera device shown in Figure 72. Figure 75B is a schematic cross-sectional view showing the steps following Figure 75A. Figure 75C is a schematic cross-sectional view showing the steps following Figure 75B. Figure 75D shows a cross-sectional view of the steps following Figure 75C. Figure 75E shows a cross-sectional view of the steps following Figure 75D. Figure 75F shows a cross-sectional view of the steps following Figure 75E.Figure 76 is a schematic diagram showing an example of the cross-sectional configuration of an important part of the camera device of Variation 20 of this disclosure. Figure 77 is a diagram showing an example of the equivalent circuit of the camera device shown in Figure 76. Figure 78A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 76. Figure 78B is a schematic cross-sectional view showing the steps following Figure 78A. Figure 78C is a schematic cross-sectional view showing the steps following Figure 78B. Figure 78D is a schematic cross-sectional view showing the steps following Figure 78C. Figure 79 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 20 of this disclosure. Figure 80 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 20 of this disclosure. Figure 81 is a schematic diagram showing an example of the cross-sectional configuration of an important part of the camera device of Variation 21 of this disclosure. Figure 82 is a schematic diagram showing an example of the planar configuration of the camera device shown in Figure 81. Figure 83A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 81. Figure 83B is a cross-sectional schematic diagram showing the steps following Figure 83A. Figure 83C is a cross-sectional schematic diagram showing the steps following Figure 83B. Figure 83D is a cross-sectional schematic diagram showing the steps following Figure 83C. Figure 83E is a cross-sectional schematic diagram showing the steps following Figure 83D. Figure 84 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 21 of this disclosure. Figure 85 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 21 of this disclosure. Figure 86 is a schematic diagram showing another example of the planar configuration of the camera device shown in Figure 81. Figure 87 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 21 of this disclosure. Figure 88 is a schematic diagram showing an example of the cross-sectional configuration of an important part of the camera device of Variation 22 of this disclosure. Figure 89 is a diagram showing an example of the equivalent circuit of the camera device shown in Figure 88. Figure 90A is a flowchart showing an example of the manufacturing steps of an important part of the camera device shown in Figure 88. Figure 90B is a schematic cross-sectional view showing the steps following Figure 90A. Figure 90C is a schematic cross-sectional view showing the steps following Figure 90B. Figure 90D is a schematic cross-sectional view showing the steps following Figure 90C. Figure 90E is a schematic cross-sectional view showing the steps following Figure 90D. Figure 90F is a schematic cross-sectional view showing the steps following Figure 90E. Figure 90G is a schematic cross-sectional view showing the steps following Figure 90F. Figure 91 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 22 of this disclosure. Figure 92 is a diagram showing one example of the equivalent circuit of the camera device shown in Figure 91. Figure 93 is a schematic diagram showing another example of the cross-sectional configuration of an important part of the camera device of Variation 22 of this disclosure. Figure 94 is a diagram showing one example of the equivalent circuit of the camera device shown in Figure 93.Figure 95A is a flowchart showing one example of the manufacturing steps of an important part of the camera device shown in Figure 93. Figure 95B is a cross-sectional view showing the steps following Figure 95A. Figure 95C is a cross-sectional view showing the steps following Figure 95B. Figure 95D is a cross-sectional view showing the steps following Figure 95C. Figure 95E is a cross-sectional view showing the steps following Figure 95D. Figure 95F is a cross-sectional view showing the steps following Figure 95E. Figure 95G is a cross-sectional view showing the steps following Figure 95F. Figure 96 is a schematic diagram showing another example of the cross-sectional structure of an important part of the camera device of Variation 22 of this disclosure. Figure 97 is a schematic diagram showing another example of the cross-sectional structure of an important part of the camera device of Variation 22 of this disclosure. Figure 98 is a schematic diagram showing another example of the cross-sectional structure of an important part of the camera device of Variation 22 of this disclosure. Figure 99 is a diagram showing an example of the schematic configuration of a camera system having the above-described embodiments and variations thereof. Figure 100 is a diagram showing an example of the camera sequence of the camera system shown in Figure 88. Figure 101 is a block diagram showing an example of the schematic configuration of a vehicle control system. Figure 102 is an explanatory diagram showing an example of the installation positions of the external information detection unit and the camera unit. Figure 103 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. Figure 104 is a block diagram showing an example of the functional configuration of the camera head and the CCU.

Claims

1. An imaging device comprising: a first semiconductor layer having a photoelectric conversion unit and a charge accumulation unit for accumulating signal charges generated by the photoelectric conversion unit in each pixel; a second semiconductor layer deposited on the first semiconductor layer, including a first surface of a pixel transistor having a three-dimensional structure and reading the signal charges from the charge accumulation unit; and a through wiring that directly connects the charge accumulation unit to the gate electrode of the pixel transistor.

2. The camera device of claim 1, wherein the pixel transistor has a fin-shaped structure.

3. The imaging device of claim 1, wherein the second semiconductor layer has a second surface opposite to the first surface and thus facing the first semiconductor layer, and the gate electrode passes through the first surface and the second surface of the second semiconductor layer.

4. The imaging device of claim 3, wherein the end of the through portion of the gate electrode that penetrates the second semiconductor layer protrudes from the second surface of the second semiconductor layer.

5. The imaging device of claim 4, wherein the through wiring connects the charge accumulation portion to the end of the gate electrode protruding from the second surface of the second semiconductor layer.

6. The imaging device of claim 3, wherein the through wiring is connected to the side of the gate electrode through the second semiconductor layer.

7. The imaging device of claim 6, wherein the through wiring is further connected to a portion of the upper surface of the gate electrode.

8. The imaging device of claim 3, wherein the pixel transistor has a plurality of fins, and the first width of the through wiring passing between the plurality of fins is narrower than the second width of the through wiring extending above the gate electrode.

9. The camera device of claim 1, wherein the pixel transistor has a fully enclosed gate structure.

10. The imaging apparatus of claim 9, wherein the pixel transistor comprises: a semiconductor layer disposed on the first surface side of the second semiconductor layer and extending in a direction substantially parallel to the planar direction of the second semiconductor layer; a gate electrode covering a portion of the upper surface, lower surface, and a pair of side surfaces of the semiconductor layer; a first insulating film and a second insulating film disposed between the semiconductor layer and the gate electrode, wherein the first insulating film covers the upper surface and the pair of side surfaces of the semiconductor layer, and the second insulating film covers the lower surface of the semiconductor layer. The second insulating film is provided to be wider than a third width in a direction orthogonal to the extending direction of the semiconductor layer.

11. The imaging device of claim 10, wherein the extension of the second insulating film extending beyond the third width of the semiconductor layer is formed below the second insulating film covering the lower surface of the semiconductor layer.

12. The imaging device of claim 10, wherein the gate electrode has a protrusion on the side facing the first semiconductor layer that is wider than the through wiring.

13. The camera device of claim 12, wherein the width of the protrusion is wider than the diameter of the through wiring.

14. The imaging device of claim 10, wherein the pixel transistor comprises: a semiconductor layer disposed on the first surface side of the second semiconductor layer and extending in a direction substantially parallel to the planar direction of the second semiconductor layer; the gate electrode covering a portion of the upper surface and lower surface and a pair of side surfaces of the semiconductor layer; and a third insulating film disposed between the semiconductor layer and the gate electrode, covering the upper surface and lower surface and the pair of side surfaces of the semiconductor layer; and the imaging device further comprises: a fourth insulating film disposed below the semiconductor layer with a specific gap.

15. The imaging device of claim 14, wherein the fourth insulating film is provided to be wider than the third width of the semiconductor layer.

16. The imaging device of claim 14, wherein the fourth insulating film is provided to be narrower than the third width of the semiconductor layer.

17. The imaging device of claim 15, wherein the gate electrode has a protrusion on the side facing the first semiconductor layer that is wider than the fourth insulating film.

18. The camera device of claim 17, wherein the width of the protrusion is wider than the diameter of the through wiring.

19. The imaging apparatus of claim 10, wherein the pixel transistor is disposed on the first surface side of the second semiconductor, and the semiconductor layer extending in a direction substantially parallel to the planar direction of the second semiconductor layer has a source region and a drain region at both ends, and a sacrificial layer is further provided directly below the semiconductor layer of the source region and the drain region, the sacrificial layer having a side surface substantially the same as the side surface of the semiconductor layer.

20. The imaging device of claim 19, wherein the semiconductor layer has a substantially constant width relative to the extension direction.

21. The camera device of claim 1, comprising an amplification transistor, a reset transistor, a selection transistor and an FD conversion gain switching transistor as the aforementioned pixel transistor.

22. The camera device of claim 21, wherein the amplifying transistor, the reset transistor, the selection transistor and the FD conversion gain switching transistor each have the aforementioned three-dimensional structure.

23. The imaging device of claim 22, wherein the gate electrode of at least one of the amplifying transistor, the reset transistor, the selection transistor and the FD conversion gain switching transistor passes through the first surface and the second surface of the second semiconductor layer, and the second surface is opposite to the first semiconductor layer on the side opposite to the first surface.

24. The imaging device of claim 21, wherein the amplifying transistor has the three-dimensional structure described above, and the reset transistor, the selection transistor and the FD conversion gain switching transistor have a planar structure.

25. A light-receiving element comprising: a first semiconductor layer having a photoelectric conversion section and a charge accumulation section for accumulating signal charges generated by the photoelectric conversion section; a second semiconductor layer deposited on the first semiconductor layer, including a first surface of a transistor having a three-dimensional structure and reading the signal charges from the charge accumulation section; and a through wiring that directly connects the charge accumulation section to the gate electrode of the transistor.