Semiconductor memory devices

Abstract

A semiconductor memory device includes: an active pattern located on a substrate, the active pattern including a source / drain pattern in an upper portion thereof; a gate electrode located on the active pattern and extending in a first direction, the gate electrode and the source / drain pattern being adjacent to each other in a second direction intersecting the first direction; and a shared contact coupled to the source / drain pattern and the gate electrode to electrically connect the source / drain pattern and the gate electrode. The shared contact includes an active contact and a gate contact electrically connected to the source / drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, the protruding portion protruding from the body portion in the second direction and extending into and embedded in the active contact.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This U.S. non - provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10 - 2021 - 0043961, filed with the Korean Intellectual Property Office on April 5, 2021, and Korean Patent Application No. 10 - 2021 - 0069543, filed with the Korean Intellectual Property Office on May 28, 2021, and the entire contents of each of the above - identified applications are incorporated herein by reference.

[0003] This disclosure relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including static random access memory (SRAM) cells and a method of manufacturing the same. Prior Art

[0004] Due to their small size, versatility, and / or low - cost characteristics, semiconductor devices are important components in the electronics industry. Semiconductor devices are classified into semiconductor memory devices configured to store data, semiconductor logic devices configured to process data, and hybrid semiconductor devices including both memory elements and logic elements. As the electronics industry progresses, the demand for semiconductor devices with improved characteristics is increasing. For example, the demand for semiconductor devices with high reliability, high performance, and / or an increasing number and types of functions is increasing. To meet such demand, the complexity and / or integration density of semiconductor devices are increasing. Summary of the Invention

[0005] Some embodiments of the inventive concept provide a semiconductor memory device having improved electrical characteristics.

[0006] Some embodiments of the inventive concept provide a method of manufacturing a semiconductor memory device having improved electrical characteristics.

[0007] According to some embodiments of the inventive concept, a semiconductor memory device may include: an active pattern located on a substrate, the active pattern including source / drain patterns in an upper portion of the active pattern; a gate electrode located on the active pattern and extending in a first direction, the gate electrode being adjacent to the source / drain patterns in a second direction crossing the first direction; and a shared contact coupled to the source / drain patterns and the gate electrode to electrically connect the source / drain patterns and the gate electrode. The shared contact may include an active contact electrically connected to the source / drain patterns and a gate contact electrically connected to the gate electrode. The gate contact may include a body portion coupled to the gate electrode and a protruding portion protruding from the body portion in the second direction. The protruding portion extends into the active contact and may be buried in the active contact.

[0008] According to some embodiments of the inventive concept, a semiconductor memory device may include SRAM cells located on a substrate. The SRAM cells may include: a first pull-up / pull-down transistor and a second pull-up / pull-down transistor; and a first node connecting a first common source / drain of the first pull-up / pull-down transistor to a first common gate of the second pull-up / pull-down transistor. The first node may include a first shared contact coupled to the first common source / drain and the first common gate to electrically connect the common source / drain and the first common gate. The first shared contact may include an active contact electrically connected to the first common source / drain, and the first shared contact may include a gate contact electrically connected to the first common gate. The gate contact may include a body portion coupled to the first common gate and a protruding portion protruding from the body portion toward the active contact. A top surface of the body portion may be coplanar with a top surface of the active contact. The protruding portion may overlap the active contact in a vertical direction, and the body portion may be offset from the active contact in a horizontal direction.

[0009] According to some embodiments of the inventive concept, a semiconductor memory device may include: a substrate including a bit cell region; a first active pattern and a second active pattern located on the bit cell region, the first active pattern being spaced apart from the second active pattern in a first direction, the first active pattern including a first source / drain pattern disposed in an upper portion of the first active pattern, the second active pattern including a second source / drain pattern disposed in an upper portion of the second active pattern; a device isolation layer disposed on the substrate to cover side surfaces of lower portions of each of the first active pattern and the second active pattern, upper portions of each of the first active pattern and the second active pattern extending above the device isolation layer; a gate electrode disposed on the first active pattern and extending in the first direction, the gate electrode and the first source / drain pattern being adjacent to each other in a second direction; a gate insulating layer located between the gate electrode and the first active pattern; a gate spacer located on at least one side surface of the gate electrode; a gate cap pattern located on the gate electrode; an interlayer insulating layer located on the gate cap pattern; an active contact extending through the interlayer insulating layer, coupled to the first source / drain pattern and the second source / drain pattern, and extending in the first direction to connect the first source / drain pattern and the second source / drain pattern to each other; a silicide pattern located between each of the first source / drain pattern and the second source / drain pattern and the active contact; a gate contact extending through the gate cap pattern and coupled to the gate electrode; and a first interconnection layer, a second interconnection layer, and a third interconnection layer stacked on the interlayer insulating layer in sequence. The gate contact may include a body portion coupled to the gate electrode and a protruding portion protruding from the body portion in the second direction. The protruding portion may extend into and be buried in the active contact.

[0010] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor memory device may include: forming an active pattern on a substrate; forming a gate electrode extending in a first direction on the active pattern; forming a source / drain pattern in an upper portion of the active pattern, the gate electrode and the source / drain pattern being adjacent to each other in a second direction intersecting the first direction; forming an active contact coupled to the source / drain pattern; forming a gate contact coupled to the active contact and the gate electrode, at least a portion of the gate contact overlapping the active contact in a vertical direction; and performing a planarization process to expose a top surface of the active contact. The active contact and the gate contact may be connected to each other as a shared contact. Brief Description of the Drawings

[0011] FIG. 1 is an equivalent circuit diagram showing an SRAM cell according to some embodiments of the concept of the present invention. FIG. 2 is a perspective view showing an interconnection layer of a semiconductor memory device according to some embodiments of the concept of the present invention. FIG. 3 is a plan view showing the memory cell shown in FIG. 2. FIG. 4 is a plan view showing a semiconductor memory device according to some embodiments of the concept of the present invention. FIGS. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D' and E-E' shown in FIG. 4, respectively. FIG. 6A is an enlarged cross-sectional view of a portion "M" shown in FIG. 5B. FIG. 6B is a perspective view schematically showing the first shared contact shown in FIG. 6A. FIG. 7 is an enlarged cross-sectional view showing a part of a comparison device, the part corresponding to the part "M" shown in FIG. 5B. FIGS. 8A to 12D are cross-sectional views showing operations of a method of manufacturing a semiconductor memory device according to some embodiments of the concept of the present invention. FIG. 13 is an enlarged cross-sectional view corresponding to the part "M" shown in FIG. 5B and showing a semiconductor memory device according to some embodiments of the concept of the present invention. FIGS. 14A, 14B and 14C are cross-sectional views taken along lines A-A', B-B' and D-D' shown in FIG. 4, respectively, and showing a semiconductor memory device according to some embodiments of the concept of the present invention. Embodiments

[0012] FIG. 1 is an equivalent circuit diagram showing a static random access memory (SRAM) cell according to some embodiments of the concept of the present invention.

[0013] Referring to FIG. 1, the SRAM cell may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first pass-gate transistor TA1, and a second pass-gate transistor TA2. The first pull-up transistor TU1 and the second pull-up transistor TU2 may be P-channel metal-oxide semiconductor (PMOS) transistors. The first pull-down transistor TD1 and the second pull-down transistor TD2, and the first pass-gate transistor TA1 and the second pass-gate transistor TA2 may be N-channel metal-oxide semiconductor (NMOS) transistors.

[0014] Both the first source / drain of the first pull-up transistor TU1 and the first source / drain of the first pull-down transistor TD1 may be connected to a first node N1. The second source / drain of the first pull-up transistor TU1 may be connected to a power line VDD, and the second source / drain of the first pull-down transistor TD1 may be connected to a ground line VSS. The gate of the first pull-up transistor TU1 and the gate of the first pull-down transistor TD1 may be electrically connected to each other. The first pull-up transistor TU1 and the first pull-down transistor TD1 may form a first inverter. The connected gate of the first pull-up transistor TU1 and the first pull-down transistor TD1 may correspond to the input terminal of the first inverter, and the first node N1 may correspond to the output terminal of the first inverter.

[0015] Both the first source / drain of the second pull-up transistor TU2 and the first source / drain of the second pull-down transistor TD2 may be connected to a second node N2. The second source / drain of the second pull-up transistor TU2 may be connected to a power line VDD, and the second source / drain of the second pull-down transistor TD2 may be connected to a ground line VSS. The gate of the second pull-up transistor TU2 and the gate of the second pull-down transistor TD2 may be electrically connected to each other. Thus, the second pull-up transistor TU2 and the second pull-down transistor TD2 may form a second inverter. The connected gate of the second pull-up transistor TU2 and the second pull-down transistor TD2 may correspond to the input terminal of the second inverter, and the second node N2 may correspond to the output terminal of the second inverter.

[0016] The first inverter and the second inverter can be combined to form a latch structure. For example, the gates of both the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to the second node N2, and the gates of both the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to the first node N1. The first source / drain of the first channel gate transistor TA1 can be connected to the first node N1, and the second source / drain of the first channel gate transistor TA1 can be connected to the first bit line BL1. The first source / drain of the second channel gate transistor TA2 can be connected to the second node N2, and the second source / drain of the second channel gate transistor TA2 can be connected to the second bit line BL2. The gates of the first channel gate transistor TA1 and the second channel gate transistor TA2 can be electrically coupled to the word line WL. Therefore, an SRAM cell according to some embodiments of the present invention concept can be achieved.

[0017] FIG. 2 is a perspective view showing an interconnection layer of a semiconductor memory device according to some embodiments of the present invention concept. FIG. 3 is a plan view showing the memory cell shown in FIG. 2.

[0018] Referring to FIGS. 2 and 3, memory cells CE can be provided on a substrate 100. Referring to FIG. 3, the memory cells CE can include first to fourth bit cells CE1 to CE4 arranged in a 2×2 array. Each of the first to fourth bit cells CE1 to CE4 can be, for example, the SRAM cell described above with reference to FIG. 1. As a representative example of the first to fourth bit cells CE1 to CE4, the structure of the first bit cell CE1 will be described in more detail with reference to FIGS. 4 and 5A to 5E. Each of the second bit cell CE2, the third bit cell CE3, and the fourth bit cell CE4 can be arranged to have a structure similar and / or symmetric to that of the first bit cell CE1.

[0019] A first interconnection layer M1, a second interconnection layer M2, and a third interconnection layer M3 can be provided on the memory cells CE. The first interconnection layer M1, the second interconnection layer M2, and the third interconnection layer M3 can be stacked in sequence. The first interconnection layer M1, the second interconnection layer M2, and the third interconnection layer M3 can be stacked in the third direction D3. The first interconnection layer M1, the second interconnection layer M2, and the third interconnection layer M3 can be formed of at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum) or include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0020] The first interconnection layer M1 may include a first bit line BL1, a second bit line BL2, and a power line VDD that may extend in a second direction D2. The power line VDD may be sandwiched between the first bit line BL1 and the second bit line BL2. When observed in a plan view, the first bit line BL1, the second bit line BL2, and the power line VDD may have a linear pattern. When measured in a first direction D1, the width of the power line VDD may be greater than the width of each of the first bit line BL1 and the second bit line BL2. The first direction D1, the second direction D2, and the third direction D3 may be perpendicular to each other.

[0021] The first interconnection layer M1 may further include at least one first lower landing pad LLP1 and at least one second lower landing pad LLP2 that may be disposed adjacent to the first bit line BL1 and the second bit line BL2. In some embodiments, the first interconnection layer M1 may include a plurality of first lower landing pads LLP1 and a plurality of second lower landing pads LLP2. The first lower landing pad LLP1 and the second lower landing pad LLP2 may be spaced apart from each other in the second direction D2. When observed in a plan view, each of the first lower landing pad LLP1 and the second lower landing pad LLP2 may be an island-shape pattern.

[0022] The first interconnection layer M1 may further include first vias (not shown in FIGS. 2 and 3) disposed respectively below the first bit line BL1, the second bit line BL2, the power line VDD, the first lower landing pad LLP1, and the second lower landing pad LLP2. The memory cell CE and the first interconnection layer M1 may be electrically connected to each other via the first vias.

[0023] The second interconnection layer M2 may include a ground line VSS and at least one upper landing pad ULP. The ground line VSS may be a mesh conductive structure. The ground line VSS may have at least one first opening OP1. Specifically, the ground line VSS may include at least one first portion P1 extending in the second direction D2 and at least one second portion P2 extending in the first direction D1. The width of the first portion P1 in the first direction D1 may be greater than the width of the second portion P2 in the second direction D2. The first opening OP1 may be defined by an adjacent pair of first portions P1 and an adjacent pair of second portions P2.

[0024] An adjacent pair of upper landing pads ULP may be located within the first opening OP1. The adjacent pair of upper landing pads ULP located within the first opening OP1 may be spaced apart from each other in the second direction D2. When observed in a plan view, the upper landing pad ULP may be an island-shape pattern.

[0025] For example, when observed in a plan view, a second portion P2 of the ground line VSS may overlap with a first lower landing pad LLP1 in a third direction D3. When observed in a plan view, the upper landing pad ULP may overlap with a second lower landing pad LLP2.

[0026] The second interconnect layer M2 may further include second vias VI2 respectively disposed under the ground line VSS and the upper landing pad ULP. The ground line VSS may be electrically connected to the first lower landing pad LLP1 of the first interconnect layer M1 via the second vias VI2. A plurality of second vias VI2 may be disposed under the ground line VSS, and a plurality of first lower landing pads LLP1 may be commonly connected to a single ground line VSS. The upper landing pad ULP may be electrically connected to the second lower landing pad LLP2 of the first interconnect layer M1 via corresponding second vias VI2.

[0027] In some embodiments, the second interconnect layer M2 may only include the ground line VSS, the upper landing pad ULP, and the second vias VI2. In other words, except for the ground line VSS, the second interconnect layer M2 may not include any other lines (e.g., bit lines, power lines, and word lines).

[0028] The third interconnect layer M3 may include word lines WL that may extend in a first direction D1. The word lines WL may be spaced apart from each other in a second direction D2. When observed in a plan view, the word lines WL may be linear patterns.

[0029] The third interconnect layer M3 may further include at least one third via VI3 disposed under the word lines WL. Each word line WL may be electrically connected to at least one upper landing pad ULP of the second interconnect layer M2 via at least one third via VI3. In other words, each word line WL may be electrically connected to at least one second lower landing pad LLP2 of the first interconnect layer M1 via the third via VI3, the upper landing pad ULP, and the second via VI2.

[0030] In some embodiments, the third interconnect layer M3 may only include the word lines WL and the third vias VI3. In other words, except for the word lines WL, the third interconnect layer M3 may not include any other lines (e.g., bit lines, power lines, and ground lines).

[0031] FIG. 4 is a plan view showing a semiconductor memory device according to some embodiments of the concepts of the present invention. FIG. 4 is a plan view showing SRAM cells (specifically, the first bit cell and the second bit cell shown in FIG. 3) according to the circuit diagram shown in FIG. 1. FIGS. 5A to 5E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' shown in FIG. 4, respectively. FIG. 6A is an enlarged cross-sectional view of a portion "M" shown in FIG. 5B. FIG. 6B is a perspective view schematically showing the first shared contact shown in FIG. 6A.

[0032] Referring to FIGS. 1, 3, 4, and 5A to 5E, each of the first bit cell CE1 and the second bit cell CE2 on the substrate 100 may include the SRAM cell shown in FIG. 1, such as the SRAM cell discussed with respect to FIG. 1. The second bit cell CE2 may be disposed adjacent to the first bit cell CE1 in the second direction D2. A first active pattern AP1, a second active pattern AP2, a gate electrode GE, an active contact AC, and a gate contact GC may be disposed on the first bit cell CE1 and the second bit cell CE2. Hereinafter, as a representative example of the bit cell, the first bit cell CE1 will be described in more detail below.

[0033] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may define the first active pattern AP1 and the second active pattern AP2. The substrate 100 may be a semiconductor substrate formed of silicon, germanium, silicon-germanium, or a compound semiconductor material or include silicon, germanium, silicon-germanium, or a compound semiconductor material. The device isolation layer ST may be formed of or include at least one insulating material (e.g., silicon oxide).

[0034] The first active pattern AP1 and the second active pattern AP2 may be some portions of the substrate 100. A trench TR may be defined between adjacent first active pattern AP1 and second active pattern AP2 in the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may be located in the trench TR. The upper portions of the first active pattern AP1 and the second active pattern AP2 may extend in the vertical direction and have a shape protruding above the device isolation layer ST. Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 may be a fin structure protruding above the device isolation layer ST in the vertical direction. For example, each of the first active pattern AP1 and the second active pattern AP2 may be an active fin.

[0035] In some embodiments, the first cell element CE1 may include a pair of first active patterns AP1 and two pairs of second active patterns AP2. One pair of the two pairs of second active patterns AP2 may form the body of the first channel gate transistor TA1 and the body of the first pull-down transistor TD1. The other pair of the two pairs of second active patterns AP2 may form the body of the second channel gate transistor TA2 and the body of the second pull-down transistor TD2. One of the first active patterns AP1 in the pair of first active patterns AP1 may form the body of the first pull-up transistor TU1. The other active pattern AP1 in the pair of first active patterns AP1 may form the body of the second pull-up transistor TU2. The distance between two active patterns AP1 in an adjacent pair of first active patterns AP1 may be greater than the distance between two active patterns AP2 in an adjacent pair of second active patterns AP2.

[0036] In some embodiments, two second active patterns AP2 may be provided instead of the two pairs (or four) of second active patterns AP2. In other words, in some embodiments, a pair of second active patterns AP2 adjacent to each other may be combined to form a single second active pattern AP2.

[0037] A first channel pattern CH1 and a first source / drain pattern SD1 may be disposed in the upper portion of the first active pattern AP1. A second channel pattern CH2 and a second source / drain pattern SD2 may be disposed in the upper portion of the second active pattern AP2. The first source / drain pattern SD1 may be a p-type impurity region. The second source / drain pattern SD2 may be an n-type impurity region. Each first channel pattern CH1 may be sandwiched between a pair of first source / drain patterns SD1, and each second channel pattern CH2 may be sandwiched between a pair of second source / drain patterns SD2.

[0038] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. The first source / drain pattern SD1 and the second source / drain pattern SD2 may have top surfaces located at a level higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be formed of a semiconductor material the same as or different from the material of the substrate 100 or may include a semiconductor material the same as or different from the material of the substrate 100. In some embodiments, the first source / drain pattern SD1 may be formed of a semiconductor material having a lattice constant greater than that of the substrate 100 or may include a semiconductor material having a lattice constant greater than that of the substrate 100. Accordingly, the first source / drain pattern SD1 may apply compressive stress to the first channel pattern CH1. In some embodiments, the second source / drain pattern SD2 may be formed of a semiconductor material the same as that of the substrate 100 or may include a semiconductor material the same as that of the substrate 100.

[0039] The second source / drain patterns SD2 on an adjacent pair of second active patterns AP2 may be combined to form a single second source / drain electrode. This may be because the distance between the pair of second active patterns AP2 is relatively small (as best shown in FIG. 5C).

[0040] The gate electrode GE may include a first gate electrode GE1 to a fourth gate electrode GE4 located on the first cell element CE1. The first gate electrode GE1 to the fourth gate electrode GE4 may extend in a first direction D1 and may cross the first active pattern AP1 and the second active pattern AP2. When observed in a plan view, the first gate electrode GE1 to the fourth gate electrode GE4 may overlap the first channel pattern CH1 and the second channel pattern CH2. The first gate electrode GE1 may be symmetric with the fourth gate electrode GE4, and the second gate electrode GE2 may be symmetric with the third gate electrode GE3.

[0041] The second gate electrode GE2 and the fourth gate electrode GE4 may be aligned parallel to the first direction D1 and parallel to each other. The insulating pattern SP may be sandwiched between the second gate electrode GE2 and the fourth gate electrode GE4 to separate the second gate electrode GE2 and the fourth gate electrode GE4 from each other. The first gate electrode GE1 and the third gate electrode GE3 may be aligned parallel to the first direction D1 and parallel to each other. As best shown in FIG. 5D, the insulating pattern SP may be sandwiched between the first gate electrode GE1 and the third gate electrode GE3 to separate the first gate electrode GE1 and the third gate electrode GE3 from each other.

[0042] As best shown in FIGS. 5A and 5B, a pair of gate spacers GS may be provided on opposite side surfaces of the gate electrode GE. The pair of gate spacers GS may extend along the gate electrode GE in a first direction D1. The pair of gate spacers GS may have a top surface that is higher than the top surface of the gate electrode GE. The top surface of the pair of gate spacers GS may be covered by a gate capping pattern GP, which will be described below.

[0043] The gate spacer GS may be formed of at least one of SiO, SiCN, SiCON, or SiN or may include at least one of SiO, SiCN, SiCON, or SiN. As another alternative, the gate spacer GS may be a multi-layer structure including at least two of SiO, SiCN, SiCON, or SiN.

[0044] The gate insulating layer GI may be sandwiched between the gate electrode GE and the first active pattern AP1 and the second active pattern AP2. The gate insulating layer GI may extend along the bottom surface of the gate electrode GE. In some embodiments, the gate insulating layer GI may be sandwiched between the gate electrode GE and the gate spacer GS.

[0045] In some embodiments, the gate insulating layer GI may include a high dielectric constant (high-k) dielectric layer or a combination of a silicon oxide layer and a high dielectric constant dielectric layer. The high dielectric constant dielectric layer may be formed of at least one high dielectric constant dielectric material having a dielectric constant higher than that of silicon oxide or may include at least one high dielectric constant dielectric material having a dielectric constant higher than that of silicon oxide. For example, the at least one high dielectric constant dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalate, and / or lead zinc niobate.

[0046] In some embodiments, the semiconductor device may include a negative capacitance (NC) field-effect transistor (FET) using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric properties and a paraelectric layer exhibiting paraelectric properties.

[0047] The ferroelectric layer may have a negative capacitance, and the paraelectric layer may have a positive capacitance. When two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance may be reduced to a value less than the capacitance of each capacitor. In contrast, when at least one capacitor in a set of capacitors connected in series has a negative capacitance, the total capacitance of the capacitors connected in series may have a positive value and may be greater than the absolute value of each capacitance.

[0048] When a ferroelectric layer having a negative capacitance is connected in series with a paraelectric layer having a positive capacitance, the total capacitance of the series-connected ferroelectric layer and paraelectric layer may increase. Due to this increase in the total capacitance, a transistor including the ferroelectric layer may have a subthreshold swing (SS) that may be less than 60 millivolts per decade of leakage current change (mV / decade) at room temperature.

[0049] The ferroelectric layer may have ferroelectric properties. As an example, the ferroelectric layer may be formed of or include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, and / or lead zirconate titanate. In some embodiments, hafnium zirconium oxide may be hafnium oxide doped with zirconium (Zr). As another alternative, hafnium zirconium oxide may be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0050] The ferroelectric layer may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0051] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0052] When the dopant is aluminum (Al), the content of aluminum in the ferroelectric layer may range from 3 atomic percent (atomic %) to 8 atomic %. Here, the content of aluminum as the dopant may be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0053] When the dopant is silicon (Si), the content of silicon in the ferroelectric layer can range from 2 atomic % to 10 atomic %. When the dopant is yttrium (Y), the content of yttrium in the ferroelectric layer can range from 2 atomic % to 10 atomic %. In the case where the dopant is gadolinium (Gd), the content of gadolinium in the ferroelectric layer can range from 1 atomic % to 7 atomic %. When the dopant is zirconium (Zr), the content of zirconium in the ferroelectric layer can range from 50 atomic % to 80 atomic %.

[0054] The paraelectric layer can have paraelectric properties. The paraelectric layer can be formed of or include at least one of, for example, silicon oxide and / or a high dielectric constant metal oxide. The metal oxides that can be used as the paraelectric layer can include at least one of, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0055] The ferroelectric layer and the paraelectric layer can be formed of or include the same material. The ferroelectric layer can have ferroelectric properties, but the paraelectric layer may not have ferroelectric properties. For example, when the ferroelectric layer and the paraelectric layer include hafnium oxide, the crystal structure of hafnium oxide in the ferroelectric layer can be different from the crystal structure of hafnium oxide in the paraelectric layer.

[0056] Only when the thickness of the ferroelectric layer is within a specific range can it exhibit ferroelectric properties. In some embodiments, the ferroelectric layer can have a thickness ranging from 0.5 nm to 10 nm, but the inventive concept is not limited to this example. Since the critical thickness associated with the emergence of ferroelectric properties can vary depending on the type of ferroelectric material, the thickness of the ferroelectric layer can change depending on the type of ferroelectric material.

[0057] In some embodiments, the gate insulating layer GI can include a single ferroelectric layer. In some embodiments, the gate insulating layer GI can include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI can have a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0058] The gate electrode GE can include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern can be disposed on the gate insulating layer GI and adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern can include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be achieved.

[0059] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), and nitrogen (N). The first metal pattern may further include carbon (C). The first metal pattern may include a plurality of work function metal layers that can be stacked on top of each other.

[0060] The second metal pattern may include a metal material having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0061] As shown in FIG. 5D, the second gate electrode GE2 may be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The fourth gate electrode GE4 may be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. In other words, the transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., a fin-type field-effect transistor (FinFET)) in which the gate electrode is disposed to three-dimensionally surround the channel pattern.

[0062] The gate cap pattern GP may be disposed on the gate electrode GE, where each gate cap pattern GP is disposed on a corresponding gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE in the first direction D1. The gate cap pattern GP may be formed of or include at least one of the following materials: a material selected to have an etching selectivity with respect to the first interlayer insulating layer 110, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140, which will be described below. For example, the gate cap pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0063] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0064] The first interlayer insulating layer 110 may include a lower insulating layer LIL and an upper insulating layer UIL. The upper insulating layer UIL may cover the gate cap pattern GP and the recessed portion RSP of the active contact AC, and the recessed portion RSP will be described below. The upper insulating layer UIL may be formed of the same or different insulating materials as the lower insulating layer LIL or may include the same or different insulating materials as the lower insulating layer LIL. For example, the lower insulating layer LIL may be formed of or include SiO, and the upper insulating layer UIL may be formed of or include SiO, SiOC, or SiC.

[0065] The active contact AC may be disposed to penetrate or extend through the first interlayer insulating layer 110 and may be coupled to the first source / drain pattern SD1 and the second source / drain pattern SD2. The active contact AC may have a top surface coplanar with the top surface of the first interlayer insulating layer 110. In some embodiments, the active contact AC may include first to eighth active contacts AC1 to AC8 located on the first bit cell CE1.

[0066] The active contact AC may be a self-aligned contact. In other words, the active contact may be formed by using a self-alignment method of the gate cap pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate cap pattern GP.

[0067] As shown in FIGS. 5C and 5E, the active contact AC may include a connection portion CNP and a recessed portion RSP. The top surface of the connection portion CNP of the active contact AC may be higher than the top surface of the recessed portion RSP. The top surface of the connection portion CNP of the active contact AC may be coplanar with the top surface of the first interlayer insulating layer 110. The upper insulating layer UIL may be disposed on the top surface of the recessed portion RSP of the active contact AC.

[0068] The first via VI1 may be located on the connection portion CNP. In other words, the connection portion CNP may extend in the vertical direction (i.e., the third direction D3) and may be in contact with the first via VI1. The active contact AC may be electrically connected to the first interconnection layer M1 via the connection portion CNP and the first via VI1.

[0069] The connection portion CNP of the second active contact AC2 can contact the first gate contact GC1 (as shown in FIG. 5B). The second active contact AC2 can be electrically connected to the first gate contact GC1 via the connection portion CNP. The connection portion CNP of the fifth active contact AC5 can contact the second gate contact GC2 (as shown in FIG. 5B). The fifth active contact AC5 can be electrically connected to the second gate contact GC2 via the connection portion CNP.

[0070] The silicide pattern SC can be sandwiched between the active contact AC and the source / drain pattern SD1 or SD2 connected to the silicide pattern SC. In other words, the active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 via the silicide pattern SC. The silicide pattern SC can be formed of at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide) or include at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0071] The gate contact GC can be disposed on the gate electrode GE and electrically connected to the gate electrode GE. The gate contact GC can penetrate or extend through the first interlayer insulating layer 110, the gate spacer GS, and the gate cap pattern GP, and the gate contact GC can be coupled to the gate electrode GE.

[0072] The top surface of the gate contact GC and the top surface of the connection portion CNP of the active contact AC can be coplanar with the top surface of the first interlayer insulating layer 110. The bottom surface of the gate contact GC can be higher than the bottom surface of the active contact AC. The bottom surface of the gate contact GC can be higher than the top surface of the recessed portion RSP of the active contact AC and lower than the top surface of the connection portion CNP.

[0073] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one metal among aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM may cover the side surface and the bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal nitride layer or may have a structure including a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0074] The gate contact GC may include a first gate contact GC1 and a second gate contact GC2 located on the first cell element CE1. The first gate contact GC1 may be coupled to the third gate electrode GE3, and the second gate contact GC2 may be coupled to the second gate electrode GE2.

[0075] As shown in FIGS. 4 and 5B, the first gate contact GC1 and the second active contact AC2 contacting each other on the first cell element CE1 may constitute a first shared contact SHC1. The third gate electrode GE3 may be electrically connected to the first source / drain pattern SD1 adjacent to the third gate electrode GE3 via the first shared contact SHC1 (e.g., via the first gate contact GC1 and the second active contact AC2). The second gate contact GC2 and the fifth active contact AC5 contacting each other may constitute a second shared contact SHC2.

[0076] The second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140 may be sequentially stacked on the first interlayer insulating layer 110. In some embodiments, the second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140 may be formed of or include silicon oxide.

[0077] The first interconnection layer M1 may be disposed in the second interlayer insulating layer 120. The first interconnection layer M1 may include a first bit line BL1, a second bit line BL2, a power line VDD, a first lower landing pad LLP1, a second lower landing pad LLP2, and a first via VI1, as described above with reference to FIG. 2.

[0078] The second internal connection layer M2 may be disposed in the third interlayer insulating layer 130. The second internal connection layer M2 may include a ground line VSS, an upper overlap pad ULP, and a second via hole VI2, as described above with reference to FIG. 2.

[0079] The third internal connection layer M3 may be disposed in the fourth interlayer insulating layer 140. The third internal connection layer M3 may include a word line WL and a third via hole VI3, as described above with reference to FIG. 2.

[0080] In the first cell CE1, the first active pattern AP1 and the second active pattern AP2 and the first gate electrode GE1 to the fourth gate electrode GE4 may form a memory transistor. The memory transistor of the first cell CE1 may include the first pull-up transistor TU1, the first pull-down transistor TD1, the second pull-up transistor TU2, the second pull-down transistor TD2, the first channel gate transistor TA1, and the second channel gate transistor TA2 described above with reference to FIG. 1.

[0081] The first gate electrode GE1 may be used as the gate of the first channel gate transistor TA1. The first gate electrode GE1 may be electrically connected to the word line WL. The second gate electrode GE2 may be used as a common gate of the first pull-down transistor TD1 and the first pull-up transistor TU1. The third gate electrode GE3 may be used as a common gate of the second pull-down transistor TD2 and the second pull-up transistor TU2. The fourth gate electrode GE4 may be used as the gate of the second channel gate transistor TA2. The fourth gate electrode GE4 may be electrically connected to the word line WL.

[0082] The first active contact AC1 may be electrically connected to the second source / drain of the first pull-down transistor TD1. The first active contact AC1 may be electrically connected to the ground line VSS.

[0083] The second active contact AC2 may be electrically connected to the common source / drain (e.g., the first source / drain) of the first pull-down transistor TD1 and the first channel gate transistor TA1. The second active contact AC2 may extend in the first direction D1 and may be electrically connected to the first source / drain of the first pull-up transistor TU1.

[0084] The first gate contact GC1 and the second active contact AC2 can form a first shared contact SHC1. The second active contact AC2 and the third gate electrode GE3 can be electrically connected to each other via the first shared contact SHC1. In other words, the common source / drain of the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to the common gate of the second pull-up transistor TU2 and the second pull-down transistor TD2 via the first shared contact SHC1. The first shared contact SHC1 can correspond to the first node N1 shown in FIG. 1.

[0085] The third active contact AC3 can be electrically connected to the second source / drain of the first channel gate transistor TA1. The third active contact AC3 can be electrically connected to the first bit line BL1 via the first via hole VI1 (as shown in FIG. 5A).

[0086] The fourth active contact AC4 can be electrically connected to the second source / drain of the first pull-up transistor TU1. The fourth active contact AC4 can be electrically connected to the power line VDD via the first via hole VI1 (as shown in FIG. 5B).

[0087] The fifth active contact AC5 can be electrically connected to the first source / drain of the second pull-up transistor TU2. The fifth active contact AC5 can extend in the first direction D1 and can be electrically connected to the common source / drain (e.g., the first source / drain) of the second pull-down transistor TD2 and the second channel gate transistor TA2.

[0088] The second gate contact GC2 and the fifth active contact AC5 can form a second shared contact SHC2. The fifth active contact AC5 and the second gate electrode GE2 can be electrically connected to each other via the second shared contact SHC2. In other words, the common source / drain of the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to the common gate of the first pull-up transistor TU1 and the first pull-down transistor TD1 via the second shared contact SHC2. The second shared contact SHC2 can correspond to the second node N2 shown in FIG. 1.

[0089] The sixth active contact AC6 can be electrically connected to the second source / drain of the second pull-up transistor TU2. The sixth active contact AC6 can be electrically connected to the power line VDD via the first via hole VI1 (as shown in FIG. 5C).

[0090] The seventh active contact AC7 can be electrically connected to the second source / drain of the second channel gate transistor TA2. The seventh active contact AC7 can be electrically connected to the second bit line BL2 via the first via hole VI1.

[0091] The eighth active contact AC8 can be electrically connected to the second source / drain of the second pull-down transistor TD2. The eighth active contact AC8 can be electrically connected to the ground line VSS.

[0092] Referring to FIGS. 6A and 6B, each of the first gate contact GC1 of the first shared contact SHC1 and the second active contact AC2 may include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM of the first gate contact GC1 may be sandwiched between the conductive pattern FM of the first gate contact GC1 and the conductive pattern FM of the second active contact AC2.

[0093] The first gate contact GC1 may include a body portion BDP coupled to the third gate electrode GE3 and a protruding portion PRP protruding from the body portion BDP in the second direction D2 (e.g., in the horizontal direction). The protruding portion PRP may overlap with the second active contact AC2. The body portion BDP may not overlap with the second active contact AC2, or in other words, the body portion BDP may be offset from the second active contact AC2. The protruding portion PRP may be in direct contact with the second active contact AC2. In other words, the first gate contact GC1 may be connected to the second active contact AC2 via the barrier pattern BM and the conductive pattern FM of the protruding portion PRP.

[0094] The protruding portion PRP may extend from the body portion BDP toward the central portion of the second active contact AC2. The protruding portion PRP may enter the upper portion of the second active contact AC2. The protruding portion PRP may have a shape buried or inserted in the second active contact AC2.

[0095] The protruding portion PRP may be located at a level higher than the bottom surface of the body portion BDP. In other words, the lowermost portion of the protruding portion PRP may be higher than the top surface of the third gate electrode GE3. In some embodiments, the top surface of the protruding portion PRP may be coplanar with the top surface of the body portion BDP. In some embodiments, the top surface of the protruding portion PRP may be lower than the top surface of the body portion BDP.

[0096] Since the protruding portion PRP of the first gate contact GC1 has a structure buried in or inserted into the second active contact AC2, the contact area between the first gate contact GC1 and the second active contact AC2 can be relatively increased. Accordingly, the contact resistance between the first gate contact GC1 and the second active contact AC2 can be relatively decreased.

[0097] The protruding portion PRP of the first gate contact GC1 can overlap with the second active contact AC2. Due to this structure of the protruding portion PRP, when the first gate contact GC1 is formed, the alignment margin between the first gate contact GC1 and the second active contact AC2 can be ensured. In other words, due to the protruding portion PRP, misalignment problems between the first gate contact GC1 and the second active contact AC2 can be prevented. This can improve the reliability of the semiconductor memory device.

[0098] FIG. 7 is an enlarged cross-sectional view showing a part of a comparative structure, and the part shown corresponds to the part “M” shown in FIG. 5B. Referring to FIG. 7, the first gate contact GC1 may not include the protruding portion PRP shown in FIG. 6. In other words, the first gate contact GC1 may be composed only of the body portion BDP. The upper side surface of the first gate contact GC1 may contact the upper side surface of the second active contact AC2 in a two-dimensional contact manner or a surface-to-surface contact manner. In this case, the contact area between the first gate contact GC1 and the second active contact AC2 can be relatively small. Accordingly, the contact resistance between the first gate contact GC1 and the second active contact AC2 can have a relatively high value.

[0099] According to some embodiments of the inventive concept, the gate contact GC and the active contact AC can be arranged to contact each other in a three-dimensional contact manner rather than a two-dimensional contact manner or a planar contact manner, and the gate contact GC and the active contact AC can form a single shared contact SHC. This can reduce the electrical resistance of the shared contact SHC (e.g., the first node N1) and improve the operating characteristics and electrical characteristics (e.g., operating speed) of the SRAM cell.

[0100] FIGS. 8A to 12D are cross-sectional views showing operations of a method of manufacturing a semiconductor memory device according to some embodiments of the inventive concept. FIGS. 8A, 9A, 10A, 11A, and 12A are cross-sectional views taken along line A-A' shown in FIG. 4. FIGS. 8B, 9B, 10B, 11B, and 12B are cross-sectional views taken along line B-B' shown in FIG. 4. FIGS. 8C, 9C, 10C, 11C, and 12C are cross-sectional views taken along line C-C' shown in FIG. 4. FIGS. 8D, 9D, 10D, 11D, and 12D are cross-sectional views taken along line D-D' shown in FIG. 4.

[0101] Referring to FIGS. 4 and 8A to 8D, the substrate 100 may be patterned to form trenches TR that define the first active pattern AP1 and the second active pattern AP2. In other words, the trenches TR may be formed between the first active pattern AP1 and the second active pattern AP2.

[0102] An isolation layer ST may be formed in the trenches TR on the substrate 100. The isolation layer ST may be formed of or include at least one insulating material (e.g., silicon oxide). The isolation layer ST may be recessed to expose upper portions of the first active pattern AP1 and the second active pattern AP2. Accordingly, the upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude above the isolation layer ST in a vertical direction.

[0103] Referring to FIGS. 4 and 9A to 9D, a sacrificial pattern PP may be formed that intersects the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP may be formed to have a linear shape extending in a first direction D1. More specifically, the formation of the sacrificial pattern PP may include: forming a sacrificial layer on the entire top surface of the substrate 100; forming a hard mask pattern MA on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer may be formed of or include polysilicon.

[0104] A pair of gate spacers GS may be formed on opposite side surfaces of each sacrificial pattern PP. The formation of the gate spacers GS may include: forming a gate spacer layer conformal to the side surfaces of the sacrificial pattern PP on the substrate 100; and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. As another option, the gate spacer layer may be a multi-layered structure including at least two of SiCN, SiCON, or SiN.

[0105] A first source / drain pattern SD1 may be formed in an upper portion of the first active pattern AP1. A pair of first source / drain patterns SD1 may be formed at a first side and a second side of each sacrificial pattern PP. More specifically, the upper portion of the first active pattern AP1 may be etched by using the hard mask pattern MA and the gate spacer GS as an etching mask to form a first recess region RS1. During the etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 may be recessed.

[0106] The first source / drain pattern SD1 may be formed by performing a selective epitaxial growth process by using an inner surface of the first recess region RS1 of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain pattern SD1, a first channel pattern CH1 may be defined between each pair of the first source / drain patterns SD1. As an example, the first source / drain pattern SD1 may be formed of a semiconductor material (e.g., SiGe) having a lattice constant greater than the lattice constant of the substrate 100 or may include a semiconductor material (e.g., SiGe) having a lattice constant greater than the lattice constant of the substrate 100. Each first source / drain pattern SD1 may be a multilayer structure including a plurality of semiconductor layers.

[0107] In some embodiments, during the selective epitaxial growth process, the first source / drain pattern SD1 may be in-situ doped with impurities. In some embodiments, after the first source / drain pattern SD1 is formed, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0108] A second source / drain pattern SD2 may be formed in an upper portion of the second active pattern AP2. A pair of second source / drain patterns SD2 may be formed at a first side and a second side of each sacrificial pattern PP. More specifically, the upper portion of the second active pattern AP2 may be etched by using the hard mask pattern MA and the gate spacer GS as an etching mask to form a second recess region RS2.

[0109] The second source / drain pattern SD2 can be formed by performing a selective epitaxial growth process using the inner surface of the second recessed region RS2 of the second active pattern AP2 as a seed layer. As a result of forming the second source / drain pattern SD2, a second channel pattern CH2 can be defined between each pair of second source / drain patterns SD2. In some embodiments, the second source / drain pattern SD2 can be formed of or include the same semiconductor material (e.g., Si) as the substrate 100. The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0110] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed sequentially by different processes. In other words, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed at different times.

[0111] Referring to FIGS. 4 and 10A to 10D, a lower insulating layer LIL can be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MA, and the gate spacer GS. In some embodiments, the lower insulating layer LIL can include a silicon oxide layer.

[0112] The lower insulating layer LIL can be planarized until the top surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MA can be removed. Thus, the first interlayer insulating layer 110 can have a top surface that is substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0113] An insulating pattern SP can be formed by removing a portion of the exposed sacrificial pattern PP and filling the removed portion with an insulating material. Due to the presence of the insulating pattern SP, the gate electrode GE to be formed in subsequent steps can be divided into a first gate electrode GE1 to a fourth gate electrode GE4.

[0114] The sacrificial pattern PP can be replaced with the gate electrode GE. Specifically, the exposed sacrificial pattern PP can be selectively removed. As a result of removing the sacrificial pattern PP, an empty space can be formed. A gate insulating layer GI and a gate electrode GE can be sequentially formed in the empty space formed by removing the sacrificial pattern PP.

[0115] The gate electrode GE and the gate spacer GS can be recessed, and then a gate cap pattern GP can be formed over the recessed gate electrode GE and the recessed gate spacer GS. The gate cap pattern GP can be formed of a material having an etching selectivity relative to the lower insulating layer LIL or include a material having an etching selectivity relative to the lower insulating layer LIL.

[0116] The active contact AC can be formed to penetrate the lower insulating layer LIL and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. More specifically, a first lithography process can be performed to form a first contact hole in the lower insulating layer LIL. The first contact hole can define the active contact AC. The first contact hole can be formed to expose the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate cap pattern GP can be used as a mask to form the first contact hole in a self-aligned manner.

[0117] A silicide pattern SC can be formed over the first source / drain pattern SD1 and the second source / drain pattern SD2 exposed via the first contact hole. The active contact AC can be formed by sequentially forming a barrier pattern BM and a conductive pattern FM in the first contact hole. The active contact AC can be formed to have a top surface coplanar with the top surface of the gate cap pattern GP and the top surface of the lower insulating layer LIL.

[0118] Referring to FIGS. 4 and 11A to 11D, a mask pattern MAP can be formed over the region of the active contact AC. The mask pattern MAP can define the region of the active contact AC that will be used as the connection portion CNP.

[0119] A recessed hole RSH can be formed by etching the region not covered by the mask pattern MAP. The mask pattern MAP can be used as an etching mask to form the recessed hole RSH. During the etching process for forming the recessed hole RSH, the upper portion of the gate cap pattern GP can be recessed. During the etching process, the remaining portion of the active contact AC not covered by the mask pattern MAP can be recessed to form a recessed portion RSP. The recessed portion RSP of the active contact AC can have a top surface lower than the top surface of the gate electrode GE. In some embodiments, during the etching process, the upper portion of the lower insulating layer LIL can also be recessed.

[0120] Referring to FIGS. 4 and 12A to 12D, the upper insulating layer UIL can be formed to fill the recessed hole RSH. The upper insulating layer UIL can be formed of the same or different insulating materials as the lower insulating layer LIL or include the same or different insulating materials as the lower insulating layer LIL. The upper insulating layer UIL can cover the top surface of the recessed portion RSP of the active contact AC. The upper insulating layer UIL and the lower insulating layer LIL can constitute the first interlayer insulating layer 110.

[0121] A sacrificial insulating layer SAL can be formed on the first interlayer insulating layer 110. The gate contact GC can be formed to penetrate the sacrificial insulating layer SAL and the gate cap pattern GP and can be electrically connected to the gate electrode GE.

[0122] More specifically, a second lithography process can be performed to form a second contact hole that penetrates the sacrificial insulating layer SAL. The second contact hole can define the gate contact GC. The second contact hole can be formed to expose the top surface of the gate electrode GE. The gate contact GC can be formed by sequentially forming a barrier pattern BM and a conductive pattern FM in the second contact hole. The gate contact GC can be formed to have a top surface coplanar with the top surface of the sacrificial insulating layer SAL.

[0123] The first gate contact GC1 in the gate contact GC can be formed to overlap a part of the second active contact AC2. Accordingly, the first gate contact GC1 can penetrate the upper part of the second active contact AC2 and can be coupled to the top surface of the third gate electrode GE3. The first gate contact GC1 can be in direct contact with the second active contact AC2, and the first gate contact GC1 and the second active contact AC2 can form a first shared contact SHC1.

[0124] Referring to FIGS. 4 and 5A to 5E, a planarization process can be performed on the gate contact GC and the sacrificial insulating layer SAL to expose the top surface of the active contact AC. Accordingly, the sacrificial insulating layer SAL can be completely removed. The gate contact GC can have a top surface coplanar with the top surface of the active contact AC.

[0125] The second interlayer insulating layer 120, the third interlayer insulating layer 130, and the fourth interlayer insulating layer 140 can be sequentially formed on the first interlayer insulating layer 110. A back-end-of-line (BEOL) process can be performed to form a first interconnect layer M1 in the second interlayer insulating layer 120, a second interconnect layer M2 in the third interlayer insulating layer 130, and a third interconnect layer M3 in the fourth interlayer insulating layer 140.

[0126] In a method of manufacturing a semiconductor memory device according to some embodiments of the inventive concept, an active contact AC may be formed, and then a gate contact GC may be formed to at least partially overlap the active contact AC. Accordingly, the gate contact GC may be formed to have a protruding portion PRP (e.g., see FIG. 6) buried in the active contact AC. Thus, the electrical resistance of a shared contact SHC (e.g., a first node N1) may be reduced and the operating characteristics and electrical characteristics (e.g., operating speed) of an SRAM cell may be improved.

[0127] FIG. 13 is an enlarged cross-sectional view corresponding to a portion “M” shown in FIG. 5B and presented to show a semiconductor memory device according to some embodiments of the inventive concept. In the following description, elements described above with reference to FIGS. 4 to 7 may be identified by the reference numerals used above, and for the sake of brevity of description, their descriptions will not be repeated.

[0128] Referring to FIG. 13, a top surface TS_P of a protruding portion PRP of a first gate contact GC1 may be lower than a top surface TS_B of a body portion BDP. A conductive pattern FM of the protruding portion PRP may be surrounded by a barrier pattern BM. A top surface of the conductive pattern FM of the protruding portion PRP may be covered by the barrier pattern BM. Since the top surface TS_P of the protruding portion PRP is formed at a level lower than the top surface TS_B of the body portion BDP, a contact area between the protruding portion PRP of the first gate contact GC1 and a third active contact AC3 may be further increased. Thus, in some embodiments, the electrical resistance of a first shared contact SHC1 may be reduced and the operating characteristics and electrical characteristics (e.g., operating speed) of an SRAM cell may be improved.

[0129] FIGS. 14A, 14B, and 14C are cross-sectional views of a semiconductor memory device taken along lines A-A′, B-B′, and D-D′ shown in FIG. 4, respectively, according to some embodiments of the inventive concept. In the following description, elements described above with reference to FIGS. 4 and 5A to 5E may be identified by the reference numerals used above, and for the sake of brevity of description, their descriptions will not be repeated.

[0130] Referring to FIGS. 4, 14A, 14B and 14C, the first active pattern AP1 and the second active pattern AP2 may be disposed on the substrate 100. The first active pattern AP1 may include a first channel pattern CH1 stacked in the vertical direction. The stacked first channel patterns CH1 may be spaced apart from each other in the third direction D3. The stacked first channel patterns CH1 may overlap each other in the vertical direction. The second active pattern AP2 may include a second channel pattern CH2 stacked in the vertical direction. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. The stacked second channel patterns CH2 may overlap each other in the vertical direction. The first channel pattern CH1 and the second channel pattern CH2 may be formed of at least one of silicon (Si), germanium (Ge) or silicon-germanium (SiGe) or include at least one of silicon (Si), germanium (Ge) or silicon-germanium (SiGe).

[0131] The first active pattern AP1 may further include a first source / drain pattern SD1. The stacked first channel patterns CH1 may be sandwiched between each pair of adjacent first source / drain patterns SD1. The stacked first channel patterns CH1 may connect a pair of adjacent first source / drain patterns SD1 to each other.

[0132] The second active pattern AP2 may further include a second source / drain pattern SD2. The stacked second channel patterns CH2 may be sandwiched between each pair of adjacent second source / drain patterns SD2. The stacked second channel patterns CH2 may connect a pair of adjacent second source / drain patterns SD2 to each other.

[0133] The gate electrode GE may cross the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. Some portions of each gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2.

[0134] The gate electrode GE may surround each of the first channel patterns CH1. More specifically, the gate electrode GE may be disposed on a first top surface TS1, a first side surface SW1, and a first bottom surface BS1 of each of the first channel patterns CH1 (see, e.g., FIG. 14C). The gate electrode GE may surround each of the second channel patterns CH2. For example, the gate electrode GE may be disposed on a second top surface TS2, a second side surface SW2, and a second bottom surface BS2 of each of the second channel patterns CH2 (see, e.g., FIG. 14C). The transistor according to some embodiments may be a three-dimensional field-effect transistor in which the gate electrode GE three-dimensionally surrounds the channel pattern CH1 or CH2 (e.g., a multi-bridge channel field-effect transistor (MBCFET) or a gate-all-around field-effect transistor (GAAFET)).

[0135] The gate insulating layer GI may be located between each of the first channel pattern CH1 and the second channel pattern CH2 and the gate electrode GE. The gate insulating layer GI may surround each of the first channel pattern CH1 and the second channel pattern CH2.

[0136] An insulating pattern (not shown) may be located on the second active pattern AP2 and sandwiched between the gate insulating layer GI and the second source / drain pattern SD2. The gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the gate insulating layer GI and the insulating pattern. In contrast, the insulating pattern may not be located on the first active pattern AP1 and may be omitted from the first active pattern AP1.

[0137] In an SRAM cell according to some embodiments of the inventive concept, each of the first node and the second node may include a shared contact formed of an active contact and a gate contact. The gate contact may include a portion protruding toward the active contact, and such a structure of the gate contact may reduce the electrical resistance of the shared contact and prevent misalignment problems between the gate contact and the active contact. Accordingly, according to some embodiments of the inventive concept, the reliability and electrical characteristics of the semiconductor memory device may be improved.

[0138] Although the exemplary embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art should understand that changes in form and detail may be made thereto without departing from the scope of the appended claims.

[0139] 100: Substrate 110: First interlayer insulating layer 120: Second interlayer insulating layer 130: Third interlayer insulating layer 140: Fourth interlayer insulating layer A-A', B-B', C-C', D-D', E-E': Lines AC: Active contact AC1: First active contact AC2: Second active contact AC3: Third active contact AC4: Fourth active contact AC5: Fifth active contact AC6: Sixth active contact AC7: Seventh active contact AC8: Eighth active contact AP1: First active pattern / Active pattern AP2: Second active pattern / Active pattern BDP: Body part BL1: First bit line BL2: Second bit line BM: Barrier pattern BS1: First bottom surface BS2: Second bottom surface CE: Memory cell CE1: First bit cell CE2: Second bit cell CE3: Third bit cell CE4: Fourth bit cell CH1: First channel pattern / Channel pattern CH2: Second channel pattern / Channel pattern CNP: Connection part D1: First direction D2: Second direction D3: Third direction FM: Conductive pattern GC: Gate contact GC1: First gate contact GC2: Second gate contact GE: Gate electrode GE1: First gate electrode GE2: Second gate electrode GE3: Third gate electrode GE4: Fourth gate electrode GI: Gate insulating layer GP: Gate cap pattern GS: Gate spacer LIL: Lower insulating layer LLP1: First lower landing pad LLP2: Second lower landing pad M: Portion M1: First interconnection layer M2: Second interconnection layer M3: Third interconnection layer MA: Hard mask pattern MAP: Mask pattern N1: First node N2: Second node OP1: First opening P1: First portion P2: Second portion PP: Sacrificial pattern PRP: Protruding portion RS1: First recessed area RS2: Second recessed area RSH: Recess hole RSP: Recessed portion SAL: Sacrificial insulating layer SC: Silicide pattern SD1: First source / drain pattern / Source / drain pattern SD2: Second source / drain pattern / Source / drain pattern SHC: Shared contact SHC1: First shared contact SHC2: Second shared contact SP: Insulating pattern ST: Device isolation layer SW1: First side surface SW2: Second side surface TA1: First channel gate transistor TA2: Second channel gate transistor TD1: First pull-down transistor TD2: Second pull-down transistor TR: Trench TS_B, TS_P: Top surface TS1: First top surface TS2: Second top surface TU1: First pull-up transistor TU2: Second pull-up transistor UIL: Upper insulating layer ULP: Upper overlap pad VDD: Power line VI1: First via hole VI2: Second via hole VI3: Third via hole VSS: Ground line WL: Word line

Claims

1. A semiconductor memory device, comprising: an active pattern located on a substrate, the active pattern including source / drain patterns in an upper portion of the active pattern; a gate electrode located on the active pattern and extending in a first direction, the gate electrode being adjacent to the source / drain patterns in a second direction crossing the first direction; and a shared contact coupled to the source / drain patterns and the gate electrode to electrically connect the source / drain patterns and the gate electrode, wherein the shared contact includes an active contact electrically connected to the source / drain patterns and a gate contact electrically connected to the gate electrode, wherein the gate contact includes a body portion coupled to the gate electrode and a protruding portion protruding from the body portion in the second direction, and wherein the protruding portion extends into and is buried in the active contact.

2. The semiconductor memory device according to claim 1, wherein the protruding portion overlaps the active contact in a third direction perpendicular to the first direction and the second direction, and wherein the body portion is offset from the active contact in a horizontal direction.

3. The semiconductor memory device according to claim 1, wherein the active contact and the gate contact each include a barrier pattern and a conductive pattern, wherein the barrier pattern covers a surface of the conductive pattern, and wherein the barrier pattern of the protruding portion is sandwiched between the conductive pattern of the protruding portion and the conductive pattern of the active contact.

4. The semiconductor memory device according to claim 1, wherein the body portion has a top surface coplanar with a top surface of the active contact.

5. The semiconductor memory device according to claim 4, wherein a top surface of the protruding portion is coplanar with the top surface of the active contact.

6. The semiconductor memory device according to claim 4, wherein a top surface of the protruding portion is lower than the top surface of the active contact.

7. The semiconductor memory device according to claim 1, wherein the protruding portion is positioned farther from the substrate than a bottom surface of the body portion is from the substrate.

8. The semiconductor memory device according to claim 1, wherein the active contact includes a connecting portion and a groove portion, wherein the connecting portion contacts the protruding portion, and wherein a top surface of the groove portion is closer to the substrate than a top surface of the connecting portion is with respect to the substrate.

9. The semiconductor memory device according to claim 8, further comprising an upper insulating layer located on the groove portion, wherein the top surface of the connecting portion is coplanar with a top surface of the upper insulating layer.

10. The semiconductor memory device according to claim 1, wherein the active pattern includes an active fin protruding above a device isolation layer, or wherein the active pattern includes a plurality of channel patterns stacked in a vertical direction.

11. A semiconductor memory device includes dynamic random access memory cells located on a substrate, wherein the dynamic random access memory cells comprise: a first pull-up / pull-down transistor and a second pull-up / pull-down transistor; and a first node connecting a first common source / drain of the first pull-up / pull-down transistor to a first common gate of the second pull-up / pull-down transistor, wherein the first node includes a first shared contact that is coupled to the first common source / drain and the first common gate to electrically connect the common source / drain and the first common gate, wherein the first shared contact includes an active contact electrically connected to the first common source / drain, and wherein the first shared contact includes a gate contact electrically connected to the first common gate, wherein the gate contact includes a body portion coupled to the first common gate and a protruding portion protruding from the body portion toward the active contact, wherein a top surface of the body portion is coplanar with a top surface of the active contact, wherein the protruding portion overlaps the active contact in a vertical direction, and wherein the body portion is offset from the active contact in a horizontal direction.

12. The semiconductor memory device of claim 11, wherein a top surface of the protruding portion is coplanar with the top surface of the active contact.

13. The semiconductor memory device of claim 11, wherein the top surface of the protruding portion is closer to the substrate than the top surface of the active contact with respect to the substrate.

14. The semiconductor memory device of claim 11, wherein the active contact includes a connecting portion and a groove portion, wherein the connecting portion contacts the protruding portion, and wherein a top surface of the groove portion is closer to the substrate than a top surface of the connecting portion with respect to the substrate.

15. The semiconductor memory device of claim 11, wherein the dynamic random access memory cell further includes a second node connecting a second common source / drain of the second pull-up / pull-down transistor to a second common gate of the first pull-up / pull-down transistor, and wherein the second node includes a second shared contact that is coupled to the second common source / drain and the second common gate to electrically connect the second common source / drain and the second common gate.

16. A semiconductor memory device comprises: A substrate, including a cell region; a first active pattern and a second active pattern located on the cell region, the first active pattern being spaced apart from the second active pattern in a first direction, the first active pattern including a first source / drain pattern disposed in an upper portion of the first active pattern, and the second active pattern including a second source / drain pattern disposed in an upper portion of the second active pattern; a device isolation layer disposed on the substrate to cover side surfaces of lower portions of each of the first active pattern and the second active pattern, and upper portions of each of the first active pattern and the second active pattern extending above the device isolation layer; A gate electrode disposed on the first active pattern and extending in the first direction, the gate electrode and the first source / drain pattern being adjacent to each other in a second direction; A gate insulating layer located between the gate electrode and the first active pattern; A gate spacer located on at least one side surface of the gate electrode; A gate cap pattern located on the gate electrode; an interlayer insulating layer located on the gate cap pattern; an active contact extending through the interlayer insulating layer, the active contact being coupled to the first source / drain pattern and the second source / drain pattern, and the active contact extending in the first direction to connect the first source / drain pattern and the second source / drain pattern to each other; A silicide pattern located between each of the first source / drain pattern and the second source / drain pattern and the active contact; a gate contact extending through the gate cap pattern and coupled to the gate electrode; and a first interconnect layer, a second interconnect layer, and a third interconnect layer stacked on the interlayer insulating layer in sequence, wherein the gate contact includes a body portion coupled to the gate electrode and a protruding portion protruding from the body portion in the second direction, and wherein the protruding portion extends into and is buried in the active contact.

17. The semiconductor memory device according to claim 16, wherein the first interconnect layer includes bit lines, and wherein the third interconnect layer includes word lines.

18. The semiconductor memory device according to claim 16, wherein the first source / drain pattern has p-type conductivity, and wherein the second source / drain pattern has n-type conductivity.

19. The semiconductor memory device according to claim 16, wherein the protruding portion overlaps the active contact in a vertical direction, and wherein the body portion is offset from the active contact in a horizontal direction.

20. The semiconductor memory device according to claim 16, wherein the gate contact and the active contact are connected to each other as a shared contact, and wherein the shared contact electrically connects the first source / drain pattern and the second source / drain pattern to the gate electrode.