Inverter circuit, semicondctor circuit, and methods of forming the same

Abstract

An inverter circuit includes: an electrically insulating structure having a planar geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a corresponding plane perpendicular to the thickness direction; a p-type semiconductor layer formed on the first surface; an n-type semiconductor layer formed on the second surface; a gate dielectric layer formed to contact the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed to contact the gate dielectric layer; a first source electrode and a first drain electrode formed to contact the p-type semiconductor layer; and a second source electrode and a second drain electrode formed to contact the n-type semiconductor layer. The inverter circuit can be connected to a voltage source, a ground voltage terminal, an input signal terminal, and an output signal terminal to operate as an inverter.

Description

Back-end-of-line CMOS Inverter with Vertical Channel and Method of Forming the Same The semiconductor industry has grown due to the continuous increase in the integration density of various electronic components such as transistors, diodes, resistors, inductors, capacitors, etc. To a large extent, these increases in integration density have come from the repeated reduction of the minimum feature size, which enables more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become smaller and smaller, and there is a continuing need to develop new materials, processes, and designs for semiconductor devices and interconnects to enable further progress. Transistors made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because they can be processed at low temperatures and thus do not damage previously fabricated devices. For example, the fabrication conditions and techniques do not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Circuits based on oxide semiconductor-based transistor devices can further include other components that can be fabricated in the BEOL process, such as capacitors, inductors, resistors, and integrated passive devices. The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and similar terms may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference number is assumed to have the same material composition and a thickness within the same thickness range. Various embodiments of the present disclosure provide semiconductor circuits and methods that may have advantages in terms of manufacturing flexibility, size reduction, and reduction of short channel effects. In this regard, an exemplary semiconductor circuit (e.g., a complementary metal-oxide-semiconductor (CMOS) inverter) is provided, which may be formed in a BEOL process and may be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed semiconductor circuits may include materials that can be processed at low temperatures, and thus may not damage previously fabricated devices (e.g., FEOL devices and MEOL devices). In addition, various embodiments of the semiconductor circuits may include a p-channel metal oxide semiconductor field effect transistor (pFET) having a vertical channel layer and an n-channel metal oxide semiconductor field effect transistor (nFET) also having a vertical channel layer. Each of the vertical p-channel and the vertical n-channel may be formed on opposite sides of a vertically oriented electrical insulation structure such that the vertical p-channel and the vertical n-channel are closely spaced relative to each other. Relative to alternative structures that do not include vertical channels, the use of such vertical channels may provide a semiconductor circuit with reduced size and may allow for a longer channel length without increasing the device size, which may mitigate the short channel effect. An example inverter circuit includes an electrical insulation structure having a slab geometry including a first surface and a second surface parallel to each other. The first surface and the second surface may each be oriented in a respective plane perpendicular to the thickness direction. The example inverter circuit may include: a p-type semiconductor layer formed on the first surface; an n-type semiconductor layer formed on the second surface; a gate dielectric layer formed in contact with the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed in contact with the gate dielectric layer; a first source electrode and a first drain electrode formed in contact with the p-type semiconductor layer; and a second source electrode and a second drain electrode formed in contact with the n-type semiconductor layer. The inverter circuit may be connected to a voltage supply, a ground voltage terminal, an input signal terminal, and an output terminal to operate as an inverter. In another example, a semiconductor circuit may include: a first layer formed of a p-type metal oxide semiconductor within the interlayer dielectric layer along a first vertical plane with respect to a horizontal interface of the interlayer dielectric layer; a second layer formed of an n-type metal oxide semiconductor within the interlayer dielectric layer along a second vertical plane with respect to the horizontal interface of the interlayer dielectric layer such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric layer. The semiconductor circuit may further include: a gate electrode having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; a gate dielectric layer separating the first vertical portion of the gate electrode from the first layer and also separating the second vertical portion of the gate electrode from the second layer; a first source electrode and a first drain electrode formed in contact with the p-type metal oxide semiconductor; and a second source electrode and a second drain electrode formed in contact with the n-type metal oxide semiconductor. An example method of forming a semiconductor circuit may include: forming an electrical insulation structure having a slab geometry including a first surface and a second surface parallel to each other and each oriented in a respective plane perpendicular to the thickness direction; forming a p-type semiconductor layer on the first surface; forming an n-type semiconductor layer on the second surface; forming a gate dielectric layer in contact with the p-type semiconductor layer and the n-type semiconductor layer; forming a gate electrode in contact with the gate dielectric layer; forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer; and forming a second source electrode and a second drain electrode in contact with the n-type semiconductor layer. FIG. 1 illustrates a semiconductor structure 100 according to various embodiments. The semiconductor structure 100 includes a substrate 102, which may be a semiconductor substrate (e.g., a commercially available silicon substrate). The substrate 102 may include a semiconductor material layer 104 at least in its upper portion. The semiconductor material layer 104 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 104 includes a single-crystalline semiconductor material (e.g., single-crystalline silicon). In one embodiment, the substrate 102 may include a single-crystalline silicon substrate comprising single-crystalline silicon material. A shallow trench isolation structure 106 including a dielectric material such as silicon oxide, for example, may be formed in the upper portion of the semiconductor material layer 104. Suitable doped semiconductor wells such as a p-type well and an n-type well, for example, may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 106. Field effect transistors 108 may be formed over the top surface of the semiconductor material layer 104. For example, each of the field effect transistors 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 including a surface portion of the substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single-crystalline semiconductor material. Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate capping dielectric 122, and a dielectric gate spacer 124. A source-side metal-semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal-semiconductor alloy region 128 may be formed on each drain electrode 112. The devices formed on the top surface of the semiconductor material layer 104 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), and are collectively referred to as a CMOS circuit 134. The semiconductor structure 100 of FIG. 1 may include a memory array region 130 in which an array of memory cells may be subsequently formed. A first exemplary structure may further include a peripheral region 132 in which metal wiring for an array of memory devices is provided. Generally, the field effect transistors 108 in the CMOS circuit 134 may be electrically connected to the electrodes of the corresponding memory cells by a set of corresponding metal interconnect structures. The devices in the peripheral region 132 (e.g., the field effect transistors 108) may provide functions for operating on the subsequently to-be-formed array of memory cells. Specifically, the devices in the peripheral region may be configured to control the programming operation, the erase operation, and the sense (read) operation of the array of memory cells. For example, the devices in the peripheral region 132 may include sense circuitry and / or programming circuitry. One or more of the field effect transistors 108 in the CMOS circuit 134 may include a semiconductor channel 114, which includes a portion of the semiconductor material layer 104 in the substrate 102. In embodiments where the semiconductor material layer 104 includes single-crystalline semiconductor material (e.g., single-crystalline silicon), the semiconductor channel 114 of each of the field effect transistors 108 in the CMOS circuit 134 may include a single-crystalline semiconductor channel (e.g., a single-crystalline silicon channel). In one embodiment, the multiple field effect transistors 108 in the CMOS circuit 134 may include corresponding nodes, which are then electrically connected to the nodes of the corresponding memory cells to be formed subsequently. For example, the multiple field effect transistors 108 in the CMOS circuit 134 may include corresponding source electrodes 110 or corresponding drain electrodes 112, which are then electrically connected to the nodes of the corresponding memory cells to be formed subsequently. In one embodiment, the CMOS circuit 134 may include a programmable control circuit configured to control the gate voltage of a set of field effect transistors 108 (the gate voltage can be used to program corresponding memory cells (e.g., ferroelectric memory cells)) and control the gate voltage of transistors (e.g., thin film transistors) to be formed subsequently. In this embodiment, the programmable control circuit may be configured to provide a first programming pulse that programs the corresponding ferroelectric dielectric material layer in the selected ferroelectric memory cell into a first polarization state, in which the electric polarization in the ferroelectric dielectric material layer points to the first electrode of the selected ferroelectric memory cell, and the programmable control circuit may be configured to provide a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state, in which the electric polarization in the ferroelectric dielectric material layer points to the second electrode of the selected ferroelectric memory cell. In one embodiment, the substrate 102 may include a single-crystalline silicon substrate, and the field effect transistor 108 may include a corresponding portion of the single-crystalline silicon substrate as a semiconductive channel. The "semiconducting" element used herein refers to an element with a conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm. The "semiconductor material" used herein refers to a material with a conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5Materials within the Siemens / cm range and capable of generating a conductivity within the range of 1.0 Siemens / cm to 1.0×10 5 Doped materials within the Siemens / cm range. According to an embodiment, the field effect transistor 108 can then be electrically connected to the drain electrode and the gate electrode of the access transistor, and the access transistor includes a semiconducting metal oxide plate to be formed above the field effect transistor 108. In one embodiment, a subset of the field effect transistors 108 can then be electrically connected to at least one of the drain electrode and the gate electrode. For example, the field effect transistor 108 can include a first word line driver and a second word line driver, the first word line driver being configured to apply a first gate voltage to a first word line through a first subset of the subsequently to-be-formed lower-level metal interconnect structures, and the second word line driver being configured to apply a second gate voltage to a second word line through a second subset of the lower-level metal interconnect structures. In addition, the field effect transistor 108 can include a bit line driver and a sense amplifier, the bit line driver being configured to apply a bit line bias voltage to the subsequently to-be-formed bit line, and the sense amplifier being configured to detect a current flowing through the bit line during a read operation. Various metal interconnect structures formed within a dielectric material layer can then be formed on the substrate 102 and semiconductor devices thereon (such as the field effect transistor 108). In an exemplary example, the dielectric material layer can include, for example, a first dielectric material layer 136 (sometimes referred to as a contact-level dielectric material layer) that can be a layer surrounding contact structures connected to the source and drain, a first interconnect-level dielectric material layer 138, and a second interconnect-level dielectric material layer 140. The metal interconnect structures can include device contact via structures 142 formed in the first dielectric material layer 136 and contacting corresponding components of the CMOS circuit 134, first metal line structures 144 formed in the first interconnect-level dielectric material layer 138, first metal via structures 146 formed in the lower portion of the second interconnect-level dielectric material layer 140, and second metal line structures 148 formed in the upper portion of the second interconnect-level dielectric material layer 140. Each of the dielectric material layers (136, 138, 140) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous carbon fluoride, its porous variant, or a combination thereof. Each of the metal interconnect structures (142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal fill material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, its alloys, and / or combinations thereof. Other suitable metal liners and metal fill materials within the scope covered by this disclosure may also be used. In one embodiment, the first metal via structure 146 and the second metal line structure 148 may be formed as an integrated line and via structure by a dual damascene process. The dielectric material layers (136, 138, 140) are referred to herein as lower-level dielectric material layers. The metal interconnect structures (142, 144, 146, 148) formed in the lower-level dielectric material layers are referred to herein as lower-level metal interconnect structures. Although this disclosure is described using an embodiment in which an array of memory cells may be formed above the second line and via level dielectric material layer 140, embodiments in which an array of memory cells may be formed at different metal interconnect levels are explicitly covered herein. Subsequently, an array of thin film transistors and an array of ferroelectric memory cells (or other types of memory cells) may be deposited over the dielectric material layers (136, 138, 140) in which the metal interconnect structures (142, 144, 146, 148) are formed. The collection of all dielectric material layers formed prior to forming the array of thin film transistors or the array of ferroelectric memory cells is collectively referred to as the lower-level dielectric material layers (136, 138, 140). The collection of all metal interconnect structures formed within the lower-level dielectric material layers (136, 138, 140) is referred to herein as the first metal interconnect structures (142, 144, 146, 148). Generally, the first metal interconnect structures (142, 144, 146, 148) formed within at least one of the lower-level dielectric material layers (136, 138, 140) may be formed over a semiconductor material layer 104 located in a substrate 102. According to an embodiment, thin film transistors may subsequently be formed in the metal interconnect level, and the thin film transistors are overlaid on the metal interconnect level including lower level dielectric material layers (136, 138, 140) and a first metal interconnect structure (142, 144, 146, 148). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower level dielectric material layers (136, 138, 140). The planar dielectric material layer is referred to herein as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material such as undoped silicate glass, doped silicate glass, organic silicate glass, or porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may range from 20 nanometers (i.e., 200 angstroms) to 300 nanometers (i.e., 3000 angstroms), but smaller and larger thicknesses may also be used. Generally, an interconnect level dielectric layer (such as the lower level dielectric material layers (136, 138, 140)) containing a metal interconnect structure (such as the first metal interconnect structure (142, 144, 146, 148)) may be formed over a semiconductor device. The insulating matrix layer 150 may be formed over the interconnect level dielectric layer. Other passive devices may be formed in the BEOL process. For example, various capacitors, inductors, resistors, and integrated passive devices may be used together with other BEOL devices. FIG. 2A is a three-dimensional perspective view of a semiconductor circuit 200 that may be formed in a BEOL process according to various embodiments, and FIG. 2B is another three-dimensional perspective view of the semiconductor circuit 200 shown in FIG. 2A. FIG. 2C is a schematic equivalent circuit 200c illustrating the semiconductor circuit 200 shown in FIGS. 2A and 2B according to various embodiments. As shown in FIGS. 2A and 2B, the semiconductor circuit 200 may include an electrically insulating structure 202 having a flat plate geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented in a respective plane perpendicular to the thickness direction (e.g., the thickness direction is along the x direction in FIGS. 2A and 2B). The semiconductor circuit 200 may further include: a p-type semiconductor layer 206a formed on the first surface 204a; an n-type semiconductor layer 206b formed on the second surface 204b; a gate dielectric layer 118 formed in contact with the p-type semiconductor layer 206a and the n-type semiconductor layer 206b; and a gate electrode 116 formed in contact with the gate dielectric layer 118. The semiconductor circuit 200 may further include: a first source electrode 110a and a first drain electrode 112a (see, for example, FIG. 2B), formed to be in contact with the p-type semiconductor layer 206a; and a second source electrode 110b and a second drain electrode 112b, formed to be in contact with the n-type semiconductor layer 206b. As shown in FIG. 2B, the first source electrode 110a may be electrically connected to a voltage source 208 (which may be maintained at a source voltage VDD, for example), and the second source electrode 110b may be connected to a ground voltage terminal 210 (which may be maintained at a ground (GND) voltage, for example). The gate electrode 116 may be connected to an input signal terminal 212, and the first drain electrode 112a and the second drain electrode 112b may be electrically connected to an output signal terminal 214. In this way, the semiconductor circuit 200 may be configured as an inverter circuit, as shown in FIG. 2C. FIG. 2C is a schematic equivalent circuit 200c illustrating the semiconductor circuit 200 shown in FIGS. 2A and 2B according to various embodiments. In this regard, the p-type semiconductor layer 206a may be configured as a vertical channel layer of a p-channel metal oxide semiconductor field effect transistor (MOSFET) (i.e., pFET 216), and the n-type semiconductor layer 206b may be configured as a vertical channel layer of an n-channel MOSFET transistor (i.e., nFET 218). Accordingly, the pFET 216 includes the p-type semiconductor layer 206a, the first source electrode 110a, the first drain electrode 112a, the gate dielectric layer 118, and the gate electrode 116. Similarly, the nFET 218 includes the n-type semiconductor layer 206b, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116. Applying a low voltage to the input signal terminal 212 turns on the pFET 216 and turns off the nFET 218. Since the source of the pFET 216 (i.e., the first source electrode 110a) is connected to the voltage source 208 having a high voltage, the output voltage V out (i.e., the voltage at the first drain electrode 112a) will have a high voltage. Similarly, applying a high voltage to the input signal terminal 212 turns on the nFET 218 and turns off the pFET 216. Since the source of the nFET 218 (i.e., the second source electrode 110b) is connected to the ground voltage terminal, the output voltage V out (i.e., the voltage at the second drain electrode 112b) will have a low voltage. In this way, a high input signal is converted into a low output signal, and a low input signal is converted into a high input signal. In this way, the semiconductor circuit 200 is configured as an inverter circuit. The semiconductor circuit 200 shown in FIGS. 2A and 2B can be formed on an interlayer dielectric layer having a horizontal interface. For example, the semiconductor circuit 200 can be formed on the insulating substrate layer 150 (see FIG. 1 for example) or on one or more additional interconnection layers on the insulating substrate layer 150. As shown in FIGS. 2A and 2B, the electrical insulating structure 202 can have a vertical orientation such that each of the first surface 204a and the second surface 204b is perpendicular to the horizontal interface of the interlayer dielectric layer (see FIG. 1 for example, where the insulating substrate layer 150 has a horizontal surface). The interlayer dielectric layer on which the semiconductor circuit 200 is formed (e.g., the lower-level dielectric material layers (136, 138, 140) in FIG. 1) can include one or more electrical interconnection structures (e.g., the first metal interconnection structures (142, 144, 146, 148) in FIG. 1), and the one or more electrical interconnection structures can be electrically connected to the semiconductor circuit 200 shown in FIGS. 2A and 2B. In this regard, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to the one or more electrical interconnection structures (142, 144, 146, 148) formed in one or more dielectric material layers (136, 138, 140) below the semiconductor circuit 200. In other embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to one or more electrical interconnection structures to be formed above the semiconductor circuit 200 later. In one or more embodiments, one or both of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b can include metal oxide semiconductors. For example, the p-type semiconductor layer 206a can include one or more of NiO, SnO, and Cu 2 O, and the n-type semiconductor layer 206b can include amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 、ZnO、GaO、Ga 2 O 3 、InO、In 2 O 3 、 InZnO, ZnO, TiO x and one or more of their alloys. In some embodiments, the n-type semiconductor layer 206b may have a composition given by In x Ga y Zn z MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn. In other embodiments, the n-type semiconductor layer 206b may include an alloy of oxygen, group III elements, and group V elements. In other embodiments, one or more of the n-type semiconductor layer and the p-type semiconductor layer may be formed of a metal oxide semiconductor having a multilayer structure. In some embodiments, as described above, the electrical insulation structure 202 may include AlO x 、 SiO 2 、 SiN x or one or more of other interlayer dielectric materials. The gate dielectric layer 118 may be a high-k dielectric material and may include one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, hafnium dioxide-alumina, etc. As will be described in more detail below, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b may include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, Al, etc. Other suitable conductor materials may be within the scope covered by this disclosure. FIG. 2D is another three-dimensional perspective view showing various dimensions of the components of the semiconductor circuit 200 shown in FIG. 2A according to various embodiments. As described above, the p-type semiconductor layer 206a may be configured as the p-channel layer of the pFET 216 device, and the n-type semiconductor layer 206b may be configured as the n-channel layer of the nFET 218 device (see, for example, FIG. 2C). In this way, when the corresponding devices (216, 218) are enabled, current may flow as shown by the dashed arrows (220a, 220b) in FIG. 2D. In this regard, when the pFET 216 is enabled (e.g., by applying a low or zero bias voltage to the gate electrode 116), positive charge carriers (i.e., "holes") may flow from the first source electrode 110a to the first drain electrode 112a (see, for example, FIG. 2B), thereby generating a first current 220a. Similarly, when the nFET 218 is enabled (e.g., by applying a high bias voltage to the gate electrode 116), negative charge carriers (i.e., electrons) may flow from the second drain electrode 112b to the second source electrode 110b, but since the current carried by the negative charge is opposite to its movement, the charge movement in the nFET 218 generates a second current 220b in the same direction as the first current 220a flowing in the pFET 216. Each of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may have a corresponding channel length 222 and a corresponding channel width 224. In various embodiments, the channel length 222 may have a value greater than 15 nanometers. An increase in the channel length 222 may mitigate short-channel effects. However, increasing the channel length 222 may cause the drive current to decrease and the size of the semiconductor circuit 200 to be larger. Therefore, the channel length 222 may be optimized to determine a value large enough to avoid short-channel effects while keeping the size of the semiconductor circuit 200 as small as possible. According to various embodiments, the channel width 224 may have a value greater than 5 nanometers and less than 500 nanometers. Each of the first source electrode 110a, the first drain electrode 112a (see, e.g., FIG. 2B), the second source electrode 110b, and the second drain electrode 112b may have a source / drain width approximately equal to the channel width 224. Each of the source / drain electrodes (110a, 110b, 112a, 112b) may also have a source / drain length 226 and a source / drain thickness 228, each of which may have a value greater than 5 nm. The electrical insulation structure 202 may have a thickness 230 greater than 5 nm and less than 500 nm. The gate electrode 116 may have a gate length 232 and a gate width 234 that may correspond to the channel length 222 and the channel width 224, respectively. In this regard, the gate length 232 may be greater than 10 nm, and the gate width 234 may be greater than 5 nm and less than 500 nm. The top portion of the gate electrode 116 may have a gate thickness 236 that may have a value greater than 10 nm and less than 150 nm. The gate dielectric layer 118 may have a gate dielectric thickness 238 greater than 2 nm and less than 20 nm. The p-type semiconductor layer 206a may have a p-type thickness 240a, and the n-type semiconductor layer 206b may have an n-type thickness 240b, and the p-type thickness 240a and the n-type thickness 240b may each be greater than 2 nm and less than 50 nm. FIG. 3A is a vertical cross-sectional view of an intermediate structure 300 that can be used to form the semiconductor circuit 200 according to various embodiments, and FIG. 3B is a top view of the intermediate structure 300 shown in FIG. 3A. The vertical plane defining the view in FIG. 3A is represented by the cross-section A–A’ in FIG. 3B. As shown in FIG. 3A, the intermediate structure 300 may include a substrate 302, an interlayer dielectric layer 202L, an etch stop layer 306L, and a photoresist 308L. The substrate 302 may be formed in a BEOL process and may thus be a dielectric layer (e.g., the interlayer dielectric layer or the insulating matrix layer 150 of FIG. 1). For example, the substrate 302 may include undoped silicate glass, doped silicate glass (e.g., deposited by decomposing tetraethylorthosilicate (TEOS)), organosilicate glass, silicon oxynitride, or silicon carbide nitride. Other suitable dielectric materials are also within the scope of the present disclosure. The dielectric material of the substrate 302 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). The thickness of the substrate 302 may each be in the range of approximately 15 nm to approximately 60 nm (e.g., approximately 20 nm to approximately 40 nm), but smaller and larger thicknesses may also be used. The interlayer dielectric layer 202L may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicate, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide - alumina, or various other insulating structures (such as a multilayer stack structure including alternating insulating layers). The interlayer dielectric layer 202L may be deposited by a conformal deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc.) or by a self - planarizing deposition process (such as spin coating). In this example, the interlayer dielectric layer 202L may be formed as a flat blanket (i.e., unpatterned) layer having a flat top surface and a flat bottom surface. The excess portion of the interlayer dielectric layer 202L may be removed from above the top surface of the intermediate structure 300 by a planarization process, such as by chemical mechanical planarization (CMP). The thickness of the interlayer dielectric layer 202L may range from approximately 5 nanometers to approximately 50 nanometers (such as approximately 20 nanometers to approximately 40 nanometers), but other embodiments may include smaller and larger thicknesses. The etch stop layer 306L may include an etch stop material, such as silicon nitride, silicon carbide, silicon nitride carbide, or a dielectric metal oxide (such as aluminum oxide, titanium oxide, tantalum oxide, etc.). The etch stop layer 306L may be deposited by a conformal deposition process or a non - conformal deposition process. In one embodiment, the etch stop layer 306L may be deposited by CVD, ALD, or PVD. The thickness of the etch stop layer 306L may range from approximately 2 nanometers to approximately 20 nanometers (such as approximately 3 nanometers to approximately 12 nanometers), but smaller and larger thicknesses may also be used. FIG. 4A is a vertical cross-sectional view of yet another intermediate structure 400 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 4B is a top view of the intermediate structure 400 shown in FIG. 4A. The vertical plane defining the view in FIG. 4A is represented by the cross-section A-A' in FIG. 4B. The photoresist 308L in FIGS. 3A and 3B can be formed as a uniform layer over the etch stop layer 306L, and then the photoresist 308L can be patterned using lithography to form the patterned photoresist 308 as shown in FIGS. 4A and 4B. According to some embodiments, the patterned photoresist 308 can be formed as an array of periodic rectangular shapes over the etch stop layer 306L. For example, the views in FIGS. 4A and 4B can correspond to one repeating unit of an array of periodic rectangular shapes. Each portion of the patterned photoresist 308 can have a width along a first horizontal direction (i.e., the x-direction in FIG. 4B) and a length along a second horizontal direction (i.e., the y-direction in FIG. 4B). The patterned photoresist 308 can then be used as a mask to pattern the etch stop layer 306L and the interlayer dielectric layer 202L, as described in more detail below with reference to FIGS. 5A and 5B. FIG. 5A is a vertical cross-sectional view of yet another intermediate structure 500 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 5B is a top view of the intermediate structure 500 shown in FIG. 5A. The vertical plane defining the view in FIG. 5A is represented by the cross-section A-A' in FIG. 5B. The intermediate structure 500 shown in FIGS. 5A and 5B can be formed from the intermediate structure 400 shown in FIGS. 4A and 4B by performing an anisotropic etching process to remove portions of the interlayer dielectric layer 202L and the etch stop layer 306L that are not masked by the patterned photoresist 308. The patterned photoresist 308 can then be removed by ashing or by dissolving it using a solvent. The electrical insulation structure 202 described above with reference to FIGS. 2A to 2D can include the remaining portion of the interlayer dielectric layer 202L after the anisotropic etching process. As shown, each electrical insulation structure 202 formed in this manner can have a planar geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented in a respective plane perpendicular to the thickness direction (e.g., the x-direction in FIG. 5A). The intermediate structure 500 also includes the remaining portion of the etch stop layer 306L, which forms a patterned etch stop layer 306 formed on top of the electrical insulation structure 202. FIG. 6A is a vertical cross-sectional view of yet another intermediate structure 600 that can be used to form semiconductor circuit 200 according to various embodiments, and FIG. 6B is a top view of intermediate structure 600 shown in FIG. 6A. The vertical plane defining the view in FIG. 6A is represented by cross-section A-A' in FIG. 6B. Intermediate structure 600 can be formed by depositing a first oxide semiconductor layer 206La over intermediate structure 500 shown in FIGS. 5A and 5B. The first oxide semiconductor layer 206La can be a p-type semiconductive material including, but not limited to, NiO, SnO, and Cu 2 O, and the p-type semiconductive material can be formed by any suitable method such as ALD, CVD, PECVD, PVD, etc. The thickness of the first oxide semiconductor layer 206La can range from approximately 2 nanometers to approximately 50 nanometers (e.g., approximately 5 nanometers to approximately 15 nanometers), but other embodiments can include smaller and larger thicknesses. After depositing the first oxide semiconductor layer 206La, intermediate structure 600 can be selectively annealed. The selective annealing process can be carried out at a temperature in the range of 200 degrees Celsius to 400 degrees Celsius using rapid thermal annealing or a furnace annealing process. The annealing can be carried out in an environment of nitrogen, oxygen, or a mixture thereof. FIG. 7A is a vertical cross-sectional view of yet another intermediate structure 700 that can be used to form semiconductor circuit 200 according to various embodiments, and FIG. 7B is a top view of intermediate structure 700 shown in FIG. 7A. The vertical plane defining the view in FIG. 7A is represented by cross-section A-A' in FIG. 7B. Intermediate structure 700 can be formed from intermediate structure 600 shown in FIGS. 6A and 6B by depositing an additional interlayer dielectric layer 202L over intermediate structure 600, followed by forming an additional patterned photoresist 308. In this regard, the additional interlayer dielectric layer 202L can be deposited by a conformal deposition process such as CVD, ALD, PVD, PECVD, etc. or by a self-planarizing deposition process such as spin coating. The excess portion of the interlayer dielectric layer 202L can be removed from above the top surface of the first oxide semiconductor layer 206La by a planarization process such as by CMP. A photoresist layer (not shown) may then be formed over the top surface of the interlayer dielectric layer 202L and the top surface of the first oxide semiconductor layer 206La. Then, the photoresist layer may be patterned using lithography techniques to produce a patterned photoresist 308, which may then be used as a mask to further etch the intermediate structure 700. As shown in FIG. 7A, the patterned photoresist 308 may be configured to shield the top portion 702 and the side portions 704 of the first oxide semiconductor layer 206La, while leaving the remaining unshielded portions of the first oxide semiconductor layer 206La and the interlayer dielectric layer 202L. The unshielded portions may then be removed in a subsequent anisotropic etching process, as described in more detail below with reference to FIGS. 8A and 8B. FIG. 8A is a vertical cross-sectional view of yet another intermediate structure 800 that may be used to form the semiconductor circuit 200 in accordance with various embodiments, and FIG. 8B is a top view of the intermediate structure 800 shown in FIG. 8A. The vertical plane defining the view in FIG. 8A is represented by the cross-section A-A' in FIG. 8B. As shown, the intermediate structure 800 may be formed from the intermediate structure 700 shown in FIG. 7 by performing an anisotropic etching process to remove the unshielded portions of the first oxide semiconductor layer 206La and the interlayer dielectric layer 202L. The patterned photoresist 308 may then be removed by ashing or by dissolving it using a solvent. The resulting intermediate structure 800 includes the electrical insulation structure 202, the patterned etch stop layer 306, and the remaining top portion 702 and side portions 704 of the first oxide semiconductor layer 206La. FIG. 9A is a vertical cross-sectional view of yet another intermediate structure 900 that may be used to form the semiconductor circuit 200 in accordance with various embodiments, and FIG. 9B is a top view of the intermediate structure 900 shown in FIG. 9A. The vertical plane defining the view in FIG. 9A is represented by the cross-section A-A' in FIG. 9B. The intermediate structure 900 shown in FIGS. 9A and 9B may be formed by further depositing an additional interlayer dielectric layer 202L over the intermediate structure 800 and forming a patterned photoresist 308 over the resulting structure. In this regard, an additional interlayer dielectric layer 202L can be deposited by a conformal deposition process (such as CVD, ALD, PVD, PECVD, etc.) or by a self-planarizing deposition process (such as spin coating). The excess portion of the interlayer dielectric layer 202L can be removed from above the top surface of the first oxide semiconductor layer 206La by a planarization process (such as by CMP). The planarization process can also remove the top portion 702 of the first oxide semiconductor layer 206La (see, for example, FIG. 8A). Then, the remaining pieces of the side portion 704 form the p-type semiconductor layer 206a of the semiconductor circuit 200 to be subsequently formed. Then, a uniform photoresist layer (not shown) can be deposited over the planarized surface of the interlayer dielectric layer 202L and the patterned etch stop layer 306. Then, the uniform photoresist layer can be patterned using lithography to form a patterned photoresist 308. As shown in FIG. 9B, the patterned photoresist 308 can include an exposed region 902 that can be etched in subsequent processing operations, as described in more detail with reference to FIGS. 10A and 10B. FIG. 10A is a vertical cross-sectional view of yet another intermediate structure 1000 that can be used to form a semiconductor circuit 200 in accordance with various embodiments, and FIG. 10B is a top view of the intermediate structure 1000 shown in FIG. 10A. The vertical plane defining the view in FIG. 10A is represented by the cross-section A-A' in FIG. 10B. The intermediate structure 1000 can be formed from the intermediate structure 900 by performing an anisotropic etching process to remove the portions of the interlayer dielectric layer 202L that are not shielded by the patterned photoresist 308. In this way, the anisotropic etching process can create trenches 1002. The presence of the trenches 1002 can allow an n-type semiconductor layer 206b to be subsequently formed on the second surface 204b of the electrical insulating structure 202, as described in more detail below with reference to FIGS. 11A through 13B. After performing the anisotropic etching process, the patterned photoresist 308 can be removed by ashing or by dissolving it using a solvent. FIG. 11A is a vertical cross-sectional view of yet another intermediate structure 1100 that can be used to form a semiconductor circuit 200 in accordance with various embodiments, and FIG. 11B is a top view of the intermediate structure 1100 shown in FIG. 11A. The vertical plane defining the view in FIG. 11A is represented by the cross-section A-A' in FIG. 11B. The intermediate structure 1100 can be formed by depositing a second oxide semiconductor layer 206Lb over the intermediate structure 1000 shown in FIGS. 10A and 10B. The second oxide semiconductor layer 206Lb can be an n-type semiconductive material, including but not limited to amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 , ZnO, GaO, Ga 2 O 3 , InO, In 2 O 3 , InZnO, ZnO, TiO x and their alloys. Other suitable semiconductive materials are also within the scope of this disclosure. For example, in various embodiments, the oxide semiconductor layer 206Lb may comprise a composition given by In x Ga y Zn z MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn. The oxide semiconductor layer 206Lb can be formed by any suitable method (such as ALD, CVD, PECVD, PVD, etc.). In an embodiment, the second oxide semiconductor layer 206Lb can be formed on the intermediate structure 1000 shown in FIGS. 10A and 10B. The thickness of the second oxide semiconductor layer 206Lb can range from approximately 2 nm to approximately 50 nm (such as approximately 5 nm to approximately 15 nm), but other embodiments can include smaller and larger thicknesses. After depositing the second oxide semiconductor layer 206Lb, the intermediate structure 600 can be optionally annealed. The optional annealing process can be carried out at a temperature in the range of 200 degrees Celsius to 400 degrees Celsius using rapid thermal annealing or furnace annealing processes. The annealing can be carried out in an environment of nitrogen, oxygen, or a mixture thereof. FIG. 12A is a vertical cross-sectional view of yet another intermediate structure 1200 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 12B is a top view of the intermediate structure 1200 shown in FIG. 12A. The vertical plane defining the view in FIG. 12A is represented by cross-section A-A' in FIG. 12B. The intermediate structure 1200 can be formed by depositing an additional interlayer dielectric layer 202L over the intermediate structure 1100 shown in FIGS. 11A and 11B. A planarization process (e.g., using CMP) can then be performed to remove the excess portion of the interlayer dielectric layer 202L and the top portion of the second oxide semiconductor layer 206Lb that is located above the top surface of the patterned etch stop layer 306. A patterned photoresist 308 can then be formed over the resulting structure. As shown in FIG. 12A, the patterned photoresist 308 can shield the side portions 1202 of the second oxide semiconductor layer 206Lb, the patterned etch stop layer 306, and the p-type semiconductor layer 206a, while leaving the other unshielded portions of the interlayer dielectric layer 202L and the second oxide semiconductor layer 206Lb. As shown in FIG. 12B, the patterned photoresist 308 can include exposed regions 902 that can be etched in subsequent processing operations, as described in more detail with reference to FIGS. 13A and 13B. FIG. 13A is a vertical cross-sectional view of yet another intermediate structure 1300 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 13B is a top view of the intermediate structure 1300 shown in FIG. 13A. The vertical plane defining the view in FIG. 13A is represented by cross-section A-A' in FIG. 13B. As shown, the intermediate structure 1300 can be formed by performing an anisotropic etching process to remove the unshielded portions of the second oxide semiconductor layer 206Lb and the interlayer dielectric layer 202L. The patterned photoresist 308 can then be removed by ashing or by dissolving it using a solvent. The resulting intermediate structure 1300 includes the electrical insulation structure 202, the p-type semiconductor layer 206a, the patterned etch stop layer 306, and the remaining portion of the second oxide semiconductor layer 206Lb that forms the n-type semiconductor layer 206b. As shown in FIGS. 13A and 13B, the anisotropic etching process can create trenches 1002 that can be filled with an additional interlayer dielectric layer 202L in subsequent processing operations, as described in more detail with reference to FIGS. 14A through 14C. FIG. 14A is a vertical cross-sectional view of yet another intermediate structure 1400 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 14B is a top view of the intermediate structure 1400 shown in FIG. 14A. FIG. 14C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 14A and 14B according to various embodiments. The intermediate structure 1400 can be formed by forming an additional interlayer dielectric layer 202L over the intermediate structure 1300 thereby filling the trenches 1002. The excess portion of the interlayer dielectric layer 202L can be removed using a planarization process (e.g., using CMP). The vertical plane defining the view in FIG. 14A is represented by the cross-section A-A' in FIG. 14B, and the vertical plane defining the view in FIG. 14C is represented by the cross-section C-C' in FIG. 14B. The cross-sectional view of FIG. 14A is used in FIGS. 15A, 15B, 16A, 16B, 17A, and 17B to illustrate the process for forming the first source electrode 110a, the second source electrode 110b, the first drain electrode 112a, and the second drain electrode 112b. The cross-sectional view of FIG. 14C is used in FIGS. 18B to 24B to illustrate the process for forming the gate electrode 116. FIG. 15A is a vertical cross-sectional view of yet another intermediate structure 1500 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 15B is a top view of the intermediate structure 1500 shown in FIG. 15A. FIG. 15C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 15A and 15B according to various embodiments. The intermediate structure 1500 can be formed by forming a patterned photoresist 308 over the intermediate structure 1400. As shown in FIGS. 15A and 15B, the patterned photoresist 308 can have openings 1502 that will allow the exposed regions of the interlayer dielectric layer 202L to be removed in a subsequent anisotropic etching process, as described in more detail with reference to FIGS. 16A to 16C. FIG. 16A is a vertical cross-sectional view of yet another intermediate structure 1600 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 16B is a top view of the intermediate structure 1600 shown in FIG. 16A. FIG. 16C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 16A and 16B according to various embodiments. The intermediate structure 1600 can be formed by performing an anisotropic etching process to remove the exposed portions of the interlayer dielectric layer 202L, thereby creating trenches 1002 in the interlayer dielectric layer 202L. As shown, each of the trenches 1002 can be formed adjacent to a corresponding p-type semiconductor layer 206a and n-type semiconductor layer 206b. The trenches 1002 can then be filled with a conductive material to form the first source electrode 110a, the second source electrode 110b, the first drain electrode 112a, and the second drain electrode 112b, as described in more detail with reference to FIGS. 17A to 17C below. FIG. 17A is a vertical cross-sectional view of yet another intermediate structure 1700 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 17B is a top view of the intermediate structure 1700 shown in FIG. 17A. FIG. 17C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 17A and 17B according to various embodiments. The intermediate structure 1700 can be formed by depositing a conductive material 1702 into the trench 1002. The conductive material 1702 can include a metal liner material and a metal fill material. The metal liner material can include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, TiC, TaC, and / or WC. The thickness of the metal liner material can range from approximately 1 nanometer to approximately 10 nanometers (e.g., approximately 3 nanometers to approximately 8 nanometers), but smaller and larger thicknesses can also be used. The metal fill material can include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal fill materials within the scope of this disclosure can also be used. The thickness of the metal fill material can range from approximately 5 nanometers to approximately 500 nanometers (e.g., approximately 20 nanometers to approximately 40 nanometers), but smaller and larger thicknesses can also be used. The metal liner material and the metal fill material can be formed by suitable deposition processes, which can include one or more of CVD processes, PVD processes, ALD processes, electroplating processes, etc. Other suitable deposition processes are within the scope of this disclosure. Then, the patterned photoresist 308 can be removed by ashing or by dissolving it using a solvent. Then, the excess portion of the conductive material 1702 can be removed from above a horizontal plane of the top surface including the interlayer dielectric layer 202L by a planarization process such as CMP, but other suitable planarization processes can also be used. The remaining portion of the conductive material 1702 forms a first source electrode 110a, a second source electrode 110b, a first drain electrode 112a, and a second drain electrode 112b (e.g., the first source electrode 110a and the second source electrode 110b are shown in FIG. 18A). In some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b can include one or more alloys of W, Mo, Co, Pd, Ti, and mixtures thereof with or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition. FIG. 18A is a vertical cross-sectional view of yet another intermediate structure 1800 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 18B is a top view of the intermediate structure 1800 shown in FIG. 18A. FIG. 18C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 18A and 18B according to various embodiments. The intermediate structure 1800 can be formed by removing the patterned photoresist 308 of the intermediate structure 1700 and planarizing the intermediate structure 1700, and then forming a new patterned photoresist 308 over the resulting structure. As shown in FIGS. 18B and 18C, the patterned photoresist 308 can have openings 1502 that will allow exposed regions of the interlayer dielectric layer 202L to be removed in a subsequent anisotropic etching process, as described in more detail with reference to FIGS. 19A to 19C. FIG. 19A is a vertical cross-sectional view of yet another intermediate structure 1900 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 19B is a top view of the intermediate structure 1900 shown in FIG. 19A. FIG. 19C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 19A and 19B according to various embodiments. The intermediate structure 1900 can be formed by performing an anisotropic etching process to remove the exposed portions of the interlayer dielectric layer 202L, thereby creating trenches 1002 in the interlayer dielectric layer 202L. As shown, each of the trenches 1002 can be formed adjacent to a corresponding p-type semiconductor layer 206a and n-type semiconductor layer 206b. The trenches 1002 can then be filled with a gate dielectric layer 118 and a conductive material to form gate electrodes 116, as described in more detail below with reference to FIGS. 20A to 24C. FIG. 20A is a vertical cross-sectional view of yet another intermediate structure 2000 that can be used to form a semiconductor circuit 200 according to various embodiments, and FIG. 20B is a top view of the intermediate structure 2000 shown in FIG. 20A. FIG. 20C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 20A and 20B according to various embodiments. The intermediate structure 2000 can be formed by depositing a gate dielectric layer 118 over the intermediate structure 1900 shown in FIG. 19. The gate dielectric layer 118 can include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicate, tantalum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina, or various other insulating structures (e.g., multilayer stack structures including alternating insulating layers). Other suitable dielectric materials are also within the scope of this disclosure. In other embodiments, the gate dielectric layer 118 can include an alternating multilayer structure that includes silicon dioxide and silicon nitride. In other embodiments, the gate dielectric layer 118 can include a ferroelectric material. The gate dielectric layer 118 can be formed by any suitable technique (such as ALD, CVD, PECVD, PVD, etc.). The thickness of the gate dielectric layer 118 can range from approximately 2 nanometers to approximately 20 nanometers (such as approximately 5 nanometers to approximately 12 nanometers), but other embodiments can include smaller and larger thicknesses. After depositing the gate dielectric layer 118, the intermediate structure 2000 can be selectively annealed. The selective annealing process can be performed at a temperature in the range of 200 degrees Celsius to 400 degrees Celsius using a rapid thermal annealing or furnace annealing process. The annealing can be performed in an environment of nitrogen, oxygen, or a mixture thereof. FIG. 21A is a vertical cross-sectional view of yet another intermediate structure 2100 that can be used to form the semiconductor circuit 200 according to various embodiments, and FIG. 21B is a top view of the intermediate structure 2100 shown in FIG. 21A. FIG. 21C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 21A and 21B according to various embodiments. The intermediate structure 2100 can be formed by depositing a conductive material 1702 over the intermediate structure 1900. The conductive material 1702 can include a metal liner material and a metal fill material. The metal liner material can include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, TiC, TaC, and / or WC. The thickness of the metal liner material can range from approximately 1 nanometer to approximately 10 nanometers (such as approximately 3 nanometers to approximately 8 nanometers), but smaller and larger thicknesses can also be used. The metal fill material can include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, its alloys, and / or its combinations. Other suitable metal liner materials and metal fill materials within the scope of this disclosure can also be used. The thickness of the metal fill material can range from approximately 5 nanometers to approximately 150 nanometers (such as approximately 20 nanometers to approximately 40 nanometers), but smaller and larger thicknesses can also be used. The metal liner material and the metal fill material can be formed by suitable deposition processes, which can include one or more of CVD processes, PVD processes, ALD processes, electroplating processes, etc. Other suitable deposition processes are within the scope of this disclosure. FIG. 22A is a vertical cross-sectional view of yet another intermediate structure 2200 that can be used to form the semiconductor circuit 200 according to various embodiments, and FIG. 22B is a top view of the intermediate structure 2200 shown in FIG. 22A. FIG. 22C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 22A and 22B according to various embodiments. The intermediate structure 2200 can be formed by forming a patterned photoresist 308 over the intermediate structure 2100. Then, the patterned photoresist 308 can be used to etch the unmasked portion of the conductive material 1702, thereby forming the gate electrode 116. FIG. 23A is a vertical cross-sectional view of yet another intermediate structure 2300 that can be used to form the semiconductor circuit 200 according to various embodiments, and FIG. 23B is a top view of the intermediate structure 2300 shown in FIG. 23A. FIG. 23C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 23A and 23B according to various embodiments. The intermediate structure 2300 can be formed by performing an anisotropic etching process to remove portions of 1702 that are not masked by the patterned photoresist 308 of the intermediate structure 2200. The patterned photoresist 308 can then be removed by ashing or by dissolving it using a solvent. As shown, the anisotropic etching process can create gate electrodes 116 that are electrically separated from each other. FIG. 24A is a vertical cross-sectional view of the semiconductor circuit 200 formed by the process described with reference to FIGS. 3A to 23C according to various embodiments, and FIG. 24B is a top view of the semiconductor circuit 200 shown in FIG. 24A. FIG. 24A is yet another vertical cross-sectional view of the semiconductor circuit shown in FIGS. 24A and 24B according to various embodiments, and FIG. 24D is a three-dimensional perspective view of the semiconductor circuit shown in FIGS. 24A to 24C. For clarity, the view of FIG. 24D shows the semiconductor circuit 200 with the surrounding interlayer dielectric layer 202L and gate dielectric 118 removed. The views of FIGS. 24A and 24C are represented by the double-headed arrows labeled A and C in FIG. 24D. The semiconductor circuit 200 of FIGS. 24A to 24D can be formed from the intermediate structure 2300 by depositing an additional interlayer dielectric layer 202L. The excess portion of the additional interlayer dielectric layer 202L can be removed above the top surface of the gate electrode 116 by a planarization process. As shown in FIGS. 24A and 24C, the planarization process can create a planar surface of the interlayer dielectric layer 202L that is flush with the surface of the gate electrode 116. In this way, additional circuit elements can be formed above the semiconductor circuit 200 in subsequent processing operations. For example, an additional interlayer dielectric layer 202L and various electrical interconnect structures can be formed above the semiconductor circuit 200. For example, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to one or more electrical interconnect structures that will be formed above the semiconductor circuit 200. As an alternative or in addition, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148) formed in one or more dielectric material layers (136, 138, 140) below the semiconductor circuit 200. FIG. 25 is a flowchart showing the operations of a method 2500 of forming a semiconductor circuit 200 according to various embodiments. In operation 2502, method 2500 may include: forming an electrically insulating structure 202 having a planar geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented in a respective plane perpendicular to a thickness direction (e.g., the x direction in FIGS. 2A, 2B, 13A, and 13B). In operation 2504, method 2500 may include forming a p-type semiconductor layer 206a on the first surface 204a. In operation 2506, method 2500 may include forming an n-type semiconductor layer 206b on the second surface 204b. In operation 2508, method 2500 may include forming a gate dielectric layer 118 in contact with the p-type semiconductor layer 206a and the n-type semiconductor layer 206b. In operation 2510, method 2500 may include forming a first source electrode 110a and a first drain electrode 112a in contact with the p-type semiconductor layer 206a. In operation 2512, method 2500 may include forming a second source electrode 110b and a second drain electrode 112b in contact with the n-type semiconductor layer 206b. In operation 2514, method 2500 may include forming a gate electrode 116 in contact with the gate dielectric layer 118. Method 2500 may further include configuring the semiconductor circuit 200 as an inverter circuit (200, 200c) by performing operations including electrically connecting the first source electrode 110a to a voltage source 208 and connecting the second source electrode 110b to a ground voltage terminal 210, electrically connecting the gate electrode 116 to an input signal terminal 212, and electrically connecting the first drain electrode 112a and the second drain electrode 112b to an output signal terminal 214. Method 2500 may further include forming the n-type semiconductor layer 206b to include amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 、ZnO、GaO、Ga 2 O 3 、InO、In 2 O 3 、InZnO、ZnO、TiO x one or more of the alloys thereof. Method 2500 may further include forming the p-type semiconductor layer 206a to include one or more of NiO, SnO, and Cu 2 O. Method 2500 may further include forming the gate dielectric layer 118 to include one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina. Method 2500 may further include forming the electrical insulating structure 202 to include one or more of AlO x , SiO 2 and SiN x one or more of them. Method 2500 may further include forming one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b to include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al. Referring to all the figures and according to various embodiments of the present disclosure, an inverter circuit (200, 200c) is provided. The inverter circuit (200, 200c) may include an electrical insulating structure 202 having a planar geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented in a respective plane perpendicular to the thickness direction (e.g., the x direction in FIGS. 2A, 2B, 13A, and 13B). The inverter circuit (200, 200c) may further include a p-type semiconductor layer 206a formed on the first surface 204a, an n-type semiconductor layer 206b formed on the second surface 204b, and a gate dielectric layer 118 formed in contact with the p-type semiconductor layer 206a and the n-type semiconductor layer 206b. The inverter circuit (200, 200c) may further include a gate electrode 116 formed in contact with the gate dielectric layer 118, a first source electrode 110a and a first drain electrode 112a formed in contact with the p-type semiconductor layer 206a, and a second source electrode 110b and a second drain electrode 112b formed in contact with the n-type semiconductor layer 206b. The first source electrode 110a may be electrically connected to a voltage source 208, and the second source electrode 110b may be connected to a ground voltage terminal 210. The gate electrode 116 may be connected to an input signal terminal 212, and the first drain electrode 112a and the second drain electrode 112b may be electrically connected to an output signal terminal 214. According to various embodiments, an electrical insulating structure 202 may be formed over an interlayer dielectric layer (150, 202L, 302) having a horizontal interface (see, e.g., FIGS. 1 and 24A-24C), and the electrical insulating structure 202 may have a vertical orientation such that each of a first surface 204a and a second surface 204b is perpendicular to the horizontal interface of the interlayer dielectric layer (150, 202L, 302). According to various embodiments, the interlayer dielectric layer (150, 202L, 302) may further include one or more electrical interconnect structures (142, 144, 146, 148), and one or more of a first source electrode 110a, a first drain electrode 112a, a second source electrode 110b, a second drain electrode 112b, and a gate electrode 116 may be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148). In some embodiments, one or both of a p-type semiconductor layer 206a and an n-type semiconductor layer 206b include a metal oxide semiconductor. For example, one or more of the n-type semiconductor layer 206b and the p-type semiconductor layer 206a may include a metal oxide semiconductor including a multi-layer structure. In other embodiments, the n-type semiconductor layer 206b may include an alloy including oxygen, a Group III element, and a Group V element. In certain embodiments, the n-type semiconductor layer 206b may include amorphous silicon, Al-doped 2 O 5 Zn 2 -doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 -, ZnO, GaO, Ga 2 O 3 -, InO, In 2 O 3 -, InZnO, ZnO, TiO x and alloys thereof. In other embodiments, the n-type semiconductor layer 206b may include In x Ga y Zn zA composition given by MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn. The p-type semiconductor layer 206a may include one or more of NiO, SnO, and Cu 2 O. Other p-type metal oxide semiconductors may also be used in other embodiments. In various embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina, and the electrical insulation structure 202 may include AlO x 、SiO 2 、SiN x or one or more of other electrical insulation materials. In some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al. In other embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b further include one or more alloys of W, Mo, Co, Pd, Ti, and mixtures thereof with N and / or O or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition. According to other embodiments, a semiconductor circuit 200 is provided. The semiconductor circuit 200 may include: a first layer of a p-type metal oxide semiconductor 206a formed in an interlayer dielectric layer (150, 202L, 302) along a first vertical plane with respect to a horizontal interface of the interlayer dielectric layer (150, 202L, 302); and a second layer of an n-type metal oxide semiconductor 206b formed in the interlayer dielectric layer (150, 202L, 302) along a second vertical plane with respect to the horizontal interface of the interlayer dielectric layer (150, 202L, 302), such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric layer (150, 202L, 302) (see, for example, FIGS. 24A and 24C). The semiconductor circuit 200 may further include: a gate electrode 116 having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; and a gate dielectric layer 118 (see, for example, FIGS. 2A, 2B, and 24A to 24D), separating the first vertical portion of the gate electrode 116 from the first layer and separating the second vertical portion of the gate electrode 116 from the second layer. The semiconductor circuit 200 may further include: a first source electrode 110a and a first drain electrode 112a formed in contact with a p-type metal oxide semiconductor; and a second source electrode 110b and a second drain electrode 112b formed in contact with an n-type metal oxide semiconductor. In another embodiment, the semiconductor circuit 200 may be configured as an inverter circuit (200, 200c), in which the first source electrode 110a is electrically connected to a voltage source 208, and the second source electrode 110b is connected to a ground voltage terminal 210, the gate electrode 116 is electrically connected to an input signal terminal 212, and the first drain electrode 112a and the second drain electrode 112b are electrically connected to an output signal terminal 214 (see, for example, FIGS. 2B and 2C). According to various embodiments, the n-type metal oxide semiconductor may include amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 、ZnO、GaO、Ga 2 O 3 、InO、In 2 O 3 、InZnO、ZnO、TiO x and one or more of their alloys, and the p-type metal oxide semiconductor includes NiO, SnO, and Cu 2One or more of those in O. In some other embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina. In addition, according to some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b may include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, Al, and alloys with N and / or O or without N and / or O of one or more of W, Mo, Co, Pd, Ti, and their mixtures. The above embodiments provide semiconductor circuits (200, 200c) and methods that may have advantages in terms of manufacturing flexibility, size reduction, and short-channel effect reduction. In this regard, an exemplary semiconductor circuit (such as a CMOS inverter (200, 200c)) is provided, which can be formed in a BEOL process and can be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. In this way, the disclosed semiconductor circuits (200, 200c) may include materials that can be processed at low temperatures, thus not damaging previously fabricated devices (such as FEOL devices and MEOL devices). In addition, an exemplary semiconductor circuit may include a p-channel metal-oxide-semiconductor field-effect transistor (pFET) 216 having a vertical channel layer 206a and an n-channel metal-oxide-semiconductor field-effect transistor (nFET) 218 also having a vertical channel layer 206b. Each of the vertical p-channel 206a and the vertical n-channel 206b may be formed on opposite sides of a vertically oriented electrical insulating structure 202 such that the vertical p-channel 206a is closely spaced relative to the vertical n-channel 206b. Relative to alternative structures that do not include vertical channels (206a, 206b), the use of such vertical channels (206a, 206b) can provide semiconductor circuits (200, 200c) with reduced size and can allow for a longer channel length without increasing the device size, which can mitigate the short-channel effect. The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure. 100: Semiconductor structure 102: Substrate 104: Semiconductor material layer 106: Shallow trench isolation structure 108: Field effect transistor 110: Source electrode 110a: First source electrode / source / drain electrode 110b: Second source electrode / source / drain electrode 112: Drain electrode 112a: First drain electrode / source / drain electrode 112b: Second drain electrode / source / drain electrode 114: Semiconductor channel 116: Gate electrode / gate structure 118: Gate dielectric layer 120: Gate electrode 122: Gate capping dielectric 124: Dielectric gate spacer 126: Source side metal-semiconductor alloy region 128: Drain side metal-semiconductor alloy region 130: Memory array region 132: Peripheral region 134: CMOS circuit 136: Lower level dielectric material layer / dielectric material layer / first dielectric material layer 138: Lower level dielectric material layer / dielectric material layer / first interconnect level dielectric material layer 140: Second interconnect level dielectric material layer / second wire and via level dielectric material layer / lower level dielectric material layer / dielectric material layer 142: Device contact via structure / metal interconnect structure / first metal interconnect structure / electrical interconnect structure 144: First metal wire structure / first metal interconnect structure / metal interconnect structure / electrical interconnect structure 146: First metal via structure / metal interconnect structure / first metal interconnect structure / electrical interconnect structure 148: Second metal wire structure / metal interconnect structure / first metal interconnect structure / electrical interconnect structure 150: Insulating substrate layer / interlayer dielectric layer 200: Semiconductor circuit / inverter circuit / CMOS inverter 200c: Equivalent circuit / inverter circuit / semiconductor circuit / CMOS inverter 202: Electrical insulation structure 202L: Interlayer dielectric layer 204a: First surface 204b: Second surface 206a: p-type semiconductor layer / p-type metal oxide semiconductor / vertical channel layer / vertical p-channel / vertical channel 206b: n-type semiconductor layer / n-type metal oxide semiconductor / vertical channel layer / vertical n-channel / vertical channel 206La: First oxide semiconductor layer 206Lb: Second oxide semiconductor layer 208: Voltage source 210: Ground voltage terminal 212: Input signal terminal 214: Output signal terminal 216: pFET / device 218: nFET / device 220a: Dotted arrow / first current 220b: Dotted arrow / second current 222: Channel length 224: Channel width 226: Source / drain length 228: Source / drain thickness 230: Thickness 232: Gate length 234: Gate width 236: Gate thickness 238: Gate dielectric thickness 240a: p-type thickness 240b: n-type thickness300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300: Intermediate structure 302: Substrate / Interlayer dielectric 306: Patterned etch stop layer 306L: Etch stop layer 308: Patterned photoresist 308L: Photoresist 702: Top portion 704, 1202: Side portions 902: Exposed area 1002: Channel 1502: Opening 1702: Conductive material 2500: Method 2502, 2504, 2506, 2508, 2510, 2512, 2514: Operations A, C: Double arrows A–A’, C-C’: Cross section GND: Ground VDD: Source voltage V out : Output voltage x, y: Directions The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a vertical cross-sectional view of a first exemplary structure after forming complementary metal-oxide-semiconductor (CMOS) transistors, a first metal interconnect structure formed in a lower-level dielectric material layer, and an isolation dielectric layer, according to various embodiments. FIG. 2A is a three-dimensional perspective view of a semiconductor circuit that may be formed in a BEOL process, according to various embodiments. FIG. 2B is another three-dimensional perspective view of the semiconductor circuit shown in FIG. 2A, according to various embodiments. FIG. 2C is a schematic equivalent circuit illustrating the semiconductor circuit shown in FIGS. 2A and 2B, according to various embodiments. FIG. 2D is another three-dimensional perspective view of the semiconductor circuit shown in FIG. 2A, according to various embodiments, and shows the various dimensions of the components of the semiconductor circuit. FIG. 3A is a vertical cross-sectional view of an intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 3B is a top view of the intermediate structure shown in FIG. 3A, according to various embodiments. FIG. 4A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 4B is a top view of the intermediate structure shown in FIG. 4A, according to various embodiments. FIG. 5A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 5B is a top view of the intermediate structure shown in FIG. 5A, according to various embodiments. FIG. 6A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 6B is a top view of the intermediate structure shown in FIG. 6A, according to various embodiments. FIG. 7A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 7B is a top view of the intermediate structure shown in FIG. 7A, according to various embodiments. FIG. 8A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 8B is a top view of the intermediate structure shown in FIG. 8A, according to various embodiments. FIG. 9A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 9B is a top view of the intermediate structure shown in FIG. 9A, according to various embodiments. FIG. 10A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 10B is a top view of the intermediate structure shown in FIG. 10A, according to various embodiments. FIG. 11A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments. FIG. 11B is a top view of the intermediate structure shown in FIG. 11A, according to various embodiments. FIG. 12A is a vertical cross-sectional view of another intermediate structure that may be used to form a semiconductor circuit, according to various embodiments.FIG. 12B is a top view of the intermediate structure shown in FIG. 12A according to various embodiments. FIG. 13A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 13B is a top view of the intermediate structure shown in FIG. 13A according to various embodiments. FIG. 14A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 14B is a top view of the intermediate structure shown in FIG. 14A according to various embodiments. FIG. 14C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 14A and 14B according to various embodiments. FIG. 15A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 15B is a top view of the intermediate structure shown in FIG. 15A according to various embodiments. FIG. 15C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 15A and 15B according to various embodiments. FIG. 16A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 16B is a top view of the intermediate structure shown in FIG. 16A according to various embodiments. FIG. 16C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 16A and 16B according to various embodiments. FIG. 17A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 17B is a top view of the intermediate structure shown in FIG. 17A according to various embodiments. FIG. 17C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 17A and 17B according to various embodiments. FIG. 18A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 18B is a top view of the intermediate structure shown in FIG. 18A according to various embodiments. FIG. 18C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 18A and 18B according to various embodiments. FIG. 19A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 19B is a top view of the intermediate structure shown in FIG. 19A according to various embodiments. FIG. 19C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 19A and 19B according to various embodiments. FIG. 20A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 20B is a top view of the intermediate structure shown in FIG. 20A according to various embodiments. FIG. 20C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 20A and 20B according to various embodiments. FIG. 21A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 21B is a top view of the intermediate structure shown in FIG. 21A according to various embodiments. FIG. 21C is yet another vertical cross-sectional view of the intermediate structure shown in FIGS. 21A and 21B according to various embodiments. FIG. 22A is a vertical cross-sectional view of yet another intermediate structure that can be used to form a semiconductor circuit according to various embodiments.FIG. 22B is a top view of the intermediate structure shown in FIG. 22A according to various embodiments. FIG. 22C is another vertical cross-sectional view of the intermediate structure shown in FIGS. 22A and 22B according to various embodiments. FIG. 23A is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor circuit according to various embodiments. FIG. 23B is a top view of the intermediate structure shown in FIG. 23A according to various embodiments. FIG. 23C is another vertical cross-sectional view of the intermediate structure shown in FIGS. 23A and 23B according to various embodiments. FIG. 24A is a vertical cross-sectional view of a semiconductor circuit formed by the process described with reference to FIGS. 3A to 23C according to various embodiments. FIG. 24B is a top view of the semiconductor circuit shown in FIG. 24A according to various embodiments. FIG. 24C is another vertical cross-sectional view of the semiconductor circuit shown in FIGS. 24A and 24B according to various embodiments. FIG. 24D is a three-dimensional perspective view of the semiconductor circuit shown in FIGS. 24A to 24C according to various embodiments. FIG. 25 is a flowchart showing the operations of a method for forming a semiconductor circuit according to various embodiments. 110a: First source electrode / source / drain electrode 110b: Second source electrode / source / drain electrode 112b: Second drain electrode / source / drain electrode 116: Gate electrode / gate structure 118: Gate dielectric layer 200: Semiconductor circuit / inverter circuit / CMOS inverter 202: Electrical insulation structure 204a: First surface 204b: Second surface 206a: p-type semiconductor layer / p-type metal oxide semiconductor / vertical channel layer / vertical p-channel / vertical channel 206b: n-type semiconductor layer / n-type metal oxide semiconductor / vertical channel layer / vertical n-channel / vertical channel x, y: Directions

Claims

1. An inverter circuit, comprising: an electrically insulating structure having a planar geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a respective plane perpendicular to a thickness direction; a p-type semiconductor layer formed on the first surface; an n-type semiconductor layer formed on the second surface; a gate dielectric layer formed in contact with the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed in contact with the gate dielectric layer; a first source electrode and a first drain electrode formed in contact with the p-type semiconductor layer; and a second source electrode and a second drain electrode formed in contact with the n-type semiconductor layer, wherein the first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, wherein the gate electrode is electrically connected to an input signal terminal, and wherein the first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

2. The inverter circuit according to claim 1, wherein the electrically insulating structure is formed over an interlayer dielectric layer having a horizontal interface, and wherein the electrically insulating structure has a vertical orientation such that each of the first surface and the second surface is perpendicular to the horizontal interface of the interlayer dielectric layer.

3. The inverter circuit according to claim 2, wherein the interlayer dielectric layer further includes one or more electrical interconnect structures, and wherein one or more of the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the gate electrode are electrically connected to the one or more electrical interconnect structures.

4. The inverter circuit according to claim 1, wherein at least one of the p-type semiconductor layer and the n-type semiconductor layer includes a metal oxide semiconductor.

5. The inverter circuit according to claim 1, wherein at least one of the n-type semiconductor layer and the p-type semiconductor layer includes a metal oxide semiconductor, the metal oxide semiconductor including a multi-layer structure.

6. The inverter circuit according to claim 1, wherein the n-type semiconductor layer includes an alloy containing oxygen, a Group III element, and a Group V element.

7. The inverter circuit according to claim 1, wherein the n-type semiconductor layer comprises amorphous silicon, Al 2 O 5 Zn 2 -doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 , ZnO, GaO, Ga 2 O 3 , InO, In 2 O 3 , InZnO, ZnO, TiO x and one or more of their alloys.

8. The inverter circuit according to claim 1, wherein the n-type semiconductor layer comprises a composition given by In x Ga y Zn z MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn.

9. The inverter circuit according to claim 1, wherein the p-type semiconductor layer comprises one or more of NiO, SnO, and Cu 2 O.

10. The inverter circuit according to claim 1, wherein the gate dielectric layer includes one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina.

11. The inverter circuit according to claim 1, wherein the electrical insulation structure includes AlO x , SiO 2 , and SiN x or more thereof.

12. The inverter circuit according to claim 1, wherein one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al.

13. The inverter circuit according to claim 1, wherein one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode further comprise one or more alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, having N and / or O or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition.

14. A semiconductor circuit, comprising: a first layer of a p-type metal oxide semiconductor formed in the interlayer dielectric along a first vertical plane with respect to a horizontal interface of the interlayer dielectric; a second layer of an n-type metal oxide semiconductor formed in the interlayer dielectric along a second vertical plane with respect to the horizontal interface of the interlayer dielectric, such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric; a gate electrode having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; a gate dielectric layer separating the first vertical portion of the gate electrode from the first layer and separating the second vertical portion of the gate electrode from the second layer; a first source electrode and a first drain electrode formed in contact with the p-type metal oxide semiconductor; and a second source electrode and a second drain electrode formed in contact with the n-type metal oxide semiconductor.

15. The semiconductor circuit according to claim 14, wherein the semiconductor circuit is configured as an inverter circuit, in which: the first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, the gate electrode is electrically connected to an input signal terminal, and the first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

16. The semiconductor circuit according to claim 14, wherein the n-type metal oxide semiconductor comprises amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 , ZnO, GaO, Ga 2 O 3 , InO, In 2 O 3 , InZnO, ZnO, TiO x and one or more of their alloys, and wherein the p-type metal oxide semiconductor comprises one or more of NiO, SnO and Cu 2 O.

17. The semiconductor circuit according to claim 14, wherein the gate dielectric layer comprises one or more of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina, and wherein one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode comprise one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, Al, and alloys of W, Mo, Co, Pd, Ti, and mixtures thereof, having N and / or O or without N and / or O.

18. A method of forming a semiconductor circuit, comprising: Form an electrical insulation structure having a planar geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a respective plane perpendicular to the thickness direction; form a p-type semiconductor layer on the first surface; form an n-type semiconductor layer on the second surface; form a gate dielectric layer in contact with the p-type semiconductor layer and the n-type semiconductor layer; form a first source electrode and a first drain electrode in contact with the p-type semiconductor layer; form a second source electrode and a second drain electrode in contact with the n-type semiconductor layer; and form a gate electrode in contact with the gate dielectric layer.

19. The method of claim 18, further comprising configuring the semiconductor circuit as an inverter circuit by performing operations that include: electrically connect the first source electrode to a voltage source and electrically connect the second source electrode to a ground voltage terminal; electrically connect the gate electrode to an input signal terminal; and electrically connect the first drain electrode and the second drain electrode to an output signal terminal.

20. The method of claim 18, further includes: Form the n-type semiconductor layer to include amorphous silicon, Al 2 O 5 Zn 2 doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga 2 O 3 , ZnO, GaO, Ga 2 O 3 , InO, In 2 O 3 , InZnO, ZnO, TiO x and at least one of their alloys; form the p-type semiconductor layer to include at least one of NiO, SnO and Cu 2 O; form the gate dielectric layer to include at least one of silicon oxide, aluminum oxide, hafnium oxide, lanthanum hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide and hafnium dioxide-alumina; form the electrical insulation structure to include AlO x , SiO 2 and SiN x and at least one of them; and form one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode to include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti and Al.