Semiconductor devices and method for manufacturing the same

Abstract

This disclosure describes a semiconductor device having a dielectric fin structure. The semiconductor device includes a channel structure on a substrate and a dielectric fin structure on the substrate and adjacent to the channel structure. The channel structure extends along a first direction. The dielectric fin structure comprises a rigid dielectric material and extends along a second direction parallel to the first direction. The semiconductor device also includes an isolation structure extending through the channel structure. The isolation structure is in contact with the dielectric fin structure.

Description

Dielectric Fin Structure for Semiconductor Devices Embodiments of the present disclosure relate to a dielectric fin structure for semiconductor devices. With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost is increasing day by day. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (finFETs). This scaling down increases the complexity of semiconductor manufacturing processes and the difficulty of process control in semiconductor devices. The present disclosure relates to a semiconductor structure, including: a channel structure on a substrate, wherein the channel structure extends in a first direction; a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction; and an isolation structure extending through the channel structure, wherein the isolation structure contacts the dielectric fin structure. The present disclosure also relates to a semiconductor device, including: a plurality of channel structures on a substrate; a plurality of dielectric fin structures on the substrate, the plurality of dielectric fin structures including a hard dielectric material, wherein the plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration; a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures; and an isolation structure extending through the gate structure and at least one of the plurality of channel structures, wherein the isolation structure contacts at least one of the plurality of dielectric fin structures. The present disclosure also relates to a method of manufacturing a semiconductor device, including: forming a channel structure on a substrate, wherein the channel structure extends in a first direction; forming a dielectric fin structure adjacent to the channel structure on the substrate, wherein the dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction; and forming an isolation structure extending through the channel structure, wherein the isolation structure contacts the dielectric fin structure. The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. As used herein, forming a first feature over a second feature means that the first and second features are formed in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed. In addition, spatial relative terms (such as, "beneath", "below", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element(s) or (one or more) feature(s). These spatial relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be noted that references in the specification to "an embodiment", "embodiment", "example embodiment", "exemplary", etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, implementation of such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described, is within the knowledge of those skilled in the art. It should be understood that the terminology or phraseology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of this specification is to be interpreted by those skilled in the relevant art(s) in light of the teachings herein. In some embodiments, the terms "about" and "substantially" may indicate that a given value varies within 20% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of that value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the value as interpreted by those skilled in the relevant art(s) in light of the teachings herein. As the demand for lower power consumption, higher performance, and smaller semiconductor devices increases, the size of semiconductor devices has been continuously scaled down. The continuous scaling of device size and the growing demand for device performance may require various process and material improvements, which may pose multiple challenges. For example, a continuous polysilicon on diffusion edge (CPODE) or a continuous metal on diffusion edge (CMODE) process can be used to pattern nanostructured transistors having a trench isolation structure. The trench isolation structure can reduce leakage current through the source / drain (S / D) epitaxial structure, the transistor channel, and the substrate. Nanostructured transistors can include finFETs, gate-all-around field-effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and transistors of other similar structures. However, the CPODE and CMODE processes may generate tensile and / or compressive forces on the surface of the substrate, causing deformation of the substrate and inducing layout-related effects (LDE) of nanostructured transistors on the substrate. The iso-dense depth loading effect of LDE may increase the leakage current of nanostructured transistors. The iso-dense critical dimension loading effect of LDE may cause damage to the S / D epitaxial structure. The gate deformation from LDE may cause threshold voltage (Vt) drift of nanostructured transistors. Various embodiments of the present disclosure provide methods for forming a dielectric fin structure in a semiconductor device (e.g., a nanostructured transistor) in an integrated circuit (IC) and / or other semiconductor devices. In some embodiments, a channel structure extending in a first direction may be formed on a substrate. A dielectric fin structure adjacent to the channel structure may be formed on the substrate. In some embodiments, the dielectric fin structure may include a hard dielectric material and extend in a second direction parallel to the first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. A gate structure may be formed on the channel structure and the dielectric fin structure. An isolation structure may be formed on the gate structure, and the isolation structure may extend through the gate structure and the channel structure. In some embodiments, the isolation structure may contact the dielectric fin structure. In some embodiments, the isolation structure may be formed through a CPODE or CMODE process. In some embodiments, the dielectric fin structure may reduce the deformation of the substrate and minimize the LDE effect of the semiconductor device on the substrate. Therefore, the dielectric fin structure may reduce device leakage current, minimize damage to the S / D epitaxial structure, and reduce Vt drift of the semiconductor device on the substrate. FIG. 1 shows a top view of a semiconductor device 100 having a dielectric fin structure according to some embodiments. FIG. 2 shows a partial isometric view of a semiconductor device 100 having a dielectric fin structure according to some embodiments. FIGS. 3 to 5 respectively show partial cross-sectional views of a semiconductor device 100 having a dielectric fin structure along lines A-A, B-B, and C-C shown in FIG. 2. In some embodiments, the semiconductor device 100 may include transistors 102A to 102C, as shown in FIG. 2. In some embodiments, the transistors 102A to 102C may include nanostructure transistors. The nanostructure transistors may include finFETs, GAA FETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and transistors of other similar structures. The nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration. In some embodiments, the transistors 102A to 102C may be n-type field effect transistors (NFETs). In some embodiments, the transistors 102A to 102C may be p-type field effect transistors (PFETs). In some embodiments, any one of the transistors 102A to 102C may be an NFET or a PFET. Although FIG. 2 shows three transistors, the semiconductor device 100 may have any number of transistors. Additionally, the semiconductor device 100 may be incorporated into an IC by using other structural components (such as conductive vias, wires, dielectric layers, passivation layers, and interconnects, not shown for simplicity). Unless otherwise specified, the discussion of each element with the same label for transistors 102A to 102C applies to each other. Additionally, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Referring to FIGS. 1 to 5, a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104, and the semiconductor device 100 may be isolated by shallow trench isolation (STI) regions 106. Each of the transistors 102A to 102C may include a fin structure 108, nanostructures 122-1, 122-2, and 122-3 (collectively referred to as "nanostructures 122"), a gate dielectric layer 124, a gate structure 112, gate spacers 114, internal spacers 121, and S / D structures 110. In some embodiments, the semiconductor device may further include trench isolation structures 113-1 and 113-2 (collectively referred to as "trench isolation structures 113"), a protective layer 115, an etch stop layer (ESL) 116, an isolation layer 117, an interlayer dielectric (ILD) layer 118, a dielectric fin structure 119, and a gate isolation structure 120. Referring to FIGS. 1 to 5, the substrate 104 may comprise a semiconductor material such as silicon. In some embodiments, the substrate 104 comprises a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, the substrate 104 comprises (i) an elemental semiconductor such as germanium; (ii) a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. Additionally, the substrate 104 may be doped, depending on design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). The STI region 106 may provide electrical isolation between the transistors 102A to 102C, as well as electrical isolation from adjacent transistors (not shown) on the substrate 104 and / or from adjacent active and passive components (not shown) integrated with or deposited on the substrate 104. In some embodiments, as shown in FIG. 5, an oxide liner 105 may be disposed between the STI region 106 and the substrate 104 for protecting the fin structure 108 and the nanostructure 122 during the formation of the STI region 106. In some embodiments, the oxide liner 105 may comprise silicon oxide or other suitable dielectric materials. The STI region 106 may be made of a dielectric material. In some embodiments, the STI region 106 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI region 106 may comprise a multi-layer structure. Referring to FIGS. 1 to 5, the nanostructure 122 and the fin structure 108 may be formed on a patterned portion of the substrate 104. Embodiments of the nanostructures and fin structures disclosed herein may be patterned by any suitable method. For example, one or more lithography processes (including double patterning processes or multi-patterning processes) may be used for patterning to obtain the nanostructures and fin structures. The double patterning process or multi-patterning process may combine a lithography process and a self-alignment process to form, for example, a pattern with a pitch smaller than the pitch obtainable using a single direct lithography process. For example, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a lithography process. Spacers may be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers may be used to pattern the nanostructures and fin structures. As shown in FIGS. 1 to 5, the nanostructures 122 and the fin structures 108 can extend along the X-axis. In some embodiments, the nanostructures 122 and the fin structures 108 can be disposed on the substrate 104. The nanostructures 122 can include a stack of nanostructures 122-1, 122-2, and 122-3, which can be in the form of nanosheets, nanowires, or nanobelts. Each nanostructure 122 can be used as a channel structure and form a channel region under the gate structure 112 of the transistors 102A to 102C. In some embodiments, the nanostructures 122 and the fin structures 108 can include semiconductor materials similar to or different from the substrate 104. In some embodiments, the nanostructures 122 and the fin structures 108 can include silicon. In some embodiments, the nanostructures 122 and the fin structures 108 can include silicon germanium. The semiconductor materials of the nanostructures 122 and the fin structures 108 can be undoped or can be in-situ doped during their formation process. In some embodiments, as shown in FIGS. 2 to 5, the nanostructures 122 under the gate structure 112 can form the channel region of the semiconductor device 100 and represent the current-carrying channel structure of the semiconductor device 100. In some embodiments, the nanostructures 122 can have a thickness in the range of about 5 nm to about 8 nm along the Z-axis. In some embodiments, the nanostructures 122 can have a width in the range of about 15 nm to about 50 nm along the Y-axis. In some embodiments, the nanostructures 122 can have a width in the range of about 15 nm to about 25 nm along the X-axis. In some embodiments, the pitch between adjacent nanostructures 122 along the Z-axis can be in the range of about 8 nm to about 12 nm. Although a three-layer nanostructure 122 is shown in FIGS. 2 to 5, the transistors 102A to 102C can have any number of nanostructures 122. Referring to FIGS. 2 to 5, the gate dielectric layer 124 can be disposed on the nanostructures 122, the fin structures 108, the STI region 106, the isolation layer 117, and the dielectric fin structure 119. In some embodiments, the gate dielectric layer 124 can be a multi-layer structure and can include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 can not include an interface layer but include a high-k dielectric layer in direct contact with the nanostructures 122. In some embodiments, the interface layer can include silicon oxide formed through a deposition process or an oxidation process. In some embodiments, the interface layer can have a thickness in the range of about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer can include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, as shown in FIGS. 2 to 5, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal fill. The one or more work function metal layers may include work function metals to tune the threshold voltage Vt of the transistors 102A to 102C. In some embodiments, the gate structures 112 of the NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structures 112 of the NFET and PFET devices may have different work function metals. In some embodiments, as shown in FIGS. 2 to 5, each nanostructure 122 may be surrounded by the gate structure 112. Thus, the gate structure 112 may be referred to as a "gate-all-around (GAA) structure", and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C". The one or more work function metal layers may surround the nanostructure 122 and may include work function metals to tune the Vt of the transistors 102A to 102C. In some embodiments, the transistors 102A to 102C may include any number of work function metal layers for Vt tuning (e.g., ultra-low Vt, low Vt, and standard Vt). In some embodiments, as shown in FIG. 5, the gate structure 112 may have a height 112h along the Z-axis from the top surface of the STI region 106. The height 112h may be in the range of about 80 nm to about 120 nm. In some embodiments, as shown in FIG. 5, the distance 112d along the Z-axis between the top surface of the gate structure 112 and the top surface of the top nanostructure 122-3 may be in the range of about 30 nm to about 40 nm. In some embodiments, the NFETs 102A to 102C may include n-type work function metal layers. The n-type work function metal layers may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium nitride silicon, or other suitable work function metals. In some embodiments, the PFETs 102A to 102C may include p-type work function metal layers. The p-type work function metal layers may include titanium nitride, titanium nitride silicon, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a stack of metal layers. The stack of metal layers may include work function metals having work function values equal to or different from each other. In some embodiments, the metal fill may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials. Referring to FIGS. 2 and 3, according to some embodiments, the gate spacer 114 can be disposed on the sidewalls of the gate structure 112 and in contact with the gate dielectric layer 124. The inner spacer 121 can be disposed adjacent to the end of the nanostructure 122 and between the S / D structure 110 and the gate structure 112. The gate spacer 114 and the inner spacer 121 can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, a low-k material, and combinations of the foregoing. In some embodiments, the gate spacer 114 and the inner spacer 121 can include the same insulating material. In some embodiments, the gate spacer 114 and the inner spacer 121 can include different insulating materials. In some embodiments, the gate spacer 114 and the inner spacer 121 can include a single insulating layer or a stack of insulating layers. In some embodiments, the gate spacer 114 and the inner spacer 121 can have a low-k dielectric material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8). The S / D structure 110 can be disposed on the fin structure 108 and on opposite sides of the gate structure 112. The S / D structure 110 can serve as the S / D regions of the transistors 102A to 102C. In some embodiments, the S / D structure 110 can have any geometric shape such as polygonal, conical, rhombic, elliptical, and circular. In some embodiments, the S / D structure 110 can include an epitaxially grown semiconductor material such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 can include an epitaxially grown semiconductor material different from the material of the substrate 104 (e.g., silicon germanium), and can apply stress to the channel region under the gate structure 112. Since the lattice constant of this epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is stressed to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material can include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium phosphide arsenide. In some embodiments, the S / D structure 110 can include silicon and can be in-situ doped with an n-type dopant (such as phosphorus and arsenic) during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors such as phosphine, arsine, and other n-type doping precursors can be used. In some embodiments, the S / D structure 110 can include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or gallium indium antimonide), and can be in-situ doped with a p-type dopant (such as boron, indium, and gallium) during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors such as diborane (B2H6), boron trifluoride (BF3), and other p-type doping precursors can be used. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, where each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and may be different from each other based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon germanium and may be different from each other based on, for example, doping concentration, epitaxial growth process conditions, and / or the relative concentration of germanium relative to silicon. Referring to FIGS. 1 to 5, the trench isolation structure 113 may be disposed on the substrate 104 and at the edges between different diffusion regions (e.g., n and p regions). In some embodiments, the trench isolation structure 113 may include a liner 113A and a dielectric filler 113B. In some embodiments, the liner 113A may include silicon nitride, silicon carbonitride, or other suitable dielectric materials. The dielectric filler 113B may include silicon oxide, silicon oxynitride, silicon oxycarbonitride, or other suitable dielectric materials. In some embodiments, the liner 113A may protect the nanostructure 122, the fin structure 108, and the substrate 104 (e.g., prevent oxidation) during the formation of the dielectric filler 113B. In some embodiments, the trench isolation structure 113 may extend through the gate structure 112, the nanostructure 122, the STI region 106, and the fin structure 108 and into the substrate 104. In some embodiments, the trench isolation structure 113 may be formed through the CPODE and / or CMODE processes to reduce the leakage current flowing through the S / D structure 110, the nanostructure 122, and the substrate 104. In some embodiments, as shown in FIGS. 1 to 5, the trench isolation structure 113 may include a short trench isolation structure extending over about 1 to about 3 fin structures 108. In some embodiments, the trench isolation structure 113 may include a long trench isolation structure extending over more than about 3 fin structures 108. In some embodiments, as shown in FIG. 3, the trench isolation structure 113 may have a height 113h along the Z-axis from the bottom surface of the trench isolation structure 113 to the top surface of the top nanostructure 122-3. The height 113h may be in the range from about 120 nm to about 250 nm. If the height 113h is less than about 120 nm, the trench isolation structure 113 cannot extend through the STI region 106 and cannot reduce the leakage current. If the height 113h is greater than about 250 nm, the well structures of the transistors 102A to 102C may be damaged and the device performance may be degraded. Additionally, the leakage current may not be further reduced, but the manufacturing cost may increase. In some embodiments, as shown in FIGS. 2 to 5, the protective layer 115 may be disposed on the STI region 106 and between the gate dielectric layer 124 and the isolation layer 117. In some embodiments, the protective layer 115 may include silicon carbonitride or other suitable materials to protect adjacent structures during the formation of the isolation layer 117. In some embodiments, the isolation layer 117 may be disposed on the protective layer 115, and the isolation layer 117 may include silicon oxide or other suitable materials. Referring to FIGS. 1 to 5, the dielectric fin structure 119 may be disposed on the isolation layer 117 and between adjacent nanostructures 122. In some embodiments, as shown in FIG. 1, the dielectric fin structures 119 and the nanostructures 122 may be disposed on the substrate 104 in an alternating configuration. In some embodiments, the dielectric fin structure 119 may include a hard dielectric material. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material may include silicon, silicon nitride, silicon carbide, silicon carbonitride, oxycarbide nitride, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric fin structure 119 may have one or more layers of different hard dielectric materials. In some embodiments, the dielectric fin structure 119 may have a higher etching resistance to remain after various etching processes. In some embodiments, the bottom surface of the dielectric fin structure 119 may be above the top surface of the top nanostructure 122-3. If the bottom surface of the dielectric fin structure 119 is below the top surface of the top nanostructure 122-3, the parasitic capacitance between adjacent nanostructure transistors may increase. In some embodiments, the dielectric fin structure 119 may reduce the deformation of the substrate 104 and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Therefore, as shown in FIG. 3, the gate structure 112 may be substantially vertical with respect to the X-axis and the Y-axis (e.g., the top surface of the nanostructure 122). In some embodiments, the gate structure 112 adjacent to the trench isolation structure 113 may be bent less than about 2 degrees. In some embodiments, in the case of having the dielectric fin structure 119, the width difference of the nanostructures 122 between the isolation region and the dense region along the X-axis may be less than about 1.5 nm, and the height difference of the trench isolation structure 113 may be less than about 15 nm. Therefore, the dielectric fin structure 119 may reduce the leakage current caused by the density-depth loading effect, minimize the damage to the S / D epitaxial structure caused by the density critical dimension loading effect, and reduce the Vt drift of the semiconductor device 100 caused by gate deformation. In some embodiments, as shown in FIG. 4, the dielectric fin structure 119 may have a width 119w in the range of from about 15 nm to about 20 nm along the Y-axis. In some embodiments, as shown in FIG. 4, the dielectric fin structure 119 may have a height 119h in the range of from about 20 nm to about 30 nm along the Z-axis. In some embodiments, a first ratio of the height 119h to the distance 120d may be in the range of from about 0.6 to about 0.8. A second ratio of the height 119h to the height 120h of the gate structure may be in the range of from about 0.15 to about 0.3. If the height 119h is less than about 20 nm, the first ratio is less than about 0.6, or the second ratio is less than about 0.15, the dielectric fin structure 119 may not be retained after the CPODE or CMODE process. If the height 119h is greater than about 30 nm, the first ratio is greater than about 0.8, or the second ratio is greater than about 0.3, the parasitic capacitance between adjacent nanoscale structure transistors may increase. In some embodiments, the width 119w, the height 119h, and the first and second ratios may depend on the hard dielectric material of the dielectric fin structure 119. In some embodiments, the bottom surface of the dielectric fin structure 119 and the top surface of the top nanoscale structure 122-3 may be substantially at the same level. In some embodiments, as shown in FIG. 4, the dielectric fin structure 119 may be surrounded by a trench isolation structure 113. Referring to FIGS. 2 to 5, the ESL 116 may be disposed on the sidewalls of the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. The ESL 116 may be configured to protect the S / D structure 110, the dielectric fin structure 119, and the gate structure 112 during the formation of the S / D contact structure on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination of the foregoing. The ILD layer 118 may be disposed on the ESL 116 over the S / D structure 110 and the dielectric fin structure 119. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide. In some embodiments, as shown in FIGS. 2 and 5, the gate isolation structure 120 may be disposed on the trench isolation structure 113. In some embodiments, the gate isolation structure 120, the dielectric fin structure 119, the isolation layer 117, and the trench isolation structure 113 may electrically isolate the gate structure 112 into two parts. In some embodiments, the gate isolation structure 120 may include silicon nitride, silicon oxide, and / or other suitable dielectric materials. In some embodiments, the gate isolation structure 120 may include a single dielectric layer or a dielectric layer stack. In some embodiments, the gate isolation structure 120, the dielectric fin structure 119, and the isolation layer 117 may vertically extend through the gate structure 112. In some embodiments, the semiconductor device 100 may further include S / D contact structures, gate contact structures, metal wires, metal vias, interconnects, and additional ILD layers, which are not described in detail for clarity. FIG. 6 is a flowchart of a method 600 for manufacturing a semiconductor device 100 having a dielectric fin structure according to some embodiments. The method 600 may not be limited to nanoscale transistor devices and may be applicable to other devices that benefit from the dielectric fin structure. Additional manufacturing operations may be performed between various operations of the method 600 and may be omitted, and such omission is merely for clarity and ease of description. Additional processes may be provided before, during, and / or after the method 600; one or more of these additional processes are briefly described herein. In addition, not all operations may be required to implement the disclosure provided herein. Additionally, some operations may be performed simultaneously or in a different order than shown in FIG. 6. In some embodiments, one or more other operations may be performed in addition to or instead of the currently described operations. For purposes of illustration, the operations shown in FIG. 6 will be described with reference to an example manufacturing process for manufacturing semiconductor device 100 as shown in FIGS. 7 to 68. FIG. 7 shows a top view of semiconductor device 100 having a dielectric fin structure at various stages of its manufacture in accordance with some embodiments. FIGS. 8 to 68 show partial isometric views and partial cross-sectional views of semiconductor device 100 having a dielectric fin structure at various stages of its manufacture in accordance with some embodiments. FIGS. 11, 14, 17, 20, 23, 26, 29, 32, 35, 37, 40, 43, 46, 49 and 52 show partial isometric views of semiconductor device 100 at various stages of its manufacture in accordance with some embodiments. FIGS. 8, 12, 15, 18, 21, 24, 27, 30, 33, 36, 38, 41, 44, 47, 50, 53, 55, 57, 59, 61, 63, 65 and 67 show partial cross-sectional views of semiconductor device 100 along the X-axis (e.g., line A-A as shown in FIG. 2) at various stages of its manufacture in accordance with some embodiments. FIGS. 9, 10, 13, 16, 19, 22, 25, 28, 31, 34, 39, 42, 45, 48, 51, 54, 56, 58, 60, 62, 64, 66 and 68 show partial cross-sectional views of semiconductor device 100 along the Y-axis (e.g., line B-B as shown in FIG. 2) at various stages of its manufacture in accordance with some embodiments. Elements in FIGS. 7 to 68 having the same reference numerals as the elements in FIGS. 1 to 5 have been described above. Referring to FIG. 6, method 600 begins with operation 610 and a process of forming a channel structure extending in a first direction on a substrate. For example, as shown in FIGS. 7 to 9, nanostructure 122 and nanostructure 820 along the X-axis can be formed on substrate 104. In some embodiments, nanostructure 122 and nanostructure 820 can be stacked in an alternating configuration. A sacrificial nanostructure 823 can be formed on nanostructure 122-3, and the sacrificial nanostructure 823 is protected by a hard mask layer 722. In some embodiments, nanostructure 122, nanostructure 820, and sacrificial nanostructure 823 can be epitaxially grown on substrate 104 and then patterned with hard mask layer 722 to form a stack of nanostructure 122 and nanostructure 820. In some embodiments, nanostructure 122, nanostructure 820, and sacrificial nanostructure 823 can be in the form of nanosheets, nanowires, or nanoribbons. In some embodiments, nanostructure 122, nanostructure 820, and sacrificial nanostructure 823 can include semiconductor materials similar to or different from substrate 104. In some embodiments, nanostructure 122, nanostructure 820, and sacrificial nanostructure 823 can include different semiconductor materials. In some embodiments, nanostructure 820 can include a semiconductor material having an etching rate and / or etching selectivity higher than that of nanostructure 122 but lower than that of sacrificial nanostructure 823. For example, nanostructure 122 can include silicon, and nanostructure 820 can include silicon germanium having a germanium atomic percentage ranging from about 10% to about 40%. Sacrificial nanostructure 823 can include silicon germanium having a germanium atomic percentage ranging from about 25% to about 60%. In some embodiments, nanostructure 122 and nanostructure 820 can include silicon doped with different dopants to have different etching rates and / or etching selectivities and to minimize the loss of nanostructure 122 during the sheet formation process of nanostructure 122. Embodiments of nanostructure 122, nanostructure 820, and sacrificial nanostructure 823 disclosed herein can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used for patterning to obtain nanostructures. The double patterning process or multi-patterning process can combine the lithography process and the self-alignment process to form, for example, a pattern with a pitch smaller than the pitch obtainable using a single direct lithography process. For example, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a lithography process. Spacers can be formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the nanostructures. After forming the nanostructure 122, the nanostructure 820, and the sacrificial nanostructure 823, a STI region 106 can be formed between the stacks of the adjacent nanostructures 122 and 820, as shown in FIGS. 9 to 16. In some embodiments, as shown in FIG. 9, an oxide liner 105 can be conformally deposited on the substrate 104, the nanostructure 122, the nanostructure 820, and the sacrificial nanostructure 823 to provide protection in the subsequent formation of the STI region 106. In some embodiments, the oxide liner 105 can include silicon oxide or other suitable dielectric materials. In some embodiments, as shown in FIG. 10, a dielectric material 1006 can be deposited on the oxide liner 105 over the substrate 104, the nanostructure 122, the nanostructure 820, and the sacrificial nanostructure 823. In some embodiments, as shown in FIGS. 11 to 13, the dielectric material 1006 can be polished through a chemical mechanical polishing (CMP) process to form the STI region 106 between the stacks of the adjacent nanostructures 122 and 820. The CMP process can remove the hard mask layer 722 and planarize the top surfaces of the STI region 106 and the sacrificial nanostructure 823. In some embodiments, as shown in FIGS. 14 to 16, the STI region 106 can be recessed, and the top surface of the STI region 106 can be below the nanostructures 122 and 820. After forming the STI region 106, a capping layer 1725 can be formed. For example, as shown in FIGS. 17 to 19, the capping layer 1725 can be conformally deposited on the STI region 106, the nanostructure 122, the nanostructure 820, and the sacrificial nanostructure 823. In some embodiments, the capping layer 1725 can include a semiconductor material having an etching rate and / or etching selectivity similar to that of the nanostructure 820 and lower than that of the sacrificial nanostructure 823. In some embodiments, the capping layer 1725 can include silicon germanium having a germanium atomic percentage ranging from about 10% to about 40%. In some embodiments, the capping layer 1725 on the top surfaces of the STI region 106 and the sacrificial nanostructure 823 can be removed through an anisotropic etching process, as shown in FIGS. 20 to 22. After the anisotropic etching process, the capping layer 1725 can remain on the sidewalls of the nanostructures 122, the nanostructure 820, and the sacrificial nanostructure 823. After the formation of the encapsulation layer 1725, the isolation layer 117 can be formed. For example, as shown in FIGS. 23 to 28, the isolation layer 117 can be formed on the STI region 106 between the stacks of the nanostructures 122 and 820. In some embodiments, as shown in FIGS. 23 to 25, the protective layer 115 can be conformally deposited on the top surface of the STI region 106 and the sacrificial nanostructure 823 and the sidewall surface of the encapsulation layer 1725. In some embodiments, the protective layer 115 can include silicon carbonitride or other suitable dielectric materials to protect the encapsulation layer 1725 and the sacrificial nanostructure 823 in subsequent processes. In some embodiments, the oxide material 2317 can be deposited on the protective layer 115 to fill the opening between the stacks of the nanostructures 122 and 820. In some embodiments, the oxide material 2317 can include silicon oxide or other suitable oxide materials. In some embodiments, as shown in FIGS. 26 to 28, the oxide material 2317 can be planarized through a CMP process and recessed through an etching process to form the isolation layer 117. In some embodiments, for lower device parasitic capacitance, the top surface of the isolation layer 117 can be above the top surface of the top nanostructure 122-3. Referring to FIG. 6, in operation 620, a dielectric fin structure adjacent to the channel structure is formed on the substrate. The dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction. For example, as shown in FIGS. 29 to 31, the dielectric fin structure 119 can be formed on the STI region 106 and on the isolation layer 117 between the stacks of the adjacent nanostructures 122 and nanostructures 820. In some embodiments, the dielectric fin structure 119 can include a hard dielectric material. In some embodiments, the hard dielectric material can have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material can have a Young's modulus greater than about 75 GPa. In some embodiments, the hard dielectric material can include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials. In some embodiments, the hard dielectric material can include silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon, aluminum oxide, or other suitable low-k dielectric materials. In some embodiments, the dielectric fin structure 119 can have a high etch resistance to remain after various etching processes. In some embodiments, the hard dielectric material in the dielectric fin structure 119 can have an etch rate lower than that of the semiconductor material in the nanostructure 122. Thus, the dielectric fin structure 119 can remain after etching through the CPODE and CMODE processes. In some embodiments, the dielectric fin structure 119 can extend along the X-axis parallel to the nanostructure 122. In some embodiments, as shown in FIG. 29, the dielectric fin structure 119 and the nanostructure 122 can be arranged in an alternating configuration on the substrate 104. In some embodiments, the bottom surface of the dielectric fin structure 119 can be higher than the top surface of the top nanostructure 122-3. In some embodiments, the dielectric fin structure 119 can reduce the deformation of the substrate 104 and minimize the LDE effect of the semiconductor device 100 on the substrate 104. Thus, the dielectric fin structure 119 can reduce the leakage current caused by the density-depth load effect, minimize the damage to the S / D epitaxial structure caused by the density critical dimension load effect, and reduce the Vt drift of the semiconductor device 100 caused by the gate deformation. Referring to FIG. 6, in operation 630, a sacrificial gate structure may be formed on the channel structure and the dielectric fin structure. For example, as shown in FIGS. 32 to 42, a sacrificial gate structure 3712 may be formed on the nanostructure 122 and the dielectric fin structure 119. In some embodiments, forming the sacrificial gate structure 3712 may include removing the sacrificial nanostructure 823, conformally depositing a liner 3524, and depositing the sacrificial gate structure 3712. In some embodiments, an etching process may remove the sacrificial nanostructure 823. Due to the etching selectivity between the dielectric fin structure 119 and the sacrificial nanostructure 823, the etching process may not remove the dielectric fin structure 119. In some embodiments, a liner 3524 may be conformally deposited on the nanostructure 122 and the dielectric fin structure 119. The liner 3524 may include silicon oxide or other suitable dielectric materials. In some embodiments, the sacrificial gate structure 3712 may be deposited on the liner 3524 over the nanostructure 122 and the dielectric fin structure 119. In some embodiments, as shown in FIGS. 40 to 42, the sacrificial gate structure 3712 may be patterned using a nitride hard mask layer 4032 and an oxide hard mask layer 4034. A spacer layer 4014 may be conformally deposited on the sacrificial gate structure 3712, the nitride hard mask layer 4032, the oxide hard mask layer 4034, the nanostructure 122, and the dielectric fin structure 119. After forming the sacrificial gate structure 3712, the S / D structure 110 can be formed, as shown in FIGS. 43 to 51. Forming the S / D structure 110 can include removing a portion of the nanostructure 122 and the nanostructure 820, forming the internal spacer 121, and epitaxially growing the S / D structure 110. In some embodiments, as shown in FIGS. 43 to 45, an anisotropic etching process can remove a portion of the nanostructure 122 and the nanostructure 820 to form recesses 4510 on each side of the sacrificial gate structure 3712. A lateral etching process can remove the ends of the nanostructure 820 to form recesses 4521 between the nanostructures 122. In some embodiments, as shown in FIGS. 46 to 48, the internal spacer 121 can be formed in the recesses 4521. In some embodiments, forming the internal spacer 121 can include: blanket depositing a spacer layer, followed by an etching process to remove the sacrificial gate structure 3712 and the spacer layer on the sidewalls and top surfaces of the nanostructure 122 and the nanostructure 820. In some embodiments, as shown in FIGS. 49 to 51, the S / D structure 110 can be epitaxially grown on the fin structure 108, and the S / D structure 110 is in contact with the nanostructure 122. In some embodiments, the S / D structure 110 can be formed between adjacent stacks of the protective layer 115, the isolation layer 117, and the dielectric fin structure 119. In some embodiments, the S / D structure 110 can be in contact with the protective layer 115. In some embodiments, the S / D structure 110 can be in-situ doped with an n-type or p-type dopant during the epitaxial growth. As shown in FIGS. 52 to 56, after forming the S / D structure 110, the ESL 116 and the ILD layer 118 can be formed on the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. In some embodiments, the ESL 116 can be conformally deposited on the S / D structure 110, the dielectric fin structure 119, and the gate spacer 114. In some embodiments, the ILD layer 118 can be blanket deposited on the ESL 116. A subsequent CMP process can planarize the top surfaces of the gate spacer 114, the ESL 116, the ILD layer 118, and the sacrificial gate structure 3712. In some embodiments, the ILD layer 118 can be recessed between the sacrificial gate structures 3712. A hard mask layer 5236 can be deposited in the recesses and on the sacrificial gate structure 3712, as shown in FIGS. 52 to 56. In some embodiments, the hard mask layer 5236 can include silicon nitride or other suitable dielectric materials. In some embodiments, as shown in FIGS. 53 and 54, the S / D structure 110 can include multiple epitaxial layers having different material compositions and doping concentrations. In some embodiments, as shown in FIGS. 55 and 56, the S / D structure 110 can further extend into the substrate 104. Referring to FIG. 6, in operation 640, an isolation structure is formed that extends through the sacrificial gate structure and the channel structure and contacts the dielectric fin structure. For example, as shown in FIGS. 58 to 68, a trench isolation structure 113-2 can be formed on the substrate 104 that extends through the sacrificial gate structure 3712 and the nanostructure 122. The trench isolation structure 113-2 can contact the dielectric fin structure 119. In some embodiments, a stack of a bottom layer 5738, an intermediate layer 5740, and a photoresist 5742 can be deposited on the hard mask layer 5236. In some embodiments, patterning can be performed in the photoresist 5742 above the sacrificial gate structure 3712 to obtain an opening 5713, as shown in FIGS. 57 and 58. After the patterning process, an opening 5713 can be formed in the hard mask layer 5236 through a dry etching process, as shown in FIGS. 59 and 60. In some embodiments, as shown in FIGS. 61 and 62, the dry etching process can remove the sacrificial gate structure 3712 and extend the opening 5713 through the sacrificial gate structure 3712. In some embodiments, the etching of the sacrificial gate structure 3712 can be directional and self-aligned. The etchant can include a hydrogen bromide-based plasma with additives of oxygen or carbon dioxide. In some embodiments, the hydrogen bromide-based plasma can be a high-density plasma generated by an inductively coupled plasma or a resonant antenna plasma source with a radio frequency (RF) power generator. In some embodiments, the RF power generator can use an alternating current (AC) operating at a frequency that is a multiple of about 13.56 MHz. In some embodiments, the RF power generator can provide a source power from about 0 W to about 2500 W to generate the plasma. In some embodiments, the RF bias power can be in the range from about 0 W to about 2000 W. In some embodiments, a pulsed plasma etching with a duty cycle from about 5% to about 95% can be used in the etching process. In some embodiments, the plasma etching process can use a bias power with zero source power to increase the directionality of the etching process. In some embodiments, the etching process chamber can be operated at a pressure in the range from about 1 mTorr to about 200 mTorr at a temperature from about 10 °C to about 200 °C. In some embodiments, to increase the etch selectivity between the sacrificial gate structure 3712 and the hard mask layer 5236, a methane-based deposition process can be used to form a polymer layer on the hard mask layer 5236. In some embodiments, an oxide (e.g., silicon oxide) can be formed during a dry etching process to improve the self-aligned etching process. In some embodiments, these oxides can be formed from silicon tetrachloride, oxygen, and hydrogen bromide. In some embodiments, a wet cleaning process can be performed to remove the oxides formed on the nanostructure 122 and the dielectric fin structure 119 during the dry etching process. In some embodiments, the wet cleaning process can include etchants such as carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), methane (CH 3 F), and hexafluorobutadiene (C 4 F 6 ). In some embodiments, as shown in FIGS. 63 and 64, an additional dry etching process can extend the opening 5713 through the nanostructure 122 until the substrate 104. In some embodiments, as shown in FIGS. 65 to 68, a trench isolation structure 113-2 can be formed in the opening 5713. In some embodiments, the trench isolation structure 113-2 can include a liner 113A and a dielectric filler 113B. The liner 113A can be conformally deposited on the hard mask layer 5236, the substrate 104, and on the sidewalls of the STI region 106, the isolation layer 117, the dielectric fin structure 119, the gate spacer 114, and the sacrificial gate structure 3712. The dielectric filler 113B can be deposited blanket on the liner 113A, and the dielectric filler 113B can fill the opening 5713, as shown in FIGS. 65 and 66. In some embodiments, a CMP process can planarize the top surfaces of the gate spacer 114, the ESL 116, the hard mask layer 5236, the trench isolation structure 113-2, and the sacrificial gate structure 3712. In some embodiments, the trench isolation structure 113-2 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide nitride, or other suitable dielectric materials. In some embodiments, the trench isolation structure 113-2 may extend through the sacrificial gate structure 3712, the nanostructure 122, the STI region 106, and the fin structure 108 into the substrate 104. In some embodiments, the trench isolation structure 113-2 may be formed by a CPODE process to reduce leakage current flowing through the S / D structure 110, the nanostructure 122, and the substrate 104. Referring to FIG. 6, in operation 650, the sacrificial gate structure may be replaced with a metal gate structure. For example, as shown in FIGS. 2 to 5, the sacrificial gate structure 3712 may be replaced with the metal gate structure 112. In some embodiments, the replacement of the gate structure 112 may include removing the sacrificial gate structure 3712, removing the nanostructure 820, and depositing the gate structure 112. These processes are not described in detail for clarity. In some embodiments, the trench isolation structure 113 may be formed after the replacement of the gate structure 112, as described in FIGS. 69 to 85. FIG. 69 is a flowchart of another method 6900 for manufacturing a semiconductor device 100 having a dielectric fin structure according to some embodiments. The method 6900 may not be limited to nanostructure transistor devices and may be applied to other devices that benefit from a dielectric fin structure. Additional manufacturing operations may be performed between various operations of the method 6900 and may be omitted, and such omission is only for clarity and ease of description. Additional processes may be provided before, during, and / or after the method 6900; one or more of these additional processes are briefly described herein. In addition, not all operations may be required to implement the disclosure provided herein. Additionally, some operations may be performed simultaneously or in a different order than shown in FIG. 69. In some embodiments, one or more other operations may be performed in addition to or instead of the currently described operations. For purposes of illustration, the operations shown in FIG. 69 will be described with reference to an exemplary manufacturing process for manufacturing semiconductor device 100 as shown in FIGS. 7 to 56 and FIGS. 70 to 85. FIGS. 7 to 56 were described above. FIGS. 70 to 85 show partial cross-sectional views of semiconductor device 100 having a dielectric fin structure at various stages of its manufacture by another method. FIGS. 70, 72, 74, 76, 78, 80, 82, and 84 show partial cross-sectional views of semiconductor device 100 according to some embodiments at various stages of its manufacture by another method along the X-axis (e.g., line A-A as shown in FIG. 2). FIGS. 71, 73, 75, 77, 79, 81, 83, and 85 show partial cross-sectional views of semiconductor device 100 according to some embodiments at various stages of its manufacture by another method along the Y-axis (e.g., line C-C as shown in FIG. 2). Elements in FIGS. 70 to 85 having the same reference numerals as elements in FIGS. 1 to 5 were described above. Referring to FIG. 69, method 6900 begins with operation 6910 and a process of forming a channel structure extending in a first direction on a substrate. In some embodiments, operation 6910 may be similar to operation 610 described above. For example, as shown in FIGS. 7 to 9, nanostructures 122 and 820 along the X-axis may be formed on substrate 104. In some embodiments, after forming nanostructures 122 and 820, an STI region 106 may be formed between stacks of adjacent nanostructures 122 and 820, as shown in FIGS. 9 to 16. In some embodiments, after forming STI region 106, a capping layer 1725 may be formed, as shown in FIGS. 17 to 19. In some embodiments, after forming capping layer 1725, an isolation layer 117 may be formed, as shown in FIGS. 23 to 28. Referring to FIG. 69, in operation 6920, a dielectric fin structure adjacent to the channel structure is formed on the substrate. The dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction. In some embodiments, operation 6920 may be similar to operation 620 described above. For example, as shown in FIGS. 29 to 31, a dielectric fin structure 119 may be formed on isolation layer 117 above STI region 106 and between stacks of adjacent nanostructures 122 and 820. In some embodiments, dielectric fin structure 119 may extend parallel to nanostructure 122 along the X-axis. Referring to FIG. 69, in operation 6930, a metal gate structure is formed on the channel structure and the dielectric fin structure. For example, as shown in FIGS. 70 and 71, a gate structure 112 can be formed on the nanostructure 122 and the dielectric fin structure 119. In some embodiments, forming the gate structure 112 may include removing the sacrificial gate structure 3712 shown in FIG. 52, removing the nanostructure 820 shown in FIG. 52, and depositing one or more work function metal layers and metal fillers around the nanostructure 122. In some embodiments, a gate isolation structure 120 can be formed in the gate structure 112 and on the dielectric fin structure 119 to divide the gate structure 112 into multiple parts. In some embodiments, a hard mask layer 7036 can be deposited on the gate structure 112, the gate spacer 114, the ESL 116, the ILD layer 118, and the gate isolation structure 120. Referring to FIG. 69, in operation 6940, an isolation structure is formed that extends through the metal gate structure and the channel structure and contacts the dielectric fin structure. For example, as shown in FIGS. 72 to 85, trench isolation structures 113-1 and 113-2 can be formed on the substrate 104 that extend through the gate structure 112 and the nanostructure 122 and contact the dielectric fin structure 119. In some embodiments, a stack of a bottom layer 7238, an intermediate layer 7240, and a photoresist 7242 can be deposited on the hard mask layer 7036. In some embodiments, patterning can be performed in the photoresist 7242 above the gate structure 112 to obtain an opening 7213, as shown in FIGS. 72 and 73. After the patterning process, an opening 7213 can be formed in the hard mask layer 7036 through a dry etching process, as shown in FIGS. 74 and 75. In some embodiments, a high-selectivity etching process can remove the gate structure 112 and extend the opening 7213 through the gate structure 112, as shown in FIGS. 76 and 77. In some embodiments, the high-selectivity etching process can include a dry etching process or a wet etching process. After the selective etching process, the gate structure 112 can be removed, while the gate dielectric layer 124 can remain on the nanostructure 122. In some embodiments, a wet cleaning process after each of the dry etching process or the wet etching process can remove any residues formed during the etching process. In some embodiments, as shown in FIGS. 78 and 79, another selective etching process can remove the gate dielectric layer 124 from the nanostructure 122. In some embodiments, the selective etching process can include a dry etching process or a wet etching process. In some embodiments, as shown in FIGS. 80 and 81, an additional dry etching process can remove the nanostructure 122 and extend the opening 7213 through the nanostructure 122 until it reaches the substrate 104. In some embodiments, as shown in FIGS. 82 to 85, trench isolation structures 113-1 and 113-2 can be formed in the opening 7213. In some embodiments, the trench isolation structures 113-1 and 113-2 can include a liner 113A and a dielectric filler 113B. The liner 113A can be conformally deposited on the hard mask layer 7036, the substrate 104, and on the sidewalls of the STI region 106, the isolation layer 117, the dielectric fin structure 119, the gate spacer 114, and the gate isolation structure 120. The dielectric filler 113B can be deposited blanket on the liner 113A, and the dielectric filler 113B can fill the opening 7213, as shown in FIGS. 82 and 83. In some embodiments, a CMP process can planarize the top surfaces of the gate spacer 114, the ESL 116, the ILD layer 118, the trench isolation structures 113-1 and 113-2, the gate isolation structure 120, and the gate structure 112. In some embodiments, the trench isolation structures 113-1 and 113-2 can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide nitride, or other suitable dielectric materials. In some embodiments, the trench isolation structures 113-1 and 113-2 can extend through the gate structure 112, the nanostructure 122, the STI region 106, and the fin structure 108 and into the substrate 104. In some embodiments, the trench isolation structures 113-1 and 113-2 can be formed through a CMODE process to reduce the leakage current flowing through the S / D structure 110, the nanostructure 122, and the substrate 104. Various embodiments of the present disclosure provide methods for forming a dielectric fin structure 119 in a semiconductor device 100. In some embodiments, nanostructures 122 extending in a first direction may be formed on a substrate 104. A dielectric fin structure 119 adjacent to the nanostructures 122 may be formed on the substrate 104. In some embodiments, the dielectric fin structure 119 may include a hard dielectric material and extend in a second direction parallel to the first direction. In some embodiments, the hard dielectric material may have a Young's modulus greater than that of silicon oxide. In some embodiments, the hard dielectric material may have a Young's modulus greater than about 75 GPa. A gate structure 112 may be formed on the nanostructures 122 and the dielectric fin structure 119. A trench isolation structure 113 may be formed on the gate structure 112, and the trench isolation structure 113 may extend through the gate structure 112 and the nanostructures 122. In some embodiments, the trench isolation structure 113 may contact the dielectric fin structure 119. In some embodiments, the trench isolation structure 113 may be formed through a CPODE or CMODE process. In some embodiments, the dielectric fin structure 119 may reduce the deformation of the substrate 104 and minimize the LDE effect of the semiconductor device on the substrate 104. Accordingly, the dielectric fin structure 119 may reduce device leakage current, minimize damage to the S / D structure 110, and reduce Vt drift of the semiconductor device on the substrate. In some embodiments, a semiconductor structure includes a channel structure on a substrate. The channel structure extends in a first direction. The semiconductor structure further includes a dielectric fin structure on the substrate and adjacent to the channel structure. The dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction. The semiconductor structure further includes an isolation structure extending through the channel structure. The isolation structure contacts the dielectric fin structure. In some embodiments, a semiconductor device includes a plurality of channel structures on a substrate and a plurality of dielectric fin structures on the substrate including a hard dielectric material. The plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration. The semiconductor device further includes a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures, and an isolation structure extending through the gate structure and at least one of the plurality of channel structures. The isolation structure contacts at least one of the plurality of dielectric fin structures. In some embodiments, a method includes: forming a channel structure on a substrate, and forming a dielectric fin structure on the substrate adjacent to the channel structure. The channel structure extends in a first direction. The dielectric fin structure includes a hard dielectric material and extends in a second direction parallel to the first direction. The method further includes forming an isolation structure extending through the channel structure. The isolation structure contacts the dielectric fin structure. It should be understood that the detailed description section (rather than the abstract section of this disclosure) is intended to explain the claims. The abstract section of this disclosure may set forth one or more embodiments, rather than all possible embodiments of this disclosure contemplated by the (one or more) inventors, and thus is not intended to limit the appended claims in any way. The foregoing disclosure outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure. 100: Semiconductor device 102A, 102B, 102C: Transistors, NFET, PFET 104: Substrate 105: Oxide liner 106: Shallow trench isolation (STI) region 108: Fin structure 110: S / D structure 112: Gate structure 112d: Distance 112h: Height 113, 113-1, 113-2: Trench isolation structure 113A: Liner 113B: Dielectric fill 114: Gate spacer 115: Protection layer 116: Etch stop layer (ESL) 117: Isolation layer 118: Interlayer dielectric (ILD) layer 119: Dielectric fin structure 119w: Width 119h: Height 120: Gate isolation structure 121: Inner spacer 122, 122-1, 122-2, 122-3, 820: Nanostructure 124: Gate dielectric layer 600, 6900: Methods 610~650, 6910~6940: Operations 722: Hard mask layer 823: Sacrificial nanostructure 1006: Dielectric material 1725: Coating layer 2317: Oxide material 3524: Liner 3712: Sacrificial gate structure 4014: Spacer layer 4032: Nitride hard mask layer 4034: Oxide hard mask layer 4510, 4521: Recess 5713: Opening 5236: Hard mask layer 5738: Bottom layer 5740: Intermediate layer 5742: Photoresist 7036: Hard mask layer 7238: Bottom layer 7240: Intermediate layer 7242: Photoresist 7213: Opening A-A, B-B, C-C: Lines As can be best understood when read in conjunction with the accompanying drawings, various aspects of this disclosure will be described in detail below. FIG. 1 shows a top view of a semiconductor device having a dielectric fin structure according to some embodiments. FIG. 2 shows an isometric view of a semiconductor device having a dielectric fin structure according to some embodiments. FIGS. 3 to 5 show cross-sectional views of a semiconductor device having a dielectric fin structure according to some embodiments. FIG. 6 is a flowchart of a method for manufacturing a semiconductor device having a dielectric fin structure according to some embodiments. FIGS. 7 to 68 show top views, isometric views, and cross-sectional views of a semiconductor device having a dielectric fin structure at various stages of its manufacture according to some embodiments. FIG. 69 is a flowchart of another method for manufacturing a semiconductor device having a dielectric fin structure according to some embodiments. FIGS. 70 to 85 show cross-sectional views of a semiconductor device having a dielectric fin structure at various stages of its manufacture by another method according to some embodiments. Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements. 100: Semiconductor device 102A, 102B, 102C: Transistors 104: Substrate 106: Shallow trench isolation (STI) region 108: Fin structure 112: Gate structure 113-1, 113-2: Trench isolation structures 114: Gate spacer 115: Protection layer 116: Etch stop layer (ESL) 117: Isolation layer 118: Interlayer dielectric (ILD) layer 119: Dielectric fin structure 120: Gate isolation structure A-A, B-B, C-C: Lines

Claims

1. A semiconductor structure, comprising: a channel structure on a substrate, wherein the channel structure extends along a first direction; a dielectric fin structure on the substrate and adjacent to the channel structure, wherein the dielectric fin structure comprises a hard dielectric material and extends along a second direction parallel to the first direction; and an isolation structure extending through the channel structure, wherein the isolation structure contacts the dielectric fin structure.

2. The semiconductor structure according to claim 1, wherein, the dielectric fin structure is located on a top surface of an isolation layer, and the hard dielectric material has a Young's modulus greater than about 75 GPa.

3. The semiconductor structure according to claim 1, further comprising: a gate structure surrounding the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

4. The semiconductor structure according to claim 3, wherein, a top surface of the dielectric fin structure is below a top surface of the gate structure.

5. The semiconductor structure according to claim 3, wherein, a ratio of a height of the isolation structure to a height of the gate structure is in a range of about 0.15 to about 0.

3.

6. The semiconductor structure according to claim 1, wherein, a top surface of the dielectric fin structure is below a top surface of the isolation structure.

7. The semiconductor structure according to claim 1, wherein, a bottom surface of the dielectric fin structure is at a same level as or above a top surface of the channel structure.

8. The semiconductor structure according to claim 1, wherein, the isolation structure extends into the substrate, and the dielectric fin structure is surrounded by the isolation structure.

9. The semiconductor structure according to claim 1, wherein, the isolation structure comprises a pad contacting the dielectric fin structure and a dielectric filler on the pad.

10. A semiconductor device, comprising: a plurality of channel structures on a substrate; a plurality of dielectric fin structures on the substrate, the plurality of dielectric fin structures comprising a hard dielectric material, wherein the plurality of channel structures and the plurality of dielectric fin structures are arranged in an alternating configuration; a gate structure surrounding the plurality of channel structures and the plurality of dielectric fin structures; and an isolation structure extending through the gate structure and at least one of the plurality of channel structures, wherein the isolation structure contacts at least one of the plurality of dielectric fin structures.

11. The semiconductor device according to claim 10, wherein, the plurality of dielectric fin structures are located on a top surface of an isolation layer, and the hard dielectric material has a Young's modulus greater than about 75 GPa.

12. The semiconductor device according to claim 10, wherein, top surfaces of the plurality of dielectric fin structures are below a top surface of the gate structure.

13. The semiconductor device according to claim 10, wherein, top surfaces of the gate structure and the isolation structure are coplanar.

14. The semiconductor device according to claim 10, wherein, The bottom surfaces of the plurality of dielectric fin structures are at the same level as or higher than the top surfaces of the plurality of channel structures.

15. The semiconductor device according to claim 10, wherein, the isolation structure extends through the plurality of channel structures and into the substrate.

16. A method, comprising: forming a channel structure on a substrate, wherein the channel structure extends in a first direction; forming a dielectric fin structure adjacent to the channel structure on the substrate, wherein the dielectric fin structure comprises a hard dielectric material and extends in a second direction parallel to the first direction; and forming an isolation structure extending through the channel structure, wherein the isolation structure contacts the dielectric fin structure.

17. The method according to claim 16, further comprising: forming a gate structure surrounding the channel structure, wherein the gate structure is between the channel structure and the dielectric fin structure.

18. The method according to claim 16, wherein, forming the dielectric fin structure comprises: forming an isolation layer on the channel structure and an adjacent channel structure; etching the isolation layer to form an opening between the channel structure and the adjacent channel structure, wherein a bottom surface of the opening is at the same level as or higher than a top surface of the channel structure; and filling the opening with the hard dielectric material, wherein the hard dielectric material has a Young's modulus greater than about 75 GPa.

19. The method according to claim 16, wherein, forming the isolation structure comprises: forming a sacrificial gate structure on the channel structure and the dielectric fin structure; etching through the sacrificial gate structure and the channel structure to form an opening; depositing a dielectric material in the opening, wherein the dielectric material contacts the dielectric fin structure; and replacing the sacrificial gate structure with a metal gate structure.

20. The method according to claim 16, wherein, forming the isolation structure comprises: forming a metal gate structure on the channel structure and the dielectric fin structure; etching through the metal gate structure and the channel structure to form an opening; and depositing a dielectric material in the opening, wherein the dielectric material contacts the dielectric fin structure.